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WO2022142531A1 - Eeprom器件及其制备方法 - Google Patents

Eeprom器件及其制备方法 Download PDF

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Publication number
WO2022142531A1
WO2022142531A1 PCT/CN2021/120720 CN2021120720W WO2022142531A1 WO 2022142531 A1 WO2022142531 A1 WO 2022142531A1 CN 2021120720 W CN2021120720 W CN 2021120720W WO 2022142531 A1 WO2022142531 A1 WO 2022142531A1
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WIPO (PCT)
Prior art keywords
selection
area
width
gate
groove
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PCT/CN2021/120720
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English (en)
French (fr)
Inventor
张松
梁志彬
李小红
金炎
王德进
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无锡华润上华科技有限公司
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Publication of WO2022142531A1 publication Critical patent/WO2022142531A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to an EEPROM device and a preparation method thereof.
  • EEPROM devices with a typical structure (Electrically Erasable Programmable Read-Only Memory), as the cell area shrinks, the cell current becomes smaller and smaller, making the EEPROM device smaller and smaller.
  • the 0s and 1s stored in EEPROM are becoming more and more indistinguishable, which in turn affects the further scaling of EEPROM device size.
  • Typical EEPROM device cell current improvement methods are to reduce the resistance and threshold of the EEPROM cell by reducing the control gate (Control Gate), reducing the distance between the control gate (Control Gate) and the select gate (Select gate), and adjusting the injection concentration.
  • Control Gate control gate
  • Select gate select gate
  • injection concentration injection concentration
  • An EEPROM device comprising:
  • the substrate includes a selection area and a storage area, and the selection area is provided with a groove;
  • a select gate formed on the select region, and the select gate is filled in the groove
  • the floating gate is formed on the storage area.
  • a preparation method of an EEPROM device comprising:
  • the substrate includes a selection area and a storage area
  • a selection gate and a floating gate are formed, the selection gate is formed on the selection region and filled in the groove, and the floating gate is formed on the storage region.
  • FIG. 1 is a schematic top view of an EEPROM device in an embodiment
  • FIG. 2 is a schematic top view of an EEPROM device in another embodiment
  • Fig. 3 is a cross-sectional view of EEPROM device along A-A' section line in Fig. 2 in an embodiment
  • FIG. 4 is a schematic cross-sectional view of a selection area in an EEPROM device in an embodiment in a direction perpendicular to the connection between the selection area and the storage area;
  • FIG. 5 is a schematic flowchart of a method for fabricating an EEPROM device in an embodiment.
  • first doping type is the second doping type, and similarly, the second doping type can be the first doping type; the first doping type and the second doping type are different doping types, such as , the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances.
  • embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques.
  • an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds.
  • the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • a typical EEPROM device consists of the following parts: a substrate, including a select region and a storage region; a select gate, formed on the select region; a floating gate, formed on the storage region; and a control gate, formed on the floating gate.
  • the commonly used method to improve the cell current of EEPROM devices is to reduce the control gate on the floating gate. Size, reduce the distance between the control gate and the selection gate, adjust the injection concentration to reduce the resistance and threshold voltage of the cell in the EEPROM device, and then achieve the purpose of improving the cell current.
  • these methods can ultimately improve the cell current to a limited extent, and cannot greatly increase the cell current of the EEPROM device, and the reliability of the EEPROM device decreases and the leakage current increases while increasing the cell current.
  • FIG. 1 it is a schematic top view of an EEPROM device in an embodiment.
  • the present application provides an EEPROM device, including: a substrate 10 , a selection gate 204 and a floating gate 302 .
  • the substrate 10 includes a selection region 20 and a storage region 30, and the selection region 20 is provided with a groove 202; the substrate 10 can use undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI) , Silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).
  • SOI silicon-on-insulator
  • SSOI Silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • germanium-on-insulator germanium-on-insulator
  • a select gate 204 is formed on the select region 20 , and the select gate 204 fills the groove 202 .
  • the selection area 20 is provided with a groove 202
  • the selection gate 204 formed in the selection area 200 includes a portion located below the upper surface of the selection area 20 and filling the groove 202 , and located above the upper surface of the selection area 20 . , and another part whose lower surface is flush with the upper surface of the selection region 20 and partially in contact; the floating gate 302 is formed on the storage region 30 .
  • the substrate includes a selection area and a storage area, a groove is opened in the selection area, a selection gate is formed on the selection area and filled in the groove, and a floating gate is formed on the storage area, so that the sidewall of the groove is formed. and the bottom are part of the channel corresponding to the selection gate.
  • the selection gate is increased.
  • the effective width of the EEPROM reduces the resistance of the selection gate, thereby achieving the purpose of increasing the cell current of the memory cell formed by the selection gate of the selection region and the floating gate of the storage region in the EEPROM device.
  • the select gate 204 and the floating gate 302 are both polysilicon gates, and the select gate 204 and the floating gate 302 are formed in the same process step.
  • the width W1 of the selection area 20 is equal to the width W2 of the storage area 30 ; wherein the width W1 of the selection area 20 and the width W2 of the storage area 30 are in the same direction and perpendicular to the selection area 20 and the storage area 30 connection direction. In other embodiments, the width W1 of the selection region 20 is greater than the width W2 of the storage region 30.
  • the width W3 of the groove 202 opened in the selection region 20 can be increased, so as to further increase the effective width of the selection gate and reduce the selection gate.
  • the direction of the width W3 of the groove 202 is the same as the direction of the width W1 of the selection area 20 .
  • the distance D1 between the sidewall of the groove 202 and the edge of the selection area 20 is not less than 0.06 ⁇ m.
  • the value of the distance D1 can be set according to the actual process. Under the condition that the width W1 of the selection area 20 remains unchanged, the smaller the distance D1 is, the larger the width W3 of the groove 202 is, and the larger the width W3 of the groove 202 is. The longer the effective width of the selection gate 204 (the total length of the cross-section of the selection gate 204 in the direction along the width W3 of the groove 202 in contact with the groove 202 ) is, the greater the impact on the floating of the selection gate of the selection area and the storage area in the EEPROM device. The cell current of the memory cell formed by the gate increases more obviously.
  • the selection area 20 is symmetrical about the centerline of the groove 202 .
  • FIG. 2 it is a schematic top view of an EEPROM device in another embodiment.
  • the EEPROM device further includes: a control gate 304 formed on the floating gate 302 .
  • the distance D2 between the interface 40 of the selection area 20 and the storage area 30 and the end 304A of the control gate 304 close to the selection gate 204 is equal to the distance D3 between the interface 40 and the end 204A of the selection gate 204 close to the control gate 304.
  • the arrangement can avoid the influence of the groove 202 on the control gate 304 .
  • control gate 304 is a polysilicon gate.
  • the width W3 of the groove 202 is smaller than the length L1 of the groove 202 ; wherein the direction of the length L1 of the groove 202 is parallel to the direction of the connection between the selection area 20 and the storage area 30 . That is, the groove 202 is a longitudinal groove along the connecting line direction of the selection area 20 and the storage area 30 .
  • the EEPROM device further includes: a bit line contact hole 206 and a source line contact hole 306 .
  • the bit line contact hole 206 is formed in the selection region 20 on the side away from the floating gate 302 ; the projection of the selection gate 204 on the upper surface of the selection region 20 and the end of the groove 202 away from the floating gate 302 are all connected to the bit line contact hole 206 There is a certain distance between them.
  • the source line contact hole 306 is formed in the storage region 30 on the side away from the selection gate 204 ; the projection of the control gate 304 on the upper surface of the storage region 30 and the projection of the floating gate 302 on the upper surface of the storage region 30 are consistent with the source line contact hole 306 There is a certain distance between them; the connection direction of the source line contact hole 306 and the bit line contact hole 206 is parallel to the connection direction of the selection area 20 and the storage area 30 .
  • FIG. 3 it is a cross-sectional view of an EEPROM device in accordance with an embodiment taken along the section line A-A' in FIG. 2.
  • the EEPROM device further includes:
  • the selection isolation structure 208 is formed between adjacent selection regions 20, and the width W4 of the selection isolation structure 208 is not smaller than the critical dimension of the EEPROM device.
  • the direction of the width W4 of the selection isolation structure 208 is perpendicular to the direction of the connection between the selection area 20 and the storage area 30 .
  • the sum of the width W4 of the selection isolation structure 208 and the width W1 of the selection area 20 is equal to a predetermined value.
  • the preset value is a parameter related to the size of the EEPROM device.
  • the width W4 of the isolation structures 208 is selected to be less than or equal to the distance between adjacent storage regions 30 in the direction of the width W4.
  • the preset value is equal to the distance between the side edges of the adjacent storage areas 30 in the same direction along the connection direction of the selection area 20 and the storage area 30 in the connection direction.
  • the width W3 of the groove 202 and/or the depth D1 of the groove 202 is less than or equal to half of the width W1 of the selection region 20 .
  • the direction of the width W1 of the selection area 20 is the same as the direction of the width W3 of the groove 202 .
  • the groove 202 has a structure that is wide at the top and narrow at the bottom, such as an inverted trapezoid structure. With this arrangement, the problem of voids in the select gate 204 filled in the groove 202 can be avoided while increasing the depth of the groove 202 . In practical applications, the shape, depth D1 and width W3 of the groove 202 can be set according to process requirements.
  • the cross section of the groove 202 perpendicular to the connection direction of the selection area 20 and the storage area 30 is a square for illustration.
  • the width W1 of the selection area 20 2a
  • the distance between the sidewall of the groove 202 and the edge of the selection area is equal.
  • the effective width W0 of the select gate 204 is equal to the sum of the two sidewalls (depth D1) of the groove 202, the bottom of the groove (width a) and the width (2a-a) of the select region 20 without the groove 202.
  • the effective width of the select gate 204 is equal to 2 times before the improvement. Select the resistance of the gate It can be seen from this that when other parameters remain unchanged, the width W of the select gate is changed from 2a to 4a, and the resistance is reduced to half of the original value.
  • the resistance that affects the cell current of the entire EEPROM structure mainly comes from the resistance of the selection gate SG, the resistance of the control gate CG and the resistance of the tunnel injection (TIM), and the resistance of the selection gate SG in a typical EEPROM structure accounts for the total resistance.
  • the cell size of the EEPROM structure can be reduced by 35%.
  • the present application also provides an electronic device, including the EEPROM device described in any one of the above.
  • FIG. 5 it is a schematic flowchart of a method for fabricating an EEPROM device in an embodiment.
  • the present application also provides a preparation method of an EEPROM device for preparing the above-mentioned EEPROM device, the preparation method comprising:
  • a substrate 10 including a selection region 20 and a storage region 30 is provided, and the substrate 10 may employ undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI) ), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.
  • SOI silicon-on-insulator
  • SSOI stacked silicon-on-insulator
  • SiGeOI silicon germanium on insulator
  • SiGeOI silicon germanium on insulator
  • GeOI germanium on insulator
  • the width W1 of the selection area 20 is equal to the width W2 of the storage area 30 ; wherein the width W1 of the selection area 20 and the width W2 of the storage area 30 are in the same direction and perpendicular to the selection area 20 and the storage area 30 connection direction. In other embodiments, the width W1 of the selection area 20 is greater than the width W2 of the storage area 30 .
  • the width W3 of the groove 202 subsequently opened in the selection area 20 can be increased, so as to further increase the effective width of the selection gate, reduce the resistance of the selection gate, and increase the floating of the selection gate of the selection area and the storage area in the EEPROM device.
  • the direction of the width W3 of the groove 202 is the same as the direction of the width W1 of the selection area 20 .
  • the distance D1 between the sidewall of the groove 202 and the edge of the selection area 20 is not less than 0.06 ⁇ m.
  • the value of the distance D1 can be set according to the actual process. Under the condition that the width W1 of the selection area 20 remains unchanged, the smaller the distance D1 is, the larger the width W3 of the groove 20 is, and the smaller the distance D1 is, the larger the width W3 of the groove 20 is.
  • the longer the effective width of the select gate 204 (the total length of the cross section of the select gate 204 in the direction along the width W3 of the groove 20 in contact with the groove 202 ), the greater the impact on the floating of the select gate of the select area and the storage area in the EEPROM device.
  • the cell current of the memory cell formed by the gate increases more obviously.
  • the selection area 20 is symmetrical about the centerline of the groove 202 .
  • the width W3 of the groove 202 is smaller than the length L1 of the groove 204 ; wherein the direction of the length L1 of the groove 202 is parallel to the direction of the connection between the selection area 20 and the storage area 30 . That is, the groove 202 is a longitudinal groove along the connecting line direction of the selection area 20 and the storage area 30 .
  • the width W3 of the groove 202 and/or the depth D1 of the groove 202 is less than or equal to half of the width W1 of the selection region 20 .
  • the direction of the width W1 of the selection area 20 is the same as the direction of the width W3 of the groove 202 .
  • step S104 before step S104, it further includes:
  • a selection isolation structure 208 is formed, and adjacent selection regions 20 are separated by the selection isolation structure 208; wherein, the width W4 of the selection isolation structure 208 is not less than the critical dimension of the EEPROM device, and the direction of the width W4 of the selection isolation structure 208 is perpendicular to the selection region 20 and the connection direction of the storage area 30.
  • the sum of the width W4 of the selection isolation structure 208 and the width W1 of the selection region 20 is equal to a preset value.
  • the width W1 of the selection region 20 increases, the width W4 of the selection isolation structure 208 decreases, and the preset value is
  • the set value is a parameter related to the size of the EEPROM device.
  • the width W4 of the isolation structures 208 is selected to be less than or equal to the distance between adjacent storage regions 30 in the direction of the width W4.
  • the preset value is equal to the distance between the side edges of the adjacent storage areas 30 in the same direction along the connection direction of the selection area 20 and the storage area 30 in the connection direction.
  • S106 forming a selection gate and a floating gate, the selection gate is formed on the selection region and filled in the groove, and the floating gate is formed on the storage region.
  • the select gate 204 and the floating gate 302 of the polysilicon structure are formed by the same step.
  • the groove 202 has a structure that is wide at the top and narrow at the bottom, such as an inverted trapezoid structure. With this arrangement, the problem of voids in the select gate 204 filled in the groove 202 can be avoided while increasing the depth of the groove 202 . In practical applications, the shape, depth D1 and width W3 of the groove 202 can be set according to process requirements.
  • the step further includes: forming a control gate 304 on the floating gate 302, wherein the distance between the interface 40 of the selection region 20 and the storage region 30 and the end 304A of the control gate 304 close to the selection gate 204 D2 is equal to the distance D3 between the interface 40 and one end 204A of the select gate 204 close to the control gate 304 .
  • the step further includes: forming the bit line contact hole 206 and the source line contact hole 306 .
  • the bit line contact hole 206 is formed in the selection region 20 on the side away from the floating gate 302 ; the projection of the selection gate 204 on the upper surface of the selection region 20 and the end of the groove 202 away from the floating gate 302 are all connected to the bit line contact hole 206 There is a certain distance between them.
  • the source line contact hole 306 is formed in the storage region 30 on the side away from the selection gate 204 ; the projection of the control gate 304 on the upper surface of the storage region 30 and the projection of the floating gate 302 on the upper surface of the storage region 30 are consistent with the source line contact hole 306 There is a certain distance between them; the connection direction of the source line contact hole 306 and the bit line contact hole 206 is parallel to the connection direction of the selection area 20 and the storage area 30 .
  • the substrate includes a selection area and a storage area, a groove is formed in the selection area, and then a selection gate and a floating gate are formed, the selection gate is formed on the selection area and filled in the groove, and the floating gate is formed in the On the storage area, so that the sidewall and bottom of the groove are part of the channel corresponding to the selection gate.
  • the effective width of the selection gate is increased, and the resistance of the selection gate is reduced, so as to achieve the purpose of increasing the cell current of the memory cell formed by the selection gate of the selection region and the floating gate of the storage region in the EEPROM device.

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Abstract

本申请涉及一种EEPROM器件及其制备方法，该器件包括：衬底，衬底包括选择区和存储区，选择区开设有凹槽；选择栅，形成于选择区上，且选择栅填入所述凹槽中；浮栅，形成于存储区上。上述EEPROM器件中，衬底包括选择区和存储区，选择区中开设有凹槽，选择栅形成于选择区上且填入凹槽中，浮栅形成于存储区上，使得凹槽的侧壁和底部均为与选择栅对应的沟道的一部分，与选择栅直接形成在选择区的上表面相比，在选择栅投影在选择区上表面的投影面积不变的情况下，增加了选择栅的有效宽度，降低了选择栅的电阻，从而达到增加EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的目的。

Description

EEPROM器件及其制备方法
相关申请的交叉引用
本申请要求于2020年12月30日提交中国专利局、申请号为202011619620.5、发明名称为“EEPROM器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别是涉及一种EEPROM器件及其制备方法。
背景技术
随着半导体技术的发展，半导体器件的尺寸逐渐缩小，增加了晶圆单位面积上形成的器件的数目，减小了单个芯片的制造成本。对于典型结构的EEPROM器件(Electrically Erasable Programmable Read-Only Memory，带电可擦写可编程只读存储器)来说，随着单元面积的缩小，单元电流(Cell current)也越来越小，使得EEPROM器件中存储的0和1越来越难以区分，进而影响EEPROM器件尺寸的进一步微缩。
典型的EEPROM器件单元电流的改善方法是通过缩小控制栅(Control Gate)、缩小控制栅(Control Gate)与选择栅(Select gate)的间距、调整注入浓度等方法来减小EEPROM单元的电阻和阈值电压，进而改善单元电流，但是，这些改善方法对EEPROM器件的单元电流的调节幅度小，而且会存在器件可靠性下降、漏电流增加等问题。
发明内容
基于此，有必要针对上述问题提供一种EEPROM器件及其制备方法。
一种EEPROM器件，包括：
衬底，衬底包括选择区和存储区，选择区开设有凹槽；
选择栅，形成于选择区上，且选择栅填入所述凹槽中；
浮栅，形成于存储区上。
一种EEPROM器件的制备方法，包括：
提供衬底，衬底包括选择区和存储区；
在选择区中形成凹槽；
形成选择栅和浮栅，选择栅形成于选择区上且填入凹槽中，浮栅形成于存储区上。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中EEPROM器件的俯视示意图；
图2为另一实施例中EEPROM器件的俯视示意图；
图3为一实施例中EEPROM器件沿图2中A-A’剖面线的剖视图；
图4为一实施例中EEPROM器件中的选择区在垂直于选择区和存储区的连线方向的剖面示意图；
图5为一实施例中EEPROM器件的制备方法的流程示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的 实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
典型的EEPROM器件由以下部分组成：衬底，包括选择区和存储区；选择栅，形成于选择区上；浮栅，形成于存储区上；控制栅，形成于浮栅上。随着EEPROM器件单元面积的缩小，单元电流(cell current)越来越小，导致越来越难以区分0和1，常用的改善EEPROM器件的单元电流的方法是通过缩小浮栅上的控制栅的尺寸、缩小控制栅和选择栅之间的间距、调整注入浓度来减小EEPROM器件中单元的电阻和阈值电压，进而达到改善单元电流的目的。但是这些方法最终对单元电流的改善程度有限，不能大幅度的增加EEPROM器件的单元电流，并且在增加单元电流的同时会出现EEPROM器件的可靠性下降、漏电流增加等问题。
参见图1，为一实施例中EEPROM器件的俯视示意图。
如图1，针对上述问题，在其中一个实施例中，本申请提供一种EEPROM器件，包括：衬底10、选择栅204浮栅302。
衬底10包括选择区20和存储区30，选择区20开设有凹槽202；该衬底10可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底10的构成材料选用单晶硅。
选择栅204形成于选择区20上，且选择栅204填入所述凹槽202中。
具体地，选择区20中开设有凹槽202，形成于选择区200的选择栅204包括位于选择区20的上表面以下、且填满凹槽202的部分，以及位于选择区20的上表面以上、且下表面与选择区20的上表面齐平且部分接触的另一部分；浮栅302形成于存储区30上。
上述EEPROM器件中，衬底包括选择区和存储区，选择区中开设有凹槽，选择栅形成于选择区上且填入凹槽中，浮栅形成于存储区上，使得凹槽的侧壁和底部均为与选择栅对应的沟道的一部分，与选择栅直接形成在选择区的上表面相比，在选择栅投影在选择区上表面的投影面积不变的情况下，增加了选择栅的有效宽度，降低了选择栅的电阻，从而达到增加EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的目的。
在其中一个实施例中，选择栅204和浮栅302均为多晶硅栅，选择栅204和浮栅302 是在同一工艺步骤中形成的。
在其中一个实施例中，选择区20的宽度W1等于存储区30的宽度W2；其中，选择区20的宽度W1和存储区30的宽度W2的方向相同，且垂直于选择区20和存储区30的连线方向。在其他实施例中，选择区20的宽度W1大于存储区30的宽度W2，通过该设置可以增加选择区20中开设的凹槽202的宽度W3，达到进一步增加选择栅的有效宽度，降低选择栅的电阻，增加EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的目的。其中，凹槽202的宽度W3的方向与选择区20的宽度W1的方向相同。
在其中一个实施例中，在选择区20的宽度W1的方向上，凹槽202的侧壁与选择区20的边缘之间的距离D1不小于0.06微米。通过设置距离D1不小于0.06微米，可以避免形成凹槽的过程中，因工艺偏差导致凹槽202在选择区20的宽度W1的方向上超出选择区20的边缘的问题。
在其他实施例中，可以根据实际工艺制程设置距离D1的数值，在选择区20的宽度W1不变的情况下，距离D1越小，凹槽202的宽度W3越大，填入凹槽202的选择栅204的有效宽度(选择栅204在沿凹槽202的宽度W3的方向上的截面与凹槽202接触的总长度)越长，对EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的增加越明显。
在其中一个实施例中，选择区20关于凹槽202的中心线左右对称。
参见图2，为另一实施例中EEPROM器件的俯视示意图。
如图2，在其中一个实施例中，EEPROM器件还包括：控制栅304，形成于浮栅302上。
其中，选择区20和存储区30的分界面40与控制栅304靠近选择栅204一端304A之间的距离D2等于分界面40与选择栅204靠近控制栅304一端204A之间的距离D3，通过该设置可以避免凹槽202对控制栅304的影响。
在其中一个实施例中，控制栅304为多晶硅栅。
在其中一个实施例中，凹槽202的宽度W3小于凹槽202的长度L1；其中，凹槽202的长度L1的方向平行于选择区20和存储区30的连线方向。即凹槽202为沿选择区20和存储区30的连线方向的纵向凹槽。
在其中一个实施例中，EEPROM器件还包括：位线接触孔206和源线接触孔306。
其中，位线接触孔206形成于远离浮栅302一侧的选择区20中；选择栅204在选择区20上表面的投影，以及凹槽202远离浮栅302的一端均与位线接触孔206之间具有一 定的距离。源线接触孔306形成于远离选择栅204一侧的存储区30中；控制栅304在存储区30上表面的投影，以及浮栅302在存储区30上表面的投影均与源线接触孔306之间具有一定的距离；源线接触孔306和位线接触孔206的连线方向平行于选择区20和存储区30的连线方向。
参见图3，为一实施例中EEPROM器件沿图2中A-A’剖面线的剖视图。
如图3所示，在其中一个实施例中，EEPROM器件还包括：
选择隔离结构208，形成于相邻的选择区20之间，选择隔离结构208的宽度W4不小于EEPROM器件的关键尺寸。
其中，选择隔离结构208的宽度W4的方向垂直于选择区20和存储区30的连线方向。
在其中一个实施例中，选择隔离结构208的宽度W4和选择区20的宽度W1的和等于预设值，当选择区20的宽度W1增大时，选择隔离结构208的宽度W4减小。预设值是与EEPROM器件的尺寸相关的参数。
在其中一个实施例中，选择隔离结构208的宽度W4小于或等于相邻的存储区30之间在宽度W4的方向上的距离。
在其中一个实施例中，所述预设值等于选择区20和存储区30的连线方向上相邻的存储区30同一方向的沿连线方向的侧边之间的距离。
在其中一个实施例中，凹槽202的宽度W3和/或凹槽202的深度D1小于或等于选择区20的宽度W1的一半。
其中，选择区20的宽度W1的方向和凹槽202的宽度W3的方向相同。
在其中一个实施例中，在垂直于选择区20和存储区30的连线方向的剖面上，凹槽202为上宽下窄的结构，例如倒梯形结构。通过该设置可以在增加凹槽202的深度的同时，避免填入凹槽202中的选择栅204中出现空洞的问题。实际应用中，可以根据工艺需要设置凹槽202的形状、深度D1和宽度W3。
如图4，以凹槽202在垂直于选择区20和存储区30的连线方向的剖面上为正方形进行示例性说明，假设选择区20的宽度W1＝2a，凹槽202的剖面为深度D1＝宽度W3＝a的正方形，且凹槽202的侧壁与选择区的边缘之间的距离相等。本申请中，选择栅204的有效宽度W0等于凹槽202的两个侧壁(深度D1)、凹槽的底部(宽度a)和选择区20未开设凹槽202的宽度(2a-a)之和，即选择栅204的有效宽度W0＝2*a+a+(2a-a)＝4a，而直接在选择区20上形成的选择栅的宽度W＝W1＝2a，由此可知，本申请中选择栅204的有效宽度等于改进前的2倍。选择栅的电阻
Figure PCTCN2021120720-appb-000001
由此可知， 在其他参数不变的情况下，选择栅的宽度W从2a变为4a，电阻降低到原来的一半。对EEPROM整个结构的单元电流产生影响的电阻主要来源于选择栅SG的电阻，控制栅CG的电阻和隧穿注入(TIM)的电阻，并且，典型的EEPROM结构中选择栅SG的电阻占总电阻的70％，选择栅SG的电阻降低到原来的一半时，EEPROM结构的总电阻降低到原来的65％(1-70％*0.5)，这样，同样尺寸下本申请中新的EEPROM结构可以带来约50％(1/65％)的单元电流提升，或者在保持单元电流不变的情况下，EEPROM结构的单元尺寸可以缩小35％。
本申请还提供一种电子设备，包括上述任一项所述的EEPROM器件。
参见图5，为一实施例中EEPROM器件的制备方法的流程示意图。
如图1-图3、图5，本申请还提供一种EEPROM器件的制备方法，用于制备上述的EEPROM器件，该制备方法包括：
S102，提供衬底，衬底包括选择区和存储区。
提供包括选择区20和存储区30的衬底10，该衬底10可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底的构成材料选用单晶硅。
在其中一个实施例中，选择区20的宽度W1等于存储区30的宽度W2；其中，选择区20的宽度W1和存储区30的宽度W2的方向相同，且垂直于选择区20和存储区30的连线方向。在其他实施例中，选择区20的宽度W1大于存储区30的宽度W2。通过该设置可以增加后续在选择区20中开设的凹槽202的宽度W3，达到进一步增加选择栅的有效宽度，降低选择栅的电阻，增加EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的目的。其中，凹槽202的宽度W3的方向与选择区20的宽度W1的方向相同。
S104，在选择区中形成凹槽。
通过光刻、刻蚀工艺，在选择区中形成深度和宽度满足需求的凹槽。
在其中一个实施例中，在选择区20的宽度W1的方向上，凹槽202的侧壁与选择区20的边缘之间的距离D1不小于0.06微米。通过设置距离D1不小于0.06微米，可以避免形成凹槽的过程中，因工艺偏差导致凹槽202在选择区20的宽度W1的方向上超出选择区20的边缘的问题。
在其他实施例中，可以根据实际工艺制程设置距离D1的数值，在选择区20的宽度W1不变的情况下，距离D1越小，凹槽20的宽度W3越大，填入凹槽20的选择栅204 的有效宽度(选择栅204在沿凹槽20的宽度W3的方向上的截面与凹槽202接触的总长度)越长，对EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的增加越明显。
在其中一个实施例中，选择区20关于凹槽202的中心线左右对称。
在其中一个实施例中，凹槽202的宽度W3小于凹槽204的长度L1；其中，凹槽202的长度L1的方向平行于选择区20和存储区30的连线方向。即凹槽202为沿选择区20和存储区30的连线方向的纵向凹槽。
在其中一个实施例中，凹槽202的宽度W3和/或凹槽202的深度D1小于或等于选择区20的宽度W1的一半。其中，选择区20的宽度W1的方向和凹槽202的宽度W3的方向相同。
在其中一个实施例中，步骤S104之前还包括：
形成选择隔离结构208，相邻的选择区20被选择隔离结构208分隔；其中，选择隔离结构208的宽度W4不小于EEPROM器件的关键尺寸，选择隔离结构208的宽度W4的方向垂直于选择区20和存储区30的连线方向。
在其中一个实施例中，选择隔离结构208的宽度W4和选择区20的宽度W1的和等于预设值，当选择区20的宽度W1增大时，选择隔离结构208的宽度W4减小，预设值是与EEPROM器件的尺寸相关的参数。
在其中一个实施例中，选择隔离结构208的宽度W4小于或等于相邻的存储区30之间在宽度W4的方向上的距离。
在其中一个实施例中，所述预设值等于选择区20和存储区30的连线方向上相邻的存储区30同一方向的沿连线方向的侧边之间的距离。
S106，形成选择栅和浮栅，选择栅形成于选择区上且填入凹槽中，浮栅形成于存储区上。
在其中一个实施例中，通过同一步骤形成多晶硅结构的选择栅204和浮栅302。
在其中一个实施例中，在垂直于选择区20和存储区30的连线方向的剖面上，凹槽202为上宽下窄的结构，例如倒梯形结构。通过该设置可以在增加凹槽202的深度的同时，避免填入凹槽202中的选择栅204中出现空洞的问题。实际应用中，可以根据工艺需要设置凹槽202的形状、深度D1和宽度W3。
在其中一个实施例中，步骤S106之后还包括：在浮栅302上形成控制栅304，其中，选择区20和存储区30的分界面40与控制栅304靠近选择栅204一端304A之间的距离D2等于分界面40与选择栅204靠近控制栅304一端204A之间的距离D3，通过该设置可 以避免凹槽202对控制栅304的影响。
在其中一个实施例中，步骤S106之后还包括：形成位线接触孔206和源线接触孔306的步骤。其中，位线接触孔206形成于远离浮栅302一侧的选择区20中；选择栅204在选择区20上表面的投影，以及凹槽202远离浮栅302的一端均与位线接触孔206之间具有一定的距离。源线接触孔306形成于远离选择栅204一侧的存储区30中；控制栅304在存储区30上表面的投影，以及浮栅302在存储区30上表面的投影均与源线接触孔306之间具有一定的距离；源线接触孔306和位线接触孔206的连线方向平行于选择区20和存储区30的连线方向。
上述EEPROM器件的制备方法，衬底包括选择区和存储区，在选择区中形成凹槽，然后形成选择栅和浮栅，选择栅形成于选择区上且填入凹槽中，浮栅形成于存储区上，使得凹槽的侧壁和底部均为与选择栅对应的沟道的一部分，与选择栅直接形成在选择区的上表面相比，在选择栅投影在选择区上表面的投影面积不变的情况下，增加了选择栅的有效宽度，降低了选择栅的电阻，从而达到增加EEPROM器件中由选择区的选择栅和存储区的浮栅构成的存储单元的单元电流的目的。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种EEPROM器件，其特征在于，包括：
    衬底，所述衬底包括选择区和存储区，所述选择区开设有凹槽；
    选择栅，形成于所述选择区上，且所述选择栅填入所述凹槽中；
    浮栅，形成于所述存储区上。
  2. 根据权利要求1所述的EEPROM器件，其特征在于，所述选择区的宽度大于所述存储区的宽度；
    其中，所述选择区的宽度和所述存储区的宽度的方向相同，且垂直于所述选择区和所述存储区的连线方向。
  3. 根据权利要求2所述的EEPROM器件，其特征在于，在所述选择区的宽度的方向上，所述凹槽的侧壁与所述选择区的边缘之间的距离不小于0.06微米。
  4. 根据权利要求1所述的EEPROM器件，其特征在于，所述凹槽的宽度小于所述凹槽的长度；
    其中，所述凹槽的长度的方向平行于所述选择区和所述存储区的连线方向。
  5. 根据权利要求4所述的EEPROM器件，其特征在于，所述凹槽的宽度和/或所述凹槽的深度小于或等于所述选择区的宽度的一半；
    其中，所述选择区的宽度的方向和所述凹槽的宽度的方向相同。
  6. 根据权利要求1所述的EEPROM器件，其特征在于，所述选择区关于所述凹槽的中心线左右对称。
  7. 根据权利要求1所述的EEPROM器件，其特征在于，所述选择栅包括位于所述选择区的上表面以下、且填满所述凹槽的部分，以及位于所述选择区的上表面以上、且下表面与所述选择区的上表面齐平且部分接触的另一部分。
  8. 根据权利要求1所述的EEPROM器件，其特征在于，还包括：
    选择隔离结构，形成于相邻所述选择区之间，所述选择隔离结构的宽度不小于所述EEPROM器件的关键尺寸；
    其中，所述选择隔离结构的宽度的方向垂直于所述选择区和所述存储区的连线方向。
  9. 根据权利要求1所述的EEPROM器件，其特征在于，还包括：
    控制栅，形成于所述浮栅上；
    其中，所述选择区和所述存储区的分界面与所述控制栅靠近所述选择栅一端之间的距离等于所述分界面与所述选择栅靠近所述控制栅一端之间的距离。
  10. 根据权利要求1所述的EEPROM器件，还包括：位线接触孔和源线接触孔。
  11. 根据权利要求10所述的EEPROM器件，其中，
    所述位线接触孔形成于远离所述浮栅一侧的所述选择区中；所述选择栅在所述选择区上表面的投影，以及所述凹槽远离所述浮栅的一端均与所述位线接触孔之间间隔设置；且
    所述源线接触孔形成于远离所述选择栅一侧的所述存储区中；所述控制栅在所述存储区上表面的投影，以及所述浮栅在所述存储区上表面的投影均与所述源线接触孔之间间隔设置。
  12. 根据权利要求10所述的EEPROM器件，其中，所述源线接触孔和所述位线接触孔的连线方向平行于所述选择区和所述存储区的连线方向。
  13. 一种EEPROM器件的制备方法，其特征在于，包括：
    提供衬底，所述衬底包括选择区和存储区；
    在所述选择区中形成凹槽；
    形成选择栅和浮栅，所述选择栅形成于所述选择区上且填入所述凹槽中，所述浮栅形成于所述存储区上。
  14. 根据权利要求13所述的制备方法，其特征在于，所述在所述选择区中形成凹槽的步骤之前还包括：
    形成选择隔离结构，相邻的所述选择区被所述选择隔离结构分隔；
    其中，所述选择隔离结构的宽度不小于所述EEPROM器件的关键尺寸，所述选择隔离结构的宽度的方向垂直于所述选择区和所述存储区的连线方向。
  15. 根据权利要求13所述的制备方法，其特征在于，所述选择区的宽度大于所述存储区的宽度，所述选择区的宽度和所述存储区的宽度的方向相同，且垂直于所述选择区和所述存储区的连线方向。
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