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WO2022048136A1 - 带铁电或负电容材料的器件及其制造方法及电子设备 - Google Patents

带铁电或负电容材料的器件及其制造方法及电子设备 Download PDF

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WO2022048136A1
WO2022048136A1 PCT/CN2021/082732 CN2021082732W WO2022048136A1 WO 2022048136 A1 WO2022048136 A1 WO 2022048136A1 CN 2021082732 W CN2021082732 W CN 2021082732W WO 2022048136 A1 WO2022048136 A1 WO 2022048136A1
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layer
gate
nanowire
ferroelectric
sheet
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PCT/CN2021/082732
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English (en)
French (fr)
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朱慧珑
黄伟兴
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中国科学院微电子研究所
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Priority to US18/025,030 priority Critical patent/US20240030313A1/en
Publication of WO2022048136A1 publication Critical patent/WO2022048136A1/zh

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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to nanowire/sheet devices having ferroelectric or negative capacitance materials, methods of making the same, and electronic devices including such nanowire/sheet devices.
  • Nanowire or nanosheet (hereafter referred to as "nanowire/sheet”) devices, especially gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on nanowires/sheets, with well-controlled short channel channel effect and realize further scaling of the device.
  • GAA gate-all-around
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • the spacing between components is getting smaller and smaller, which makes the overlap capacitance between components increase in the total device capacitance. It is desirable to reduce these overlapping capacitances, especially between the gate and the underlying substrate below the nanowire/sheet.
  • an object of the present disclosure is, at least in part, to provide a nanowire/sheet device having a ferroelectric or negative capacitance material, a method for manufacturing the same, and an electronic device including such a nanowire/sheet device.
  • a nanowire/sheet device comprising: a substrate; a nanowire/sheet on the substrate spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/sheet; ferroelectric or negative capacitive material layers formed on the sidewalls of the nanowires; and source/drain layers located at opposite ends of the nanowires/sheets and in contact with the nanowires/sheets.
  • a method of fabricating a nanowire/sheet device comprising: disposing a nanowire/sheet spaced apart from a surface of the substrate on a substrate; forming a surrounding nanowire/sheet on the substrate forming a dummy gate on the sidewall of the dummy gate using a ferroelectric or negative capacitance material; and removing the dummy gate and forming a gate electrode in the gate trench formed by the removal of the dummy gate inside the spacer.
  • a method of fabricating a nanowire/sheet device comprising: disposing a nanowire/sheet spaced apart from a surface of the substrate on a substrate; forming a surrounding nanowire/sheet on the substrate A dummy gate of the chip; forming a spacer on the sidewall of the dummy gate; and removing the dummy gate, and forming a ferroelectric or negative capacitance material layer in the gate trench formed by the removal of the dummy gate inside the spacer; A gate electrode is formed in the gate trench of the layer of ferroelectric or negative capacitance material.
  • an electronic device including the above nanowire/sheet device.
  • a layer of ferroelectric or negative capacitance material is provided on the sidewall of the gate electrode.
  • This layer of ferroelectric or negative capacitive material may be in the form of spacers.
  • Device characteristics such as threshold voltage (Vt), leakage induced barrier lowering (DIBL), subthreshold swing (SS), etc. can be easily tuned by adjusting the material of the ferroelectric or negative capacitance material layer.
  • Figures 1 to 18(b) schematically illustrate some stages in the process of fabricating a nanowire/sheet device device according to an embodiment of the present disclosure
  • Figures 1, 3(a), 4(a), 5(b), 6, 7(a), 7(b), 8(a), 9(a), 9(b), 10, 11 (a), 12(a), 13(a), 14(a), 15(a), 16(a), 17(a), 18(a) are cross-sectional views along line AA',
  • Figures 3(b), 4(b), 8(b), 11(b), 12(b), 13(b), 14(b), 15(b), 16(b), 17(b) , 18(b) is a cross-sectional view along the BB' line
  • FIG. 2(a), 2(b), 5(a), and 9(c) are plan views, and FIG. 2(a) shows the positions of the AA' line and the BB' line.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element.
  • a layer/element when a layer/element is “on” another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under” the other layer/element.
  • a nanowire/sheet device may include one or more nanowires or nanosheets (referred to simply as “nanowires/sheets") to serve as channels.
  • the nanowires/sheets can be suspended relative to the substrate and can extend substantially parallel to the surface of the substrate.
  • the individual nanowires/sheets can be aligned in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate).
  • the nanowires/sheets may extend in a first direction, and opposite ends in the first direction may be connected to the source/drain layers.
  • the source/drain layers may comprise a different semiconductor material than the nanowires/sheets in order to enable stress engineering.
  • the gate electrode may intersect each nanowire/sheet in a second direction (eg, perpendicular) to the first direction, and thus may surround the perimeter of each nanowire/sheet, forming a gate all around (GAA) structure.
  • GAA gate all around
  • a ferroelectric or negative capacitance material layer may be disposed on the sidewall of the gate electrode.
  • Ferroelectric materials are generally in one of two polarization states, such as one of upward polarization or downward polarization. But under some special conditions (special matching of capacitance), ferroelectric materials can be stabilized between two polarization states, the so-called negative capacitance state.
  • the device can exhibit different properties such as threshold voltage (Vt), leakage induced barrier lowering (DIBL), subthreshold swing (SS), etc.
  • a negative capacitance can be introduced between the gate electrode and the source/drain, which can even result in the total capacitance between the gate and the source/drain being less than zero (which can result in less than zero at 300K 60mV/dec SS).
  • a decrease in the overall capacitance of the semiconductor device may be caused.
  • This layer of ferroelectric or negative capacitive material may be in the form of spacers.
  • a spacer may be a spacer formed on the dummy gate, so that a gate trench for forming a gate electrode is defined after the dummy gate is removed, and a gate dielectric layer and a gate electrode may be formed in the gate trench.
  • the layer of ferroelectric or negative capacitive material in the form of spacers may be the gate spacers of the device and may extend along substantially the entire height of the sidewalls of the gate electrode.
  • the so-called “substantially the entire height” or “the main part of the height” may refer to the remaining part of the height, except for the margin that needs to be considered due to process fluctuations or some residues in other steps occupying a small part of the height The height is occupied by the grid sidewalls.
  • this layer of ferroelectric or negative capacitive material may extend continuously on the sidewall and bottom surfaces of the gate electrode.
  • the material layer of ferroelectric or negative capacitance material can be formed in the gate trench defined after the dummy gate (the sidewalls including the ferroelectric or negative capacitance material can also be formed on the sidewall) are removed.
  • a ferroelectric or negative capacitance material layer may be formed between the gate dielectric layer and the gate electrode, or may be formed between the inner wall of the gate trench and the gate dielectric layer.
  • a potential equalization layer may be introduced to equalize the potential on the gate electrode surface.
  • a potential equalization layer may be disposed between the gate dielectric layer and the ferroelectric or negative capacitance material layer.
  • Nanowires/sheets can be provided on the substrate spaced from the surface of the substrate and dummy gates formed around the nanowires/sheets.
  • Dummy gate spacers may be formed on sidewalls of the dummy gate.
  • the dummy gate spacers may be in a single-layer or multi-layer configuration, wherein at least one layer may be a layer of ferroelectric or negative capacitance material.
  • the dummy gate may be removed to form gate trenches inside the dummy gate spacers.
  • a ferroelectric or negative capacitance material layer (which may be omitted in the case where the dummy gate spacer includes a ferroelectric or negative capacitance material layer) and a gate electrode may be formed.
  • a potential equalization layer may also be formed between the gate dielectric layer and the ferroelectric or negative capacitance material layer.
  • the present disclosure may be presented in various forms, some examples of which are described below.
  • the selection of various materials takes into account etch selectivity in addition to their function (eg, semiconductor material for forming active regions, dielectric material for forming electrical isolation).
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then such etching Can be selective, and the material layer can have etch selectivity relative to other layers exposed to the same etch recipe.
  • FIG. 1 to 18(b) schematically illustrate some stages in a flow of fabricating a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various forms of substrates including, but not limited to, bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is used as an example for description.
  • SOI semiconductor-on-insulator
  • compound semiconductor substrates such as SiGe substrates, and the like.
  • a bulk Si substrate is used as an example for description.
  • a silicon wafer is provided as the substrate 1001 .
  • an isolation portion defining layer 1003 may be formed for defining the positions of the isolation portions to be formed later.
  • an etch stop layer 1005 may be formed on the isolation portion defining layer 1003, on the isolation portion defining layer 1003, an etch stop layer 1005 may be formed.
  • the etch stop layer 1005 can set a stop position when etching the spacer-defining layer 1003 later, especially if there is no etch option between the spacer-defining layer 1003 and the gate-defining layer (eg, 1007) formed later In the case of low performance or etch selectivity.
  • the etch stop layer 1005 may be omitted when the etch selectivity is provided between the isolation portion defining layer 1003 and the gate defining layer formed later.
  • a stack of alternating gate defining layers 1007, 1011, 1015 and nanowire/sheet defining layers 1009, 1013 may be formed.
  • the gate-defining layers 1007, 1011, 1015 may define the positions of the gate stacks to be formed subsequently, and the nanowire/sheet-defining layers 1009, 1013 may define the positions of the nanowires/sheets to be formed subsequently.
  • the uppermost layer may be the gate defining layer 1015, such that each nanowire/sheet defining layer 1009, 1013 is covered above and below by the gate defining layer to subsequently form an all around gate configuration.
  • nanowire/sheet defining layers 1009, 1013 are formed, and thus two nanowires/sheets are formed in the final device.
  • the present disclosure is not limited thereto, and the number of nanowire/sheet defining layers to be formed and the gate defining layers to be formed may be determined according to the number of nanowires/sheets to be formed finally (which may be one or more). the number of layers.
  • Isolator defining layer 1003, etch stop layer 1005, and gate defining layers 1007, 1011, 1015 and nanowire/sheet defining layers 1009, 1013 may be semiconductor layers formed on substrate 1001 by, for example, epitaxial growth.
  • the nanowire/sheet defining layers 1009, 1013 may be of good crystal quality and may be of a single crystal structure to subsequently provide single crystal nanowires/sheets for use as channels. There may be etch selectivity between adjacent ones of these semiconductor layers so that they can be processed differently later.
  • the etch stop layer 1005 and nanowire/sheet defining layers 1009, 1013 may include Si
  • the spacer defining layer 1003 and gate defining layers 1007, 1011, 1015 may include SiGe (the atomic percentage of Ge is, for example, about 10 to 40%, and can be gradually changed to reduce defects).
  • Each semiconductor layer may have a substantially uniform thickness, extending generally parallel to the surface of the substrate 1001 .
  • the thickness of the spacer defining layer 1003 may be about 30 nm to 80 nm
  • the thickness of the etch stop layer 1005 may be about 3 nm to 15 nm
  • the thickness of the gate defining layers 1007, 1011 and 1015 may be about 20 nm to 40 nm
  • the thickness of the nanowire/ The thickness of the sheet-defining layers 1009, 1013 may be about 5 nm to 15 nm.
  • the nanowires/sheets can be patterned.
  • a mask such as photoresist 1017a or 1017b may be formed on the above stack, and the photoresist 1017a or 1017b may be patterned into nanowires by photolithography ( Figure 2( a)) or nanosheets (Fig. 2(b)).
  • the width W of the nanosheets can determine the device width at which the device provides current.
  • the case of nanowires is mainly exemplified, but the descriptions are equally applicable to the case of nanosheets.
  • the photoresist 1017a or 1017b can be used as a mask to selectively etch each layer on the substrate 1001 in turn by, for example, reactive ion etching (RIE), Etching can be stopped at substrate 1001 .
  • RIE reactive ion etching
  • the layers on the substrate 1001 are patterned into preliminary nanowires or nanosheets corresponding to the photoresist 1017a or 1017b.
  • the length of the prepared nanowires/sheets (longitudinal dimension, that is, the length in the horizontal direction in the orientation of Figure 3(a)) can be smaller than the length of the nanowires/sheets that need to be formed to serve as channels, which This is to subsequently get nanowires/sheets self-aligned with dummy gates (gate stacks) for use as channels.
  • the photoresist 1017a or 1017b may be removed.
  • isolations 1019 such as shallow trench isolation (STI) may be formed on the substrate 1001 .
  • the STI 1019 can be performed by depositing an oxide (eg, silicon oxide) on a substrate, subjecting the deposited oxide to a planarization process such as chemical mechanical polishing (CMP), and applying the planarized oxide to the planarized oxide, such as by wet It is formed by etching back by etching or vapor phase or dry etching.
  • CMP chemical mechanical polishing
  • a thin etch stop layer 1019' (eg, about 1 nm to 5 nm thick) may be formed on the surface of the semiconductor layer patterned in nanowire/sheet form on substrate 1001, eg, by deposition.
  • the etch stop layer 1019' may also include oxide, and is thus shown as a thin layer integral with the STI 1019.
  • the gate-defining layers 1007, 1011, and 1015 are located on the upper and lower sides of the nanowire/sheet-defining layers 1009 and 1013.
  • a gate defining layer 1021 may be formed on the STI 1019 and the etch stop layer 1019'.
  • gate-defining layer 1021 may be formed by depositing substantially the same or similar material (and thus having substantially the same or similar etch selectivity for processing together) as previous gate-defining layers 1007, 1011, 1015, and The resulting material is formed by planarization such as CMP.
  • the gate-defining layer 1021 may comprise SiGe having substantially the same or similar atomic percentage of Ge as the gate-defining layers 1007 , 1011 , 1015 .
  • a hard mask layer 1023 may be formed, for example, by deposition, to facilitate patterning.
  • the hard mask layer 1023 may include nitride (eg, silicon nitride).
  • the gate-defining layers 1007, 1011, 1015, 1021 may be patterned in a direction that intersects, eg, vertical (eg, the horizontal direction in FIGS. , the vertical direction in Fig. 5(a), the dummy gate extending in the direction perpendicular to the paper in Fig. 5(b)).
  • a photoresist 1025 may be formed on the hard mask layer 1023, and the photoresist 1025 may be patterned into stripes extending in this direction by photolithography. Then, the photoresist 1025 can be used as a mask to selectively etch the layers between the STIs 1019 on the substrate 1001 by, for example, RIE, and the etching can be stopped at the substrate 1001 .
  • the nanowire/sheet defining layers 1009, 1013 are formed into nanowires or nanosheets that can then be used to provide channels (in the following, the nanowire/sheet defining layers 1009, 1013 are referred to as nanowires/sheets 1009, 1013) , and are surrounded by gate defining layers 1007, 1011, 1015, 1021 (which may be collectively referred to as "dummy gates").
  • the nanowires/sheets 1009, 1013 can be self-aligned to the dummy gates. Afterwards, the photoresist 1025 can be removed.
  • the surfaces of the substrate 1001 are exposed, and these exposed surfaces can be helpful for the subsequent growth of the source/drain layers.
  • the STI 1019 may be in contact with the isolation portion defining layer 1003, and may be self-aligned to the dummy gate while extension (see Figure 8(b)).
  • spacers may be formed on the sidewalls of the dummy gate.
  • a self-alignment technique can be used to form the sidewalls. For example, as shown in FIG.
  • gate defining layers 1007, 1011, 1015, 1021 may be selectively etched relative to nanowires/sheets 1009, 1013 (in this example, Si), The sidewalls are recessed inward to a certain depth, eg, about 3 nm to 25 nm, relative to the sidewalls of the hardmask layer 1023 or the sidewalls of the nanowires/sheets 1009, 1013.
  • the respective concave depths of the gate defining layers 1007 , 1011 , 1015 and 1021 are substantially the same, and the concave depths on the left and right sides are substantially the same.
  • atomic layer etching ALE
  • the spacer-defining layer 1003 is also SiGe, and thus can also be recessed to substantially the same depth. Accordingly, the corresponding sidewalls of the gate defining layers 1007 , 1011 , 1015 , 1021 (and the isolation portion defining layer 1003 ) after etching can be substantially coplanar.
  • a ferroelectric material or a negative capacitance material may be used to form the spacers.
  • Ferroelectric materials are generally in one of two polarization states, such as one of upward polarization or downward polarization. But under some special conditions (special matching of capacitance), ferroelectric materials can be stabilized between two polarization states, the so-called negative capacitance state.
  • Ferroelectric materials include, for example, Hf oxides such as HfZrO containing Zr, Si and/or Al.
  • a layer 1027 of a ferroelectric or negative capacitance material of a certain thickness may be formed on the substrate 1001 by, for example, deposition.
  • the thickness of the deposited ferroelectric or negative capacitive material layer 1027 is sufficient to fill the aforementioned recess, eg, about 3 nm to 30 nm.
  • a dielectric layer 1029 may be formed in a substantially conformal manner.
  • the dielectric layer 1029 may include an oxide or a high-k dielectric such as HfO 2 .
  • the laterally extending portion of the dielectric material layer 1027 may be removed by, for example, vertical RIE, leaving its vertically extending portion (including the underside of the hard mask layer 1023 ) part), thereby forming sidewalls 1027.
  • the sidewalls of the spacers 1027 may be substantially coplanar with the sidewalls of the hard mask layer 1023 (and the sidewalls of the nanowires/sheets 1009, 1013).
  • FIG. 9( a ) shows an example of forming a side wall in the situation shown in FIG. 7( b ).
  • a dielectric layer 1029 is interposed between the spacers 1027 of ferroelectric or negative capacitance material and the dummy gate. Through material selection and thickness setting of the dielectric layer 1029, the total capacitance between the gate and the source-drain can be adjusted.
  • the dielectric layer 1029 is also called the spacer of the dummy gate.
  • the dielectric layer 1029 may be replaced with a layer of ferroelectric or negative capacitance material, and the spacers 1027 may be replaced with conventional dielectric spacers.
  • the spacers may be formed in a multi-layer configuration, where one or several layers are ferroelectric or negative capacitive materials and the remaining layers are conventional dielectric materials.
  • FIG. 9( b ) shows an example in which a potential equalization layer 1031 is further formed between the spacer 1027 and the dielectric layer 1029 .
  • the potential equalization layer 1031 can make the potential substantially evenly distributed on the surface of the spacer 1027 .
  • the potential equalization layer 1031 may include a conductive layer such as a metal or alloy, and the metal or alloy may contain at least one of the elements Ti, Ru, Co, and Ta, such as TiN, Co, Ru, TaN, etc., with a thickness of about 0.5 nm to 2nm.
  • Potential equalization layers may also be used in the case of other spacer configurations described in connection with Figure 9(a).
  • the extension direction of the dummy gate (for example, the vertical direction in FIG. 9( c ) ) to cut off the dummy gate to avoid a source-drain short circuit that may be caused by the presence of the conductive layer as shown by the dotted line in FIG. 9( c ).
  • the sidewalls of each nanowire/sheet are exposed to the outside (and may be substantially coplanar with the sidewalls of the hardmask layer).
  • the sidewalls of the exposed nanowires/sheets and the exposed surface of the substrate 1001 may be seeded to form the source/drain layer 1033, eg, by selective epitaxial growth.
  • the source/drain layer 1033 may be formed to meet the exposed sidewalls of all nanowires/sheets.
  • the source/drain layer 1033 may include various suitable semiconductor materials. To enhance device performance, the source/drain layer 1033 may contain a semiconductor material with a different lattice constant than the nanowires/sheets to apply stress to the nanowires/sheets in which the channel regions will be formed. For example, for an n-type device, the source/drain layer 1033 may include Si:C (C atomic percentage is, for example, about 0.1 to 3%) to apply tensile stress; for a p-type device, the source/drain layer 1033 may include SiGe ( The atomic percentage of Ge is, for example, about 20 to 80%) to apply compressive stress.
  • the source/drain layer 1033 may be doped to a desired conductivity type (n-type doping for n-type devices, p-type doping for p-type devices), eg, by in-situ doping or ion implantation.
  • the source/drain layers grown from the sidewalls of the nanowires/sheets meet the source/drain layers grown from the surface of the substrate 1001 . This helps dissipate heat or enhance stress in the channel, which in turn improves device performance. Additionally, in other embodiments of the present disclosure, the source/drain layers grown from the sidewalls of the nanowires/sheets and the source/drain layers grown from the surface of the substrate 1001 are spaced apart from each other.
  • a replacement gate process may be performed.
  • an interlayer dielectric layer 1035 may be formed on the substrate 1001 .
  • the interlayer dielectric layer 1035 may be formed by depositing an oxide, performing a planarization process such as CMP on the deposited oxide, and etch back the planarized oxide.
  • the interlayer dielectric layer 1035 may expose the hard mask layer 1023 but cover the source/drain layer 1033 . Afterwards, the hard mask layer 1023 may be removed by selective etching to expose the gate defining layer 1021 .
  • the dummy gate that is, all gate defining layers, should be removed and replaced with a gate stack.
  • the isolation portion defining layer 1003 may be processed first, and specifically, the isolation portion may be replaced. To this end, a processing channel to the spacer-defining layer 1003 may be formed.
  • the height of the gate defining layer 1021 can be reduced so that the top surface is lower than the top surface of the spacer defining layer 1003, but still maintains a certain thickness so that the mask layer (see FIG. 12 (see FIG. 12 ( 1037) in a) and 12(b) can shield all gate defining layers 1007, 1011, 1015 above the top surface of the spacer-defining layer 1003, while exposing the spacer-defining layer 1003.
  • ALE can be used for fine control of etch depth.
  • other gate defining layers 1007, 1011, 1015 may not be affected due to the presence of the etch stop layer 1019'.
  • a mask layer such as a photoresist 1037 may be formed on the gate defining layer 1021 .
  • the photoresist 1037 can be patterned into a strip shape extending along the extending direction of the nanowires/sheets by photolithography, and can shield the nanowires/sheets and the outer surfaces of the gate defining layers 1007, 1011, 1015 (with sandwiched between them). etch stop layer 1019'). Due to the existence of the gate defining layer 1021 , a part of the surface of the isolation portion defining layer 1003 is not shielded by the photoresist 1037 .
  • the gate defining layer 1021 may be sequentially removed, the portion of the etch stop layer 1019 ′ exposed due to the removal of the gate defining layer 1021 may be removed, and the portion of the etch stop layer 1019 ′ exposed due to the removal of the portion of the etch stop layer 1019 ′ may be removed.
  • the exposed isolation portion defines the layer 1003 .
  • voids are formed under the etch stop layer 1005 . Since the isolation portion defining layer 1003 and the above nanowires/sheets and gate defining layers are defined by the same hard mask layer, the isolation portion defining layer 1003 and the respective nanowires/sheets and gate defining layers above are in the vertical direction. and thus the voids due to the removal of the spacer-defining layer 1003 can be self-aligned to the respective nanowire/sheet, gate-defining layer above. Afterwards, the photoresist 1037 can be removed.
  • the etch stop layer 1005 is also a semiconductor material and is connected between opposing source/drain layers, which can result in leakage paths.
  • the etch stop layer 1005 can be cut between the opposing source/drain layers by selective etching, such as wet etching using a TMAH solution.
  • the ends of the etch stop layer 1005 may be left so as not to affect the source/drain layers on both sides.
  • the remaining end of the etch stop layer 1005 may not protrude to the inside of the spacer to avoid contact with the gate defining layer (which is subsequently replaced with a gate stack) inside the spacer.
  • the inner sidewalls of the remaining etch stop layer 1005 may be recessed with respect to the inner sidewalls of the spacers. Since the etching starts from the middle, the opposite ends of the etch stop layer 1005 that are left may be substantially symmetrical. Additionally, in this example, both the etch stop layer 1005 and the substrate 1001 include silicon, so that the substrate 1001 may also be partially etched away. Thus, the gap between the lowermost gate-defining layer 1007 and the substrate 1001 can be increased, while still maintaining substantial alignment with the respective nanowires/sheets and gate-defining layers above.
  • the voids thus formed may be filled with a dielectric material, such as a low-k dielectric material, to form spacers 1039 .
  • the material of the isolation portion 1039 may have etch selectivity relative to the STI 1019, such as oxynitride (eg, silicon oxynitride).
  • oxynitride eg, silicon oxynitride
  • isolation 1039 may be formed by depositing sufficient oxynitride on substrate 1001 and etch back the oxynitride as deposited by RIE.
  • the isolations 1039 thus formed can be self-aligned to the respective nanowires/sheets, gate defining layers above.
  • the isolation portion 1039 ′ when the dielectric material is deposited, the isolation portion 1039 ′ may form a hollow structure due to the limited space of the above-mentioned voids. In this case, the dielectric constant of the isolation portion 1039' can be further reduced.
  • the thin etch stop layer 1019' can be removed by selective etching to expose the gate defining layer, and further by selective etching, the gate can be removed limit layer.
  • gate trenches (corresponding to the space originally occupied by each gate definition layer) are formed on the inner side of the sidewall spacer 1027, above the STI 1019 and the isolation portion 1039.
  • a gate dielectric layer 1041 and a gate electrode 1043 may be formed in sequence to obtain a final gate stack.
  • the gate dielectric layer 1041 may include a high-k gate dielectric such as HfO2 with a thickness of about 2 nm-10 nm; the gate electrode 1043 may include a work function adjustment layer such as TiN, TiAlN, TaN, etc., and a gate conductor layer such as W, Co, Ru, etc.
  • an interfacial layer may also be formed, eg, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.3 nm-2 nm.
  • ALD atomic layer deposition
  • nanowire/sheet devices may include nanowires/sheets 1009, 1013 (which may be fewer or greater in number) spaced apart from substrate 1001 and surrounding Gate electrode 1043 of nanowires/sheets 1009, 1013.
  • the gate electrode 1043 is opposite to the nanowires/sheets 1009 and 1013 via the gate dielectric layer 1041 .
  • Spacers 1027 formed of ferroelectric or negative capacitance materials are formed on the sidewalls of the gate electrodes 1043 (may be referred to as "gate spacers"). As mentioned above, ferroelectric or negative capacitive materials can switch between two polarization states or be in a negative capacitive state.
  • the device can exhibit different properties such as threshold voltage (Vt), leakage induced barrier lowering (DIBL), subthreshold swing (SS), etc.
  • Vt threshold voltage
  • DIBL leakage induced barrier lowering
  • SS subthreshold swing
  • the capacitance value between the gate electrode 1043 and the source/drain layer may be less than zero.
  • nanowire/sheet devices can be used in both memory devices and logic devices.
  • the nanowire/sheet device may also include isolation 1039 .
  • the spacers 1039 can be self-aligned to the nanowires/sheets 1009, 1013 or to the gate electrodes.
  • Spacers 1027 of ferroelectric or negative capacitance material may also be formed on the sidewalls of the isolation portion 1039 . Thus, the capacitance between the gate electrode 1043 and the substrate 1001 can be reduced.
  • the inner sidewalls of the sidewalls 1027 may be substantially coplanar in the vertical direction, thereby providing the same grid length.
  • the outer sidewalls of the gate spacers 1027 may also be coplanar in the vertical direction, and may be coplanar with the sidewalls of the nanowires/sheets 1009 and 1013 .
  • a ferroelectric or negative capacitance material layer 1045 may also be inserted to adjust the capacitance value and device performance.
  • the ferroelectric or negative capacitance material layer 1045 may include HfZrO with a thickness of about 2 nm to 15 nm.
  • the ferroelectric or negative capacitance material layer 1045 can be formed first, and then the gate dielectric layer 1041 and the gate electrode 1043 are formed, so that the gate dielectric layer 1041 is interposed between the ferroelectric or negative capacitance material layer 1045 and the gate electrode 1043 .
  • the spacers 1027 are not limited to using ferroelectric materials or negative capacitance materials, and conventional dielectric materials such as nitride can also be used.
  • a potential equalization layer 1047 may be formed on the surface of the ferroelectric or negative capacitance material layer 1045 to equalize the potential.
  • the potential equalization layer 1047 is interposed between the gate dielectric layer 1041 and the ferroelectric or negative capacitance material layer 1045 .
  • the potential equalization layer 1047 may include a conductive layer such as a metal or alloy, and the metal or alloy may contain at least one of the elements Ti, Ru, Co, and Ta, such as TiN, Co, Ru, TaN, etc., with a thickness of about 0.5 nm to 2nm.
  • the potential equalization layer 1047 may be interposed between the ferroelectric or negative capacitive material layer 1045 and the gate dielectric layer 1041 .
  • Nanowire/sheet devices may be applied to various electronic devices.
  • integrated circuits ICs
  • electronic devices constructed therefrom ICs
  • the present disclosure also provides an electronic device including the above nanowire/sheet device.
  • the electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, power banks, and the like.
  • a method of fabricating a system on a chip is also provided.
  • the method may include the methods described above.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

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Abstract

公开了一种具有铁电或负电容材料的纳米线/片器件及其制造方法及包括这种纳米线/片器件的电子设备。根据实施例，半导体器件可以包括：衬底；衬底上与衬底的表面间隔开的纳米线/片；围绕纳米线/片的栅电极；在栅电极的侧壁上形成的铁电或负电容材料层；以及位于纳米线/片的相对两端且与纳米线/片相接的源/漏层。

Description

带铁电或负电容材料的器件及其制造方法及电子设备
相关申请的引用
本申请要求于2020年9月7日递交的题为“带铁电或负电容材料的器件及其制造方法及电子设备”的中国专利申请202010932029.9的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有铁电或负电容材料的纳米线/片器件及其制造方法及包括这种纳米线/片器件的电子设备。
背景技术
纳米线或纳米片(以下简称为“纳米线/片”)器件，特别是基于纳米线/片的全环绕栅(GAA)金属氧化物半导体场效应晶体管(MOSFET)，能很好地控制短沟道效应，并实现器件的进一步微缩。然而，随着不断小型化，部件间的间隔越来越小，这使得各部件之间的交迭电容在器件总电容中的占比增加。希望降低这些交迭电容，特别是纳米线/片之下的栅与底部衬底之间的电容。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有铁电或负电容材料的纳米线/片器件及其制造方法及包括这种纳米线/片器件的电子设备。
根据本公开的一个方面，提供了一种纳米线/片器件，包括：衬底；衬底上与衬底的表面间隔开的纳米线/片；围绕纳米线/片的栅电极；在栅电极的侧壁上形成的铁电或负电容材料层；以及位于纳米线/片的相对两端且与纳米线/片相接的源/漏层。
根据本公开的另一方面，提供了一种制造纳米线/片器件的方法，包括：在衬底上设置与衬底的表面间隔开的纳米线/片；在衬底上形成围绕纳米线/片的伪栅；在伪栅的侧壁上利用铁电或负电容材料形成侧墙；以及去除伪栅，并在侧墙内侧由于伪栅的去除而形成的栅槽中形成栅电极。
根据本公开的另一方面，提供了一种制造纳米线/片器件的方法，包括：在衬底上设置与衬底的表面间隔开的纳米线/片；在衬底上形成围绕纳米线/片的伪栅；在伪栅的侧壁上形成侧墙；以及去除伪栅，并在侧墙内侧由于伪栅的去除而形成的栅槽中形成铁电或负电容材料层；以及在形成有铁电或负电容材料层的栅槽中形成栅电极。
根据本公开的另一方面，提供了一种电子设备，包括上述纳米线/片器件。
根据本公开的实施例，在栅电极的侧壁上设置有铁电或负电容材料层。这种铁电或负电容材料层可以呈侧墙形式。通过调节铁电或负电容材料层的材料，可以容易地调节器件特性，如阈值电压(Vt)、漏致势垒降低(DIBL)、亚阈值摆幅(SS)等。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至18(b)示意性示出了根据本公开实施例的制造纳米线/片器件器件的流程中的一些阶段，
其中，图1、3(a)、4(a)、5(b)、6、7(a)、7(b)、8(a)、9(a)、9(b)、10、11(a)、12(a)、13(a)、14(a)、15(a)、16(a)、17(a)、18(a)是沿AA′线的截面图，
图3(b)、4(b)、8(b)、11(b)、12(b)、13(b)、14(b)、15(b)、16(b)、17(b)、18(b)是沿BB′线的截面图，
图2(a)、2(b)、5(a)、9(c)是俯视图，图2(a)中示出了AA′线和BB′线的位置。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些 细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种纳米线/片器件。具体地，器件可以包括一个或多个纳米线或纳米片(简称为“纳米线/片”)，以用作沟道。纳米线/片可以相对于衬底悬空，且可以实质上平行于衬底的表面延伸。各纳米线/片在竖直方向(例如，实质上垂直于衬底表面的方向)上可以对准。纳米线/片可以在第一方向上延伸，且在第一方向上的相对两端可以连接到源/漏层。源/漏层可以包括与纳米线/片不同的半导体材料，以便实现应力工程。另外，栅电极可以沿与第一方向相交(例如，垂直)的第二方向与各纳米线/片相交，并因此可以围绕各纳米线/片的外周，从而形成全环绕栅(GAA)结构。
根据本公开的实施例，在栅电极的侧壁上可以设置有铁电或负电容材料层。铁电材料一般处在两种极化状态中的一种，例如向上极化或向下极化之中的一种。但在一些特殊条件下(电容的特殊匹配)，铁电材料可以稳定在两种极化状态之间，即所谓的负电容状态。根据铁电或负电容材料所处的状态不同，器件可以表现出不同的性能，例如阈值电压(Vt)、漏致势垒降低(DIBL)、亚阈值摆幅(SS)等。在铁电或负电容材料处于负电容状态时，可以在栅电极与源/漏之间可以引入负电容，甚至可以导致栅与源/漏之间的总电容小于零(可以导致在300K下小于60mV/dec的SS)。于是，可以导致半导体器件的总体电容的下降。
这种铁电或负电容材料层可以呈侧墙的形式。例如，这种侧墙可以是在伪栅上形成的侧墙，从而在去除伪栅之后限定了用于形成栅电极的栅槽，在栅槽中可以形成栅介质层以及栅电极。
也即，侧墙形式的铁电或负电容材料层可以是器件的栅侧墙，并且可以沿 着栅电极的侧壁的实质上整个高度延伸。在本文中，所谓“实质上整个高度”或者“高度的主要部分”，可以是指除了由于工艺波动而需要考虑的余量或者其他步骤中的一些残留占据一小部分高度之外，其余部分的高度均被栅侧墙占据。
或者，这种铁电或负电容材料层可以在栅电极的侧壁和底面上连续延伸。这种情况下，铁电或负电容材料材料层可以形成在伪栅(侧壁上也可以形成包括铁电或负电容材料的侧墙)去除之后所限定的栅槽中。例如，铁电或负电容材料层可以形成在栅介质层与栅电极之间，或者可以形成在栅槽的内壁与栅介质层之间。
另外，可以引入电势均衡层，以均衡栅电极表面上的电势。例如，电势均衡层可以设置在栅介质层与铁电或负电容材料层之间。
这种半导体器件例如可以如下制造。可以在衬底上设置与衬底的表面间隔开的纳米线/片，并形成围绕纳米线/片的伪栅。可以在伪栅的侧壁上形成伪栅侧墙。伪栅侧墙可以是单层或多层配置，其中至少一层可以是铁电或负电容材料层。可以去除伪栅，从而在伪栅侧墙内侧形成栅槽。在栅槽中，可以形成铁电或负电容材料层(在伪栅侧墙包括铁电或负电容材料层的情况下，可以省略)以及栅电极。另外，在栅槽中，还可以在栅介质层与铁电或负电容材料层之间形成电势均衡层。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至18(b)示意性示出了根据本公开实施例的制造半导体器件的流程中的一些阶段。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合 物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001上，可以形成隔离部限定层1003，用于限定随后将要形成的隔离部的位置。在隔离部限定层1003上，可以形成刻蚀停止层1005。刻蚀停止层1005可以在随后对隔离部限定层1003进行刻蚀时设定停止位置，特别是在隔离部限定层1003与之后形成的栅限定层(例如，1007)之间不具备刻蚀选择性或刻蚀选择性较低的情况下。或者，在隔离部限定层1003与之后形成的栅限定层之间具备刻蚀选择性的情况下，可以省略刻蚀停止层1005。
在刻蚀停止层1005上，可以形成栅限定层1007、1011、1015和纳米线/片限定层1009、1013交替设置的堆叠。栅限定层1007、1011、1015可以限定随后将要形成的栅堆叠的位置，纳米线/片限定层1009、1013可以限定随后将要形成的纳米线/片的位置。在该堆叠中，最上层可以是栅限定层1015，从而各纳米线/片限定层1009、1013在上下方均被栅限定层覆盖，以便随后形成全围绕栅配置。在该示例中，形成了两个纳米线/片限定层1009、1013，并因此在最终的器件中形成两个纳米线/片。但是，本公开不限于此，可以根据最终要形成的纳米线/片的数目(可以为一个或多个)，确定要形成的纳米线/片限定层的数目以及相应地确定要形成的栅限定层的数目。
隔离部限定层1003、刻蚀停止层1005以及栅限定层1007、1011、1015和纳米线/片限定层1009、1013可以是通过例如外延生长而在衬底1001上形成的半导体层。于是，纳米线/片限定层1009、1013可以具有良好的晶体质量，并可以是单晶结构，以便随后提供单晶的纳米线/片以用作沟道。这些半导体层之中相邻的半导体层之间可以具有刻蚀选择性，以便随后能够被不同地处理。例如，刻蚀停止层1005以及纳米线/片限定层1009、1013可以包括Si，而隔离部限定层1003以及栅限定层1007、1011、1015可以包括SiGe(Ge的原子百分比例如为约10％至40％，且可以逐渐变化以降低缺陷)。各半导体层可以具有实质上均匀的厚度，从而与衬底1001的表面大致平行延伸。例如，隔离部限定层1003的厚度可以为约30nm至80nm，刻蚀停止层1005的厚度可以为约3nm至15nm，栅限定层1007、1011、1015的厚度可以为约20nm至40nm，纳米线/片限定层1009、1013的厚度可以为约5nm至15nm。
接下来，可以构图纳米线/片。例如，如图2(a)和2(b)所示，可以在上述堆叠上形成掩模如光刻胶1017a或1017b，通过光刻将光刻胶1017a或1017b构图为纳米线(图2(a))或纳米片(图2(b))的形式。在纳米片的情况下，纳米片的宽度W可以确定器件提供电流的器件宽度。在以下描述中，主要以纳米线的情形为例，但是这些描述同样适用于纳米片的情形。然后，如图3(a)和3(b)所示，可以光刻胶1017a或1017b为掩模，通过例如反应离子刻蚀(RIE)，依次选择性刻蚀衬底1001上的各层，刻蚀可以停止于衬底1001。这样，衬底1001上的各层被构图为与光刻胶1017a或1017b相应的预备纳米线或纳米片。在此，预备纳米线/片的长度(纵向尺度，也即，在图3(a)的取向下水平方向上的长度)可以小于需要形成的用作沟道的纳米线/片的长度，这是为了随后得到与伪栅(栅堆叠)自对准的纳米线/片以用作沟道。之后，可以去除光刻胶1017a或1017b。
为电隔离的目的，如图4(a)和4(b)所示，可以在衬底1001上形成隔离部1019，例如浅沟槽隔离(STI)。例如，STI 1019可以通过在衬底上淀积氧化物(例如，氧化硅)，对淀积的氧化物进行平坦化处理例如化学机械抛光(CMP)，并对平坦化后的氧化物例如通过湿法刻蚀或者气相或干法刻蚀等进行回蚀来形成。另外，在衬底1001上已构图为纳米线/片形式的半导体层的表面上，可以通过例如淀积，形成一薄刻蚀停止层1019′(例如，厚度为约1nm至5nm)。在此，刻蚀停止层1019′可以同样包括氧化物，且因此被示出为与STI 1019一体的薄层。
如上所述，栅限定层1007、1011、1015位于纳米线/片限定层1009、1013上、下两侧，为形成全环绕栅，还可以在图4(b)所示取向下的左右两侧形成另一栅限定层。例如，如图5(a)和5(b)所示，可以在STI 1019以及刻蚀停止层1019′上形成栅限定层1021。例如，栅限定层1021可以通过淀积与之前的栅限定层1007、1011、1015基本上相同或类似的材料(从而具有基本上相同或相似的刻蚀选择性，以便一起处理)，并对淀积的材料进行平坦化处理如CMP来形成。在该示例中，栅限定层1021可以包括Ge原子百分比与栅限定层1007、1011、1015基本上相同或类似的SiGe。
在栅限定层1021上，可以通过例如淀积，形成硬掩模层1023，以便于构 图。例如，硬掩模层1023可以包括氮化物(例如，氮化硅)。
可以将栅限定层1007、1011、1015、1021构图为沿与预备纳米线/片的延伸方向(例如，图5(a)和图5(b)中的水平方向)相交例如垂直的方向(例如，图5(a)中的竖直方向，图5(b)中垂直于纸面的方向)延伸的伪栅。例如，可以在硬掩模层1023上形成光刻胶1025，并通过光刻将光刻胶1025构图为沿该方向延伸的条形。然后，可以光刻胶1025为掩模，通过例如RIE，依次对衬底1001上STI 1019之间的各层进行选择性刻蚀，刻蚀可以停止于衬底1001。结果，纳米线/片限定层1009、1013形成为随后可以用来提供沟道的纳米线或纳米片(在下面，将纳米线/片限定层1009、1013称作纳米线/片1009、1013)，且被栅限定层1007、1011、1015、1021(可以一起称作“伪栅”)所围绕。纳米线/片1009、1013可以自对准于伪栅。之后，可以去除光刻胶1025。
另外，如图5(b)所示，在伪栅两侧，露出了衬底1001的表面，这些露出的表面可以有助于随后生长源/漏层。另外，在隔离部限定层1003在伪栅延伸方向(图中垂直于纸面的方向)上的相对两侧，STI 1019可以与隔离部限定层1003相接，且可以自对准于伪栅而延伸(参见图8(b))。
考虑栅空间的限定以及栅与源/漏之间的隔离，可以在伪栅的侧壁上形成侧墙。为保证各纳米线/片1009、1013上下的栅长相同，在此可以利用自对准技术来形成侧墙。例如，如图6所示，可以相对于纳米线/片1009、1013(在该示例中，Si)，选择性刻蚀栅限定层1007、1011、1015、1021(在该示例中，SiGe)，使其侧壁相对于硬掩模层1023的侧壁或者纳米线/片1009、1013的侧壁向内凹入一定深度，例如约3nm至25纳米。优选地，栅限定层1007、1011、1015、1021各自的凹入深度实质上相同，且在左右两侧的凹入深度实质上相同。例如，可以使用原子层刻蚀(ALE)来实现良好的刻蚀控制。在该示例中，隔离部限定层1003同样为SiGe，因此也可以凹入实质上相同的深度。于是，刻蚀后栅限定层1007、1011、1015、1021(以及隔离部限定层1003)相应的侧壁可以实质上共面。
在如此形成的凹入中，可以形成侧墙。根据实施例，为了优化器件性能，可以采用铁电材料或负电容材料来形成侧墙。铁电材料一般处在两种极化状态中的一种，例如向上极化或向下极化之中的一种。但在一些特殊条件下(电容 的特殊匹配)，铁电材料可以稳定在两种极化状态之间，即所谓的负电容状态。铁电材料包括例如含Zr、Si和/或A1的Hf氧化物如HfZrO。
根据一个实施例，如图7(a)所示，可以通过例如淀积，在衬底1001上形成一定厚度的铁电或负电容材料层1027。淀积的铁电或负电容材料层1027的厚度足以填满上述凹入，例如为约3nm至30nm。根据另一实施例，如图7(b)所示，在形成铁电或负电容材料层1027之前，可以先以大致共形的方式形成一电介质层1029。例如，电介质层1029可以包括氧化物或高k电介质如HfO 2。
之后，如图8(a)和8(b)所示，可以通过例如竖直方向的RIE，去除电介质材料层1027的横向延伸部分，留下其竖直延伸部分(包括硬掩模层1023下方的部分)，从而形成侧墙1027。侧墙1027的侧壁可以与硬掩模层1023的侧壁(以及纳米线/片1009、1013的侧壁)实质上共面。
另外，图9(a)示出了在图7(b)所示的情形下形成侧墙的示例。可以看到，电介质层1029介于铁电或负电容材料的侧墙1027与伪栅之间。通过电介质层1029的材料选择以及厚度设定，可以调整栅与源漏之间的总电容。这种情况下，电介质层1029也称为伪栅的侧墙。备选地，电介质层1029可以替换为铁电或负电容材料层，而侧墙1027可以替换为常规电介质侧墙。或者，侧墙可以形成为多层配置，其中的一层或若干层为铁电或负电容材料，而其余层为常规电介质材料。
另外，图9(b)示出了在侧墙1027与电介质层1029之间进一步形成电势均衡层1031的示例。电势均衡层1031可以使电势在侧墙1027的表面上大致均衡分布。例如，电势均衡层1031可以包括导电层如金属或合金，金属或合金中可以含元素Ti、Ru、Co和Ta中至少之一，例如TiN、Co、Ru、TaN等，厚度为约0.5nm至2nm。在结合图9(a)描述的其他侧墙配置的情形下，也可以使用电势均衡层。
另外，在伪栅的外周侧壁上形成导电层例如电势均衡层的情况下，如图9(c)所示，可以在伪栅的延伸方向(例如，图9(c)中的竖直方向)切断伪栅，以避免如图9(c)中的虚线所示的由于导电层的存在而可能导致的源漏间短路。
以下，主要以图8(a)和8(b)所示的情形为例进行描述。
如图8(a)和8(b)所示，在与伪栅的延伸方向(图8(a)中垂直于纸面的方向) 相交(例如，垂直)的方向(图8(a)中的水平方向)上，各纳米线/片的侧壁暴露于外(且可以与硬掩模层的侧壁实质上共面)。如图10所示，可以暴露的纳米线/片的侧壁以及暴露的衬底1001的表面为种子，通过例如选择性外延生长，形成源/漏层1033。源/漏层1033可以形成为与所有纳米线/片的暴露侧壁相接。源/漏层1033可以包括各种合适的半导体材料。为增强器件性能，源/漏层1033可以包含晶格常数与纳米线/片不同的半导体材料，以向其中将形成沟道区的纳米线/片施加应力。例如，对于n型器件，源/漏层1033可以包括Si：C(C原子百分比例如为约0.1％至3％)，以施加拉应力；对于p型器件，源/漏层1033可以包括SiGe(Ge原子百分比例如为约20％至80％)，以施加压应力。另外，源/漏层1033可以通过例如原位掺杂或离子注入，被掺杂为所需的导电类型(对于n型器件为n型掺杂，对于p型器件为p型掺杂)。
在图10所示的实施例中，从纳米线/片的侧壁生长的源/漏层与从衬底1001的表面生长的源/漏层相接。这有助于散热或增强沟道中的应力，进而提高器件性能。另外，在本公开的其他实施例中，从纳米线/片的侧壁生长的源/漏层与从衬底1001的表面生长的源/漏层彼此间隔开。
接下来，可以进行替代栅工艺。
例如，如图11(a)和11(b)所示，可以在衬底1001上形成层间电介质层1035。例如，可以通过淀积氧化物，对淀积的氧化物进行平坦化处理如CMP，并回蚀平坦化后的氧化物，来形成层间电介质层1035。层间电介质层1035可以露出硬掩模层1023，但覆盖源/漏层1033。之后，可以通过选择性刻蚀，去除硬掩模层1023，以露出栅限定层1021。
为进行替代栅工艺，应该将伪栅即所有的栅限定层都去除，并替换为栅堆叠。在此，考虑到最下方的栅限定层1007下方的隔离部的形成，可以先对隔离部限定层1003进行处理，具体地，替换为隔离部。为此，可以形成到隔离部限定层1003的加工通道。
例如，可以通过选择性刻蚀，使栅限定层1021的高度降低至顶面低于隔离部限定层1003的顶面，但仍然保持有一定厚度，以便随后形成的掩模层(参见图12(a)和12(b)中的1037)能遮蔽隔离部限定层1003顶面上方的所有栅限定层1007、1011、1015，同时将隔离部限定层1003露出。例如，可以使用 ALE，以便很好地控制刻蚀深度。在此，由于刻蚀停止层1019′的存在，其他栅限定层1007、1011、1015可以不受影响。
然后，如图12(a)和12(b)所示，可以在栅限定层1021上形成掩模层例如光刻胶1037。可以通过光刻，将光刻胶1037构图为沿着纳米线/片的延伸方向延伸的条形，并可以遮蔽纳米线/片以及栅限定层1007、1011、1015的外表面(之间夹有刻蚀停止层1019′)。由于栅限定层1021的存在，隔离部限定层1003的一部分表面未被光刻胶1037遮蔽。之后，可以通过选择性刻蚀，依次去除栅限定层1021，去除由于栅限定层1021的去除而露出的刻蚀停止层1019′的部分，去除由于刻蚀停止层1019′的该部分的去除而露出的隔离部限定层1003。于是，在刻蚀停止层1005下方形成了空隙。由于隔离部限定层1003与上方的各纳米线/片、栅限定层通过相同的硬掩模层来限定，故而隔离部限定层1003与上方的各纳米线/片、栅限定层在竖直方向上对准，且因此由于隔离部限定层1003的去除而导致的空隙可以自对准于上方的各纳米线/片、栅限定层。之后，可以去除光刻胶1037。
在该示例中，刻蚀停止层1005也为半导体材料且连接在相对的源/漏层之间，这会导致漏电路径。为此，如图13(a)和13(b)所示，可以通过选择性刻蚀，例如使用TMAH溶液的湿法腐蚀，在相对的源/漏层之间切断刻蚀停止层1005。可以保留刻蚀停止层1005的端部，以免影响两侧的源/漏层。另一方面，留下的刻蚀停止层1005的端部可以没有伸出到侧墙内侧，以免与侧墙内侧的栅限定层(随后被替换为栅堆叠)相接触。也即，留下的刻蚀停止层1005的内侧壁相对于侧墙的内侧壁可以凹入。由于从中部开始刻蚀，因此留下的刻蚀停止层1005的相对端部可以基本上对称。另外，在该示例中，刻蚀停止层1005和衬底1001均包括硅，于是衬底1001也可以刻蚀掉一部分。于是，最下方的栅限定层1007与衬底1001之间的空隙可以增大，但仍然可以保持与上方的各纳米线/片、栅限定层实质上对准。
如图14(a)和14(b)所示，可以在如此形成的空隙中填充电介质材料例如低k电介质材料，以形成隔离部1039。隔离部1039的材料可以相对于STI 1019具备刻蚀选择性，例如氮氧化物(例如，氮氧化硅)。例如，可以通过在衬底1001上淀积足够的氮氧化物，并回蚀如RIE所淀积的氮氧化物，来形成隔离 部1039。如此形成的隔离部1039可以自对准于上方的各纳米线/片、栅限定层。
根据另一实施例，如图15(a)和15(b)所示，在淀积电介质材料时，由于上述空隙的空间受限，隔离部1039′可以形成中空结构。这种情况下，可以进一步降低隔离部1039′的介电常数。
接下来，如图16(a)和16(b)所示，可以通过选择性刻蚀，去除薄的刻蚀停止层1019′，以露出栅限定层，并进一步通过选择性刻蚀，去除栅限定层。于是，在侧墙1027内侧，STI 1019和隔离部1039上方，形成了栅槽(对应于各栅限定层原先所占据的空间)。在如此形成的栅槽中，可以依次形成栅介质层1041和栅电极1043，得到最终的栅堆叠。例如，栅介质层1041可以包括高k栅介质如HfO2，厚度为约2nm-10nm；栅电极1043可以包括功函数调节层如TiN、TiAlN、TaN等以及栅导体层如W、Co、Ru等。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.3nm-2nm。
如图16(a)和16(b)所示，根据实施例的纳米线/片器件可以包括与衬底1001间隔开的纳米线/片1009、1013(数目可以更少或更多)以及围绕纳米线/片1009、1013的栅电极1043。栅电极1043介由栅介质层1041与纳米线/片1009、1013相对。由铁电或负电容材料形成的侧墙1027形成在栅电极1043的侧壁上(可以称为“栅侧墙”)。如上所述，铁电或负电容材料可以在两种极化状态之间转换或者处于负电容状态。根据铁电或负电容材料所处的状态不同，器件可以表现出不同的性能，例如阈值电压(Vt)、漏致势垒降低(DIBL)、亚阈值摆幅(SS)等。在铁电或负电容材料处于负电容状态时，栅电极1043与源/漏层之间的电容值可以小于零。
当铁电材料在不同极化状态中相互转换时，可以依据不同极化状态而导致的不同器件状态如Vt来存储数据，因此器件可以用在存储器件中。另外，当把铁电材料稳定在两种极化状态之间时(呈负电容)，由此导致的负电容值可以减小器件中的交迭电容，并因此可以改善器件性能，器件于是可以用在逻辑器件中。因此，根据本公开的的纳米线/片器件既可以用于存储器件也可以用于逻辑器件。
该纳米线/片器件还可以包括隔离部1039。如上所述，隔离部1039可以自 对准于纳米线/片1009、1013或者栅电极。铁电或负电容材料的侧墙1027也可以形成在隔离部1039的侧壁上。于是，可以降低栅电极1043与衬底1001之间的电容。具体地，在最下方的栅电极1043与衬底1001之间，存在由隔离部1039形成的(正)电容与由侧墙1027形成的(负)电容的并联，由此它们的总电容相对于最下方的栅电极1043与衬底1001之间全部是常规电介质的情况减小。
侧墙1027的内侧壁在竖直方向上可以实质上共面，从而可以提供相同的栅长。另外，栅侧墙1027的外侧壁在竖直方向上也可以共面，且可以与纳米线/片1009、1013的侧壁共面。
根据本公开的另一实施例，如图17(a)和17(b)所示，在栅介质层1041与栅电极1043之间，还可以插入铁电或负电容材料层1045，以调节电容值及器件性能。例如，铁电或负电容材料层1045可以包括HfZrO，厚度为约2nm至15nm。或者，可以先形成铁电或负电容材料层1045，再形成栅介质层1041与栅电极1043，于是栅介质层1041介于铁电或负电容材料层1045与栅电极1043之间。这种情况下，侧墙1027不限于采用铁电材料或负电容材料，也可以采用常规电介质材料如氮化物。
根据本公开的另实施例，如图18(a)和18(b)所示，可以在铁电或负电容材料层1045的表面上形成电势均衡层1047，用以均衡电势。在该示例中，电势均衡层1047介于栅介质层1041与铁电或负电容材料层1045之间。例如，电势均衡层1047可以把包括导电层如金属或合金，金属或合金中可以含元素Ti、Ru、Co和Ta中至少之一，例如TiN、Co、Ru、TaN等，厚度为约0.5nm至2nm。或者，在栅介质层1041介于铁电或负电容材料层1045与栅电极1043之间的情况下，电势均衡层1047可以介于铁电或负电容材料层1045与栅介质层1041之间。
以上结合图16(a)至18(b)的描述同样适用于参考图9(a)至9(c)描述的配置。
根据本公开实施例的纳米线/片器件可以应用于各种电子设备。例如，可以基于这样的纳米线/片器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述纳米线/片器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种 电子设备例如智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (37)

  1. 一种纳米线/片器件，包括：
    衬底；
    所述衬底上与所述衬底的表面间隔开的纳米线/片；
    围绕所述纳米线/片的栅电极；
    在所述栅电极的侧壁上形成的铁电或负电容材料层；以及
    位于所述纳米线/片的相对两端且与所述纳米线/片相接的源/漏层。
  2. 根据权利要求1所述的纳米线/片器件，其中，所述纳米线/片器件依据所述铁电或负电容材料层的状态而表现出不同的阈值电压。
  3. 根据权利要求1或2所述的纳米线/片器件，其中，所述栅电极与所述源/漏层之间的电容值小于零。
  4. 根据权利要求1或2所述的纳米线/片器件，其中，所述铁电或负电容材料层是所述纳米线/片器件的栅侧墙。
  5. 根据权利要求4所述的纳米线/片器件，其中，所述铁电或负电容材料层沿着所述栅电极的侧壁的实质上整个高度延伸。
  6. 根据权利要求4所述的纳米线/片器件，还包括：
    介于所述栅电极与所述纳米线/片之间以及介于所述栅电极与所述铁电或负电容材料层之间的栅介质层，
    其中，所述铁电或负电容材料层沿着所述栅介质层的侧壁的实质上整个高度延伸。
  7. 根据权利要求4所述的纳米线/片器件，还包括：
    在所述铁电或负电容材料层面对所述栅电极的侧壁以及上、下表面上形成的电势均衡层。
  8. 根据权利要求7所述的纳米线/片器件，还包括：
    在所述铁电或负电容材料层面对所述栅电极的侧壁以及上、下表面上形成的电介质层，所述电势均衡层介于所述电介质层与所述铁电或负电容材料层之间。
  9. 根据权利要求1所述的纳米线/片器件，还包括：
    在所述栅电极的侧壁以及所述栅电极面向所述纳米线/片的表面上形成的栅介质层，
    其中，所述铁电或负电容材料层介于所述栅电极与所述栅介质层之间，或者所述栅介质层介于所述铁电或负电容材料层与所述栅电极之间。
  10. 根据权利要求9所述的纳米线/片器件，还包括：
    介于所述铁电或负电容材料层与所述栅介质层之间的电势均衡层。
  11. 根据权利要求9或10所述的纳米线/片器件，还包括：
    在所述栅电极的侧壁上形成的栅侧墙，其中所述铁电或负电容材料层、所述栅介质层和所述栅电极位于所述栅侧墙限定的空间内。
  12. 根据权利要求11所述的纳米线/片器件，其中，所述栅侧墙包括铁电或负电容材料。
  13. 根据权利要求4或11所述的纳米线/片器件，其中，所述栅侧墙背对所述栅电极的侧壁与所述纳米线/片的侧壁在竖直方向上实质上共面。
  14. 根据权利要求4或11所述的纳米线/片器件，其中，所述栅侧墙面向所述栅电极的侧壁在竖直方向上实质上共面。
  15. 根据权利要求4或11所述的纳米线/片器件，还包括：
    所述栅电极的最接近所述衬底的表面与所述衬底之间的隔离部，其中所述隔离部自对准于所述纳米线/片。
  16. 根据权利要求15所述的纳米线/片器件，其中，所述栅侧墙还形成在所述隔离部的侧壁上，其中所述隔离部还延伸到所述栅侧墙在所述隔离部的侧壁上的部分的顶面上。
  17. 根据权利要求16所述的纳米线/片器件，其中，所述栅侧墙在所述隔离部的侧壁上的部分与所述栅侧墙中与之最接近的另一部分之间在竖直方向上间隔开的距离是实质上均匀的。
  18. 根据权利要求16所述的纳米线/片器件，还包括：所述栅侧墙在所述隔离部的侧壁上的部分与所述栅侧墙中与之最接近的另一部分之间的半导体材料层，其中所述半导体材料层在所述隔离部的外侧。
  19. 根据权利要求15所述的纳米线/片器件，其中，所述隔离部具有中空结构。
  20. 根据权利要求7或10所述的半导体器件，其中，所述电势均衡层是金属或合金。
  21. 根据权利要求20所述的半导体器件，其中，所述金属或合金中含元素Ti、Ru、Co和Ta中至少之一。
  22. 根据权利要求1所述的纳米线/片器件，其中，设置有多个所述纳米线/片，每个所述纳米线/片彼此实质上平行延伸，且在竖直方向上实质上对准。
  23. 根据前述任一权利要求所述的纳米线/片器件，所述铁电或负电容材料包括含Zr、Si和/或Al的Hf氧化物。
  24. 一种制造纳米线/片器件的方法，包括：
    在衬底上设置与所述衬底的表面间隔开的纳米线/片；
    在衬底上形成围绕所述纳米线/片的伪栅；
    在所述伪栅的侧壁上利用铁电或负电容材料形成侧墙；以及
    去除伪栅，并在侧墙内侧由于伪栅的去除而形成的栅槽中形成栅电极。
  25. 根据权利要求24所述的方法，还包括：
    在所述栅槽中形成铁电或负电容材料层。
  26. 一种制造纳米线/片器件的方法，包括：
    在衬底上设置与所述衬底的表面间隔开的纳米线/片；
    在衬底上形成围绕所述纳米线/片的伪栅；
    在所述伪栅的侧壁上形成侧墙；以及
    去除伪栅，并在侧墙内侧由于伪栅的去除而形成的栅槽中形成铁电或负电容材料层；以及
    在形成有所述铁电或负电容材料层的所述栅槽中形成栅电极。
  27. 根据权利要求26所述的方法，其中，利用铁电或负电容材料形成所述侧墙。
  28. 根据权利要求25或26所述的方法，其中，沿所述栅槽的内表面连续形成所述铁电或负电容材料层。
  29. 根据权利要求28所述的方法，还包括：
    沿所述栅槽的内表面形成栅介质层，其中所述铁电或负电容材料层介于所述栅介质层与所述栅电极之间，或者所述栅介质层介于所述铁电或负电容材料 层与所述栅电极之间。
  30. 根据权利要求29所述的方法，还包括：
    形成介于所述栅介质层与所述铁电或负电容材料层之间的电势均衡层。
  31. 根据权利要求24或26所述的方法，其中，设置纳米线/片包括：
    在衬底上形成隔离部限定层；
    在隔离部限定层上形成一个或多个栅限定层以及一个或多个纳米线/片限定层交替设置的堆叠；
    将所述堆叠和所述隔离部限定层构图为沿第一方向延伸的预备纳米线/片；
    在所述衬底上形成另一栅限定层以覆盖所述堆叠和所述隔离部限定层；
    将所述另一栅限定层构图为沿与第一方向相交的第二方向延伸的条形；以及
    以条形的所述另一栅限定层为掩模，将所述堆叠和所述隔离部限定层构图为线状或片状，
    其中，被构图为线状或片状的所述纳米线/片限定层形成所述纳米线/片。
  32. 根据权利要求31所述的方法，其中，
    形成伪栅包括：选择性刻蚀所述隔离部限定层和所述栅限定层，使其侧壁相对于所述纳米线/片的侧壁向内凹入，其中所述栅限定层形成所述伪栅，
    形成侧墙包括：在所述凹入中形成侧墙。
  33. 根据权利要求32所述的方法，还包括：
    沿所述凹入的内表面形成电介质层；
    在所述电介质层上形成电势均衡层，
    其中，所述侧墙形成在所述电势均衡层上。
  34. 根据权利要求32所述的方法，还包括：
    在隔离部限定层上形成刻蚀停止层，其中所述堆叠形成在所述刻蚀停止层上，
    其中，在形成侧墙之后，该方法还包括：
    在所述纳米线/片在所述第一方向上的相对两侧形成与所述纳米线/片相接的源/漏层；
    从所述纳米线/片在所述第二方向上的相对两侧，通过选择性刻蚀，
    去除所述隔离部限定层；
    通过选择性刻蚀，去除所述刻蚀停止层的中部；以及
    在由于所述隔离部限定层和所述刻蚀停止层的中部的去除而导致的空间中填充电介质材料，形成隔离部。
  35. 根据权利要求34所述的方法，其中，所述隔离部具有中空结构。
  36. 一种电子设备，包括如权利要求1至23中任一项所述的半导体器件。
  37. 根据权利要求36所述的电子设备，包括智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
PCT/CN2021/082732 2020-09-07 2021-03-24 带铁电或负电容材料的器件及其制造方法及电子设备 WO2022048136A1 (zh)

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