WO2021184248A1 - Method and device for measuring power of processor cores - Google Patents
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- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
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- This application relates to the field of chip technology, and in particular to a method and device for measuring processor core power.
- the processor may include multiple processor cores.
- multiple processor cores share the same power domain (power supply network and power supply circuit), and the processor can obtain the power of multiple processor cores according to the voltage and current of the power domain. The sum of actual power.
- the processor can also obtain the estimated power of each processor core according to several strategies that can calculate the estimated power.
- the estimated power of each processor core can be used to adjust the frequency and voltage of each processor core.
- the voltage and current of the power domain can be read by the monitoring device in the power supply device. Based on the actually read voltage and current values of the power domain, the actual power consumption value of the power domain can be calculated to realize the control of the processor Power management.
- the estimation strategy for the estimated power of the processor cores can essentially be understood as: estimation based on the power consumption model of the activity coefficient and power consumption coefficient of each processor core.
- the processor core can be divided into different modules. In a preset period, the number of times each module is activated is the activity coefficient of each module, and each module is in the preset period. The power generated when activated once is the power consumption coefficient of each module. However, in a preset period, each time a module is activated, the power consumption coefficient generated by it is not a fixed value, that is, the power consumption coefficient generated by a module may be different when it is activated two times.
- the power consumption coefficient of a module is the average power consumption obtained by fitting the power consumption coefficient generated when a module is activated multiple times in a preset period through linear regression, that is, the average power consumption obtained by the fitting.
- the power consumption is used as the power consumption coefficient of a module in a preset period. Therefore, in a preset period, the estimated power and actual power of a processor core obtained by the activity coefficient and power consumption coefficient of each module of a processor core will inevitably have errors.
- each processor core When the estimated power of each processor core has a large error from the actual power, it may cause a large error in the estimated power, which may cause the total actual power of the processor to exceed the power limit of the maximum power supply current of the processor, or it may cause The processor's power cannot be fully utilized, resulting in a decrease in processor performance.
- the embodiments of the present application provide a method and device for measuring the power of a processor core, which can reduce the error between the estimated power of the processor core and the actual power.
- a method for measuring the power of a processor core includes: determining the sum of the estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor; determining processing The total actual power of multiple processor cores in the processor core processor; the estimated power of each processor core is calibrated according to the total estimated power and the total actual power to obtain the calibrated power of each processor core.
- the present application can calibrate the estimated power of each processor core according to the relative relationship between the estimated power sum and the actual power sum.
- the calibrated power of each processor core after calibration can more accurately reflect the actual power of each processor core, and the error between the estimated power and the actual power of the multi-core processor can be reduced, so that the required power can be reserved.
- the margin is reduced, so that the processor can obtain the maximum performance in the design as much as possible, and realize more efficient power management of the processor.
- the method further includes: adjusting the frequency and voltage of each processor core according to the calibration power of each processor core.
- the processor's Performance is better.
- calibrating the estimated power of each processor core according to the sum of the estimated power of the processor cores and the sum of the actual power of the processor cores includes: determining according to the sum of the estimated power of the processor cores and the sum of the actual power of the processor cores Calibration coefficient; the estimated power of each processor core is calibrated according to the processor core calibration coefficient.
- the calibration coefficient may be, for example, the ratio ⁇ of the actual power sum to the estimated power sum.
- the calibrated power of the processor core can be obtained according to the estimated power of the processor core and the value of ⁇ , so that the calibrated power is closer to the actual power of the processor core than the estimated power.
- the power headroom can be set to be smaller, so that the processor performance is better.
- determining the total estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor includes: according to the estimated power of each processor core in the processor And the static power of the power domain of multiple processor cores, determine the sum of the estimated power of multiple processor cores; wherein, the static power of the power domain of multiple processor cores refers to the leakage current of the power domain of multiple processor cores The resulting power consumption.
- the static power of the processor core power domain is also considered, the sum of the estimated power of multiple processor cores can be made to represent the real power more accurately. Power situation.
- the method before determining the sum of the estimated power of multiple processor cores, the method further includes: determining the estimated power of each processor core. That is, before determining the total estimated power, the estimated power corresponding to each processor core can be determined first.
- determining the estimated power of each processor core includes: determining the estimated power of each processor core according to the active power of each processing core and the basic power of each processor core; where, the active power Used to indicate the power consumed by at least one power consumption characterization signal of each processing core when it is in an active state, and base power is used to indicate at least one power consumption characterization signal of each processing core when each processor is not in an active state The power consumed by the core.
- the power consumption characterization signal selected for each processor core may not cover all the power consumption events of the processor core (even if it can be covered, the value of B is 0). Therefore, after obtaining the basic For power, the estimated power of each processor core can be obtained according to the active power and the basic power, so that the estimated power can more accurately reflect the actual power of the processor core.
- the active power of each processor core is determined in the following manner: the activity coefficient of at least one power consumption characteristic signal of each processor core and the power consumption coefficient of at least one power consumption characteristic signal are obtained. Said activity power, the activity coefficient of each power consumption characterization signal is used to reflect the coefficient when each power consumption characterization signal is in the active state, and the power consumption coefficient of each power consumption characterization signal The power consumed when in an active state. For example, the activity coefficient of each power consumption characterization signal can be multiplied by the power consumption coefficient, and then the products corresponding to each power consumption characterization signal can be summed to obtain the active power of a processor core.
- the method further includes: adjusting the power consumption of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core coefficient.
- the estimated power of each processor core is measured, and then the power consumption coefficient is obtained by fitting the estimated power and the activity coefficient.
- the estimated power obtained by measurement always has an error. Therefore, in this application, if the power consumption coefficient obtained is fitted according to the sum of the actual power, the estimated power obtained by the calculation of the power consumption coefficient will be relatively more accurate.
- a device for measuring processor core power including: a power consumption monitor and a frequency controller, and the frequency controller is used to obtain the estimated power of each processor core in the processor according to the power consumption monitor Determine the total estimated power of multiple processor cores included in the processor; the frequency controller is also used to determine the total actual power of multiple processor cores in the processor; the frequency controller is also used to determine the total estimated power and actual power The power sum calibrates the estimated power of each processor core to obtain the calibrated power of each processor core.
- the frequency controller is also used to adjust the frequency and voltage of each processor core according to the calibration power of each processor core.
- the frequency controller is used to determine the calibration coefficient according to the total estimated power and the total actual power; and calibrate the estimated power of each processor core according to the calibration coefficient.
- the frequency controller is used to: determine the sum of the estimated power of multiple processor cores according to the estimated power of each processor core in the processor and the static power of the power domain of the multiple processor cores; where The static power of the power domain of multiple processor cores refers to the power consumption generated by the leakage current of the power domain of multiple processor cores.
- the power monitor is used to determine the estimated power of each processor core.
- the power monitor is used to determine the estimated power of each processor core according to the active power of each processing core and the basic power of each processor core; where the active power is used to indicate each The power consumed by at least one power consumption characterizing signal of each processing core when it is in an active state, and the basic power is used to indicate the power consumed by each processor core when at least one power consumption characterizing signal of each processing core is not in an active state. Consumption.
- the power consumption monitor is used to obtain the active power according to the activity coefficient of at least one power consumption characterization signal and the power consumption coefficient of at least one power consumption characterization signal of each processor core, and each power consumption characterization
- the activity coefficient of the signal is used to reflect the coefficient when each power consumption characterization signal is in the active state
- the power consumption coefficient of each power consumption characterization signal is used to reflect the power consumption of each power consumption characterization signal each time it is active .
- the frequency controller is also used to adjust the activity coefficient of at least one power consumption characterization signal of each processor core according to the total actual power and the activity coefficient of at least one power consumption characterization signal of each processor core. Power consumption factor.
- a computer-readable storage medium including a program or instruction, when the processor core program or instruction is executed by a processor, such as the method described in the first aspect and any one of the possible designs of the first aspect Be executed.
- a computer program product is provided.
- the electronic device executes the method described in the first aspect and any one of the possible designs of the first aspect.
- a communication device in a fifth aspect, includes the second aspect or a device corresponding to any one of the possible designs of the second aspect.
- a chip in a sixth aspect, includes the second aspect or a device corresponding to any possible design of the second aspect.
- FIG. 1 is an applicable communication device for processing provided by an embodiment of this application
- FIG. 2 is a schematic structural diagram of a processor provided by an embodiment of the application.
- FIG. 3 is a flowchart of a method for measuring processor core power according to an embodiment of the application
- FIG. 4 is a schematic diagram of a method for determining a power consumption coefficient and basic power provided by an embodiment of the application
- FIG. 5 is a schematic flowchart of a silicon power consumption coefficient calibration process provided by an embodiment of the application.
- Fig. 6 is a block diagram of a computing system provided by an embodiment of the application.
- This application can be applied to all types of processors designed in a common power domain with multiple processor cores. Among them, obtaining the estimated power consumption of each processor core of the processor is a necessary condition for efficient power management of the processor.
- the actual power of each processor core cannot be directly obtained by measurement. Therefore, it is necessary to estimate the power of each processor core through a certain strategy.
- the power of each processor core obtained by the power estimation method is bound to have an error with the actual power of each processor core. Therefore, this application is used to further correct the estimated power, so that each process after the correction
- the calibrated power of the processor core is more similar to the actual power of each processor core than the estimated power before correction.
- the processor provided in the present application can be applied to various communication devices, and the communication device can be, for example, a chip or a terminal device.
- the chip may be a system-on-chip (SoC) with multiple processor cores.
- the terminal device may be a mobile terminal, such as a mobile phone 11, a pad 12, or a notebook computer 13, etc.; the terminal device may also be a non-mobile terminal, such as a desktop computer 14. If the terminal device is a mobile terminal, its processor may be a multi-processor core processor, and the multi-processor core processor may be, for example, an SoC.
- FIG. 2 is a processor 20 with a multi-processor core common power domain design provided by an embodiment of the application. Take the processor 20 including four processor cores (processor core 0, processor core 1, processor core 2, and processor core 3) as an example.
- the processor 20 may include a processor core power plane 21 and a non-processor core power plane 22. It should be noted that the processor 20 shown in FIG. 2 is only an example of the processor, and the processor may also include other power supply plane designs.
- the processor core power plane 21 may include 4 processor cores, a power consumption monitor 211 corresponding to each processor core, a power supply circuit 212, and a frequency controller 213.
- the non-processor core power plane 22 may include an external cache, an internal memory, a general-purpose unit, an accelerator, and an input/output control unit & interface unit. It should be noted that the power consumption monitor 211 may also be located on other power planes in practical applications.
- the power consumption monitor 211 may periodically monitor the behavior of the power consumption characterization signal of the corresponding processor core to obtain the estimated power initially estimated for the processor core, and send the estimated power to the frequency controller 213.
- the frequency controller 213 can be used to summarize the estimated power sent by each power consumption monitor 211, and finally determine the total estimated power when the processor 20 is running, and provide data support for the frequency and voltage adjustment of the processor 20.
- the frequency controller 213 is located in the processor core power plane 21, but in some other applications, the frequency controller 213 may also be located in other power planes.
- the power supply circuit 212 can provide the frequency controller 213 with the voltage and current of the processor core power plane 21, and the frequency controller 213 can obtain the current total actual power of each processor core of the processor 20 according to the voltage and current.
- this application can further correct the estimated power so that the estimated power of each processor core after correction is more similar to the actual power of each processor core than the estimated power before correction.
- the specific solution may be: the frequency controller 213 may process the sum of the actual power obtained according to the voltage and current provided by the power supply circuit 212, and the estimated power obtained according to the estimated power sent by the power consumption monitor 211.
- the estimated power of the processor core is calibrated to obtain the calibrated power of each processor core after calibration. Since the total estimated power will have an error relative to the total actual power, when the relative relationship between the total estimated power and the error of the actual power total is obtained from the total estimated power and the total actual power, the relative relationship can be compared with the estimated power of each processor core.
- the estimated power of each processor core may be further calibrated, so that the frequency controller 213 can perform the calibration of each processor core according to a more accurate calibration power. Adjust the frequency and voltage of each processor core when it is running.
- the software architecture of the frequency controller 213 can be improved to implement the solution of the present application, for example, firmware used to implement the solution of the present application can be added to the frequency controller 213; the hardware of the frequency controller 213 can also be modified.
- the architecture is improved to implement the solution of the present application; it is also possible to improve both the software architecture and the hardware architecture of the frequency controller 213 to implement the solution of the present application, which is not limited in this application.
- the embodiment of the present application provides a method for measuring the power of a processor core. As shown in FIG. 3, the method includes:
- steps 301 to 304 may be performed periodically, that is, in each preset period, the estimated power of each processor core may be calibrated once.
- a preset period may be, for example, 100 us, or other values, which is not limited in this application.
- each power consumption monitor 211 may perform periodic power estimation for the corresponding processor core to obtain the estimated power of each processor core in each preset period.
- the estimated power may be the active power of the corresponding processor core.
- the active power is used to indicate the power consumed by at least one power consumption characterization signal of each processing core when the signal is in an active state. Wherein, for a power consumption characterization signal, its active state may be that the power consumption characterization signal is in an overturned or high level state.
- the active power of each processor core may be determined in the following manner: the active power is obtained according to the power consumption coefficient of at least one power consumption characterization signal and the activity coefficient of at least one power consumption characterization signal of each processor core.
- a processor core can correspond to multiple power consumption characterization signals, and one power consumption characterization signal corresponds to an activity coefficient and a power consumption coefficient;
- the power consumption characterization signal is participation statistics The estimated power signal of a processor core, and the activity coefficient of each power consumption characterization signal is used to reflect the coefficient when each power consumption characterization signal is in an active state.
- a power consumption characterization signal For example, corresponding to a power consumption characterization signal, its corresponding activity coefficient can be understood as the number of times the power consumption characterization signal is inverted or the number of clock cycles at a high level.
- the power consumption coefficient of each power consumption characterization signal is used to reflect the power consumption of each power consumption characterization signal each time it is in an active state.
- the power consumption coefficient used to determine the active power may be determined by linear fitting in advance.
- the estimated power (active power) of each processor core can be determined according to the calculation method of the following formula 1:
- P m C 0 W 0 +C 1 W 1 +C 2 W 2 +...+C n W n , where P m represents the estimated power of the m-th processor core in a preset period, C 0 , C 1.
- C 2 ...C n represents the activity coefficients corresponding to the n power consumption characterization signals of the mth processor core, W 0 , W 1 , W 2 ...W n represents the n power consumption of the mth processor core Characterize the power consumption coefficient corresponding to the signal respectively.
- m and n are integers greater than or equal to zero.
- 302. Determine the total estimated power of multiple processor cores included in the processor according to the estimated power (active power) of each processor core in the processor.
- the power consumption monitor 211 may send the estimated power of the corresponding processor core to the frequency controller 213, and the frequency controller 213 calculates multiple processors based on the received estimated power of the multiple processor cores. The sum of the estimated power of the processor cores.
- the static power of the processor core power plane 21 may also be monitored.
- static power that is, leakage power consumption
- P leak The addition of the static power P leak can make the sum of the estimated power of multiple processor cores more accurately characterize the real power situation.
- the voltage and temperature when the static power consumption is obtained may be provided by the power supply circuit 212 to the frequency controller 213, and the frequency controller 213 calculates the static power according to the voltage and temperature.
- the power supply voltage V and the power supply current I of the power domain of the processor core power plane 21 can be obtained.
- the power supply circuit 212 may obtain the power supply voltage V and the power supply current I, and provide the obtained power supply voltage V and the power supply current I to the frequency controller 213, and the frequency controller 213 determines the power supply voltage V and the power supply current I I calculates the total actual power consumption of multiple processor cores P total'.
- the estimated power of each processor core may be calibrated according to the relative relationship between the total estimated power and the total actual power to obtain the calibrated power of each processor core after calibration.
- the calibration coefficient ⁇ can be obtained according to the relative relationship between the estimated power sum P total and the actual power sum P total ′ obtained in a preset period.
- the estimated power P m of each processor core is calibrated according to the calibration coefficient ⁇ , and the calibrated power P m 'of each processor core after calibration is obtained.
- the value of ⁇ may be a value greater than or equal to 1, or a value less than 1.
- the calibration coefficient ⁇ when the calibration coefficient ⁇ is obtained, it can be stated that the actual power sum P total ′ is ⁇ times the estimated power sum P total. Similarly, it can be considered that the actual power of each processor core is approximately n times the estimated power P m of the corresponding processor core.
- the calibration coefficient is 1.1, that is, the total actual power is 1.1 times the total estimated power.
- the estimated power P m of the m-th processor core is 5w
- the actual power of the m-th processor core is also approximately 1.1 times the estimated power. Therefore, according to formula 6, the calibrated power of the m-th processor core P m 'is 5.5w.
- the calibrated power of 5.5w is closer to the actual power of the m-th processor core.
- Step 304 may be executed by the frequency controller 213.
- the frequency controller 213 may send the obtained calibration power of each processor core to the power consumption monitor 211 corresponding to each processor core.
- Each power consumption monitor 211 can adjust the frequency and voltage of the corresponding processor core according to the obtained calibration power.
- the relative relationship between the sum of actual power of multiple processor cores and the sum of estimated power of multiple processor cores can be further used to obtain the estimated power of each processor core.
- the processor when the estimated power of the processor core is less than the actual power, and the error between the estimated power and the actual power is large, the processor will continue to control the operation of the processor core, but the actual power may have reached the power consumption limit of over-current control.
- the estimated power after calibration is obtained using this application, the actual power of the processor core can be effectively prevented from reaching the power consumption limit; when the estimated power of the processor core is greater than the actual power, the processor core is estimated too high at this time The estimated power of the processor core, but the actual power does not reach the estimated power value, so there will be more power margins that have not been used.
- the estimated power after calibration is obtained using this application, the estimated power of the processor core can be closer to the actual Power, power headroom can be fully utilized, which can achieve more efficient power management of the processor.
- the above steps 301 to 305 can occur when the chip has been applied to the terminal device, and the estimated power of each processor core in the chip is calibrated.
- the basic power of the processor core can be understood as the power consumed by each processor core when at least one power consumption characterization signal of each processor core is not in an active state.
- the basic power can be obtained during the pre-silicon simulation of the chip. Therefore, in some embodiments, before step 301, a pre-silicon simulation of the chip may be performed to obtain the basic power of multiple processor cores. Therefore, before step 301, as shown in FIG. 4, the method may further include:
- the selection should be based on the principle of reducing the number of signals as much as possible on the basis of covering all power consumption scenarios.
- the selection criteria for the power consumption characterization signal may include: clock gating signals that control a large number of registers; signals that have characterization significance for power consumption events, such as the transmit signal of the transmit queue.
- the selection of test cases needs to cover all possible power consumption scenarios in principle. Once the power consumption scenario coverage of the test case is not comprehensive, it may happen that the power consumption coefficient obtained by the fitting deviates too much from the true value.
- Step 401 can be performed by a designer.
- the data points corresponding to each processor core when the processor runs the test case include activity coefficients corresponding to multiple power consumption characterization signals of each processor core, and the estimated power of each processor core .
- the test case can be run through PTPX (prime-time PX) simulation to obtain the data points used by each processor core to fit the basic power.
- the data point includes the activity coefficients corresponding to the n power consumption characterization signals of the m-th processor core: C 0 , C 1 , C 2 ...C n , and corresponding to the m-th processor core The estimated power P m ".
- step 402 may be executed by the power consumption monitor 211 corresponding to each processor core.
- the activity coefficients corresponding to the n power consumption characteristic signals of the m-th processor core C 0 , C 1 , C 2 ... C n
- the corresponding estimation of the m-th processor core Linear regression fitting is performed on the power, and the power consumption coefficients W 0 , W 1 , W 2 ...W n and the basic power B corresponding to the m-th processor core are obtained.
- the basic power B corresponding to each processor core can also be obtained by fitting.
- the basic power can also be understood as the power consumed when the n power consumption characteristic signals of a processor core are not inverted or in a low level state within a preset period.
- the power consumption characterization signal selected for each processor core can cover all the power consumption events of the processor core, the value of B is 0. Therefore, when the basic power is obtained, it can be based on the power consumption of each processor core.
- the active power and the basic power of each processor core determine the estimated power of each processor core, so that the estimated power can more accurately reflect the actual power of the processor core. That is, the formula one in step 301 can be replaced with:
- B m represents the basic power of the m-th processor core in a preset cycle.
- step 403 may be executed by the power consumption monitor 211 corresponding to each processor core.
- steps 401 to 403 are the power consumption coefficient and the basic power obtained by performing the pre-silicon simulation, then the power consumption coefficient can be calibrated once after the silicon.
- the calibration at this time may be the calibration of the power consumption coefficient when the chip has not been applied to the actual terminal equipment.
- the calibration of the power consumption coefficient can occur before step 301 and after step 403, that is, after the power consumption coefficient and the basic power corresponding to each processor core are obtained by the silicon pre-silicon simulation, and after the calculation of multiple processors Before calibrating the estimated power of the core, calibrate the power consumption coefficients of multiple processor cores.
- step 403 the method further includes step 404:
- This calibration method is similar to the principle of obtaining the power consumption coefficient in steps 401 to 403.
- the post-silicon calibration of the power consumption coefficient can eliminate the influence of the error of the power consumption coefficient of the pre-silicon simulation and the post-silicon simulation.
- the power consumption coefficient may be continuously calibrated. At this time, the power consumption coefficient is calibrated when the chip has been applied to the terminal device. As shown in Figure 5. Therefore, the method may also include:
- the power consumption coefficient of each processor core is calibrated according to the total actual power of multiple processor cores and the activity coefficient corresponding to each processor core.
- the period for calibrating the consumption coefficient may be greater than the aforementioned preset period for calibrating the estimated power.
- the first period may be the sum of the durations of multiple preset periods.
- the multiple processor cores of the processor core power plane 21 can be taken as a whole, that is, in each first cycle, the actual power sum P total 'of multiple processor cores and multiple
- the activity coefficient C mn of the power consumption characterization signal of the processor core performs linear regression fitting to obtain the power consumption coefficient W mn and the basic power B′ corresponding to each power consumption characterization signal.
- C mn represents the activity coefficient of the nth power consumption characterization signal of the mth processor core.
- W mn represents the power consumption coefficient of the nth power consumption characterization signal of the mth processor core.
- B' is the sum of the basic power of multiple processor cores in the first cycle.
- linear regression fitting can be performed on P total ', C 00 , C 01 , C 02 ... C 0n , C 10 , C 11 , C 12 ... C 1n ... C m0 , C m1 , C m2 ... C mn , Get W 00 , W 01 , W 02 ... W 0n , W 10 , W 11 , W 12 ... W 1n ... W m0 , W m1 , W m2 ... W mn and B'.
- the power consumption monitoring unit 211 corresponding to each processor core may obtain the activity coefficient C mn of the corresponding processor core, and send C mn to the frequency controller 213, and the frequency controller 213 may obtain the activity coefficient C mn according to the activity coefficient C mn. mn and the actual power sum P total ′ obtained in step 303 obtain the power consumption coefficient W mn .
- the power consumption coefficient can be calibrated in real time according to the power consumption data when the chip is working in real time, so that a more accurate estimated power of each processor core can be calculated according to the power consumption coefficient obtained by the real-time calibration.
- FIG. 6 illustrates a block diagram of a computing system 100 according to an embodiment of the present application.
- the computing system 60 may include one or more central processing units (CPU) or processors 602-1 to 602-p (may be referred to as "multiple processors 602" or “processors 602" herein).
- the processor 602 can communicate via a bus (or interconnection network) 604.
- the processor 602 may include a general-purpose processor, a network processor (processing data transmitted on the computer network 603) or other types of processors (including reduced instruction set computing (RISC) processors or complex instruction set computers (complex instruction set computer, CISC)).
- RISC reduced instruction set computing
- CISC complex instruction set computer
- multiple processors 602 may have a single or multiple core design.
- the processor 602 with a multi-core design can integrate different types of processor cores on the same integrated circuit (IC) die.
- the processor 602 with a multi-core design can be implemented as a symmetric or asymmetric multi-processor.
- one or more processors 602 may be the same as or similar to the processor of FIG.
- the computing system 60 of the present application may also include a chipset 606.
- the chipset 606 can also communicate with the bus 604.
- the chipset 606 may include a graphics memory controller hub (GMCH) 608.
- the GMCH 608 may include a memory controller 110 that communicates with the memory 112.
- the memory 112 may store data, which includes a sequence of instructions executed by the processor 602 or any other device included in the computing system 60.
- the memory 112 may include one or more volatile storage (or memory) devices, such as random access memory (RAM), dynamic RAM (DRAM), and synchronous DRAM (synchronous dynamic RAM, SDRAM), static RAM (static RAM, SRAM) or other types of storage devices. It is also possible to use non-volatile memory, such as a hard disk. Other devices may communicate via the bus 604, such as multiple CPUs and/or multiple system memories.
- the GMCH 608 may also include a graphics interface 114 for communicating with the graphics accelerator 116 and a display (not shown in the figure).
- the display for example, a flat panel display, a cathode-ray-tube (CRT), a projection screen, etc.
- the graphics interface 114 may communicate with the graphics interface 114 through, for example, a signal converter, wherein the signal conversion The converter converts the digital representation of the image stored in a storage device (for example, video memory or system memory) into a display signal that is interpreted and displayed by the display.
- the display signal generated by the display device can pass through various control devices before being interpreted by the display and then displayed thereon.
- the computing system 60 of the present application may further include an input/output control center (input/output controller hub, ICH) 120, and the ICH 120 may provide an interface for I/O devices that communicate with the computing system 60.
- the ICH 120 can pass through a peripheral device bridge (or controller) 124 (for example, a Peripheral Component Interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral device bridges). Or the controller) communicates with the bus 122.
- the peripheral device bridge 124 may provide a data path between the processor 602 and peripheral devices.
- multiple buses 122 can communicate with the ICH 120.
- bus 122 may also communicate with an audio device 126, one or more hard disk drives 128, and one or more network interface devices 130 (which communicate with the computer network 603).
- the disclosed device and method may be implemented in other ways.
- the device embodiments described above are merely illustrative.
- the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be divided. It can be combined or integrated into another device, or some features can be omitted or not implemented.
- the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
- the units described as separate parts may or may not be physically separate.
- the parts displayed as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
- the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
- the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
- the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium.
- the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product, and the software product is stored in a storage medium. It includes several instructions to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application.
- the aforementioned storage media include: U disk, mobile hard disk, read only memory (read only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.
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Abstract
The present application relates to the technical field of chips, and disclosed are a method and device for measuring the power of processor cores, capable of reducing errors between estimated power and actual power of the processor cores. The method comprises: determining, according to estimated power of each processor core in a processor, the sum of estimated power of multiple processor cores comprised in the processor; determining the sum of actual power of the multiple processor cores in the processor; and calibrating the estimated power of each processor core according to the sum of the estimated power and the sum of the actual power to obtain a calibrated power of each processor core. The embodiments of the present application can be used for calibrating the estimated power of each processor core of a multi-core processor.
Description
本申请涉及芯片技术领域,尤其涉及一种测量处理器核功率的方法和装置。This application relates to the field of chip technology, and in particular to a method and device for measuring processor core power.
处理器可以包括多个处理器核。在多个处理器核的共享电源域的设计中,多个处理器核共享同一个电源域(供电网络和供电电路),处理器可以根据该电源域的电压和电流获取多个处理器核的实际功率总和。同时,处理器还可以根据数种可以计算估计功率的策略获取每个处理器核的估计功率。而每个处理器核的估计功率可以用于调整每个处理器核的频率和电压。该电源域的电压、电流可以由供电装置内的监测装置读取,基于实际读取的该电源域的电压、电流值,可以计算得出该电源域的实际功耗值,以实现对处理器的功耗管理。The processor may include multiple processor cores. In the design of the shared power domain of multiple processor cores, multiple processor cores share the same power domain (power supply network and power supply circuit), and the processor can obtain the power of multiple processor cores according to the voltage and current of the power domain. The sum of actual power. At the same time, the processor can also obtain the estimated power of each processor core according to several strategies that can calculate the estimated power. The estimated power of each processor core can be used to adjust the frequency and voltage of each processor core. The voltage and current of the power domain can be read by the monitoring device in the power supply device. Based on the actually read voltage and current values of the power domain, the actual power consumption value of the power domain can be calculated to realize the control of the processor Power management.
目前,针对处理器核的估计功率的估算策略本质上都可以理解为:基于每个处理器核的活动系数和功耗系数的功耗模型进行估算。例如在一种估算策略中,可以将处理器核划分为不同的模块,在一个预设周期内,每个模块被激活的次数为每个模块的活动系数,每个模块在该预设周期内被激活一次时产生的功率为每个模块的功耗系数。但是,在一个预设周期内,某个模块每次被激活时,其产生的功耗系数并不是定值,即可能一个模块某两次被激活时产生的功耗系数可能不同。而一个模块的功耗系数是通过线性回归的方式,对一个模块在一个预设周期下多次被激活时产生的功耗系数进行拟合得到的平均功耗,即将该拟合得到的平均功耗作为一个模块在一个预设周期内的功耗系数。因此,一个预设周期下,通过一个处理器核的每个模块的活动系数和功耗系数得到的该处理器核的估计功率与实际功率难免存在误差。当每个处理器核的估计功率与实际功率误差较大时,可导致由于估计功率误差较大的影响,可能导致处理器的实际功率总和超过处理器的最大供电电流的功率限制,也可能导致处理器的功率不能得到充分利用,从而导致处理器性能下降。At present, the estimation strategy for the estimated power of the processor cores can essentially be understood as: estimation based on the power consumption model of the activity coefficient and power consumption coefficient of each processor core. For example, in an estimation strategy, the processor core can be divided into different modules. In a preset period, the number of times each module is activated is the activity coefficient of each module, and each module is in the preset period. The power generated when activated once is the power consumption coefficient of each module. However, in a preset period, each time a module is activated, the power consumption coefficient generated by it is not a fixed value, that is, the power consumption coefficient generated by a module may be different when it is activated two times. The power consumption coefficient of a module is the average power consumption obtained by fitting the power consumption coefficient generated when a module is activated multiple times in a preset period through linear regression, that is, the average power consumption obtained by the fitting. The power consumption is used as the power consumption coefficient of a module in a preset period. Therefore, in a preset period, the estimated power and actual power of a processor core obtained by the activity coefficient and power consumption coefficient of each module of a processor core will inevitably have errors. When the estimated power of each processor core has a large error from the actual power, it may cause a large error in the estimated power, which may cause the total actual power of the processor to exceed the power limit of the maximum power supply current of the processor, or it may cause The processor's power cannot be fully utilized, resulting in a decrease in processor performance.
发明内容Summary of the invention
本申请实施例提供一种测量处理器核功率的方法和装置,能够降低处理器核的估计功率与实际功率的误差。The embodiments of the present application provide a method and device for measuring the power of a processor core, which can reduce the error between the estimated power of the processor core and the actual power.
为达到上述目的,本申请实施例采用如下技术方案:In order to achieve the foregoing objectives, the following technical solutions are adopted in the embodiments of this application:
第一方面,提供一种测量处理器核功率的方法,包括:根据处理器中每个处理器核的估计功率确定处理器核处理器所包含的多个处理器核的估计功率总和;确定处理器核处理器中多个处理器核的实际功率总和;根据估计功率总和以及实际功率总和对每个处理器核的估计功率进行校准,以得到每个处理器核的校准功率。In a first aspect, a method for measuring the power of a processor core is provided, which includes: determining the sum of the estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor; determining processing The total actual power of multiple processor cores in the processor core processor; the estimated power of each processor core is calibrated according to the total estimated power and the total actual power to obtain the calibrated power of each processor core.
也可以说,本申请可以根据估计功率总和与实际功率总和的相对关系,对每个处理器核的估计功率进行校准。这样,可以使得校准后每个处理器核的校准功率更能准确反映每个处理器核的实际功率,能够降低对多核处理器的估计功率与实际功率的误差,这样可以使得需要预留的功率余量减小,使得处理器可以尽可能的得到设计中的 最大性能,实现对处理器更高效的功耗管理。It can also be said that the present application can calibrate the estimated power of each processor core according to the relative relationship between the estimated power sum and the actual power sum. In this way, the calibrated power of each processor core after calibration can more accurately reflect the actual power of each processor core, and the error between the estimated power and the actual power of the multi-core processor can be reduced, so that the required power can be reserved. The margin is reduced, so that the processor can obtain the maximum performance in the design as much as possible, and realize more efficient power management of the processor.
在一种可能的设计中,该方法还包括:根据每个处理器核的校准功率对每个处理器核的频率和电压进行调整。In a possible design, the method further includes: adjusting the frequency and voltage of each processor core according to the calibration power of each processor core.
由于校准后的估计功率,即校准功率相对校准前的估计功率更接近每个处理器核的实际功率,因此,根据校准功率对处理器核的电压和频率进行调整时,更能使得处理器的性能发挥到更优。Since the estimated power after calibration, that is, the calibrated power is closer to the actual power of each processor core than the estimated power before calibration, when the voltage and frequency of the processor core are adjusted according to the calibrated power, the processor's Performance is better.
在一种可能的设计中,根据处理器核估计功率总和以及处理器核实际功率总和对每个处理器核的估计功率进行校准包括:根据处理器核估计功率总和以及处理器核实际功率总和确定校准系数;根据处理器核校准系数对每个处理器核的估计功率进行校准。In a possible design, calibrating the estimated power of each processor core according to the sum of the estimated power of the processor cores and the sum of the actual power of the processor cores includes: determining according to the sum of the estimated power of the processor cores and the sum of the actual power of the processor cores Calibration coefficient; the estimated power of each processor core is calibrated according to the processor core calibration coefficient.
该校准系数例如可以是实际功率总和与估计功率总和的比值η。当实际功率总和的值是估计功率总和的值的η倍时,可以近似的认为每个处理器核的实际功率也是估计功率的η倍。因此,根据处理器核的估计功率与η值可以得到处理器核的校准功率,使该校准功率相对估计功率更接近处理器核的实际功率。当估计功率更接近实际功率时,功率余量就可以设置的较小,从而使得处理器性能发挥到更优。The calibration coefficient may be, for example, the ratio η of the actual power sum to the estimated power sum. When the value of the total actual power is n times the value of the estimated power sum, it can be approximated that the actual power of each processor core is also n times the estimated power. Therefore, the calibrated power of the processor core can be obtained according to the estimated power of the processor core and the value of η, so that the calibrated power is closer to the actual power of the processor core than the estimated power. When the estimated power is closer to the actual power, the power headroom can be set to be smaller, so that the processor performance is better.
在一种可能的设计中,根据处理器中每个处理器核的估计功率确定处理器所包含的多个处理器核的估计功率总和,包括:根据处理器中每个处理器核的估计功率和多个处理器核的电源域的静态功率,确定多个处理器核的估计功率总和;其中,多个处理器核的电源域的静态功率是指多个处理器核的电源域的漏电电流所产生的功耗。In a possible design, determining the total estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor includes: according to the estimated power of each processor core in the processor And the static power of the power domain of multiple processor cores, determine the sum of the estimated power of multiple processor cores; wherein, the static power of the power domain of multiple processor cores refers to the leakage current of the power domain of multiple processor cores The resulting power consumption.
由于估计功率总和与实际功率总和还是存在误差,这样在计算估计功率总和时,如果还考虑处理器核电源域的静态功率时,可以使得多个处理器核的估计功率总和更准确的表征真实的功率情况。Since there is still an error between the estimated power sum and the actual power sum, when calculating the estimated power sum, if the static power of the processor core power domain is also considered, the sum of the estimated power of multiple processor cores can be made to represent the real power more accurately. Power situation.
在一种可能的设计中,在确定多个处理器核的估计功率总和之前,该方法还包括:确定每个处理器核的估计功率。即在确定估计功率总和之前,可以先确定每个处理器核对应的估计功率。In a possible design, before determining the sum of the estimated power of multiple processor cores, the method further includes: determining the estimated power of each processor core. That is, before determining the total estimated power, the estimated power corresponding to each processor core can be determined first.
在一种可能的设计中,确定每个处理器核的估计功率包括:根据每个处理核的活动功率和每个处理器核的基础功率确定每个处理器核的估计功率;其中,活动功率用于指示每个处理核的至少一个功耗表征信号在处于活动状态时所消耗的功率,基础功率用于指示每个处理核的至少一个功耗表征信号在未处于活动状态时每个处理器核所消耗的功耗。In a possible design, determining the estimated power of each processor core includes: determining the estimated power of each processor core according to the active power of each processing core and the basic power of each processor core; where, the active power Used to indicate the power consumed by at least one power consumption characterization signal of each processing core when it is in an active state, and base power is used to indicate at least one power consumption characterization signal of each processing core when each processor is not in an active state The power consumed by the core.
这是考虑到,为每个处理器核选取的功耗表征信号可能并未覆盖到该处理器核的全部的功耗事件(即使可以覆盖到,B的值为0),因此,在得到基础功率时,可以根据活动功率以及基础功率获取每个处理器核的估计功率,使得估计功率更能准确的反应处理器核的实际功率。This is considering that the power consumption characterization signal selected for each processor core may not cover all the power consumption events of the processor core (even if it can be covered, the value of B is 0). Therefore, after obtaining the basic For power, the estimated power of each processor core can be obtained according to the active power and the basic power, so that the estimated power can more accurately reflect the actual power of the processor core.
在一种可能的设计中,每个处理器核的活动功率通过如下方式确定:根据每个处理器核的至少一个功耗表征信号的活动系数和至少一个功耗表征信号的功耗系数得到所述活动功率,每个功耗表征信号的活动系数用于反映每个功耗表征信号处于活动状态时的系数,每个功耗表征信号的功耗系数用于反映每个功耗表征信号每次处于活动状态时所消耗的功耗。例如可以将每个功耗表征信号的活动系数和功耗系数相乘,再 将每个功耗表征信号对应的乘积求和,即可得到一个处理器核的活动功率。In a possible design, the active power of each processor core is determined in the following manner: the activity coefficient of at least one power consumption characteristic signal of each processor core and the power consumption coefficient of at least one power consumption characteristic signal are obtained. Said activity power, the activity coefficient of each power consumption characterization signal is used to reflect the coefficient when each power consumption characterization signal is in the active state, and the power consumption coefficient of each power consumption characterization signal The power consumed when in an active state. For example, the activity coefficient of each power consumption characterization signal can be multiplied by the power consumption coefficient, and then the products corresponding to each power consumption characterization signal can be summed to obtain the active power of a processor core.
在一种可能的设计中,该方法还包括:根据实际功率总和以及每个处理器核的至少一个功耗表征信号的活动系数,调整每个处理器核的至少一个功耗表征信号的功耗系数。In a possible design, the method further includes: adjusting the power consumption of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core coefficient.
一般在得到功耗系数时,是根据对每个处理器核的估计功率进行测量,进而根据估计功率和活动系数拟合得到功耗系数。但是测量得到的估计功率总有误差,因此,本申请中,如果根据实际功率总和拟合得到的功耗系数时,该功耗系数用于计算得到的估计功率会相对更准确。Generally, when the power consumption coefficient is obtained, the estimated power of each processor core is measured, and then the power consumption coefficient is obtained by fitting the estimated power and the activity coefficient. However, the estimated power obtained by measurement always has an error. Therefore, in this application, if the power consumption coefficient obtained is fitted according to the sum of the actual power, the estimated power obtained by the calculation of the power consumption coefficient will be relatively more accurate.
第二方面,提供一种测量处理器核功率的装置,包括:功耗监测器和频率控制器,频率控制器,用于根据功耗监测器得到的处理器中每个处理器核的估计功率确定处理器所包含的多个处理器核的估计功率总和;频率控制器,还用于确定处理器中多个处理器核的实际功率总和;频率控制器,还用于根据估计功率总和以及实际功率总和对每个处理器核的估计功率进行校准,以得到每个处理器核的校准功率。第二方面的有益效果可以参见第一方面对测量处理器核功率的方法的说明。In a second aspect, a device for measuring processor core power is provided, including: a power consumption monitor and a frequency controller, and the frequency controller is used to obtain the estimated power of each processor core in the processor according to the power consumption monitor Determine the total estimated power of multiple processor cores included in the processor; the frequency controller is also used to determine the total actual power of multiple processor cores in the processor; the frequency controller is also used to determine the total estimated power and actual power The power sum calibrates the estimated power of each processor core to obtain the calibrated power of each processor core. For the beneficial effects of the second aspect, reference may be made to the description of the method for measuring processor core power in the first aspect.
在一种可能的设计中,频率控制器还用于:根据每个处理器核的校准功率对每个处理器核的频率和电压进行调整。In a possible design, the frequency controller is also used to adjust the frequency and voltage of each processor core according to the calibration power of each processor core.
在一种可能的设计中,频率控制器用于:根据估计功率总和以及实际功率总和确定校准系数;根据校准系数对每个处理器核的估计功率进行校准。In a possible design, the frequency controller is used to determine the calibration coefficient according to the total estimated power and the total actual power; and calibrate the estimated power of each processor core according to the calibration coefficient.
在一种可能的设计中,频率控制器用于:根据处理器中每个处理器核的估计功率和多个处理器核的电源域的静态功率,确定多个处理器核的估计功率总和;其中,多个处理器核的电源域的静态功率是指多个处理器核的电源域的漏电电流所产生的功耗。In a possible design, the frequency controller is used to: determine the sum of the estimated power of multiple processor cores according to the estimated power of each processor core in the processor and the static power of the power domain of the multiple processor cores; where The static power of the power domain of multiple processor cores refers to the power consumption generated by the leakage current of the power domain of multiple processor cores.
在一种可能的设计中,功耗监测器用于:确定每个处理器核的估计功率。In one possible design, the power monitor is used to determine the estimated power of each processor core.
在一种可能的设计中,功耗监测器用于:根据每个处理核的活动功率和每个处理器核的基础功率确定每个处理器核的估计功率;其中,活动功率用于指示每个处理核的至少一个功耗表征信号在处于活动状态时所消耗的功率,基础功率用于指示每个处理核的至少一个功耗表征信号在未处于活动状态时每个处理器核所消耗的功耗。In a possible design, the power monitor is used to determine the estimated power of each processor core according to the active power of each processing core and the basic power of each processor core; where the active power is used to indicate each The power consumed by at least one power consumption characterizing signal of each processing core when it is in an active state, and the basic power is used to indicate the power consumed by each processor core when at least one power consumption characterizing signal of each processing core is not in an active state. Consumption.
在一种可能的设计中,功耗监测器用于:根据每个处理器核的至少一个功耗表征信号的活动系数和至少一个功耗表征信号的功耗系数得到活动功率,每个功耗表征信号的活动系数用于反映每个功耗表征信号处于活动状态时的系数,每个功耗表征信号的功耗系数用于反映每个功耗表征信号每次处于活动状态时所消耗的功耗。In a possible design, the power consumption monitor is used to obtain the active power according to the activity coefficient of at least one power consumption characterization signal and the power consumption coefficient of at least one power consumption characterization signal of each processor core, and each power consumption characterization The activity coefficient of the signal is used to reflect the coefficient when each power consumption characterization signal is in the active state, and the power consumption coefficient of each power consumption characterization signal is used to reflect the power consumption of each power consumption characterization signal each time it is active .
在一种可能的设计中,频率控制器还用于:根据实际功率总和以及每个处理器核的至少一个功耗表征信号的活动系数,调整每个处理器核的至少一个功耗表征信号的功耗系数。In a possible design, the frequency controller is also used to adjust the activity coefficient of at least one power consumption characterization signal of each processor core according to the total actual power and the activity coefficient of at least one power consumption characterization signal of each processor core. Power consumption factor.
第三方面,提供一种计算机可读存储介质,包括程序或指令,当处理器核程序或指令被处理器运行时,如第一方面以及第一方面的任一种可能的设计所述的方法被执行。In a third aspect, a computer-readable storage medium is provided, including a program or instruction, when the processor core program or instruction is executed by a processor, such as the method described in the first aspect and any one of the possible designs of the first aspect Be executed.
第四方面,提供一种计算机程序产品,当计算机程序产品在计算机上运行时,使得电子设备执行如第一方面以及第一方面的任一种可能的设计所述的方法。In a fourth aspect, a computer program product is provided. When the computer program product runs on a computer, the electronic device executes the method described in the first aspect and any one of the possible designs of the first aspect.
第五方面,提供一种通信装置,该通信装置包括第二方面或第二方面的任一种可 能的设计对应的装置。In a fifth aspect, a communication device is provided. The communication device includes the second aspect or a device corresponding to any one of the possible designs of the second aspect.
第六方面,提供一种芯片,该芯片包括第二方面或第二方面的任一种可能的设计对应的装置。In a sixth aspect, a chip is provided, and the chip includes the second aspect or a device corresponding to any possible design of the second aspect.
图1为本申请实施例提供的一种处理的可应用的通信装置;FIG. 1 is an applicable communication device for processing provided by an embodiment of this application;
图2为本申请实施例提供的一种处理器的结构示意图;FIG. 2 is a schematic structural diagram of a processor provided by an embodiment of the application;
图3为本申请实施例提供的一种测量处理器核功率的方法流程图;FIG. 3 is a flowchart of a method for measuring processor core power according to an embodiment of the application;
图4为本申请实施例提供的一种确定功耗系数和基础功率的方法示意图;FIG. 4 is a schematic diagram of a method for determining a power consumption coefficient and basic power provided by an embodiment of the application;
图5为本申请实施例提供的一种硅功耗系数校准的流程示意图;FIG. 5 is a schematic flowchart of a silicon power consumption coefficient calibration process provided by an embodiment of the application;
图6为本申请实施例提供的一种计算系统的框图。Fig. 6 is a block diagram of a computing system provided by an embodiment of the application.
本申请可应用于各类多处理器核共电源域设计的处理器。其中,获取处理器每个处理器核的估计功耗,是对处理器进行高效电源管理的必要条件。This application can be applied to all types of processors designed in a common power domain with multiple processor cores. Among them, obtaining the estimated power consumption of each processor core of the processor is a necessary condition for efficient power management of the processor.
由于多处理器核共电源域的设计,每个处理器核的实际功率无法直接通过测量获得,因此,需要通过一定的策略对每个处理器核的功率进行估算。但是,通过功率估算方法得到的每个处理器核的功率,势必与每个处理器核的实际功率存在误差,因此,本申请用于对估算得到的功率进行进一步校正,使得校正后每个处理器核的校准功率相对校正前的估计功率更近似于每个处理器核的实际功率。Due to the design of a common power domain for multiple processor cores, the actual power of each processor core cannot be directly obtained by measurement. Therefore, it is necessary to estimate the power of each processor core through a certain strategy. However, the power of each processor core obtained by the power estimation method is bound to have an error with the actual power of each processor core. Therefore, this application is used to further correct the estimated power, so that each process after the correction The calibrated power of the processor core is more similar to the actual power of each processor core than the estimated power before correction.
如图1所示,本申请提供的处理器可以应用于多种通信装置中,该通信装置例如可以为芯片或终端设备。该芯片可以为具有多处理器核的系统级芯片(system on chip,SoC)。该终端设备可以为移动终端,例如为手机11、pad12或笔记本电脑13等;终端设备还可以非移动终端,例如可以为台式电脑14。若终端设备为移动终端,其处理器可以为多处理器核处理器,多处理器核处理器例如可以为SoC。As shown in FIG. 1, the processor provided in the present application can be applied to various communication devices, and the communication device can be, for example, a chip or a terminal device. The chip may be a system-on-chip (SoC) with multiple processor cores. The terminal device may be a mobile terminal, such as a mobile phone 11, a pad 12, or a notebook computer 13, etc.; the terminal device may also be a non-mobile terminal, such as a desktop computer 14. If the terminal device is a mobile terminal, its processor may be a multi-processor core processor, and the multi-processor core processor may be, for example, an SoC.
图2为本申请实施例提供的一种多处理器核共电源域设计的处理器20。以该处理器20包括4个处理器核(处理器核0、处理器核1、处理器核2以及处理器核3)为例。处理器20可以包括处理器核电源平面21和非处理器核电源平面22。需要说明的是,图2示出的处理器20仅为处理器的一种示例,处理器还可以包括其他电源平面设计。其中,处理器核电源平面21可以包括4个处理器核、与每个处理器核对应的功耗监测器211、供电电路212以及频率控制器213。非处理器核电源平面22可以包括外部缓存、内部存储器、通用单元、加速器以及输入/输出控制单元&接口单元。需要说明的是,功耗监测器211在实际应用中也可以处于其他电源平面上。FIG. 2 is a processor 20 with a multi-processor core common power domain design provided by an embodiment of the application. Take the processor 20 including four processor cores (processor core 0, processor core 1, processor core 2, and processor core 3) as an example. The processor 20 may include a processor core power plane 21 and a non-processor core power plane 22. It should be noted that the processor 20 shown in FIG. 2 is only an example of the processor, and the processor may also include other power supply plane designs. The processor core power plane 21 may include 4 processor cores, a power consumption monitor 211 corresponding to each processor core, a power supply circuit 212, and a frequency controller 213. The non-processor core power plane 22 may include an external cache, an internal memory, a general-purpose unit, an accelerator, and an input/output control unit & interface unit. It should be noted that the power consumption monitor 211 may also be located on other power planes in practical applications.
功耗监测器211可以通过周期性地监测对应的处理器核的功耗表征信号的行为,得到为该处理器核初步估算的估计功率,并将估计功率发送给频率控制器213,频率控制器213可用于汇总各个功耗监测器211发送的估计功率,最终确定处理器20运行时的估计功率总和,为处理器20的频率和电压调节提供数据支撑。在图2示出的处理器20中,频率控制器213位于处理器核电源平面21中,但是在其他一些应用中,频率控制器213也可以位于其他电源平面。供电电路212可以向频率控制器213提供处理器核电源平面21的电压和电流,频率控制器213可以根据电压和电流得到处理器20各个处理器核当前的实际功率总和。The power consumption monitor 211 may periodically monitor the behavior of the power consumption characterization signal of the corresponding processor core to obtain the estimated power initially estimated for the processor core, and send the estimated power to the frequency controller 213. The frequency controller 213 can be used to summarize the estimated power sent by each power consumption monitor 211, and finally determine the total estimated power when the processor 20 is running, and provide data support for the frequency and voltage adjustment of the processor 20. In the processor 20 shown in FIG. 2, the frequency controller 213 is located in the processor core power plane 21, but in some other applications, the frequency controller 213 may also be located in other power planes. The power supply circuit 212 can provide the frequency controller 213 with the voltage and current of the processor core power plane 21, and the frequency controller 213 can obtain the current total actual power of each processor core of the processor 20 according to the voltage and current.
对于上文提到的,本申请可以对估算得到的功率进行进一步校正,使得校正后每个处理器核的估计功率相对校正前的估计功率更近似于每个处理器核的实际功率,在本申请实施例中,具体方案可以为:频率控制器213可以根据供电电路212提供的电压和电流得到的实际功率总和,与根据功耗监测器211发送的估计功率得到的估计功率总和对每个处理器核的估计功率进行校准,得到校准后每个处理器核的校准功率。由于估计功率总和相对实际功率总和会存在误差,在根据估计功率总和与实际功率总和得到估计功率总和与实际功率总和的误差的相对关系时,可以根据该相对关系与每个处理器核的估计功率得到更接近每个处理器核的实际功率的校准功率。也就是说,本申请在得到每个处理器核的估计功率时,还可以对每个处理器核的估计功率进行进一步的校准,使得频率控制器213可以根据更为准确的校准功率进行对每个处理器核运行时的频率和电压进行调整。As mentioned above, this application can further correct the estimated power so that the estimated power of each processor core after correction is more similar to the actual power of each processor core than the estimated power before correction. In the application embodiment, the specific solution may be: the frequency controller 213 may process the sum of the actual power obtained according to the voltage and current provided by the power supply circuit 212, and the estimated power obtained according to the estimated power sent by the power consumption monitor 211. The estimated power of the processor core is calibrated to obtain the calibrated power of each processor core after calibration. Since the total estimated power will have an error relative to the total actual power, when the relative relationship between the total estimated power and the error of the actual power total is obtained from the total estimated power and the total actual power, the relative relationship can be compared with the estimated power of each processor core. Get the calibrated power closer to the actual power of each processor core. That is to say, when the estimated power of each processor core is obtained in this application, the estimated power of each processor core may be further calibrated, so that the frequency controller 213 can perform the calibration of each processor core according to a more accurate calibration power. Adjust the frequency and voltage of each processor core when it is running.
在本申请实施例中,可以对频率控制器213的软件架构进行改进实现本申请的方案,例如在频率控制器213中添加用于实现本申请方案的固件;也可以对频率控制器213的硬件架构进行改进实现本申请的方案;也可以是对频率控制器213的软件架构和硬件架构都进行改进实现本申请的方案,本申请对此不做限定。In the embodiment of the present application, the software architecture of the frequency controller 213 can be improved to implement the solution of the present application, for example, firmware used to implement the solution of the present application can be added to the frequency controller 213; the hardware of the frequency controller 213 can also be modified. The architecture is improved to implement the solution of the present application; it is also possible to improve both the software architecture and the hardware architecture of the frequency controller 213 to implement the solution of the present application, which is not limited in this application.
下面对本申请的方案进行进一步说明。The solution of the present application will be further explained below.
本申请实施例提供一种测量处理器核功率的方法,如图3所示,该方法包括:The embodiment of the present application provides a method for measuring the power of a processor core. As shown in FIG. 3, the method includes:
301、确定处理器的多个处理器核的估计功率。301. Determine estimated power of multiple processor cores of a processor.
在一些实施例中,步骤301-步骤304可以是周期性的执行,也就是每个预设周期下,可以对每个处理器核的估计功率进行一次校准。一个预设周期例如可以为100us,也可以为其他值,本申请不做限定。In some embodiments, steps 301 to 304 may be performed periodically, that is, in each preset period, the estimated power of each processor core may be calibrated once. A preset period may be, for example, 100 us, or other values, which is not limited in this application.
在一些实施例中,当处理器20运行程序时,每个功耗监测器211可以为对应的处理器核进行周期性的功率估计,得到每个预设周期下每个处理器核的估计功率。该估计功率可以是对应的处理器核的活动功率。活动功率用于指示每个处理核的至少一个功耗表征信号在处于活动状态时所消耗的功率。其中,对于一个功耗表征信号,其活动状态可以是该功耗表征信号处于翻转或高电平状态。In some embodiments, when the processor 20 runs the program, each power consumption monitor 211 may perform periodic power estimation for the corresponding processor core to obtain the estimated power of each processor core in each preset period. . The estimated power may be the active power of the corresponding processor core. The active power is used to indicate the power consumed by at least one power consumption characterization signal of each processing core when the signal is in an active state. Wherein, for a power consumption characterization signal, its active state may be that the power consumption characterization signal is in an overturned or high level state.
其中,每个处理器核的活动功率可以通过如下方式确定:根据每个处理器核的至少一个功耗表征信号的功耗系数和至少一个功耗表征信号的活动系数得到活动功率。其中,对于任一个处理器核,一个处理器核可以对应多个功耗表征信号,一个功耗表征信号对应一个活动系数和一个功耗系数;对于一个处理器核,功耗表征信号为参与统计一个处理器核的估计功率的信号,每个功耗表征信号的活动系数用于反映每个功耗表征信号处于活动状态时的系数。例如对应一个功耗表征信号,其对应的活动系数可以理解为该功耗表征信号的翻转次数或处于高电平的时钟周期数。每个功耗表征信号的功耗系数用于反映每个功耗表征信号每次处于活动状态时所消耗的功耗。Wherein, the active power of each processor core may be determined in the following manner: the active power is obtained according to the power consumption coefficient of at least one power consumption characterization signal and the activity coefficient of at least one power consumption characterization signal of each processor core. Among them, for any processor core, a processor core can correspond to multiple power consumption characterization signals, and one power consumption characterization signal corresponds to an activity coefficient and a power consumption coefficient; for a processor core, the power consumption characterization signal is participation statistics The estimated power signal of a processor core, and the activity coefficient of each power consumption characterization signal is used to reflect the coefficient when each power consumption characterization signal is in an active state. For example, corresponding to a power consumption characterization signal, its corresponding activity coefficient can be understood as the number of times the power consumption characterization signal is inverted or the number of clock cycles at a high level. The power consumption coefficient of each power consumption characterization signal is used to reflect the power consumption of each power consumption characterization signal each time it is in an active state.
其中,用于确定活动功率的功耗系数可以是通过事先的线性拟合确定的。例如,每个处理器核的估计功率(活动功率)可以是根据如下公式一的计算方式确定的:Wherein, the power consumption coefficient used to determine the active power may be determined by linear fitting in advance. For example, the estimated power (active power) of each processor core can be determined according to the calculation method of the following formula 1:
P
m=C
0W
0+C
1W
1+C
2W
2+…+C
nW
n,其中,P
m表示第m个处理器核在一个预设周期内的估计功率,C
0、C
1、C
2…C
n表示第m个处理器核的n个功耗表征信号分别对应的活动系数,W
0、W
1、W
2…W
n表示第m个处理器核的n个功耗表征信号分别对应的 功耗系数。m和n为大于或等于0的整数。
P m =C 0 W 0 +C 1 W 1 +C 2 W 2 +...+C n W n , where P m represents the estimated power of the m-th processor core in a preset period, C 0 , C 1. C 2 …C n represents the activity coefficients corresponding to the n power consumption characterization signals of the mth processor core, W 0 , W 1 , W 2 …W n represents the n power consumption of the mth processor core Characterize the power consumption coefficient corresponding to the signal respectively. m and n are integers greater than or equal to zero.
302、根据处理器中每个处理器核的估计功率(活动功率)确定处理器所包含的多个处理器核的估计功率总和。302. Determine the total estimated power of multiple processor cores included in the processor according to the estimated power (active power) of each processor core in the processor.
将每个处理器核的估计功率相加,可以得到多个处理器核的估计功率总和。Add the estimated power of each processor core to get the sum of the estimated power of multiple processor cores.
在一些实施例中,功耗监测器211可以将对应的处理器核的估计功率发送给频率控制器213,频率控制器213根据接收到的多个处理器核的估计功率计算得到处理器多个处理器核的估计功率总和。In some embodiments, the power consumption monitor 211 may send the estimated power of the corresponding processor core to the frequency controller 213, and the frequency controller 213 calculates multiple processors based on the received estimated power of the multiple processor cores. The sum of the estimated power of the processor cores.
例如,估计功率总和的计算方式可以如公式二:P
total=P
0+P
1+P
2…+P
m,其中,P
total表示一个预设周期下,多个处理器核的估计功率总和,P
0、P
1、P
2…P
m表示m+1个处理器核分别对应的估计功率。
For example, the calculation method of the estimated power sum can be as in formula 2: P total =P 0 +P 1 +P 2 …+P m , where P total represents the sum of estimated power of multiple processor cores in a preset period, P 0 , P 1 , P 2 ... P m represent the estimated power corresponding to m+1 processor cores.
在一些实施例中,在计算估计功率总和时,每个预设周期下,在监测每个处理器核的功耗系数时,还可以监测处理器核电源平面21的静态功率。对于处理器核电源平面21,静态功率即泄漏功耗,是指处理器核电源平面21中的多个处理器核的电源域的漏电电流所产生的功耗。静态功耗的获取方式可以有多种。在一些实施例中,静态功耗可以依据漏电电流公式得到,即P
leak=f(V,T),P
leak表示一个预设周期下,处理器核电源平面21的静态功率,即将静态功率以基于处理器核电源平面21的电压和温度的关系进行计算。如此一来,估计功率总和的计算方式还可以如公式三:P
total=P
0+P
1+P
2…+P
m+P
leak。静态功率P
leak的加入,可以使得多个处理器核的估计功率总和更准确的表征真实的功率情况。
In some embodiments, when calculating the total estimated power, in each preset period, when monitoring the power consumption coefficient of each processor core, the static power of the processor core power plane 21 may also be monitored. For the processor core power plane 21, static power, that is, leakage power consumption, refers to the power consumption generated by the leakage current of the power domains of multiple processor cores in the processor core power plane 21. There are many ways to obtain static power consumption. In some embodiments, the static power consumption can be obtained according to the leakage current formula, that is, P leak = f (V, T), P leak represents the static power of the processor core power plane 21 in a preset period, that is, the static power is The calculation is based on the relationship between the voltage and temperature of the processor core power plane 21. In this way, the calculation method of the estimated power sum can also be as in formula 3: P total =P 0 +P 1 +P 2 …+P m +P leak . The addition of the static power P leak can make the sum of the estimated power of multiple processor cores more accurately characterize the real power situation.
在一些实施例中,获取静态功耗时的电压和温度可以由供电电路212提供给频率控制器213,由频率控制器213根据电压和温度计算得到静态功率。In some embodiments, the voltage and temperature when the static power consumption is obtained may be provided by the power supply circuit 212 to the frequency controller 213, and the frequency controller 213 calculates the static power according to the voltage and temperature.
303、确定处理器中多个处理器核的实际功率总和。303. Determine the total actual power of multiple processor cores in the processor.
在一些实施例中,在一个预设周期下,可以获取处理器核电源平面21的电源域的供电电压V和供电电流I,通过公式四:P
total'=VI,计算得到一个预设周期下多个处理器核的实际功耗总和。其中,P
total'表示一个预设周期下,多个处理器核的实际功耗总和。
In some embodiments, in a preset period, the power supply voltage V and the power supply current I of the power domain of the processor core power plane 21 can be obtained. According to formula 4: P total '=VI, it is calculated that under a preset period The sum of the actual power consumption of multiple processor cores. Among them, P total'represents the total actual power consumption of multiple processor cores in a preset period.
在一些实施例中,可以由供电电路212获取供电电压V和供电电流I,将获取得到的供电电压V和供电电流I提供给频率控制器213,由频率控制器213根据供电电压V和供电电流I计算得到多个处理器核的实际功耗总和P
total'。
In some embodiments, the power supply circuit 212 may obtain the power supply voltage V and the power supply current I, and provide the obtained power supply voltage V and the power supply current I to the frequency controller 213, and the frequency controller 213 determines the power supply voltage V and the power supply current I I calculates the total actual power consumption of multiple processor cores P total'.
304、根据估计功率总和以及实际功率总和对每个处理器核的估计功率进行校准,得到每个处理器核的校准功率。304. Calibrate the estimated power of each processor core according to the total estimated power and the total actual power to obtain the calibrated power of each processor core.
在一些实施例中,可以根据估计功率总和以及实际功率总和的相对关系,对每个处理器核的估计功率进行校准,得到校准后每个处理器核的校准功率。In some embodiments, the estimated power of each processor core may be calibrated according to the relative relationship between the total estimated power and the total actual power to obtain the calibrated power of each processor core after calibration.
在一些实施例中,可以根据一个预设周期下得到的估计功率总和P
total和实际功率总和P
total'的相对关系,获得校准系数η,例如校准系数η的计算方式如公式五:η=P
total'/P
total。根据校准系数η对每个处理器核的估计功率P
m进行校准,得到校准后每个处理器核的校准功率P
m'。
In some embodiments, the calibration coefficient η can be obtained according to the relative relationship between the estimated power sum P total and the actual power sum P total ′ obtained in a preset period. For example, the calculation method of the calibration coefficient η is as shown in formula 5: η=P total '/P total . The estimated power P m of each processor core is calibrated according to the calibration coefficient η , and the calibrated power P m 'of each processor core after calibration is obtained.
其中,η的值可以是大于或等于1的数值,也可以是小于1的数值。Wherein, the value of η may be a value greater than or equal to 1, or a value less than 1.
在一些实施例中,当得到校准系数η时,可以说明实际功率总和P
total'是估计功率 总和P
total的η倍。类似的,可以认为每个处理器核的实际功率也大约是相应的处理器核的估计功率P
m的η倍。因此,以校准系数η校准每个处理器核的估计功率P
m,可以得到每个处理器核校准后的校准功率P
m',该校准功率P
m'相对估计功率P
m更能准确的反应每个处理器核的实际功率。因此,每个处理器核的校准功率P
m'的计算方式可以如公式六:P
m'=η*P
m。也就是说,每个处理器核的校准功率P
m'是对应的处理器核的估计功率P
m的η倍。
In some embodiments, when the calibration coefficient η is obtained, it can be stated that the actual power sum P total ′ is η times the estimated power sum P total. Similarly, it can be considered that the actual power of each processor core is approximately n times the estimated power P m of the corresponding processor core. Thus, the calibration factor to calibrate each processor core η estimated power P m, P m can be calibrated power after each calibration processor core ', the calibrated power P m' power P m is more accurate response relative estimation The actual power of each processor core. Therefore, the calculation method of the calibration power P m 'of each processor core can be as in formula 6: P m '=η*P m . That is, the calibrated power P m ′ of each processor core is n times the estimated power P m of the corresponding processor core.
举例来说,校准系数为1.1,即实际功率总和是估计功率总和的1.1倍。假设第m个处理器核的估计功率P
m为5w,那么认为第m个处理器核的实际功率也大约是估计功率的1.1倍,因此,根据公式六,第m个处理器核的校准功率P
m'为5.5w。该校准功率5.5w更接近第m个处理器核的实际功率。
For example, the calibration coefficient is 1.1, that is, the total actual power is 1.1 times the total estimated power. Assuming that the estimated power P m of the m-th processor core is 5w, then the actual power of the m-th processor core is also approximately 1.1 times the estimated power. Therefore, according to formula 6, the calibrated power of the m-th processor core P m 'is 5.5w. The calibrated power of 5.5w is closer to the actual power of the m-th processor core.
步骤304可以是频率控制器213执行。Step 304 may be executed by the frequency controller 213.
305、根据每个处理器核的校准功率对每个处理器核的频率和电压进行调整。305. Adjust the frequency and voltage of each processor core according to the calibration power of each processor core.
频率控制器213可以将得到的每个处理器核的校准功率发送给每个处理器核对应的功耗监测器211。每个功耗监测器211可以根据得到的校准功率调整相应的处理器核的频率和电压。The frequency controller 213 may send the obtained calibration power of each processor core to the power consumption monitor 211 corresponding to each processor core. Each power consumption monitor 211 can adjust the frequency and voltage of the corresponding processor core according to the obtained calibration power.
由此,本申请实施例通过在得到多核处理器每个处理器核的估计功率时,还可以进一步根据多个处理器核的实际功率总和以及多个处理器核的估计功率总和的相对关系,对每个处理器核的估计功率进行校准,使得校准后每个处理器核的校准功率更能准确反映每个处理器核的实际功率,能够降低对对于多核处理器估算每个处理器核的估计功率与实际功率的误差,实现更高效的功耗管理。例如当处理器核的估计功率小于实际功率,且估计功率与实际功率误差较大时,那么处理器会继续控制该处理器核运行,但是实际功率有可能已经达到了过流控制的功耗限制,而利用本申请得到校准后的估计功率时,可以有效防止处理器核的实际功率达到功耗限制;当处理器核的估计功率大于实际功率时,这时由于过高的估计了处理器核的估计功率,但是实际功率并未达到估计功率值,因此会存在较多的功率余量未被使用,而利用本申请得到校准后的估计功率时,可以使得处理器核的估计功率更接近实际功率,功率余量可被充分利用,可实现对处理器更高效的功耗管理。Therefore, in the embodiment of the present application, when the estimated power of each processor core of the multi-core processor is obtained, the relative relationship between the sum of actual power of multiple processor cores and the sum of estimated power of multiple processor cores can be further used to obtain the estimated power of each processor core. Calibrate the estimated power of each processor core, so that the calibrated power of each processor core after calibration can more accurately reflect the actual power of each processor core, which can reduce the estimation of each processor core for multi-core processors. Estimate the error between the estimated power and the actual power to achieve more efficient power management. For example, when the estimated power of the processor core is less than the actual power, and the error between the estimated power and the actual power is large, the processor will continue to control the operation of the processor core, but the actual power may have reached the power consumption limit of over-current control. , And when the estimated power after calibration is obtained using this application, the actual power of the processor core can be effectively prevented from reaching the power consumption limit; when the estimated power of the processor core is greater than the actual power, the processor core is estimated too high at this time The estimated power of the processor core, but the actual power does not reach the estimated power value, so there will be more power margins that have not been used. When the estimated power after calibration is obtained using this application, the estimated power of the processor core can be closer to the actual Power, power headroom can be fully utilized, which can achieve more efficient power management of the processor.
以上步骤301~305可以发生在芯片已应用到终端设备中时,对芯片中每个处理器核的估计功率的校准。The above steps 301 to 305 can occur when the chip has been applied to the terminal device, and the estimated power of each processor core in the chip is calibrated.
考虑到为每个处理器核选取的功耗表征信号可能并未覆盖到该处理器核的全部的功耗事件,因此,在计算每个处理器核的估计功率时,还可以考虑每个处理器核的基础功率。基础功率可以理解为每个处理器核的至少一个功耗表征信号在未处于活动状态时每个处理器核所消耗的功率。该基础功率可以是在芯片的硅前仿真时得到。因此,在一些实施例中,在步骤301之前,可以进行芯片的硅前仿真,以获得多个处理器核的基础功率。因此,在步骤301之前,如图4所示,该方法还可以包括:Considering that the power consumption characteristic signal selected for each processor core may not cover all the power consumption events of the processor core, therefore, when calculating the estimated power of each processor core, you can also consider each processing The basic power of the processor core. The basic power can be understood as the power consumed by each processor core when at least one power consumption characterization signal of each processor core is not in an active state. The basic power can be obtained during the pre-silicon simulation of the chip. Therefore, in some embodiments, before step 301, a pre-silicon simulation of the chip may be performed to obtain the basic power of multiple processor cores. Therefore, before step 301, as shown in FIG. 4, the method may further include:
401、确定每个处理器核对应的功耗表征信号以及仿真时使用的测试用例。401. Determine a power consumption characterization signal corresponding to each processor core and a test case used in simulation.
在一些实施例中,选取功耗表征信号时,应该本着在覆盖全部功耗场景的基础上,尽量精简信号数量的原则进行选取。In some embodiments, when selecting the power consumption characterization signal, the selection should be based on the principle of reducing the number of signals as much as possible on the basis of covering all power consumption scenarios.
在一些实施例中,功耗表征信号的选取标准可以有:控制大量寄存器的时钟门控 信号;对于功耗事件有表征意义的信号,如发射队列的发射信号。In some embodiments, the selection criteria for the power consumption characterization signal may include: clock gating signals that control a large number of registers; signals that have characterization significance for power consumption events, such as the transmit signal of the transmit queue.
在一些实施例中,测试用例的选取原则上需要覆盖所有可能出现的功耗场景。一旦测试用例的功耗场景覆盖不全面,可能出现拟合得到的功耗系数偏离真实值过大的情况。In some embodiments, the selection of test cases needs to cover all possible power consumption scenarios in principle. Once the power consumption scenario coverage of the test case is not comprehensive, it may happen that the power consumption coefficient obtained by the fitting deviates too much from the true value.
步骤401可以由设计人员执行。Step 401 can be performed by a designer.
402、获取处理器运行测试用例时,每个处理器核对应的数据点,数据点包括多每个处理器核的多个功耗表征信号对应的活动系数,以及每个处理器核的估计功率。402. Obtain the data points corresponding to each processor core when the processor runs the test case, the data points include activity coefficients corresponding to multiple power consumption characterization signals of each processor core, and the estimated power of each processor core .
在一些实施例中,可以通过PTPX(prime-time PX)仿真运行测试用例,获取每个处理器核用以拟合基础功率的数据点。对于第m个处理器核,该数据点包括第m个处理器核的n个功耗表征信号对应的活动系数:C
0、C
1、C
2…C
n,以及第m个处理器核对应的估计功率P
m”。
In some embodiments, the test case can be run through PTPX (prime-time PX) simulation to obtain the data points used by each processor core to fit the basic power. For the m-th processor core, the data point includes the activity coefficients corresponding to the n power consumption characterization signals of the m-th processor core: C 0 , C 1 , C 2 …C n , and corresponding to the m-th processor core The estimated power P m ".
在一些实施例中,步骤402可以是每个处理器核对应的功耗监测器211执行。In some embodiments, step 402 may be executed by the power consumption monitor 211 corresponding to each processor core.
403、根据每个处理器核的数据点进行线性回归拟合,获取每个处理器核的功耗系数和基础功率。403. Perform linear regression fitting according to the data points of each processor core, and obtain the power consumption coefficient and basic power of each processor core.
即对第m个处理器核,根据第m个处理器核的n个功耗表征信号对应的活动系数:C
0、C
1、C
2…C
n,以及第m个处理器核对应的估计功率进行线性回归拟合,得到第m个处理器核对应的功耗系数W
0、W
1、W
2…W
n以及基础功率B。
That is, for the m-th processor core, the activity coefficients corresponding to the n power consumption characteristic signals of the m-th processor core: C 0 , C 1 , C 2 … C n , and the corresponding estimation of the m-th processor core Linear regression fitting is performed on the power, and the power consumption coefficients W 0 , W 1 , W 2 …W n and the basic power B corresponding to the m-th processor core are obtained.
即在进行线性回归拟合得到功耗系数的同时,还可以拟合得到每个处理器核对应的基础功率B。对于一个处理器核,该基础功率还可以理解为一个处理器核的n个功耗表征信号在预设周期内处于未翻转或处于低电平状态时消耗的功率。That is, while linear regression fitting is performed to obtain the power consumption coefficient, the basic power B corresponding to each processor core can also be obtained by fitting. For a processor core, the basic power can also be understood as the power consumed when the n power consumption characteristic signals of a processor core are not inverted or in a low level state within a preset period.
当为每个处理器核选取的功耗表征信号可以覆盖到该处理器核的全部的功耗事件时,B的值为0,因此,在得到基础功率时,可以根据每个处理器核的活动功率以及每个处理器核的基础功率确定每个处理器核的估计功率,使得估计功率更能准确的反应处理器核的实际功率。即步骤301中的公式一可以替换为:When the power consumption characterization signal selected for each processor core can cover all the power consumption events of the processor core, the value of B is 0. Therefore, when the basic power is obtained, it can be based on the power consumption of each processor core. The active power and the basic power of each processor core determine the estimated power of each processor core, so that the estimated power can more accurately reflect the actual power of the processor core. That is, the formula one in step 301 can be replaced with:
P
m=C
0W
0+C
1W
1+C
2W
2+…+C
nW
n+B
m,B
m表示第m个处理器核在一个预设周期下的基础功率。
P m =C 0 W 0 +C 1 W 1 +C 2 W 2 +...+C n W n +B m , B m represents the basic power of the m-th processor core in a preset cycle.
在一些实施例中,步骤403可以是每个处理器核对应的功耗监测器211执行。In some embodiments, step 403 may be executed by the power consumption monitor 211 corresponding to each processor core.
如果步骤401~步骤403是进行硅前仿真得到的功耗系数和基础功率,那么在硅后,可以对功耗系数进行一次校准。此时的校准可以是芯片还未应用到实际的终端设备中时对功耗系数的校准。此时对功耗系数的校准可以是发生在步骤301之前,和步骤403之后,也就是在硅前仿真得到每个处理器核对应的功耗系数以及基础功率之后,且在对多个处理器核的估计功率进行校准之前,对多个处理器核的功耗系数先进行校准。If steps 401 to 403 are the power consumption coefficient and the basic power obtained by performing the pre-silicon simulation, then the power consumption coefficient can be calibrated once after the silicon. The calibration at this time may be the calibration of the power consumption coefficient when the chip has not been applied to the actual terminal equipment. At this time, the calibration of the power consumption coefficient can occur before step 301 and after step 403, that is, after the power consumption coefficient and the basic power corresponding to each processor core are obtained by the silicon pre-silicon simulation, and after the calculation of multiple processors Before calibrating the estimated power of the core, calibrate the power consumption coefficients of multiple processor cores.
因此,在步骤403之后,该方法还包括步骤404:Therefore, after step 403, the method further includes step 404:
404、对每个处理器核的功耗系数进行校准。404. Calibrate the power consumption coefficient of each processor core.
该校准方式与步骤401~403中得到功耗系数的原理类似。This calibration method is similar to the principle of obtaining the power consumption coefficient in steps 401 to 403.
本申请中,硅后对功耗系数的校准,可以消除硅前仿真与硅后仿真的功耗系数的误差带来的影响。In this application, the post-silicon calibration of the power consumption coefficient can eliminate the influence of the error of the power consumption coefficient of the pre-silicon simulation and the post-silicon simulation.
本申请实施例中,在步骤305之后,即在校准估计功率之后,还可以对功耗系数继续进行校准,此时对功耗系数的校准是芯片已应用到终端设备中时。如图5所示。 因此,该方法还可以包括:In the embodiment of the present application, after step 305, that is, after the estimated power is calibrated, the power consumption coefficient may be continuously calibrated. At this time, the power consumption coefficient is calibrated when the chip has been applied to the terminal device. As shown in Figure 5. Therefore, the method may also include:
306、根据多个处理器核的实际功率总和以及每个处理器核的至少一个功耗表征信号的活动系数,调整每个处理器核的至少一个功耗表征信号的功耗系数。306. Adjust the power consumption coefficient of at least one power consumption characterizing signal of each processor core according to the total actual power of the multiple processor cores and the activity coefficient of the at least one power consumption characterizing signal of each processor core.
也可以理解为,根据多个处理器核的实际功率总和以及每个处理器核对应的活动系数,对每个处理器核的功耗系数进行校准。It can also be understood that the power consumption coefficient of each processor core is calibrated according to the total actual power of multiple processor cores and the activity coefficient corresponding to each processor core.
在一些实施例中,对耗系数校准的周期可以大于上述对估计功率进行校准的预设周期。例如功耗系数校准的周期记为第一周期时,第一周期可以是多个预设周期的时长之和。In some embodiments, the period for calibrating the consumption coefficient may be greater than the aforementioned preset period for calibrating the estimated power. For example, when the period of power consumption coefficient calibration is recorded as the first period, the first period may be the sum of the durations of multiple preset periods.
在一些实施例中,可以将处理器核电源平面21的多个处理器核作为一个整体,即在每个第一周期下,可以利用多个处理器核的实际功率总和P
total'以及多个处理器核的功耗表征信号的活动系数C
mn进行线性回归拟合,得到每个功耗表征信号对应的功耗系数W
mn以及基础功率B'。C
mn表示第m个处理器核的第n个功耗表征信号的活动系数。W
mn表示第m个处理器核的第n个功耗表征信号的功耗系数。B'为第一周期下多个处理器核的基础功率之和。
In some embodiments, the multiple processor cores of the processor core power plane 21 can be taken as a whole, that is, in each first cycle, the actual power sum P total 'of multiple processor cores and multiple The activity coefficient C mn of the power consumption characterization signal of the processor core performs linear regression fitting to obtain the power consumption coefficient W mn and the basic power B′ corresponding to each power consumption characterization signal. C mn represents the activity coefficient of the nth power consumption characterization signal of the mth processor core. W mn represents the power consumption coefficient of the nth power consumption characterization signal of the mth processor core. B'is the sum of the basic power of multiple processor cores in the first cycle.
此时,P
total'、C
mn以及W
mn的关系可以表示为:
At this time, the relationship between P total ', C mn and W mn can be expressed as:
P
total'=C
00W
00+C
01W
01+C
02W
02+…+C
0nW
0n+C
10W
10+C
11W
11+C
12W
12+…+C
1nW
1n+…+C
m0W
m0+C
m1W
m1+C
m2W
m2+…+C
mnW
mn+B'。
P total '=C 00 W 00 +C 01 W 01 +C 02 W 02 +…+C 0n W 0n +C 10 W 10 +C 11 W 11 +C 12 W 12 +…+C 1n W 1n +…+ C m0 W m0 +C m1 W m1 +C m2 W m2 +…+C mn W mn +B'.
也就是说,可以对P
total'、C
00、C
01、C
02…C
0n、C
10、C
11、C
12…C
1n…C
m0、C
m1、C
m2…C
mn进行线性回归拟合,得到W
00、W
01、W
02…W
0n、W
10、W
11、W
12…W
1n…W
m0、W
m1、W
m2…W
mn以及B'。
In other words, linear regression fitting can be performed on P total ', C 00 , C 01 , C 02 … C 0n , C 10 , C 11 , C 12 … C 1n … C m0 , C m1 , C m2 … C mn , Get W 00 , W 01 , W 02 … W 0n , W 10 , W 11 , W 12 … W 1n … W m0 , W m1 , W m2 … W mn and B'.
在一些实施例中,每个处理器核对应的功耗监测单元211可以获取对应的处理器核的活动系数C
mn,并将C
mn发送给频率控制器213,频率控制器213根据活动系数C
mn以及在步骤303中得到的实际功率总和P
total'得到功耗系数W
mn。
In some embodiments, the power consumption monitoring unit 211 corresponding to each processor core may obtain the activity coefficient C mn of the corresponding processor core, and send C mn to the frequency controller 213, and the frequency controller 213 may obtain the activity coefficient C mn according to the activity coefficient C mn. mn and the actual power sum P total ′ obtained in step 303 obtain the power consumption coefficient W mn .
307、根据校准后的功耗系数确定下一个预设周期每个处理器核的估计功率。307. Determine the estimated power of each processor core in the next preset period according to the calibrated power consumption coefficient.
这样,可以根据芯片实时工作时的功耗数据,实时校准功耗系数,从而可以根据实时校准得到的功耗系数计算得到每个处理器核更准确的估计功率。In this way, the power consumption coefficient can be calibrated in real time according to the power consumption data when the chip is working in real time, so that a more accurate estimated power of each processor core can be calculated according to the power consumption coefficient obtained by the real-time calibration.
以上结合图3、图4以及图5详细说明了本申请实施例的方法。以下结合图6说明本申请实施例的计算系统的框图。图6说明了根据本申请的实施例的计算系统100的框图。The method of the embodiment of the present application is described in detail above with reference to FIG. 3, FIG. 4, and FIG. 5. The block diagram of the computing system of the embodiment of the present application will be described below with reference to FIG. 6. FIG. 6 illustrates a block diagram of a computing system 100 according to an embodiment of the present application.
计算系统60可以包括一个或多个中央处理器单元(central processing unit,CPU)或处理器602-1到602-p(本文可以称为“多个处理器602”或“处理器602”)。处理器602可以经由总线(或互连网络)604进行通信。处理器602可以包括通用处理器、网络处理器(处理在计算机网络603上传送的数据)或其它类型的处理器(包括精简指令集计算机(reduced instruction set computing,RISC)处理器或复杂指令集计算机(complex instruction set computer,CISC))。此外,多个处理器602可以具有单个或多个核心的设计。具有多核心设计的处理器602可以将不同类型的处理器核心集成到相同的集成电路(integrated circuit,IC)管芯上。此外,具有多核心设计的处理器602可以实现为对称的或不对称的多处理器。在实施例中,一个或多个处理器602可以与图2的处理器相同或相似。The computing system 60 may include one or more central processing units (CPU) or processors 602-1 to 602-p (may be referred to as "multiple processors 602" or "processors 602" herein). The processor 602 can communicate via a bus (or interconnection network) 604. The processor 602 may include a general-purpose processor, a network processor (processing data transmitted on the computer network 603) or other types of processors (including reduced instruction set computing (RISC) processors or complex instruction set computers (complex instruction set computer, CISC)). In addition, multiple processors 602 may have a single or multiple core design. The processor 602 with a multi-core design can integrate different types of processor cores on the same integrated circuit (IC) die. In addition, the processor 602 with a multi-core design can be implemented as a symmetric or asymmetric multi-processor. In an embodiment, one or more processors 602 may be the same as or similar to the processor of FIG. 2.
本申请的计算系统60还可以包括芯片组606。芯片组606还可以与总线604进行通信。芯片组606可以包括图形和存储控制集线器(graphics memory controller hub,GMCH)608。GMCH 608可以包括与存储器112进行通信的存储器控制器110。存储器112可以存储数据,其包括由处理器602或计算系统60中包括的任何其它设备执行的指令的序列。在本申请的一个实施例中,存储器112可以包括一个或多个易失性存储(或存储器)设备,例如随机存取存储器(random access memory,RAM)、动态RAM(dynamic RAM,DRAM)、同步DRAM(synchronous dynamic RAM,SDRAM)、静态RAM(static RAM,SRAM)或其它类型的存储设备。还可以使用非易失性存储器,例如硬盘。其它设备可以经由总线604进行通信,例如多个CPU和/或多个系统存储器。The computing system 60 of the present application may also include a chipset 606. The chipset 606 can also communicate with the bus 604. The chipset 606 may include a graphics memory controller hub (GMCH) 608. The GMCH 608 may include a memory controller 110 that communicates with the memory 112. The memory 112 may store data, which includes a sequence of instructions executed by the processor 602 or any other device included in the computing system 60. In an embodiment of the present application, the memory 112 may include one or more volatile storage (or memory) devices, such as random access memory (RAM), dynamic RAM (DRAM), and synchronous DRAM (synchronous dynamic RAM, SDRAM), static RAM (static RAM, SRAM) or other types of storage devices. It is also possible to use non-volatile memory, such as a hard disk. Other devices may communicate via the bus 604, such as multiple CPUs and/or multiple system memories.
GMCH 608还可以包括与图形加速器116进行通信的图形接口114以及显示器(图中未示出)。在本申请的实施例中,显示器(例如,平板显示器、阴极射线管(cathode-ray-tube,CRT)、投影屏幕等)可以通过例如信号转换器与图形接口114进行通信,其中所述信号转换器将在存储设备(例如,视频存储器或系统存储器)中存储的图像的数字表示转换为由显示器解释并显示的显示器信号。在由显示器解释并随后在其上显示之前,由显示设备产生的显示器信号可以通过各种控制设备。The GMCH 608 may also include a graphics interface 114 for communicating with the graphics accelerator 116 and a display (not shown in the figure). In the embodiment of the present application, the display (for example, a flat panel display, a cathode-ray-tube (CRT), a projection screen, etc.) may communicate with the graphics interface 114 through, for example, a signal converter, wherein the signal conversion The converter converts the digital representation of the image stored in a storage device (for example, video memory or system memory) into a display signal that is interpreted and displayed by the display. The display signal generated by the display device can pass through various control devices before being interpreted by the display and then displayed thereon.
本申请的计算系统60还可以包括输入/输出控制中心(input/output controller hub,ICH)120,ICH 120可以向与计算系统60进行通信的I/O设备提供接口。ICH 120可以通过外围设备桥(或控制器)124(例如,外围设备部件互连(Peripheral Component Interconnect,PCI)桥、通用串行总线(universal serial bus,USB)控制器或其它类型的外围设备桥或控制器)与总线122进行通信。外围设备桥124可以在处理器602与外围设备之间提供数据路径。此外,多个总线122可以与ICH 120进行通信。The computing system 60 of the present application may further include an input/output control center (input/output controller hub, ICH) 120, and the ICH 120 may provide an interface for I/O devices that communicate with the computing system 60. The ICH 120 can pass through a peripheral device bridge (or controller) 124 (for example, a Peripheral Component Interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral device bridges). Or the controller) communicates with the bus 122. The peripheral device bridge 124 may provide a data path between the processor 602 and peripheral devices. In addition, multiple buses 122 can communicate with the ICH 120.
此外,总线122还可以与音频设备126、一个或多个硬盘驱动器128以及一个或多个网络接口设备130(其与计算机网络603进行通信)进行通信。In addition, the bus 122 may also communicate with an audio device 126, one or more hard disk drives 128, and one or more network interface devices 130 (which communicate with the computer network 603).
通过以上实施方式的描述,所属领域的技术人员可以了解到,为描述的方便和简洁,仅以上述各功能模块的划分进行举例说明,实际应用中,可以根据需要而将上述功能分配由不同的功能模块完成,即将装置的内部结构划分成不同的功能模块,以完成以上描述的全部或者部分功能。Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of the description, only the division of the above-mentioned functional modules is used as an example. The function module is completed, that is, the internal structure of the device is divided into different function modules to complete all or part of the functions described above.
在本申请所提供的几个实施例中,应该理解到,所揭露的装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述模块或单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个装置,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed device and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be divided. It can be combined or integrated into another device, or some features can be omitted or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是一个物理单元或多个物理单元,即可以位于一个地方,或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate parts may or may not be physically separate. The parts displayed as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以 是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现,也可以采用软件功能单元的形式实现。In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个可读取存储介质中。基于这样的理解,本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来,该软件产品存储在一个存储介质中,包括若干指令用以使得一个设备(可以是单片机,芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括:U盘、移动硬盘、只读存储器(read only memory,ROM)、随机存取存储器(random access memory,RAM)、磁碟或者光盘等各种可以存储程序代码的介质。If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product, and the software product is stored in a storage medium. It includes several instructions to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read only memory (read only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.
以上内容,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。The above content is only the specific implementation of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Covered in the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims (18)
- 一种测量处理器核功率的方法,其特征在于,包括:A method for measuring processor core power, which is characterized in that it includes:根据处理器中每个处理器核的估计功率确定所述处理器所包含的多个处理器核的估计功率总和;Determining the sum of the estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor;确定所述处理器中多个处理器核的实际功率总和;Determining the sum of actual power of multiple processor cores in the processor;根据所述估计功率总和以及所述实际功率总和对每个处理器核的估计功率进行校准,以得到所述每个处理器核的校准功率。Calibrate the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core.
- 根据权利要求1所述的方法,其特征在于,所述方法还包括:The method according to claim 1, wherein the method further comprises:根据每个处理器核的校准功率对每个处理器核的频率和电压进行调整。The frequency and voltage of each processor core are adjusted according to the calibrated power of each processor core.
- 根据权利要求1或2所述的方法,其特征在于,所述根据所述估计功率总和以及所述实际功率总和对每个处理器核的估计功率进行校准包括:The method according to claim 1 or 2, wherein the calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum comprises:根据所述估计功率总和以及所述实际功率总和确定校准系数;Determining a calibration coefficient according to the estimated power sum and the actual power sum;根据所述校准系数对每个处理器核的估计功率进行校准。The estimated power of each processor core is calibrated according to the calibration coefficient.
- 根据权利要求1-3任一项所述的方法,其特征在于,所述根据处理器中每个处理器核的估计功率确定所述处理器所包含的多个处理器核的估计功率总和,包括:The method according to any one of claims 1 to 3, wherein the determining the sum of the estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor, include:根据所述处理器中每个处理器核的估计功率和所述多个处理器核的电源域的静态功率,确定所述多个处理器核的估计功率总和;Determining the total estimated power of the multiple processor cores according to the estimated power of each processor core in the processor and the static power of the power domain of the multiple processor cores;其中,所述多个处理器核的电源域的静态功率是指所述多个处理器核的电源域的漏电电流所产生的功耗。Wherein, the static power of the power domains of the multiple processor cores refers to the power consumption generated by the leakage currents of the power domains of the multiple processor cores.
- 根据权利要求1-4任一项所述的方法,其特征在于,在确定所述多个处理器核的估计功率总和之前,所述方法还包括:The method according to any one of claims 1 to 4, wherein before determining the sum of the estimated power of the multiple processor cores, the method further comprises:确定每个处理器核的估计功率。Determine the estimated power of each processor core.
- 根据权利要求5所述的方法,其特征在于,所述确定每个处理器核的估计功率包括:The method according to claim 5, wherein said determining the estimated power of each processor core comprises:根据每个处理器核的活动功率和每个处理器核的基础功率确定每个处理核的估计功率,其中,所述活动功率用于指示每个处理核的至少一个功耗表征信号在处于活动状态时所消耗的功率,所述基础功率用于指示每个处理核的至少一个功耗表征信号在未处于所述活动状态时每个处理器核所消耗的功耗。The estimated power of each processing core is determined according to the active power of each processor core and the basic power of each processor core, where the active power is used to indicate that at least one power consumption characterizing signal of each processing core is active. The power consumed in the state, where the basic power is used to indicate the power consumption of each processor core when at least one power consumption characterization signal of each processing core is not in the active state.
- 根据权利要求6所述的方法,其特征在于,所述每个处理器核的活动功率通过如下方式确定:The method according to claim 6, wherein the active power of each processor core is determined in the following manner:根据每个处理器核的至少一个功耗表征信号的活动系数和至少一个功耗表征信号的功耗系数得到所述活动功率,每个功耗表征信号的活动系数用于反映每个功耗表征信号处于所述活动状态时的系数,每个功耗表征信号的功耗系数用于反映每个功耗表征信号每次处于所述活动状态时所消耗的功耗。The active power is obtained according to the activity coefficient of at least one power consumption characterization signal and the power consumption coefficient of at least one power consumption characterization signal of each processor core, and the activity coefficient of each power consumption characterization signal is used to reflect each power consumption characterization The coefficient when the signal is in the active state, and the power consumption coefficient of each power consumption characteristic signal is used to reflect the power consumption of each power consumption characteristic signal each time when the signal is in the active state.
- 根据权利要求7所述的方法,其特征在于,所述方法还包括:The method according to claim 7, wherein the method further comprises:根据所述实际功率总和以及所述每个处理器核的至少一个功耗表征信号的活动系数,调整每个处理器核的至少一个功耗表征信号的功耗系数。Adjust the power consumption coefficient of at least one power consumption characterizing signal of each processor core according to the actual power sum and the activity coefficient of the at least one power consumption characterizing signal of each processor core.
- 一种测量处理器核功率的装置,其特征在于,包括功耗监测器和频率控制器,其中:A device for measuring the power of a processor core is characterized by comprising a power consumption monitor and a frequency controller, wherein:所述频率控制器,用于根据所述功耗监测器得到的处理器中每个处理器核的估计功率确定所述处理器所包含的多个处理器核的估计功率总和;The frequency controller is configured to determine the total estimated power of multiple processor cores included in the processor according to the estimated power of each processor core in the processor obtained by the power consumption monitor;所述频率控制器,还用于确定所述处理器中多个处理器核的实际功率总和;The frequency controller is also used to determine the total actual power of multiple processor cores in the processor;所述频率控制器,还用于根据所述估计功率总和以及所述实际功率总和对每个处理器核的估计功率进行校准,以得到所述每个处理器核的校准功率。The frequency controller is further configured to calibrate the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core.
- 根据权利要求9所述的装置,其特征在于,所述频率控制器还用于:The device according to claim 9, wherein the frequency controller is further used for:根据每个处理器核的校准功率对每个处理器核的频率和电压进行调整。The frequency and voltage of each processor core are adjusted according to the calibrated power of each processor core.
- 根据权利要求9或10所述的装置,其特征在于,所述频率控制器用于:The device according to claim 9 or 10, wherein the frequency controller is used for:根据所述估计功率总和以及所述实际功率总和确定校准系数;Determining a calibration coefficient according to the estimated power sum and the actual power sum;根据所述校准系数对每个处理器核的估计功率进行校准。The estimated power of each processor core is calibrated according to the calibration coefficient.
- 根据权利要求9-11任一项所述的装置,其特征在于,所述频率控制器用于:The device according to any one of claims 9-11, wherein the frequency controller is used for:根据所述处理器中每个处理器核的估计功率和所述多个处理器核的电源域的静态功率,确定所述多个处理器核的估计功率总和;Determining the total estimated power of the multiple processor cores according to the estimated power of each processor core in the processor and the static power of the power domain of the multiple processor cores;其中,所述多个处理器核的电源域的静态功率是指所述多个处理器核的电源域的漏电电流所产生的功耗。Wherein, the static power of the power domains of the multiple processor cores refers to the power consumption generated by the leakage currents of the power domains of the multiple processor cores.
- 根据权利要求9-12任一项所述的装置,其特征在于,所述功耗监测器用于:The device according to any one of claims 9-12, wherein the power consumption monitor is configured to:确定每个处理器核的估计功率。Determine the estimated power of each processor core.
- 根据权利要求13所述的装置,其特征在于,所述功耗监测器用于:The device according to claim 13, wherein the power consumption monitor is used for:根据每个处理核的活动功率和每个处理器核的基础功率确定每个处理器核的估计功率;Determine the estimated power of each processor core according to the active power of each processing core and the basic power of each processor core;其中,所述活动功率用于指示每个处理核的至少一个功耗表征信号在处于活动状态时所消耗的功率,所述基础功率用于指示每个处理核的至少一个功耗表征信号在未处于所述活动状态时每个处理器核所消耗的功耗。Wherein, the active power is used to indicate the power consumed by at least one power consumption characterization signal of each processing core when it is in an active state, and the basic power is used to indicate that at least one power consumption characterization signal of each processing core is in an active state. The power consumption of each processor core when in the active state.
- 根据权利要求14所述的装置,其特征在于,所述功耗监测器用于:The device according to claim 14, wherein the power consumption monitor is used for:根据每个处理器核的至少一个功耗表征信号的活动系数和至少一个功耗表征信号的功耗系数得到所述活动功率,每个功耗表征信号的活动系数用于反映每个功耗表征信号处于所述活动状态时的系数,每个功耗表征信号的功耗系数用于反映每个功耗表征信号每次处于所述活动状态时所消耗的功耗。The active power is obtained according to the activity coefficient of at least one power consumption characterization signal and the power consumption coefficient of at least one power consumption characterization signal of each processor core, and the activity coefficient of each power consumption characterization signal is used to reflect each power consumption characterization The coefficient when the signal is in the active state, and the power consumption coefficient of each power consumption characteristic signal is used to reflect the power consumption of each power consumption characteristic signal each time when the signal is in the active state.
- 根据权利要求15所述的装置,其特征在于,所述频率控制器还用于:The device according to claim 15, wherein the frequency controller is further used for:根据所述实际功率总和以及所述每个处理器核的至少一个功耗表征信号的活动系数,调整每个处理器核的至少一个功耗表征信号的功耗系数。Adjust the power consumption coefficient of at least one power consumption characterizing signal of each processor core according to the actual power sum and the activity coefficient of the at least one power consumption characterizing signal of each processor core.
- 一种计算机可读存储介质,其特征在于,包括程序或指令,当所述程序或指令被处理器运行时,如权利要求1至8中任意一项所述的方法被执行。A computer-readable storage medium, characterized by comprising a program or instruction, and when the program or instruction is executed by a processor, the method according to any one of claims 1 to 8 is executed.
- 一种计算机程序产品,其特征在于,当计算机程序产品在计算机上运行时,使得电子设备执行如权利要求1至8中任意一项所述的方法。A computer program product, characterized in that, when the computer program product runs on a computer, it causes an electronic device to execute the method according to any one of claims 1 to 8.
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