CN100533344C - Method, system and processor for testing thermal regulation control of real-time software - Google Patents

Abstract

To provide a thermal management solution for guaranteeing real-time use nature even in a temperature condition which requires throttling of a processor. A computer implemented method, a data processing system and the processor are provided for thermal throttling control for testing of real-time software. At least one thermal control setting is received. A thermal management system is set to a test mode using the at least one thermal control setting. The test mode indicates thermal throttling control using the thermal control setting. The real-time software is executed under the test mode, and a test is performed as to whether a real-time deadline associated with the real-time software is met under the test mode. At least one thermal control setting is recorded as a passing thermal control setting in response to the real-time software meeting the real-time deadline.

Description

Method, system and processor for testing thermal regulation control of real-time software

technical field

This application relates generally to the use of thermal management. More particularly, the present application relates to a computer-implemented method, data processing system, and processor for testing thermal regulation control of real-time software.

Background technique

处理器内核和八个单指令多数据(SIMD)协处理器内核的多内核芯片，能够进行大规模浮点处理，针对运算密集型工作负载和宽带富媒体应用而进行了优化。高速存储控制器和高带宽总线接口也集成到芯片上。Cell BE的突破性多内核体系结构和超高速通信能力在很多情况下以最新PC处理器性能的10倍递送大大改善的实时响应。Cell BE是操作系统中立的并同时支持多个操作系统。这种类型的处理器的应用的范围可以从具有显著增强的真实感的下一代游戏系统，到形成家庭数字媒体和流式传送内容中心(hub)的系统，到用于开发和分布数字内容的系统，并且到加速可视化和超级计算应用的系统。The first-generation heterogeneous Cell Broadband Engine ^TM (BE) processor is a 64-bit Power

A multicore chip with processor cores and eight single-instruction multiple-data (SIMD) coprocessor cores, capable of massive floating-point processing, is optimized for compute-intensive workloads and broadband-rich media applications. A high-speed memory controller and a high-bandwidth bus interface are also integrated on-chip. Cell BE's breakthrough multi-core architecture and ultra-high-speed communication capabilities deliver greatly improved real-time response in many cases at 10 times the performance of the latest PC processors. Cell BE is OS neutral and supports multiple operating systems simultaneously. Applications for this type of processor can range from next-generation gaming systems with dramatically enhanced realism, to systems forming home digital media and streaming content hubs, to systems for developing and distributing digital content. systems, and to systems that accelerate visualization and supercomputing applications.

Today's multi-core processors are often limited by thermal considerations. Typical solutions include cooling and power management. Cooling can be expensive and/or difficult to integrate. Power management is generally a crude measure to "throttle" a large portion of a processor, or the entire processor, in response to reaching a thermal limit. Other techniques such as thermal management help with these rough measures by only regulating units that exceed a given temperature. However, most thermal management techniques affect the real-time assurance of the application. Accordingly, it would be beneficial to provide a thermal management solution that provides a method for the processor to ensure real-time performance of applications even in the presence of conditions that require the processor's thermal conditions to be adjusted. In the event that real-time guarantees cannot be met, the application manager is notified so that corrective actions can be implemented.

Contents of the invention

Various aspects of the illustrative embodiments provide a computer-implemented method, data processing system, and processor for testing thermal regulation control of real-time software. The illustrative embodiments receive at least one thermal control setting. The illustrative embodiment places the thermal management system into a test mode using the at least one thermal control setting, wherein the test mode indicates thermal regulation control using the thermal control setting. The illustrative embodiments execute real-time software in a test mode and test whether real-time deadlines associated with the real-time software are met in the test mode. In response to the real-time software meeting the real-time deadline, the illustrative embodiment records the at least one thermal control setting as a passed thermal control setting. In response to the real-time software failing to meet the real-time deadline, the at least one thermal control setting is logged as a failed thermal control setting.

The illustrative embodiment determines whether there is also at least one thermal control setting at which real-time software can be tested that will increase throttling. In response to the presence of a thermal control setting that would increase the amount of adjustment, the illustrative embodiment executes and tests the real-time software a second time with the increased amount of adjustment.

The illustrative embodiment determines whether there is also at least one thermal control setting that will reduce the amount of adjustment, at which the real-time software can be tested. In response to the presence of a thermal control setting that would reduce the throttling, the illustrative embodiment executes and tests the real-time software a second time with the reduced throttling.

The test mode in the illustrative embodiments may specify either a constant tuning state of the thermal management system or a random tuning state of the thermal management system. Stochastic tuning states inject random thermal events to more realistically simulate tuning interactions and software execution.

The thermal control settings may include the amount of adjustment to be initiated and the duration for the test mode to be initiated. The amount of adjustment to be initialized may be the percentage of time the unit is off to the time the unit is running. The time the unit is stopped and the time the unit is running can be scaled according to the value of the scale register. The duration for the test pattern to be initialized may be the actual number of clock cycles the unit stops and runs.

Passed or failed thermal control settings can be stored in a data structure. The test mode can be set in the thermal management control register. An integrated circuit may be a heterogeneous multi-core processor.

Description of drawings

The novel features believed characteristic of the illustrative embodiments are set forth in the appended claims. However, the illustrative embodiments themselves, together with their preferred modes of use, further objects and advantages, are best understood by reference to the following detailed description of the illustrative embodiments when read in conjunction with the accompanying drawings, in which:

1 depicts an illustration of a network of data processing systems that may implement aspects of the illustrative embodiments;

2 depicts a block diagram of a data processing system in which aspects of the illustrative embodiments may be implemented;

Figure 3 depicts an exemplary diagram of a Cell BE chip that can implement various aspects of the illustrative embodiments;

FIG. 4 shows an example thermal management system in accordance with an illustrative embodiment;

FIG. 5 depicts a temperature profile and various points at which interruptions and dynamic adjustments may occur, in accordance with an illustrative embodiment;

6 depicts a flowchart of operations for recording maximum temperature, in accordance with an illustrative embodiment;

7 depicts a flowchart of operations for tracking thermal data through performance monitoring, according to another illustrative embodiment;

8A and 8B depict a flowchart of operations for advanced thermal interrupt generation, according to additional illustrative embodiments;

FIG. 9 depicts a flowchart for supporting deep power-saving modes and partially benign operation in a thermal management system, according to an additional illustrative embodiment;

10 depicts a flowchart of operations for a thermal throttling control feature that enables real-time testing of a thermal-aware software application independent of temperature, in accordance with additional illustrative embodiments;

11 depicts a flowchart of operations for implementing thermal throttling control with minimal impact on interrupt latency, in accordance with additional illustrative embodiments;

12 depicts a flowchart of operations for hysteresis in thermal regulation, according to additional illustrative embodiments; and

FIG. 13 depicts a flowchart of operations for implementing thermal throttling logic, according to an additional illustrative embodiment.

Detailed ways

The illustrative embodiments relate to thermal regulation control for testing real-time software. 1-2 are provided as exemplary illustrations of data processing environments in which illustrative embodiments may be implemented. It should be understood that FIGS. 1-2 are only exemplary, and are not intended to expressly or imply any limitation on the environment in which various aspects of the embodiments can be implemented. Many modifications may be made to the described environment without departing from the spirit and scope of the illustrative embodiments.

Referring now to the drawings, FIG. 1 depicts an illustration of a network of data processing systems in which aspects of the illustrative embodiments may be implemented. Network data processing system 100 is a network of computers on which the illustrative embodiments may be implemented. Network data processing system 100 contains network 102 , which is the medium used to provide communications links between various devices and computers connected together within network data processing system 100 . Network 102 may include connections such as wires, wireless communication links, or fiber optic cables.

In the depicted example, server 104 and server 106 are connected to network 102 and consequently storage unit 108 . Additionally, clients 110 , 112 and 114 are connected to network 102 . These clients 110, 112 and 114 may be, for example, personal computers or network computers. In the depicted example, server 104 provides data such as boot files, operating system images, and applications to clients 110 , 112 , and 114 . In this example, clients 110 , 112 , and 114 are clients to server 104 . Network data processing system 100 may include additional servers, clients, and other devices not shown.

In the depicted example, network data processing system 100 is the Internet with network 102 representing a global collection of networks and gateways that communicate with each other using the Transmission Control Protocol/Internet Protocol (TCP/IP) suite of protocols. At the heart of the Internet is a backbone of high-speed data communication lines between major nodes or host computers, including thousands of business, government, educational and other computer systems that route data and messages. Of course, the network data processing system 100 can also be implemented as various types of networks, such as an intranet, a local area network (LAN) or a wide area network (WAN). FIG. 1 is intended as an example, and not as an architectural limitation for the different illustrative embodiments.

Referring now to FIG. 2 , a block diagram of a data processing system in which aspects of the illustrative embodiments may be implemented is shown. Data processing system 200 is an example of a computer, such as server 104 or client 110 in FIG. 1, in which computer usable code or instructions implementing the processes of the illustrative embodiments may reside.

In the depicted example, data processing system 200 employs a hub architecture including north bridge and memory controller hub (MCH) 202 and south bridge and input/output (I/O) controller hub (ICH) 204 . Processing unit 206 , main memory 208 and graphics processor 210 are connected to northbridge and memory controller hub 202 . Graphics processor 210 may be connected to Northbridge and storage controller hub 202 through an accelerated graphics port (AGP).

In the depicted example, LAN adapter 212 is connected to Southbridge and I/O controller hub 204 . Audio adapter 216, keyboard and mouse adapter 220, modem 222, read only memory (ROM) 224, hard disk drive (HDD) 226, CD-ROM drive 230, universal serial bus (USB) port and other communication ports 232, and PCI PCIe device 234 is connected to Southbridge and I/O controller hub 204 via bus 238 and bus 240 . PCI/PCIe devices may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, PCIe does not. ROM 224 may be, for example, a flash binary input/output system (BIOS).

Hard disk drive 226 and CD-ROM drive 230 are connected to Southbridge and I/O controller hub 204 by bus 240 . Hard disk drive 226 and CD-ROM drive 230 may use, for example, integrated drive electronics (IDE) or serial advanced technology attachment (SATA) interfaces. Super I/O (SIO) devices 236 may be connected to Southbridge and I/O controller hub 204 .

 

 XP(Microsoft和Windows是微软公司在美国、其他国家或同时在美国和其他国家的商标)。诸如Java^TM编程系统之类的面向对象编程系统可以结合操作系统而运行，并提供从在数据处理系统200上执行的Java程序或应用对操作系统的调用(Java是Sun微系统公司在美国、其他国家或同时在美国和其他国家的商标)。An operating system runs on processing unit 206 and coordinates and provides control of various components within data processing system 200 in FIG. 2 . As a client, the operating system can be a commercially available operating system, such as

XP (Microsoft and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both). An object-oriented programming system such as the Java ^™ programming system can run in conjunction with an operating system and provide calls to the operating system from Java programs or applications executing on data processing system 200 country or both in the United States and other countries).

操作系统或LINUX操作系统的IBM eServer^TM 

计算机系统(eServer、pSeries和AIX是国际商业机器公司在美国、其他国家或同时在美国和其他国家的商标，而Linux是Linux Torvalds在美国、其他国家或同时在美国和其他国家的商标)。数据处理系统200可以是在处理单元206中包括多个处理器的对称多处理器(SMP)系统。作为选择，可以采用单处理器系统。As a server, data processing system 200 may be, for example, running a high-level interactive implementation

OS or IBM eServer ^TM with LINUX OS

Computer Systems (eServer, pSeries and AIX are trademarks of International Business Machines Corporation in the United States, other countries, or both, and Linux is a trademark of Linux Torvalds in the United States, other countries, or both). Data processing system 200 may be a symmetric multiprocessor (SMP) system including multiple processors in processing unit 206 . Alternatively, a single processor system may be used.

Instructions for the operating system, object-oriented programming system, and applications or programs reside on storage devices such as hard drive 226 and may be loaded into main memory 208 for execution by processing unit 206 . The processes of the illustrative embodiments are performed by processing unit 206 using computer usable program code, which may be located in a memory such as main memory 208 , read only memory 224 , or in one or more peripheral devices 226 and 230 .

Those of ordinary skill in the art should understand that, according to different implementations, the hardware in FIGS. 1-2 may vary. Other internal hardware or peripherals, such as flash memory, equivalent non-volatile memory, or optical disk drives, may be used in addition to or in place of the hardware described in Figures 1-2. Likewise, the processes of the illustrative embodiments may also be applied to multiprocessor data processing systems.

In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA) configured with flash memory to provide non-volatile memory for storing operating system files and/or user-generated data. .

A bus system may include one or more buses, such as bus 238 or bus 240 shown in FIG. 2 . Of course, the bus system may be implemented using any type of communication framework or architecture that provides for the transfer of data between different components or devices attached to the framework or architecture. A communications unit may include one or more devices used to transmit or receive data, such as modem 222 or network adapter 212 of FIG. 2 . The memory may be, for example, main memory 208 , read-only memory 224 , or a cache such as found in north bridge and memory controller hub 202 in FIG. 2 . The examples depicted in FIGS. 1-2 and the above examples are not meant to imply architectural limitations. For example, data processing system 200 also may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a PDA.

FIG. 3 depicts an exemplary diagram of a Cell BE chip that may implement aspects of the illustrative embodiments. The Cell BE chip 300 is a single-chip multiprocessor implementation for distributed processing targeting media-rich applications such as game consoles, desktop systems, and servers.

处理器单元(PPE)301、协处理器单元(SPU)310、311和312、以及存储器流控制器(MFC)305、306和307。尽管通过示例示出了协处理器单元(SPE)302、303和304以及PPE 301，但是可以支持任意类型的处理器单元。尽管图3只示出了三个SPE 302、303和304，但示例性的Cell BE芯片300的实现包括一个PPE 301和八个SPE。CELL处理器的SPE是设计为加速媒体和数据流工作负载的新处理器体系结构的第一实现。Cell BE chip 300 can be logically divided into the following functional components: Power PC

A processor unit (PPE) 301 , coprocessor units (SPU) 310 , 311 and 312 , and memory flow controllers (MFC) 305 , 306 and 307 . Although co-processor units (SPE) 302, 303, and 304 and PPE 301 are shown by way of example, any type of processor unit may be supported. Although FIG. 3 only shows three SPEs 302, 303, and 304, an exemplary implementation of the Cell BE chip 300 includes one PPE 301 and eight SPEs. SPE for CELL processors is the first implementation of a new processor architecture designed to accelerate media and streaming workloads.

处理器单元(PPU)308的指令集不同，例如，PPU 308可以在Power^TM体系结构中执行基于精简指令集计算机(RISC)的指令，而SPU 310、311和312执行向量化的指令。The Cell BE chip 300 may be a system-on-chip, so that each cell shown in FIG. 3 may be provided on a single microprocessor chip. Furthermore, Cell BE chip 300 is a heterogeneous processing environment where each SPU 310, 311 and 312 can receive different instructions from every other SPU in the system. In addition, the instruction set of SPU 310, 311 and 312 is the same as that of Power PC

The processor unit (PPU) 308 has a different instruction set, for example, the PPU 308 may execute Reduced Instruction Set Computer (RISC) based instructions in the Power ^(TM) architecture, while the SPUs 310, 311 and 312 execute vectorized instructions.

Each SPE includes an SPU 310, 311 or 312, its own local storage (LS) area 313, 314 or 315 and a dedicated MFC 305, 306 or 307 with an associated memory management unit (MMU) 316, 317 or 318 to store Also handles memory protection and access permission information. Also, although an SPU is shown by way of example, any type of processor unit may be supported. In addition, the Cell BE chip 300 implements an cell interconnect bus (EIB) 319 and other I/O structures to enable on-chip and external data flow.

 Asic Cell(RRAC)接口的一端，该接口为Cell BE 300提供灵活的输入和输出(FlexIO_0和FlexIO_1)353。EIB 319 serves as the main on-chip bus for PPE 301 and SPEs 302 , 303 and 304 . Additionally, the EIB319 interfaces with other on-chip interface controllers dedicated for off-chip access. The on-chip interface controller includes a storage interface controller (MIC) 320 and a Cell BE interface unit (BEI) 323, wherein the MIC320 provides two extremely fast data rate I/O (XIO) storage channels 321 and 322, and the BEI 323 provides the Cell BE 300 Two high-speed external I/O channels and internal interrupt control. BEI 323 is implemented as Bus Interface Controllers (BICs, labeled BIC0 and BIC1 ) 324 and 325 and I/O Interface Controller (IOC) 326 . Two high-speed external I/O channels connect to the Redwood

One end of the Asic Cell (RRAC) interface, which provides flexible input and output (FlexIO_0 and FlexIO_1) 353 for the Cell BE 300 .

Each SPU 310, 311 or 312 has a corresponding LS region 313, 314 or 315 and a co-execution unit (SXU) 354, 355 or 356. Each individual SPU 310, 311 or 312 can only execute instructions (including data load and store operations) from within its associated LS region 313, 314 or 315. For this reason, MFC direct memory access (DMA) operations perform all required data transfers to and from memory elsewhere in the system through the dedicated MFCs 305, 306, and 307 of the SPUs 310, 311, and 312.

中，应用通过有效地址(EA)来引用存储位置(或设备)，然后该EA被映射成存储位置(或设备)的虚拟地址(VA)，然后该VA被映射为RA。EA是由应用用来引用存储器和/或设备的地址。这种映射使操作系统能够分配比系统中物理上更多的存储器(也就是称为VA的虚拟存储器)。存储映射是系统中所有设备(包括存储器)和它们对应的RA的列表。存储映射是对标识设备或存储器将响应的RA的真实地址空间的映射。A program running on an SPU 310, 311 or 312 refers to its own LS region 313, 314 or 315 using only the LS address. However, each SPU's LS region 313, 314 or 315 is also assigned a real address (RA) within the system-wide memory map. The RA is the address to which the device will respond. on PowerPC

In , an application refers to a storage location (or device) by an effective address (EA), which is then mapped to a virtual address (VA) of the storage location (or device), which is then mapped to an RA. EAs are addresses used by applications to reference memory and/or devices. This mapping enables the operating system to allocate more memory than is physically present in the system (also known as virtual memory called VA). A storage map is a list of all devices (including storage) in the system and their corresponding RAs. A memory map is a map of the real address space of an RA that identifies a device or memory to which it will respond.

中有三个状态(问题、特权和管理)。特权软件是在特权或管理状态下运行的软件。这些状态有不同的访问特权。例如，特权软件可以访问用于将真实存储器映射成应用的EA的数据结构寄存器。问题状态是在运行应用并通常被禁用访问系统管理资源(诸如用于映射真实存储器的数据结构)时处理器通常所处的状态。This enables privileged software to map the LS region to the processor's EA for direct memory access transfers between the LS region of one SPU and the LS region of another SPU. PPE 301 can also use EA to directly access any SPU's LS region. exist

There are three states in (Problem, Privileged, and Admin). Privileged software is software that runs under a privileged or administrative state. These states have different access privileges. For example, privileged software may access the data structure registers used to map real memory to the application's EA. The problem state is the state the processor typically is in when running applications and is typically disabled from accessing system management resources, such as the data structures used to map real memory.

MFC DMA data commands always include an LS address and an EA. DMA commands copy the contents of storage from one location to another. In this case, MFC DMA commands copy data between EA and LS addresses. The LS address points directly to the LS region 313, 314 or 315 of the associated SPU 310, 311 or 312 corresponding to the MFC command queue. The command queue is a queue of MFC commands. There is one queue for commands from the SPU and one queue for commands from the PXU or other devices. But the EA can be arranged or mapped to access any other memory storage area in the system, including LS areas 313, 314, and 315 of other SPEs 302, 303, and 304.

Main memory (not shown) is shared by PPU 308, PPE 301, SPEs 302, 303, and 304 and I/O devices (not shown) in a system such as that shown in FIG. All information stored in main memory is visible to all processors and devices in the system. Programs use EAs to refer to main memory. Since the MFC Proxy Command Queue, Control and Status facilities have RAs and use EAs to map RAs, it is possible for Power processor units to use EAs to initiate DMA operations between the main memory and local memory of the associated SPE 302, 303, and 304.

As an example, when a program running on an SPU 310, 311 or 312 needs to access main memory, the SPU program generates a DMA command with the appropriate EA and LS address and places it into the command queue of its MFC 305, 306 or 307 middle. After a command is queued by the SPU program, the MFC 305, 306 or 307 executes the command and transfers required data between the LS area and the main memory. The MFC 305, 306 or 307 provides a second proxy command queue for commands generated by other devices such as the PPE 301. The MFC proxy command queue is typically used to store programs into local storage before starting the SPU. MFC proxy commands can also be used for context store operations.

The EA address provides the MFC with an address that can be translated to the RA by the MMU. The translation process allows for virtualization of system memory and access protection to memory and devices in the real address space. Since the LS area is mapped into the real address space, the EA can also point to all SPU LS areas.

存储子系统(PPSS)309。PPU 308包含处理器执行单元(PXU)329、一级(L1)高速缓存330、MMU 331和替换管理表(RMT)332。PPSS309包括可高速缓存接口单元(CIU)333、不可高速缓存单元(NCU)334、二级(L2)高速缓存328、RMT 335和总线接口单元(BIU)327。BIU 327将PPSS 309连接到EIB 319。The PPE 301 on the Cell BE chip 300 includes a 64-bit PPU308 and a Power PC

Storage Subsystem (PPSS) 309 . The PPU 308 includes a Processor Execution Unit (PXU) 329 , a Level 1 (L1) cache 330 , an MMU 331 , and a Replacement Management Table (RMT) 332 . PPSS 309 includes cacheable interface unit (CIU) 333 , non-cacheable unit (NCU) 334 , level two (L2) cache 328 , RMT 335 and bus interface unit (BIU) 327 . BIU 327 connects PPSS 309 to EIB 319 .

The SPU 310, 311 or 312 and the MFC 305, 306 and 307 communicate with each other through a one-way channel with capacity. Channels are essentially FIFOs accessed using one of the 34 SPU instructions, Read Channel (RDCH), Write Channel (WRCH), and Read Channel Count (RDCHCNT). RDCHCNT returns the amount of information in the channel. Capacity is the depth of the FIFO. The channels carry data to and from the MFCs 305, 306 and 307, the SPUs 310, 311 and 312. BIUs 339, 340 and 341 connect the MFCs 305, 306 and 307 to the EIB 319.

The MFCs 305, 306 and 307 provide the SPUs 310, 311 and 312 with two main functions. The MFC 305, 306 and 307 moves data between the SPU 310, 311 or 312, the LS area 313, 314 or 315 and the main memory. In addition, MFCs 305, 306 and 307 provide synchronization facilities between SPUs 310, 311 and 312 and other devices in the system.

The implementation of MFC 305, 306 and 307 has four functional units: Direct Memory Access Controller (DMAC) 336, 337 and 338, MMU 316, 317 and 318, Atomic Unit (ATO) 342, 343 and 344, RMT 345, 346 and 347 and BIU 339, 340 and 341. DMACs 336, 337, and 338 maintain and process MFC command queues (MFC CMDQ) (not shown), which include MFC SPU command queues (MFC SPUQ) and MFC proxy command queues (MFC PrxyQ). The sixteen-entry MFC SPUQ handles MFC commands received from the SPU channel interface. The eight-entry MFC PrxyQ handles MFC commands from other devices such as the PPE 301 or SPEs 302, 303 and 304 through memory-mapped input and output (MMIO) load and store operations. Typical direct memory access commands move data between the LS area 313, 314 or 315 and main memory. The EA parameter of the MFC DMA command is used to point to the main storage device, including main memory, local memory and all devices with RA. The local memory parameter of the MFC DMA command is used to point to the associated local memory.

In virtual mode, MMUs 316, 317 and 318 provide address translation and memory protection facilities to handle EA translation requests from DMACs 336, 337 and 338 and return translated addresses. The MMU of each SPE maintains a segment watchdog buffer (SLB) and a translation watchdog buffer (TLB). SLB converts EA to VA, and TLB converts VA from SLB to RA. The EA is used by the application and is usually a 32-bit or 64-bit address. Different applications or multiple copies of an application may use the same EA to reference different storage locations (eg, two copies of an application, both using the same EA, require two different physical storage locations). To accomplish this, the EA is first converted into a larger VA space that is common to all applications running under the operating system. The conversion of EA to VA is performed by SLB. The VA is then translated to RA using the TLB, which is a cache of page tables or mapping tables containing VA to RA mappings. This table is maintained by the operating system.

ATOs 342, 343 and 344 provide the level of data caching necessary to maintain synchronization with other processing units in the system. Atomic direct memory access commands provide a means for coprocessor units to perform in synchronization with other units.

The main function of BIUs 339, 340 and 341 is to provide interfaces for SPEs 302, 303 and 304 to the EIB. The EIB 319 provides a communication path between all processor cores on the Cell BE chip 300 and the external interface controller attached to the EIB 319.

提供的高速高度串行存储器。由Rambus提供的宏访问极速数据速率动态随机存取存储器，该存储器在本文中称为XIO 321和322。MIC 320 provides an interface between EIB 319 and one or both of XIOs 321 and 322 . Extreme Data Rate (XDR ^TM ) Dynamic Random Access Memory (DRAM) is developed by Rambus

High-speed highly serial memory provided. Macro-access extreme data rate dynamic random access memories provided by Rambus, referred to herein as XIO 321 and 322.

MIC 320 is just a slave on EIB 319. The MIC 320 acknowledges commands within its configured address range corresponding to memory in the supported hubs.

BICs 324 and 325 manage on-chip or off-chip data transfers from EIB 319 to either of the two external devices. BIC 324 and 325 can exchange non-coherent services with I/O devices, or it can extend EIB 319 to another device, which can even be another Cell BE chip. When used to extend the EIB 319, the bus protocol maintains coherence between the cache in the Cell BE chip 300 and the cache in an attached external device, which may be another Cell BE chip.

The IOC 326 handles commands initiated in the I/O interface device and sent to the associated EIB 319. The I/O interface device can be any device attached to the I/O interface, such as an I/O bridge chip with multiple I/O devices or another Cell BE chip 300 accessed in a non-uniform manner. The IOC 326 also intercepts accesses on the EIB 319 to memory-mapped registers residing in or after the I/O bridge chip or non-coherent Cell BE chip 300 and routes them to the correct I/O interface. The IOC 326 also includes an internal interrupt controller (IIC) 349 and an I/O address translation unit (I/O Trans) 350 .

Pervasive logic (pervasive logic) 351 is a controller that provides clock management, test features and power-on sequence for Cell BE chip 300 . Pervasive logic can provide a thermal management system for the processor. The pervasive logic includes connections to other devices in the system through Joint Test Action Group (JTAG) or SPI (Serial Peripheral Interface) interfaces known in the art.

Although specific examples of how the various components may be implemented have been provided, this is not meant to limit the architectures in which aspects of the illustrative embodiments may be used. Aspects of the illustrative embodiments may be used in conjunction with any multi-core processor system.

During the execution of the application or software, the temperature of the area inside the Cell BE chip may rise. If left unchecked, the temperature may rise above the maximum specified junction temperature, causing incorrect operation or physical damage. To avoid these situations, the Cell BE chip's digital thermal management unit monitors and attempts to control the temperature inside the Cell BE chip during operation. The digital thermal management unit consists of a thermal management control unit (TMCU) and ten distributed digital thermal sensors (DTS) as described here.

One sensor is located in one of the eight SPEs, one sensor is located in the PPE, and one sensor is adjacent to the linear thermal diode. Linear thermal diodes are on-chip diodes that calculate temperature. These sensors are located adjacent to areas within the associated unit that typically experience the greatest rise in temperature during execution of most applications. The thermal control unit monitors the feedback from each of these sensors. If the temperature of the sensor rises above a programmable point, the thermal control unit may be configured to cause interruption of the PPE or one or more SPEs and dynamically adjust execution of the associated PPE or SPE.

Stopping and running the PPE or SPE for a programmable number of cycles provides the necessary accommodations. Interrupts enable privileged software to take corrective action, while dynamic regulation attempts to keep the temperature inside the broadband engine chip below a programmable level without software intervention. Privileged software sets the throttling level at or below the recommended setting provided by the application. Each application may be different.

If adjusting the PPE or SPE is not effectively managing the temperature and the temperature continues to rise, the pervasive logic 351 stops the clock of the Cell BE chip when the temperature reaches the thermal overload temperature (defined by the programmable configuration data). The thermal overload feature protects Cell BE chips from physical damage. Recovery from this situation requires a hard reset. The temperature of the area monitored by the DTS is not necessarily the hottest point within the associated PPE or SPE.

FIG. 4 shows an example thermal management system in accordance with an illustrative embodiment. The thermal management system may be implemented as an integrated circuit, such as that provided by pervasive logic unit 351 of FIG. 3 . Thermal management systems can be ASICs, processors, multiprocessors, or heterogeneous multicore processors. The thermal management system is divided between ten distributed DTSs and Thermal Management Control Units (TMCUs) 402, only DTSs 404, 406, 408 and 410 are shown for simplicity. Each of DTS 404 and 406 in SPU sensor 440, DTS 408 in PPU sensor 442, and DTS 410 in sensor 444 adjacent to a linear thermal diode (not shown) provides a current temperature sense signal. This signal indicates that the temperature is equal to or less than the current temperature detection range set by TMCU 402. The TMCU 402 uses the status of the signals from the DTS 404, 406, 408 and 410 to continuously track the temperature of the DTS 404, 406, 408 or 410 of each PPE or SPE. As the temperature is tracked, the TMCU 402 provides the current temperature as a value representing the temperature within the associated PPE or SPE. The factory that calibrates individual sensors sets internal calibration memory 428 .

In addition to the units of TMCU 402 described above, TMCU 402 includes multiplexers 446 and 450, working registers 448, comparators 452 and 454, serializer 456, thermal management control state machine 458, and data flow (DF) unit 460. Multiplexers 446 and 450 combine the various outgoing and incoming signals for transmission on a single medium. Working registers 448 hold the results of multiplications performed in TMCU 402. Comparators 452 and 454 provide a compare function for the two inputs. Comparator 452 is a greater than or equal to comparator. Comparator 454 is a greater than comparator. Serializer 456 converts low-speed parallel data from a source to high-speed serial data for transmission. Serializer 456 works in conjunction with deserializers 462 and 464 on SPU sensor 440 . Deserializers 462 and 464 convert received high-speed serial data into low-speed parallel data. Thermal management control state machine 458 initiates internal initialization of TMCU 402. DF unit 460 controls data to and from thermal management control state machine 458 .

TMCU 402 may be configured to use interrupt logic 416 to raise an interrupt to the PPE to use throttling logic 418 to dynamically throttle execution of the PPE or SPE.

The TMCU 402 compares the value representing the temperature to a programmable cutout temperature and a programmable setpoint. Each DTS has an independently programmable cutout temperature. If the temperature is within the programmed interrupt temperature range, the TMCU 402 generates an interrupt to the PPE, if enabled. An interrupt is generated if the temperature is above or below a programmed level depending on the direction bit described below. In addition, a second programmable interrupt temperature may trigger an attention signal to the system controller. The system controller is on the system board and connects to the CellBE on the SPI port.

If the temperature sensed by the DTS associated with the PPE or SPE is at or above the throttling point, the TMCU 402 regulates the performance of the PPE or SPE by independently starting and stopping the PPE or one or more SPEs. Software can control the rate and frequency of throttling using thermal management registers such as the Thermal Management Stop Time Register and the Thermal Management Scale Register.

FIG. 5 depicts a temperature profile and various points at which interruptions and dynamic adjustments may occur, according to an illustrative embodiment. In FIG. 5, line 500 may represent the temperature of the PPE or SPE. If the PPE or SPE is functioning normally, then no adjustments are made in the area marked with an "N". When the temperature of the PPE or SPE reaches a throttling point, the TMCU begins to throttle the execution of the associated PPE or SPE. Regions where regulation occurs are marked with a "T". When the temperature of the PPE or SPE drops below the end regulation point, execution returns to normal operation.

If for any reason the temperature continues to rise and reaches a temperature at or above the full turndown point, the TMCU 402 stops the PPE or SPE until the temperature drops below the full turndown point. Areas where PPE or SPE are discontinued are marked with an "S". Stopping the PPE or SPE when the temperature is at or above the full regulation point is called core stop safety.

In this exemplary illustration, the interrupt temperature is set above the throttling point; therefore, the TMCU 402 generates an interrupt, which is a notification to the software that the corresponding PPE or SPE because the temperature was or is still above the core stop temperature Stopped notification; assuming the Thermal Interrupt Mask Register (TM_ISR) is set active, see 422 in Figure 4, enabling the PPE or SPE to continue during a pending interrupt. If dynamic scaling is disabled, privileged software manages thermal conditions. Failure to manage thermal conditions may result in incorrect operation of the associated PPE or SPE or thermal shutdown caused by the thermal overload function.

Returning to FIG. 4 , the thermal sensor status registers include a thermal sensor current temperature status register 412 and a thermal sensor maximum temperature status register 414 . These registers enable software to read the current temperature of each DTS, determine the maximum temperature reached over a period of time, and raise an interrupt when the temperature reaches a programmable temperature. The thermal sensor status register has an associated real address page that can be marked as administratively privileged.

Thermal sensor current temperature status register 412 contains an encoded or digital value of the current temperature for each DTS. Due to latency in sensor temperature detection, latency in reading these registers, and normal temperature fluctuations, the temperature reported in these registers is at an earlier point in time and may not reflect the actual temperature at the time the software received the data. Since each sensor has dedicated control logic, the control logic within DTS 404, 408 and 410 samples all sensors in parallel. The TMCU 402 updates the contents of the thermal sensor current temperature status register 412 at the end of the sampling period. TMCU 402 changes the value in thermal sensor current temperature status register 412 to the current temperature. The TMCU 402 polls for a new current temperature every SenSampTime cycle. The SenSampTime configuration field controls the length of the sampling period.

Thermal sensor maximum temperature status register 414 contains the digitally encoded maximum temperature reached by each sensor since the time thermal sensor maximum temperature status register 414 was last read. Reading these registers by software or any off-chip device such as off-chip device 472 or off-chip I/O device 474 causes TMCU 402 to copy the current temperature of each sensor into the registers. After the read, the TMCU 402 continues to track the maximum temperature from that point on. Each register is read independently. A read of one register does not affect the contents of the other register.

Each sensor has dedicated control logic, so the control logic within DTS 404, 406, 408 and 410 samples all sensors in parallel. TMCU 402 changes the value in thermal sensor maximum temperature status register 414 to the current temperature. The TMCU 402 polls for a new current temperature every SenSampTime cycle. The SenSampTime configuration field controls the length of the sampling period.

The thermal sensor interrupt register in interrupt logic 416 controls the generation of thermal management interrupts to the PPE. The set of registers includes Thermal Sensor Interrupt Temperature Register 420 (TS_ITR1 and TS_ITR2), Thermal Sensor Interrupt Status Register 422 (TS_ISR), Thermal Sensor Interrupt Mask Register 424 (TS_IMR), and Thermal Sensor Global Interrupt Temperature Register 426 (TS_GITR). Thermal sensor interrupt temperature register 420 and thermal sensor global interrupt temperature register 426 contain codes for the temperature that caused the thermal management of the PPE to be interrupted.

When the temperature coded in digital format for the sensor in thermal sensor current temperature status register 412 is greater than or equal to the interrupt temperature code for the corresponding sensor in thermal sensor interrupt temperature register 420, TMCU 402 sets the corresponding Status bits (TS_ISR[Sx]). When the temperature code for any sensor in the thermal sensor current temperature status register 412 is greater than or equal to the global interrupt temperature code in the thermal sensor global interrupt temperature register 426, the TMCU 402 sets the corresponding status bit (TS_ISR) in the thermal sensor interrupt status register 422 [Gx]).

If any Thermal Sensor Interrupt Status Register 422 bit (TS_ISR[Sx]) is set and the corresponding mask bit (TS_IMR[Mx]) in Thermal Sensor Interrupt Mask Register 424 is also set, then the TMCU 402 asserts a thermal management interrupt signal to the PPE . If any Thermal Sensor Interrupt Status Register 422 bit (TS_ISR[Gx]) is set and the corresponding mask bit (TS_IMR[Cx]) in Thermal Sensor Interrupt Mask Register 424 is also set, then the TMCU 402 asserts a thermal management interrupt signal to the PPE .

To clear an interrupt condition, privileged software should set any corresponding mask bit in the thermal sensor interrupt mask register to '0'. To enable thermal management interrupts, privileged software guarantees that the temperature is below the interrupt temperature for the corresponding sensor, and then executes the following sequence. Enabling an interrupt while the temperature is not below the interrupt temperature may result in an immediate thermal management interrupt.

1. Write a "1" to the corresponding status bit in thermal sensor interrupt status register 422.

2. Write a "1" to the corresponding mask bit in thermal sensor interrupt mask register 424 .

Thermal sensor interrupt temperature register 420 contains the interrupt temperature level for sensors located in the SPE, PPE and adjacent to the linear thermal diode. The TMCU 402 compares the interrupt temperature level encoded in this register with the corresponding interrupt temperature code in the thermal sensor current temperature status register 412. The results of these comparisons generate thermal management interrupts. The interrupt temperature level is independent for each sensor.

Thermal sensor global interrupt temperature register 426 contains a second interrupt temperature level in addition to the individual interrupt temperature level set in thermal sensor interrupt temperature register 420 . This level applies to all sensors in the Cell BE chip. The TMCU 402 compares the encoded global interrupt temperature level in this register to each sensor's current temperature encoding. The results of these comparisons generate thermal management interrupts.

The purpose of the global interrupt temperature is to provide an early indication of temperature rise in the Cell BE chip. Privileged software and system controllers can use this information to initiate measures to control temperature, such as increasing fan-in speed, rebalancing application software between units, and so on.

Thermal sensor interrupt status register 422 identifies which registers satisfy the interrupt condition. An interrupt condition refers to a specific condition that each thermal sensor interrupt status register 422 bit has, and an interrupt may occur when the specific condition is met. The actual interrupt is only submitted to the PPE if the corresponding mask bit is set.

The thermal sensor interrupt status register 422 includes three groups of status bits, namely digital sensor global threshold interrupt status bit (TS_ISR[Gx]), digital sensor threshold interrupt status bit (TS_ISR[Sx]) and digital sensor global threshold interrupt status bit (TS_ISR[Sx]). [Gb]).

When the sensor temperature code in the thermal sensor current temperature status register 412 is greater than or equal to the interrupt temperature code of the corresponding sensor in the thermal sensor interrupt temperature register 420 and the corresponding direction bit TM_IMR[Bx]='0 in the thermal sensor interrupt mask register 424 ', the TMCU 402 sets the status bit (TS_ISR[Sx]) in the Thermal Sensor Interrupt Status Register 422. In addition, when the sensor temperature code in the thermal sensor current temperature status register 412 is lower than the interrupt temperature code of the corresponding sensor in the thermal sensor interrupt temperature register 420 and the corresponding direction bit TM_IMR[Bx] in the thermal sensor interrupt mask register 424=' When 1', TMCU 402 sets thermal sensor interrupt status register 422, namely TS_ISR[Sx].

When the current temperature of any participating sensor is greater than or equal to the current temperature of thermal sensor global interrupt temperature register 426 and thermal sensor interrupt mask register 424TM_IMR[B _G ]='0', TMCU 402 sets thermal sensor interrupt status register 422, i.e. TS_ISR[ Gx]. The TS_ISR[Gx] bits of the individual thermal sensor interrupt status register 422 indicate which individual sensors meet these conditions.

When the current temperature of all participating sensors in thermal sensor interrupt mask register 424TM_IMR[Cx] is lower than the current temperature of thermal sensor global interrupt temperature register 426 and thermal sensor interrupt mask register 424TM_IMR[B _G ]='1', TMCU 402 Sets the Thermal Sensor Interrupt Status Register 422, ie TS_ISR[Gb]. Since the current temperature of all participating sensors is lower than the current temperature of the thermal sensor global interrupt temperature register 426, only one status bit (TS_ISR[Gb]) in the thermal sensor interrupt status register 422 is present for the global subthreshold interrupt condition.

Once a status bit (TS_ISR[Sx], TS_ISR[Gx], or TS_ISR[Gb]) in Thermal Sensor Interrupt Status Register 422 is set to '1', the TMCU 402 maintains that status until reset to '0' by privileged software '. Privileged software resets the status bits to '0' by writing a '1' to the corresponding bit in thermal sensor interrupt status register 422.

Thermal sensor interrupt mask register 424 contains two fields for individual sensors and multiple fields for global interrupt conditions. An interrupt condition refers to a specific condition that each thermal sensor interrupt status register 422 bit has, and an interrupt may occur when the specific condition is met. The actual interrupt is only submitted to the PPE if the corresponding mask bit is set.

The digital thermal limit interrupt fields of the two thermal sensor interrupt mask registers for individual sensors are TS_IMR[Mx] and TS_IMR[Bx]. Mask bits TS_IMR[Mx] of thermal sensor interrupt mask register 424 prevent interrupt status bits from generating thermal management interrupts to the PPE. Direction bit TS_IMR[Bx] of thermal sensor interrupt mask register 424 sets the temperature direction of the interrupt condition to be above or below the corresponding temperature in thermal sensor interrupt temperature register 420 . Setting TS_IMR[Bx] of Thermal Sensor Interrupt Mask Register 424 to '1' sets the temperature of the interrupt condition to be lower than the corresponding temperature in Thermal Sensor Interrupt Temperature Register 420 . Setting TS_IMR[Bx] of thermal sensor interrupt mask register 424 to '0' sets the temperature of the interrupt condition to be equal to or higher than the corresponding temperature in thermal sensor interrupt temperature register 420 .

The thermal sensor interrupt mask register 424 fields for global interrupt conditions are TS_IMR[Cx], TS_IMR[B _G ], TS_IMR[Cgb], and TS_IMR[A]. Mask bits TS_IMR[Cx] of thermal sensor interrupt mask register 424 prevent global threshold interrupts and select which sensors participate in global sub-threshold interrupt conditions. Direction bits TS_IMR[B _G ] of thermal sensor interrupt mask register 424 select the temperature direction for the global interrupt condition. Mask bit TS_IMR[Cgb] of thermal sensor interrupt mask register 424 prevents interrupts below the global threshold. Thermal sensor interrupt mask register 424TS_IMR[A] raises an attention signal to the system controller. The attention signal is a signal to the system controller that the pervasive logic requires attention or has a status for the system controller. Attention signals can be mapped to interrupts in the system controller. The system controller is on the system plane (planer) and is connected to the CellBroadband Engine on the SPI port.

Setting TS_IMR[B _G ] of thermal sensor interrupt mask register 424 to '1' sets the temperature range for the global interrupt condition to that of all participating sensors when set in TS_IMR[Cx] of thermal sensor interrupt mask register 424 Occurs when temperatures are below the global interrupt temperature level. Setting TS_IMR[B _G ] of thermal sensor interrupt mask register 424 to '0' sets the temperature range for the global interrupt condition to be when the temperature of any participating sensor is greater than or equal to the corresponding temperature in thermal sensor global interrupt temperature register 426 happens when. If TS_IMR[A] of thermal sensor interrupt mask register 424 is set to '1', then any thermal sensor interrupt mask register 424 TS_IMR[Cx] bit and its corresponding thermal sensor interrupt status register 422 status bit (TS_ISR[Gx]) are both When set to '1' the TMCU 402 raises an attention signal. In addition, TMCU 402 raises an attention signal when both TS_IMR[Cgb] of thermal sensor interrupt mask register 424 and TS_ISR[Gb] of thermal sensor interrupt status register 422 are set to '1'.

The TMCU 402 submits a thermal management interrupt to the PPE when any Thermal Sensor Interrupt Mask Register 424 TS_IMR[Mx] bit and its corresponding Thermal Sensor Interrupt Status Register 422 Status bit (TS_ISR[Sx]) are both set to '1'. The TMCU 402 generates a thermal management interrupt when any thermal sensor interrupt mask register 424 TS_IMR[Cx] bit and its corresponding thermal sensor interrupt status register 422 status bit (TS_ISR[Gx]) are both set to '1'. Additionally, the TMCU 402 submits a thermal management interrupt to the PPE when both TS_IMR[Cgb] of the thermal sensor interrupt mask register 424 and TS_ISR[Gb] of the thermal sensor interrupt status register 422 are set to '1'.

The dynamic thermal management registers in the tuning logic 418 contain parameters for controlling the performance tuning of the PPE or SPE. The dynamic thermal management register is a group of registers, including thermal management control register 430 (TM_CR1 and TM_CR2), thermal management regulation point register 432 (TM_TPR), thermal management stop time register 434 (TM_STR1 and TM_STR2), thermal management regulation ratio register 436 ( TM_TSR) and Thermal Management System Interrupt Mask Register 438 (TM_SIMR).

The thermal management trim point register 432 sets the trim temperature point for the sensor. Two separate throttling temperature points, ThrottlePPE and ThrottleSPE, may be set in thermal management throttling point register 432, one for the PPE and the other for the SPE. Also included in this register are temperature points for disabling regulation and stopping the PPE or SPE. Execution regulation of PPE or SPE begins when the temperature is at or above the regulation point. Throttling stops when the temperature drops below the temperature used to disable throttling (TM_TPR[EndThrottlePPE/EndThrottleSPE]). If the temperature reaches a full throttle temperature or a stop temperature (TM_TPR[FullThrottlePPE/FullThrottleSPE]), the TMCU 402 stops execution of the PPE or SPE. Thermal management control register 430 controls throttling behavior.

The thermal management stop time register 434 and the thermal management throttling ratio register 436 control throttling frequency and throttling amount. When the temperature reaches the regulation point, TMCU 402 stops the corresponding PPE or SPE for a certain number of clocks, which is multiplied by the corresponding ratio in the thermal management regulation ratio register 436 by the stop time in the corresponding value in the thermal management stop time register 434 value to specify. The TMCU 402 then enables the PPE or SPE to run for a number of clocks specified by the run time multiplied by the corresponding scale value, where the run time is the difference between an implementation-dependent fixed amount of time minus the stop time . The programmable scale value in thermal management throttling scale register 436 is a multiplier for stop time and run time. An example could be (Stop*Scale)/(Run*Scale)((Stop Time*Scale)/(Run Time*Scale)). The percentage of time the core is stalled remains the same, but the period is increased or the frequency is decreased. This sequence continues until the temperature drops below disable regulation (TM_TPR[EndThrottlePPE/EndThrottleSPE]).

Thermal management system interrupt mask register 438 selects which PPE interrupt will cause TMCU 402 to disable throttling. The TMCU 402 will continue to block throttling while these interrupts are still pending and the mask still selects the pending interrupt. If the mask is deselected or the interrupt is no longer pending, the TMCU 402 will no longer block interrupts.

The thermal management control register 430 sets the throttling mode independently for each PPE or SPE. Split the control bits between the two registers. Below are five different modes that can be set independently for each PPE or SPE:

Disable dynamic scaling (including kernel stop safety);

Normal operation (dynamic scaling and kernel halted safety enabled);

Always throttle PPE or SPE (kernel stop safety enabled);

disable kernel stop safety (enable dynamic scaling and disable kernel stop safety);

Always tune PPE or SPE and disable kernel stop safety.

Privileged software should set the control ratio to normal operation for the PPE or SPE running the application or operating system. If the PPE or SPE is not running application code, privileged software should set the control bits to disabled. The "always adjust PPE or SPE" mode is intended for application development. These modes are useful for determining whether an application can operate under extreme regulation conditions. Enabling PPE or SPE to execute with dynamic scaling or kernel stall security disabled should only be done when privileged software is actively managing thermal events.

Thermal management system interrupt mask register 438 controls which PPE interrupt causes thermal management logic to temporarily stop regulating the PPE. TMCU 402 temporarily suspends mediation of these two threads while the interrupt is pending, regardless of which thread the interrupt is directed to. When an interrupt is no longer pending, throttling can continue as long as the throttling condition still exists. The throttling of the SPE is never disabled based on a system interrupt condition. The PPE interruption conditions that can take precedence over conditioning conditions are as follows:

external

Reducer

Hypervisor reducer

system error

thermal management

Thermal management throttling point register 432 contains encoded temperature points at which execution throttling of the PPE or SPE begins and ends. This register also contains the encoded temperature point at which the execution of the PPE or SPE is fully tuned.

Software uses the value in the Thermal Management Throttle Point register to set the three temperature points for changing between the three thermal management states: normal operation (N), throttling PPE or SPE (T), and stop PPE or SPE(S). The TMCU 402 supports separate temperature points for PPE and SPE.

When the encoded sensor current temperature in the thermal sensor current temperature status register 412 is equal to or greater than the throttling temperature (ThrottlePPE/ThrottleSPE), if enabled, execution throttling of the corresponding PPE or SPE will begin. Execution of throttling continues until the encoded current temperature of the corresponding sensor is less than the encoded temperature of the end throttling (EndThrottlePPE/EndThrottleSPE). As a safety measure, if the encoded current temperature is equal to or greater than the full throttling point (FullThrottlePPE/FullThrottleSPE), then the TMCU 402 stops the corresponding PPE or SPE.

The thermal management stop time register 434 controls the amount of throttling applied to a particular PPE or SPE while in the thermal management throttling state. The value set by software in thermal management stop time register 434 indicates the amount of time the core will be stopped relative to the amount of time the core is allowed to run (stop/run) or the percentage of time the core is stopped. Thermal management throttling scale register 436 controls the actual number of clocks (NClks) that the PPE or SPE stops and runs.

Thermal management throttling scale register 436 controls the actual number of cycles that the PPE or SPE is stopped and run during the thermal management throttling state. The value in this register is a multiple of the configuration ring setting TM_config[MinStopSPE]. The following equations calculate the actual number of stop and run cycles:

SPE running and stopping time:

SPE_StopTime=(TM_STR1[StopCore(x)]*

TM_Config[MinStopSPE])*TM_TSR[ScaleSPE]

SPE_RunTime＝(32-TM_STR1[StopCore(x)])*

TM_Config[MinStopSPE])*TM_TSR[ScaleSPE]

单元运行和停止时间：power

Unit run and stop times:

PPE_StopTime=(TM_STR2[StopCore(8)]*

TM_Config[MinStopPPE])*TM_TSR[ScalePPE]

PPE_RunTime＝(32-TM_STR2[StopCore(8)])*

TM_Config[MinStopPPE])*TM_TSR[ScalePPE]

Run and stop times can be changed by interrupts and privileged software writing to various thermal management registers.

On-chip performance monitor 466 may provide performance monitoring that may track thermal data provided by temperature sensing devices such as DTS 404 , 406 , 408 , and 410 . Thermal data may be stored in memory 470 or written to an off-chip device 472 such as main memory 208 of FIG. 2 or to a south bridge and input/output (I/O) controller hub (ICH) such as FIG. 2 An off-chip I/O device 474 such as 204. Controller 468 located in performance monitor 466 controls the determination of where to send thermal data.

Although the following description is directed to one instruction stream and one processor, the instruction stream may be a set of instruction streams and the processor may be a set of processors. That is, a group can be a single instruction stream and a single processor or two or more instruction streams and processors.

With the architecture described above, many improvements have been made and programmability has been added to the thermal management and thermal regulation of the Cell BE chips. Some of these improvements and added programmability enable key features while others enhance usability.

FIG. 6 depicts a flowchart of operations for recording maximum temperature, in accordance with an illustrative embodiment. As operations begin, the computer system that includes the Cell BE chip, such as the Cell BE chip 300 of FIG. 3, starts up or restarts (step 602). As mentioned before, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 of FIG. 3 . For each DTS such as DTS 404, 406, 408 and 410 of FIG. Temperature Status Register 412 . The current temperature status register stores its target DTS and the current temperature since the DTS was last sensed by a thermal management control state machine, such as thermal management control state machine 458 of FIG. 4 . The maximum temperature status register stores its target DTS maximum temperature since the last time the computer system read the maximum temperature status register or since the computer system was restarted. The maximum temperature status register can be read using any number of devices such as processors, integrated circuits, or by using a serial peripheral interface (SPI) port or a joint test action group (JTAG) port. However, reading registers through the JTAG port does not cause a reboot.

Illustratively limiting the following discussion to one DTS, the maximum temperature after a computer system startup or restart (step 602 ) is zero. Once the thermal management control state machine senses the temperature of the DTS, the thermal management control state machine sends the sensed temperature of the DTS to a comparator, such as comparator 454 of FIG. 4 (step 604). The comparator compares the sensed temperature to the current maximum temperature for the DTS stored in the maximum temperature status register (step 606). If at step 606 the sensed temperature is higher than the current maximum temperature stored in the maximum temperature status register, then the sensed temperature becomes the new maximum temperature and the thermal management control state machine records the new maximum temperature into the maximum temperature status register (step 608) . That is, the thermal management control state machine overrides or replaces the current maximum temperature stored in the maximum temperature status register. If the sensed temperature is lower than or equal to the current maximum temperature stored in the maximum temperature status register at step 606, then the maximum temperature status register holds the existing current maximum temperature in the maximum temperature status register (step 610).

The current maximum temperature in the maximum temperature status register stays at the maximum temperature until the computer system reads the maximum temperature status register in the form of a read request (step 612) or the computer system is restarted. If the current maximum temperature is not read, then operation returns to step 604 . If the computer system reads the current maximum temperature at step 612 , the thermal management control state machine resets the current maximum temperature to the current temperature in the current temperature status register (step 614 ) and operation returns to step 604 .

For an example of this operation, if the DTS for a particular unit, such as a processor core or the processor itself, is to sense temperatures of 67°C, 70°C, 75°C, 72°C, and 74°C over a period of time, then the maximum temperature state The maximum temperature in the register will be 75°C. If the computer system issues a read request after the fourth sense of the DTS, the maximum temperature returned will be 75°C. However, at this point the thermal management control state machine resets the maximum temperature to the current temperature, and after the last sense performed by the DTS, the maximum temperature in the maximum temperature status register will be 74°C.

Thus, the purpose of the Max Temperature Status Register is to record the maximum temperature the DTS has reached since the Max Temperature Register was last read. This maximum temperature information helps the operating system determine the maximum temperature the DTS reached during application or program execution without continuously polling the current temperature register. Continuous polling will affect the performance of the system and therefore may affect the maximum temperature. Also, polling for the current temperature does not guarantee that the maximum temperature will be read. This is the case if the maximum temperature occurs between multiple readings of the current temperature.

7 depicts a flowchart of operations for tracking thermal data through performance monitoring, according to another illustrative embodiment. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . Performance monitoring may be provided by a performance monitor, such as performance monitor 466 of FIG. 4 . Performance monitoring can track thermal data provided by temperature sensing devices such as DTS 404, 406, 408 and 410 of FIG. 4 in their internal memory, such as memory 470 of FIG. Main memory such as 208 or off-chip device 472 of FIG. 4, or write to such as the south bridge of FIG. I/O devices such as 474.

Performance Monitoring supports two main tracing modes: tracing for a fixed period of time and continuous tracing. The track of thermal performance may be a track such as track 500 of FIG. 5 . Performance monitoring can also specify the configuration of the sampling frequency to control the time period between two consecutive samples. Additionally, thermal information compression can be used to increase the sampling interval. One compression technique is to store hot information only when changes occur. A count of the number of identical thermal samples may also be stored with the thermal information. This is a useful technique because thermal information typically changes slowly.

As operations for tracking thermal data by the performance monitor begin, a thermal management control state machine, such as thermal management control state machine 458 of FIG. 4, sets the performance monitor into tracking mode (step 702). Illustratively limiting the following discussion to one DTS, the thermal management control state machine senses the temperature of the DTS (step 704) and sends the sensed temperature of the DTS to a current temperature status register and/or other data structure for storage (step 706) . At this point the thermal management control state machine determines whether the performance monitor is still running (step 708). Once the performance monitor is started in step 702, the performance monitor will run for a user-specified period of time or until stopped by the user via user input. However, the performance monitor can also be stopped based on certain thermal conditions. This specific thermal condition is called a trigger, such as a logic analyzer that looks for a specific condition on a set of signals. The use of flip-flops is useful in software debugging. For example, a user can set the performance monitor to stop or checkstop the system when a thermal condition is reached. This enables the user to determine exactly which code or combination of codes is causing the thermal condition. If the performance monitor is still running at step 708, then operation returns to step 704.

Returning to step 708, if the performance monitor is no longer running, the thermal management control state machine reads the temperature information stored in memory and graphically displays the stored information to the user (step 710), after which the operation ends. The sensed temperature sent to the current temperature status register and/or other data structures at step 706 may also be displayed while the operation is still in the process indicated by arrow 712 (step 710 ), rather than waiting for the trace to end.

Thus, the performance monitor tracks thermal data provided by DTS. Automatic tracking of thermal data eliminates the need for software to continuously poll the current temperature register. Performance monitoring is important for collecting hot data for workloads because performance monitoring does not require the insertion of additional code to poll for hot data, which could change the behavior of the workload. In other words, performance monitoring provides a non-intrusive way to track thermal signature data of software applications in real time. An additional benefit of sending thermal information to the performance monitor is the ability to trigger or stop logging of thermal information on pre-specified thermal conditions. Additionally, performance monitors can also be used to shut down the system (or checkout) when thermal conditions are met. Doing so enables the user to determine which code segment or combination of code segments is producing the thermal condition. Users can then rewrite code segments or avoid specific combinations, thus avoiding hot events.

8A and 8B depict flow diagrams of operations for advanced thermal interrupt generation, according to further illustrative embodiments. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . Advanced thermal interrupt generation is another feature that helps the operating system handle thermal events. Advanced thermal interrupt logic is part of a thermal management control unit such as TMCU 402 of FIG. 4 . A thermal interrupt alerts the operating system when there is a thermal condition (that is, the chip temperature rises above a certain threshold). In this case, the operating system should take corrective measures to reduce the chip temperature. Corrective action can be handled by a software interrupt handler, which is a piece of code that handles the thermal condition and initiates corrective action. The operating system then waits for the thermal condition to dissipate before continuing normal operation. This usually requires the operating system to wait a specific amount of time and then poll the processor's temperature to determine if it is safe to continue normal operation. Using advanced thermal interrupt generation, the operating system can set up an interrupt to detect when the temperature drops below a certain threshold, eliminating the need to poll the current temperature register. The combination of thermal sensor interrupt mask register 424 (TS_IMR) and thermal sensor interrupt status register 422 (TS_ISR) of FIG. 4 makes it easier for the operating system to handle thermal events.

Advanced thermal interrupt generation can be performed on a local level or a global level. That is, advanced hot interrupt generation can be performed individually (locally) on a specific DTS or on all (global) DTSs such as DTSs 404, 406, 408 and 410 of FIG. The direction bits of the thermal sensor interrupt mask register are B _G and B _X . The interrupt direction defines the conditions under which an interrupt is generated. An interruption may occur when the temperature changes from below the interruption temperature to at or above the interruption temperature, or when the temperature changes from above or at the interruption temperature to below the interruption temperature. The thermal management control state machine identifies the condition with the direction bits B _G and B _X in the interrupt mask register. B _G is the global direction bit. When B _G is set to '0', the thermal management control state machine generates an interrupt when the temperature of any DTS is greater than or equal to the global interrupt temperature. When B _G is set to '1', the thermal management control state machine generates an interrupt when the temperature of all DTSs is lower than the global interrupt temperature. B _X is the local direction bit, where X is the number of individually associated DTSs. When B _X is set to '0', the thermal management control state machine generates an interrupt when the temperature of an individual DTS is greater than or equal to the DTS interrupt temperature. When B _X is set to '1', the thermal management control state machine generates an interrupt when the temperature of an individual DTS is lower than the DTS interrupt temperature. The thermal interrupt status register (TS_ISR) records which sensor caused the high-level thermal interrupt. Software reads this register to determine which condition occurred and which sensor or sensors caused the interrupt. Once read by software, the thermal management control state machine resets the status bit in the thermal interrupt status register.

Thus, operations generated for high-level thermal interrupts can be shown both globally and locally. FIG. 8A depicts the generation of a global high-level thermal interrupt, and FIG. 8B describes the generation of a local high-level thermal interrupt. As operation begins in the global advanced thermal interrupt generation of FIG. 8A, the thermal management control state machine sets the global interrupt temperature T to temperature T1 and the global interrupt direction _BG to '0' (step 802). The thermal management control state machine senses the temperature of the DTS (step 804). The thermal management control state machine determines whether any temperature sensed from the DTS is greater than or equal to temperature T1 (step 806). If no sensed temperature is greater than or equal to temperature T1 , then operation returns to step 804 . If any sensed temperature is greater than or equal to temperature T1 at step 806, the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which sensor or sensors caused the interrupt (step 808). The operating system will then service the interrupt and can either slow down the workload on the processor or offload part of the processor's workload to another processor in the system.

After generating the interrupt, the thermal management control state machine sets the global interrupt temperature T to temperature T2 and the global interrupt direction _BG to '1' (step 810). The temperature T2 should be set to be less than or equal to the temperature T1. The thermal management control state machine again senses the temperature of the DTS (step 812). The thermal management control state machine determines if all sensed temperatures from the DTS are below temperature T2 (step 814). If no sensed temperature is below temperature T2 , then operation returns to step 812 . If at step 814 all sensed temperatures are below temperature T2, then the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which sensor or sensors caused the interrupt (step 816). At this point, it is now safe for the operating system to continue normal operation. The operating system will then service the interrupt and restore the system to normal operation. Next, the operation returns to step 802, where the global breakout temperature T is set to temperature T1 and the global breakout direction _BG is set to '0'.

An example of this operation is that all DTSs have a global interrupt temperature of 80°C and a global interrupt direction of '0'. Once any DTS of an associated unit such as the processor core or the processor itself senses a temperature greater than or equal to 80°C, the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which The sensor or which sensors caused the interrupt. The operating system will then service the interrupt and can either slow down the workload on the processor or offload part of the processor's workload to another processor in the system. Also, at this point the thermal management control state machine may reset the global interrupt temperature to an exemplary 77°C and set the global interrupt direction to '1'. The workload will continue to operate in slow mode or remain unprocessed by the processor until the DTS senses a temperature below 77°C for all DTSs. Once the thermal management control state machine determines that the sensed temperature is below 77°C, the thermal management control state machine generates another interrupt. The thermal management control state machine sets the global interrupt temperature to 80°C, sets the global interrupt direction to '0', and then the operating system continues normal operation of the workload.

Turning to FIG. 8B, the illustrative embodiment is limited to one DTS, but the illustrative embodiment is the same for each DTS. As operations begin for local advanced thermal interrupt generation, the thermal management control state machine sets the local interrupt temperature T to temperature T3 and the local interrupt direction B _X to '0' (step 852 ). The thermal management control state machine senses the temperature of the DTS (step 854). The thermal management control state machine determines whether the temperature sensed from the DTS is greater than or equal to temperature T3 (step 856). If the sensed temperature is not greater than or equal to temperature T3 , then operation returns to step 854 . If the sensed temperature is greater than or equal to temperature T3, the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which sensor or sensors caused the interrupt (step 858). The operating system will then service the interrupt and may slow down the workload on the processor or offload part of the processor's workload to other units within the processor or to another processor in the system.

After the thermal management control state machine generates the interrupt, the thermal management control state machine sets the local interrupt temperature T to temperature T4 and the global interrupt direction B _X to '1' (step 860). The temperature T4 should be set to be less than or equal to the temperature T3. The thermal management control state machine again senses the temperature of the DTS (step 862). The thermal management control state machine determines whether the temperature sensed from DTS is lower than temperature T4 (step 864). If the sensed temperature is not lower than temperature T4, then operation returns to step 862. If the sensed temperature is lower than temperature T4, the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which sensor or sensors caused the interrupt (step 866). At this point, it is now safe for the operating system to continue normal operation. The operating system will then service the interrupt and restore the system to normal operation. Next, operation returns to step 852, where the thermal management control state machine sets the global interrupt temperature T to temperature T3 and the global interrupt direction B _X to '0'.

An example of this operation is given a DTS with a local interruption temperature of 80°C and a local interruption direction of '0'. Once the associated cell's DTS senses a temperature greater than or equal to 80°C, the thermal management control state machine generates an interrupt and sets the corresponding status bit in the thermal interrupt status register to record which sensor or sensors caused the interrupt. The operating system will then service the interrupt and can either slow down the workload on the processor or offload part of the processor's workload to another processor in the system. Also, at this point the thermal management control state machine may reset the local interrupt temperature to an exemplary 77°C and set the local interrupt direction to '1'. The workload will continue to run in slow mode or remain off the processor unit until the DTS senses a temperature below 77°C. Once the thermal management control state machine determines that the sensed temperature is below 77°C, the thermal management control state machine generates another interrupt. The thermal management control state machine sets the local interrupt temperature to 80°C and the local interrupt direction to '0', and then the operating system continues normal operation of the workload.

In this way, advanced thermal interrupt generation enables the operating system to program interrupt generation to follow the direction of temperature change and eliminates the need for an interrupt handler to continuously poll the current temperature in the event of a thermal interrupt.

FIG. 9 depicts a flow diagram for supporting deep power saving mode and partially benign operation in a thermal management system, according to an additional illustrative embodiment. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . In the Cell BE chip 300 in FIG. 3 , there are multiple energy-saving modes. Depending on how each power saving mode is implemented, some power saving modes may limit the accessibility of DTSs such as DTSs 404, 406, 408, and 410 of FIG. 4 . For example, if an SPU such as SPUs 310, 311, and 312 of FIG. The path between a serializer such as serializer 456 and a DTS such as DTS 404 of FIG. 4 does not work. Another example of a power saving mode may be a case where the power is turned off. In this case, actual DTS may be disabled. Another example is where the thermal management control state machine determines if a sensor or unit within the processor is broken during manufacturing testing. If a sensor or unit is redundant, the manufacturer can mark that sensor or unit as defective, resulting in a partially good processor that will have only a limited number of units or sensors functioning. In either case, a thermal management control state machine, such as thermal management control state machine 458 of FIG. ).

Returning to FIG. 9 , a flowchart for supporting deep power saving modes and partially benign operation in a thermal sensing and thermal management system is depicted. As operation begins, the thermal management control state machine tracks the state of the DTS using data from each DTS (step 902). The thermal management control state machine stores these data into internal calibration memory, such as internal calibration memory 428 of FIG. 4 . As previously mentioned, power saving modes, disqualified DTSs, or the SPU communicating with the thermal management control state machine through a data stream such as data stream 460 of FIG. 4 may inhibit the operation of a particular DTS. The partial good condition reported by the fabrication process has similar effects to power save mode, except that partial good is a permanent condition and DTS should be permanently disabled. In the event that an SPU is marked as bad, the thermal management control state machine shuts down the entire SPU and disables the serializer. In the event that a DTS is marked as unqualified, the thermal management control state machine masks the DTS. The thermal management control state machine determines whether the DTS or SPU is faulty or functional (step 904). If the DTS or the SPU is unqualified, the thermal management control state machine masks the DTS (step 906), and then the operation ends.

In order to shield the DTS in the power management state, the thermal management control state machine resets the relevant current temperature state register in the current temperature state register such as the current temperature state register 412 of FIG. 4 to 0x0, and 0x0 is the minimum temperature setting . An alternative could also be to assign the associated current temperature status register code by setting the status bit to indicate that DTS is masked, which can be more accurate than just resetting the sensor reading. The thermal management control state machine then stops communication to and from the DTS from the current temperature status register. Stopping communication is an optional step, primarily to save power and not perform useless overhead work. The thermal management control state machine then generates a signal indicating that the DTS is now disabled and should not participate in thermal management tasks. Finally, the thermal management control state machine resets the state of the DTS. When a DTS-related unit such as the processor core or the processor itself exits the energy-saving mode, the thermal management control state machine continues to communicate with the DTS, continues to update the current temperature status register, and sends a message that the DTS can participate in the thermal management task. Signal.

Returning to step 904, if both the DTS and the SPU are functional, the thermal management control state machine begins communicating with the DTS (step 908). The thermal management control state machine monitors the power management state of the SPU to determine when the SPU enters a power saving mode (step 910). Operation returns to step 908 before the SPU enters the power saving mode. If the SPU enters power saving mode and DTS is disabled, then the thermal management control state machine disables DTS using the method discussed above in connection with step 906 (step 912). With the indication of whether DTS is disabled or active, the thermal management control state machine continues to monitor the power management status of the SPU (step 914). Operation returns to step 912 before the SPU exits the power saving mode. When the SPU exits the energy-saving mode and the DTS is no longer disabled, the thermal management control state machine begins to communicate with the DTS, continues to update the current temperature status register, and sends a signal that the DTS can participate in the thermal management task (step 916), and then the operation returns Go to step 908.

In this way, masking the temperature readings of DTSs that are partially good, failing, or in power saving mode isolates inoperative or disabled DTSs from participating in thermal management tasks.

10 depicts a flow diagram of operations for a thermal throttling control feature that enables real-time testing of a thermal-aware software application independent of temperature, according to additional illustrative embodiments. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . Thermal management control registers, such as thermal management control register 430 of FIG. 4 provide access and configuration for various thermal throttling control features. Thermal throttling is designed to reduce temperature by penalizing performance with throttled thermal events.

A thermal management stop time register, such as thermal management stop time register 434 of FIG. 4 , together with a thermal management throttling scale register, such as thermal management throttling scale register 436 of FIG. 4 , sets the throttling amount and throttling behavior. In real-time systems, real-time deadlines need to be guaranteed. It is important for software developers and quality assurance teams to know and test the maximum throttle, which is the maximum setting of the Thermal Management Stop Time Register and Thermal Management Throttle Scale Register that a program or code segment can tolerate and still guarantee the real-time deadline of the real-time system. Instead of adjusting the actual temperature of the hardware to cause a thermal event and thus trigger a throttling condition, the thermal management control state machine provides a mode that always provides throttling regardless of temperature. The thermal management control state machine sets this mode in the thermal management control register, which sets the chip into constant regulation. This feature helps software developers to test and ensure their code meets real-time standards.

As operation begins, thermal control settings for the Thermal Management Stop Time Register and the Thermal Management Throttle Scale Register are received (step 1002). The Thermal Management Control State Machine uses the settings of the Thermal Management Stop Time Register and the Thermal Management Throttle Scale Register to determine how throttling is performed. Then, the thermal management control state machine sets the test mode and sets the thermal management control registers to always throttle settings (step 1004). The program is then run for a real-time confirmation that the software or program will meet the real-time deadline under the thermal control settings of the Thermal Management Stop Time Register and Thermal Management Throttle Scale Register (1006). The test pattern can be any type of regulation pattern, such as constant regulation or random regulation. The thermal management control state machine then determines whether a real-time deadline is met (step 1008). If the real-time deadline is not met, the thermal management control state machine records the thermal control settings of the current thermal management stop time register and thermal management throttling scale register as failed (step 1010). The thermal management control state machine then determines if there are any new thermal management stop time registers and thermal management throttling scale register thermal control settings that will reduce the throttling (step 1012). If there are new thermal control settings for the thermal management stop time register and the thermal management scaling register, the operation returns to step 1002 . If at step 1002 there are no new thermal control settings for the Thermal Management Stop Time Register and Thermal Management Throttle Scale Register, then the operation ends.

Returning to step 1008, if the real-time deadline is met, the thermal management control state machine records the thermal control settings of the current thermal management stop time register and thermal management adjustment ratio register as pass (step 1014). The thermal management control state machine determines whether there are any new thermal management stop time registers and thermal management throttling scale register thermal control settings that will increase the throttling (step 1016). If there are new thermal control settings for the thermal management stop time register and the thermal management scaling register, the operation returns to step 1002 . If at step 1016 there are no new thermal control settings for the Thermal Management Stop Time Register and Thermal Management Throttle Scale Register, then the operation ends.

In this way, providing an always-on mode of operation helps software developers test and ensure their code meets real-time deadlines under worst-case thermal conditions. Software developers and quality assurance teams can use this feature to determine the maximum amount of adjustment that a program or piece of code can tolerate and still be guaranteed to meet the real-time deadlines of a real-time system. Once the thermal management control state machine has determined and validated the maximum amount of throttling, software can set an interrupt to occur when full throttling occurs. If the thermal management control state machine always generates this interrupt, the thermal management control state machine notifies the application that there may be a violation or non-satisfaction of real-time guarantees.

In addition to always adjusting control settings, implementations may also provide modes for injecting random thermal events or directing random thermal events to simulate a more realistic interaction of tuning and software execution. The technique is similar to randomly injecting errors on the bus to test error recovery code.

11 depicts a flowchart of operations for implementing thermal throttling control with minimal impact on interrupt latency, according to additional illustrative embodiments. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . When any part of a computer system is placed in a throttling condition, the throttling condition can degrade the performance of the entire system. The reduction in performance increases interrupt latency based on how long it will take to service the interrupt and how long the interrupt will be serviced. An increase in interrupt latency has a severe impact on the system as a whole, so it is desirable and necessary to minimize the impact of thermal throttling on interrupt latency. Minimizing the impact of thermal throttling due to interrupt latency is a feature for PPU throttling control such as that performed by PPU 308 of FIG. 3 . SPUs such as SPUs 310, 311 and 312 of FIG. 3 do not get interrupts and therefore are not affected by this feature.

As operation begins, a thermal management control state machine such as thermal management control state machine 458 of FIG. 4 monitors all PPU interrupt status bits and thermal management system interrupt mask registers, such as thermal management system interrupt mask register 438 ( Step 1102). The thermal management system interrupt mask register controls the masking of interrupts. The thermal management control state machine determines whether there are any unmasked interrupts pending (step 1104). If there are no interrupts pending or there are interrupts pending but masked, then operation returns to step 1102 .

If there are unmasked interrupts pending at step 1104, the thermal management control state machine temporarily disables any throttling mode, whether partial throttling or full throttling state (step 1106). Disabling throttling mode enables the PPU to temporarily run at full performance and service any pending interrupts without any delay caused by thermal throttling effects. Likewise, the thermal management control state machine monitors all PPU interrupt status and thermal management system interrupt mask registers (step 1108). The thermal management control state machine determines whether there are any unmasked interrupts pending (step 1110). If there are no interrupts pending or there are interrupts pending but masked, then operation returns to step 1108 . When the interrupt status clears at step 1110 , the thermal management control state machine returns the PPU to the initial throttling mode (step 1112 ), and operation returns to step 1102 .

An interrupt handler can choose to clear the interrupt status bit at the beginning or end of the interrupt handler routine. The interrupt handler may be located in a Power processor unit such as Power processor unit 301 of FIG. 3 or in software executed by the Power processor unit. If the interrupt handler chooses to clear the interrupt status bit at the beginning and also wishes to avoid any performance degradation of the PPU, the interrupt handler can disable thermal throttling before clearing the interrupt status bit. That is, interrupts do not cause changes in control registers. Thus, throttling is still enabled, but is suspended by a thermal management control unit such as TMCU 402 of FIG. 4 when an unmasked interrupt occurs. If an interrupt handler should reset the interrupt status before servicing the interrupt, the handler should set the control register to disable throttling (or reduce throttling to an acceptable level), reset the interrupt, and service the interrupt , then re-enable the throttling or set the throttling amount back to the previous level. An example disabling of thermal throttling may be performed by setting a thermal management control register, such as thermal management control register 430 of FIG. 4, to 0XX, where X is a "does not care". At the end of the interrupt routine, the interrupt handler should set the thermal management control registers back to their initial values. If the interrupt handler clears the interrupt status bit at the end of the interrupt routine, then no extra work is required and the thermal management control state machine will keep the PPU out of throttling mode as long as the interrupt status bit is active.

12 depicts a flowchart of operations for hysteresis in thermal regulation, according to an additional illustrative embodiment. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . Hysteresis in thermal regulation is the lag between making a change such as a regulation or ending a regulation and the response or effect of that change. For example, if the set point is set to 75°C and the end set point is set to 72°C, then the hysteresis range is from 75°C to 72°C. Figure 5 depicts thermal regulation hysteresis.

A thermal management throttling point register such as thermal management throttling point register 432 of FIG. 4 provides two temperature settings: a throttling temperature and an end throttling temperature. The throttling temperature should be set higher than the end throttling temperature. The temperature difference defines the amount of hysteresis between the regulation temperature and the end regulation temperature, thus providing a programmable hysteresis.

Illustratively limiting the following discussion to one DTS, as operation of hysteretic thermal throttling begins, the thermal management control state machine sets the throttling temperature and the end throttling temperature in the thermal management throttling point register (step 1202). The thermal management control state machine senses the temperature of the DTS (step 1204). The thermal management control state machine determines whether the temperature sensed from the DTS is greater than or equal to the regulated temperature (step 1206). If the sensed temperature is not greater than or equal to the adjusted temperature, the operation returns to step 1204 . If the sensed temperature is greater than or equal to the regulated temperature at step 1206, the thermal management control state machine initiates a regulated mode (step 1208).

Likewise, the thermal management control state machine senses the temperature of the DTS (step 1210). The thermal management control state machine determines whether the temperature sensed from the DTS is greater than or equal to the end throttling temperature (step 1212). If the sensed temperature is not less than the end adjustment temperature, the operation returns to step 1210 . If the sensed temperature is less than the end throttling temperature at step 1212 , the thermal management control state machine disables throttling mode (step 1214 ) and operation returns to step 1204 .

Thus, assuming the thermal management control registers are properly configured to allow throttling mode, the thermal management control state machine causes the unit to enter throttling mode when the temperature rises to or above the throttling temperature. The thermal management control state machine keeps the unit in throttling mode until the temperature drops below the end throttling temperature. If the end throttling temperature is less than the throttling temperature, the identified hysteresis allows the unit to cool down sufficiently before throttling mode is disabled. Without hysteresis, the unit could enter and exit regulation mode very frequently and reduce the overall efficiency of regulation and the efficiency of the processor.

An exemplary processor throttling method may be accomplished by blocking dispatch of instructions. If throttling is enabled and disabled frequently, the processor's pipeline may be flushed frequently, reducing processing power. Another exemplary processor throttling method can be accomplished by slowing down the clock frequency.

FIG. 13 depicts a flowchart of operations for implementing thermal throttling logic, according to an additional illustrative embodiment. Figure 13 shows a complete thermal management solution as described in the previous figures. As mentioned above, the Cell BE chip includes a thermal management system provided by the pervasive logic unit 351 in FIG. 3 . A TMCU, such as TMCU 402 of FIG. 4, includes a number of dynamic thermal management registers. The dynamic thermal management registers are thermal management control registers, thermal management throttling point registers, thermal management stop time registers, thermal management throttling ratio registers, and thermal management system interrupt mask registers, such as thermal management control registers 430 (TM_CR1 and TM_CR2) of FIG. Thermal Management Throttle Point Register 432 (TM_TPR), Thermal Management Stop Time Register 434 (TM_STR1 and TM_STR2), Thermal Management Throttle Scale Register 436 (TM_TSR), and Thermal Management System Interrupt Mask Register 438 (TM_SIMR).

The thermal management throttling point register sets the throttling point for DTS. Two independent throttling points, one for the PPE and one for the SPE, can be set in the thermal management throttling point register. Also included in this register are temperature points for enabling and disabling throttling or stopping the PPE or SPE. Performed regulation of the PPE or SPE begins when the temperature is at or about the regulation point. Throttling stops when the temperature drops below the temperature at which throttling is disabled. Execution of PPE or SPE is stopped if the temperature reaches the full regulation temperature or the stop temperature.

The thermal management control state machine uses the thermal management stop time register and the thermal management throttling ratio register to control the throttling frequency and throttling amount. When the temperature reaches the throttling point, the thermal management control state machine will stop the corresponding PPE or SPE for the number of clocks specified by the corresponding scale value in the thermal management throttling scale register. The thermal management control state machine then enables the PPE or SPE to run for the number of clocks specified by the run value in the thermal management stop time register multiplied by the corresponding scale value. This sequence continues until the temperature drops below the disabled regulation.

The Thermal Management Control State Machine uses the Thermal Management System Interrupt Mask Register to select which interrupts disable throttling of the PPE while the interrupt is pending.

The thermal management control register sets the throttling mode independently for each PPE or SPE. Below are five different modes that can be set independently for each PPE or SPE:

Disable dynamic scaling (including kernel stop safety);

Normal operation (dynamic scaling and kernel halted safety enabled);

Always throttle PPE or SPE (kernel stop safety enabled);

disable kernel stop safety (enable dynamic scaling and disable kernel stop safety);

Always tune PPE or SPE and disable kernel stop safety.

As an operation for implementing the thermal throttling logic, the thermal management control state machine sets the throttling temperature and the end throttling temperature in the thermal management throttling point register (step 1302). The thermal management control state machine senses the temperature of the DTS (step 1304). The thermal management control state machine determines whether the temperature sensed from the DTS is greater than or equal to the regulated temperature (step 1306). If the sensed temperature is not greater than or equal to the adjusted temperature, the operation returns to step 1304 . If the sensed temperature is greater than or equal to the regulated temperature, the thermal management control state machine initiates a regulated mode (step 1308).

The thermal management control state machine then controls throttling by the throttling type represented by the value indicated in the thermal management control register (step 1310). Once the throttling mode is indicated, the thermal management control state machine limits throttling by the amount of throttling indicated in the thermal management stop time register (step 1312). The stall time register sets the ratio, or throttling percentage, between the time the processor will stall and the time the processor will be allowed to run. Finally, the thermal management control state machine scales the stalled duration and run time by the value specified in the thermal management scale register (step 1314). At this time, the operation is divided into concurrent operations, that is, step 1316 and step 1322 . At step 1316, the thermal management control state machine senses the temperature of the DTS. The thermal management control state machine determines if the temperature sensed from the DTS is less than the regulated temperature (step 1318). If the sensed temperature is not less than the end regulation temperature, the operation returns to step 1316 . If DTS is less than the end throttling temperature, the thermal management control state machine disables throttling mode (step 1320 ) and operation returns to step 1304 .

Returning to step 1314, after the final throttling limit is achieved, the thermal management control state machine concurrently monitors the status of all PPU interrupts for any pending interrupts (step 1322). If an interruption is encountered while implementing throttling, the thermal management control state machine temporarily disables any throttling mode until the interrupt has been serviced, at which point throttling is enabled regardless of the partial or full throttling state and operation returns to step 1308 . Refer to FIG. 11 for an in-depth discussion of monitoring interrupt status.

Thus, the thermal interrupt logic of the thermal management system included in the Cell BE chip provides a dynamic means to manage the thermal state of the Cell BE chip and protect the Cell BE chip and its components.

The illustrative embodiments can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. The illustrative embodiments are implemented in software, including but not limited to firmware, resident software, microcode, and the like.

Furthermore, the illustrative embodiments may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system And use. For the purposes of this description, a computer-usable or computer-readable medium is any medium that can contain, store, communicate, propagate or transport a program for use by or in connection with an instruction execution system, device or device tangible equipment.

A medium may be an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system (or device or arrangement) or a propagation medium. Examples of computer readable media include semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read only memory (ROM), hard disk, and optical disk. Current examples of optical disks include compact disk - read only memory (CD-ROM), compact disk - read/write (CD-R/W) and DVD.

A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. Storage units may include local memory used during actual execution of the program code, bulk storage, and cache memory. In order to reduce the number of code fetches from bulk storage during execution, the cache memory provides temporary access to at least a portion of the program code. storage.

Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be connected to the system either directly or through intervening I/O controllers.

Network adapters may also be connected to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.

The description of the illustrative embodiments has been presented for purposes of illustration and description, and is not intended to be exhaustive or to limit the invention to the illustrative embodiments in the form disclosed. Many modifications and alterations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the illustrative embodiments, the practical application, and to enable others of ordinary skill in the art to understand the description for various embodiments with various modifications as are suited to the particular use contemplated. sexual embodiment.

Claims (24)

1. computer implemented method that is used in the thermal conditioning control of integrated circuit test real-time software comprises:

Receive at least one heat control setting;

Use described at least one heat control that heat management system is set and be set to test pattern, wherein said test pattern shows the thermal conditioning control of using described heat control to be provided with;

Under described test pattern, carry out described real-time software;

Whether test is satisfied the real-time time limit that is associated with described real-time software under described test pattern;

As described real-time software is satisfied the response in described real-time time limit, described at least one heat control setting is recorded as the heat control setting of passing through; And

As described real-time software is not satisfied the response in described real-time time limit, described at least one heat control setting is recorded as the heat control setting of failure.

2. method according to claim 1, is provided with step, execution in step, testing procedure and recording step and is carried out by the heat management control state machine that resides in the described integrated circuit wherein said receiving step.

3. method according to claim 1 further comprises:

Determine whether also to exist at least one will increase the heat control setting of regulated quantity, wherein under this heat control is provided with, can test described real-time software; And

As response, use the regulated quantity that increases to carry out and test for the second time described real-time software to existing the described heat control that will increase regulated quantity to be provided with.

4. method according to claim 1 further comprises:

Determine whether also to exist at least one will reduce the heat control setting of regulated quantity, wherein under this heat control is provided with, can test described real-time software; And

As response, use the regulated quantity that reduces to carry out and test for the second time described real-time software to existing the described heat control that will reduce regulated quantity to be provided with.

5. method according to claim 1, wherein said test pattern are specified the adjustment state all the time of described heat management system.

6. method according to claim 1, wherein said test pattern are specified the adjustment state at random of described heat management system.

7. method according to claim 6, wherein said adjustment state are at random injected at random incident heat with the interaction of analog regulation and the execution of software more realistically.

8. method according to claim 1, wherein said heat control setting comprise the regulated quantity that will be initialised and at duration of the described test pattern that will be initialised.

9. method according to claim 8, the wherein said regulated quantity that will be initialised are the number percent of the time of the time that stops of unit and the operation of described unit.

10. method according to claim 9, the time of time that wherein said unit stops and the operation of described unit is to come convergent-divergent according to the value of ratio register.

11. method according to claim 8, the wherein said duration at the described test pattern that will be initialised is the actual clock periodicity that the unit stops and moving.

12. method according to claim 1, the wherein said heat control setting of passing through is stored in the data structure.

13. method according to claim 1, the heat control setting of wherein said failure is stored in the data structure.

14. method according to claim 1, wherein said test pattern is provided with in the heat management control register.

15. method according to claim 1, wherein said integrated circuit are heterogeneous multi-core processors.

16. a data handling system that is used in the thermal conditioning control of integrated circuit test real-time software comprises:

Be used to receive the device that at least one heat control is provided with;

Be used to use described at least one heat control that the device that heat management system is set to test pattern is set, wherein said test pattern shows the thermal conditioning control of using described heat control to be provided with;

Be used under described test pattern, carrying out the device of described real-time software;

For use in testing for whether satisfying the device in the real-time time limit that is associated with described real-time software under the described test pattern; And

Be used for as described real-time software is satisfied the response in described real-time time limit, described at least one heat control setting is recorded as the heat control setting of passing through, and, described at least one heat control setting is recorded as the device of the heat control setting of failure as described real-time software is not satisfied the response in described real-time time limit.

17. system according to claim 16 also comprises:

Be used to determine whether also to exist the device of at least one heat control that will increase regulated quantity setting, wherein under this heat control is provided with, can test described real-time software; And

Be used for using the regulated quantity that increases to carry out and test for the second time the device of described real-time software as response to existing the described heat control that will increase regulated quantity to be provided with.

18. system according to claim 16 also comprises:

Be used to determine whether also to exist the device of at least one heat control that will reduce regulated quantity setting, wherein under this heat control is provided with, can test described real-time software; And

Be used for using the regulated quantity that reduces to carry out and test for the second time the device of described real-time software as response to existing the described heat control that will reduce regulated quantity to be provided with.

19. system according to claim 16, wherein said test pattern is specified at least one in the adjustment state at random of the adjustment state all the time of described heat management system or described heat management system.

20. incident heat injects at random with the interaction of analog regulation and the execution of software more realistically in system according to claim 19, wherein said adjustment state at random.

21. system according to claim 16, wherein said heat control setting comprises the regulated quantity that will be initialised and at duration of the described test pattern that will be initialised.

The number percent of the time of time that 22. system according to claim 21, the wherein said regulated quantity that will be initialised are the unit to be stopped and the operation of described unit.

23. system according to claim 22, the time of time that wherein said unit stops and the operation of described unit is to come convergent-divergent according to the value of ratio register.

24. system according to claim 21, the wherein said duration at the described test pattern that will be initialised is the actual clock periodicity that the unit stops and moving.

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