[go: up one dir, main page]

WO2021013229A1 - 级联型变流器多子模块的测试电路、系统及其控制方法 - Google Patents

级联型变流器多子模块的测试电路、系统及其控制方法 Download PDF

Info

Publication number
WO2021013229A1
WO2021013229A1 PCT/CN2020/103857 CN2020103857W WO2021013229A1 WO 2021013229 A1 WO2021013229 A1 WO 2021013229A1 CN 2020103857 W CN2020103857 W CN 2020103857W WO 2021013229 A1 WO2021013229 A1 WO 2021013229A1
Authority
WO
WIPO (PCT)
Prior art keywords
tested
module
sub
current
voltage
Prior art date
Application number
PCT/CN2020/103857
Other languages
English (en)
French (fr)
Inventor
马柯
姜山
李恩溢
Original Assignee
上海交通大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201910665460.9A external-priority patent/CN110426649B/zh
Priority claimed from CN201910665459.6A external-priority patent/CN110488114A/zh
Priority claimed from CN201910668891.0A external-priority patent/CN110488115B/zh
Application filed by 上海交通大学 filed Critical 上海交通大学
Priority to US17/283,566 priority Critical patent/US11899067B2/en
Publication of WO2021013229A1 publication Critical patent/WO2021013229A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/34—Testing dynamo-electric machines
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G01R31/42—AC power supplies
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for AC mains or AC distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to the field of power electronics technology, in particular, to a test circuit, a test system and a control method for multiple sub-modules of a cascaded converter.
  • Cascaded H-Bridge (CHB), ModularMultiLevelConverter (MMC) cascaded converters are composed of sub-modules cascaded, and its own structure makes it easy to expand, especially in high-voltage, large-capacity operating scenarios with good prospects.
  • CHB Charge-Bridge
  • MMC ModularMultiLevelConverter
  • the reliability of the module therefore, it has become a more efficient and cost-saving method to evaluate the reliability of the cascaded system through the cascaded converter sub-module operating condition simulation test circuit. Since the operating characteristics of the sub-module are closely related to the converter, in order to ensure the long-term reliable operation of the converter, it is of great significance to test the operating characteristics of the sub-module under actual working conditions.
  • the existing test platform has a single test working condition and control mode. Due to the limitation of the DC voltage of the power supply, simultaneous testing of multiple sub-modules cannot be achieved. The power supply requirements are high and the test efficiency is low. Therefore, a simple and reliable test circuit is needed to accurately simulate the operating conditions of the tested sub-module in the actual system, and to achieve simultaneous testing of multiple sub-modules under multiple operating conditions, and reduce the impact on the test DC voltage. Requirements to improve test efficiency.
  • the current modulation method of cascaded converters is mainly the nearest level approach modulation method.
  • the pulse voltage output by the sub-module of the cascade converter has the characteristics of large pulse amplitude and wide pulse width.
  • the sub-module may be turned on or off for a long time, which makes the module under test pulse
  • the voltage has a great interference to the current controller, which makes it difficult for the current controller to control the current stably.
  • the Chinese invention patents with patent numbers ZL201910083488.1 and ZL201910083490.9 can simulate the operating conditions of any sub-module of the cascaded converter, but the sub-modules operating in different operating conditions are coupled to each other in the test circuit It increases the difficulty of control and cannot suppress the voltage pulse interference caused by the recent level approach modulation. That is to say, in the traditional cascaded converter sub-module operating condition simulation test circuit, there is no effective method to suppress the voltage pulse interference caused by the nearest level approach modulation.
  • the art usually adds additional auxiliary circuits and controls the auxiliary circuit to operate in coordination with the sub-modules, so as to offset the interference of the sub-module pulse voltage on the current controller.
  • the additional control circuit increases the complexity of the control and the manufacturing cost of the analog test circuit, and the control delay caused by the dead zone of the switch will cause the synchronization of the auxiliary circuit and the pulse voltage to decrease, and the auxiliary circuit cannot be well offset Interference of pulse voltage. Therefore, there is an urgent need in the art for a simpler and more cost-effective cascaded converter sub-module operating condition simulation technology and corresponding current control method.
  • the purpose of the present invention is to provide a test circuit with multiple sub-modules of a cascaded converter and a control method thereof.
  • a test circuit with multiple sub-modules of a cascaded converter comprising: a current generator and a tested module group, the current generator provides a test current to the tested module group;
  • the tested module adopts any of the following forms:
  • the tested module group includes two tested bridge arms, each tested bridge arm contains a number of tested sub-modules connected in series, and the two tested bridge arms are in a reverse series connection structure; two tested bridge arms The tested sub-modules in the bridge arms simulate the rectification and/or inverter operation conditions of the cascade converter respectively; the two tested bridge arms have the same or different structures;
  • the tested module group includes one or more tested units, and the tested units are connected in series; each tested unit includes two tested sub-modules connected in reverse series, two reverse connected in series The tested sub-modules respectively simulate the rectification or inverter operating conditions of the cascaded converter; the DC components of the capacitor voltage of the two tested sub-modules connected in reverse series have opposite directions and are equal in magnitude;
  • the tested module group and its internal tested sub-modules can be arranged in any order in the test circuit without changing the electrical connection relationship; when the tested module receives the test sent by the current generator When the current is present, the tested module simulates the voltage signal of the cascaded converter sub-module, or simulates the voltage signal and current signal of the cascaded converter sub-module.
  • the current generator includes: a single-phase converter and a filter; wherein:
  • the module group under test includes two bridge arms under test with the same structure
  • the first end of the single-phase converter is connected to the input end of the filter
  • the output end of the filter is connected to the series connected first end.
  • the input ends of the two tested bridge arms are connected
  • the second end of the single-phase converter is connected to the input end of the first tested bridge arm in series
  • the output end of the first tested bridge arm Connected to the output end of the second tested bridge arm;
  • the series sequence of the single-phase converter, filter, first tested bridge arm, and second tested bridge arm can be changed arbitrarily;
  • the first terminal of the single-phase converter is connected to the input terminal of the filter, and the filter output terminal is connected to the serially connected unit under test.
  • the first input end of the test unit is connected, and the second end of the single-phase converter is connected to the second input end of the tested unit in series; the single-phase converter, the filter, and the tested unit are connected in series.
  • the series sequence can be changed arbitrarily.
  • the tested submodule includes: a bridge circuit and a capacitor, and the bridge circuit and the capacitor are connected in parallel.
  • the bridge circuit includes a half-bridge circuit or a full-bridge circuit;
  • the filter includes any type of an L-type filter, a CL-type filter, an LC-type filter, and an LCL-type filter.
  • the tested sub-module corresponds to a sub-module in the actual cascaded converter
  • the current generated by the current generator corresponds to the bridge arm of the tested sub-module in the actual cascaded converter
  • the current, or phase current; the test current includes: the upper and lower arm currents of each phase of the cascaded converter, or the current of each phase.
  • the second aspect of the present invention provides a cascaded converter sub-module test system, including: a current generator, a tested module group, a cascaded converter system parameter model, a current controller, and a voltage controller;
  • the current generator is used to provide a specific test current to the tested module group
  • the tested module group includes one or more tested bridge arms, each tested bridge arm includes one or more tested sub-modules connected in series, and the tested bridge arms are in a reverse series relationship; or ,
  • the tested module group includes one or more tested units, each of the tested units includes two tested sub-modules connected in reverse series, and the tested units are in a series relationship; When the test module group receives the current sent by the current generator, the tested module group outputs the voltage signal of the tested submodule;
  • the cascaded converter system parameter model is used to output current and voltage reference signals corresponding to the actual cascaded converter system parameters and operating conditions to the current controller and voltage controller;
  • a current controller for controlling the test current generated by the current generator and generating control signals required by the current generator
  • the voltage controller is used to control the capacitor voltage of the tested sub-module in the tested module group and to generate the switch control signal of the tested sub-module in the tested module.
  • the current controller specifically completes one or two of the following controls:
  • the voltage controller generates each tested module group based on the capacitance voltage signal of each internal tested sub-module output by the tested module group and the reference voltage signal output by the cascaded converter system parameter model
  • the control signal of the switch device in the sub-module so that the capacitance voltage of each sub-module under test in the tested module is balanced, and the capacitance voltage of each sub-module under test is the same as the sub-modules that need to be simulated in the actual cascade converter.
  • the capacitor voltage of the module is the same.
  • the voltage controller includes: a capacitor voltage equalization module and a switch modulation module; wherein:
  • the capacitor voltage equalization module is based on the test current output by the current generator, the capacitor voltage of each tested sub-module within the tested module group, and the reference voltage output by the cascaded converter system parameter model Signal to generate the target voltage signal of the tested module; wherein, the reference voltage signal includes an average capacitor voltage and a sub-module reference voltage;
  • the switch modulation module determines the number of tested sub-modules according to the target voltage signal generated by the capacitor voltage equalization module, and controls each tested module in the tested module according to the test current signal output by the current generator The switching status of the submodule.
  • the capacitor voltage equalization module includes an average value element, a sign judgment element, an adder, a multiplier, and a PI controller, wherein the average value element is connected to the sign judgment element through the output of the adder , And connected in series with the PI controller after passing through the multiplier;
  • the capacitor voltage equalization module performs closed-loop control on the capacitor voltage of the tested sub-module in the tested module, and the closed-loop control strategy is as follows:
  • the average value Vavg1 and Vavg2 of the capacitor voltages of the tested submodules in the tested bridge arm are respectively compared with the reference capacitor voltage signals V ref1 and V ref2 output by the cascade converter system parameter model to obtain the capacitance voltage difference value;
  • the capacitance voltage difference is respectively multiplied by the direction of the test current signal output by the current generator, and then superimposed with the voltage reference signals u ref1 and u ref2 output by the cascade converter system parameter model after passing through the proportional-integral controller , As the input signal of the switch modulation module; the output signal of the capacitor voltage equalization module determines the number of input sub-modules in the next switching cycle;
  • the switch modulation module adopts a voltage modulation method to determine the pulse signal of each tested sub-module in the tested module based on the set carrier waveform and the target voltage signal generated by the capacitor voltage equalization module, or determine the pulse signal of the tested sub-module according to the capacitor voltage Sort and determine the pulse signal of each tested sub-module in the tested module based on the direction of the test current, so that the capacitor voltage of the tested sub-module in the tested module is the same as the sub-module that needs to be simulated in the actual cascade converter The capacitor voltage is the same.
  • the third aspect of the present invention provides a current control method of a cascaded converter sub-module test system, which is used to suppress the interference of the pulse voltage of the tested module caused by the nearest level approximation modulation on the current output waveform; Specifically, by compensating the feedforward voltage in the current controller, the pulse voltage interference of the tested module caused by the nearest level approach modulation is cancelled; among them:
  • the feedforward voltage used for compensation is generated in any of the following ways:
  • the first method Calculate the difference between the input number of the tested sub-module in the inverter state and the input number of the tested sub-module in the rectification state, and combine the capacitor voltage of a single sub-module to generate a feedforward voltage;
  • the second method First, sample the port pulse voltage signal of the tested module through a voltage sampler; then perform low-pass filtering on the sampled voltage signal to filter out the sampling error caused by the switch dead zone; finally, set the low The filtered voltage signal is used as the feedforward voltage;
  • the feedforward voltage that changes synchronously with the pulse voltage at the port of the tested module is compensated to the output of the proportional integral resonant regulator in the current controller, so as to offset the interference caused by the pulse voltage at the port of the tested module and avoid the interference caused by the pulse voltage.
  • the current distortion is compensated to the output of the proportional integral resonant regulator in the current controller, so as to offset the interference caused by the pulse voltage at the port of the tested module and avoid the interference caused by the pulse voltage.
  • the method is suitable for current control of a cascaded converter sub-module test system under the nearest level approximation modulation; or, it is applied to a cascaded converter sub-module test system under carrier phase shift modulation ⁇ current control.
  • the fourth aspect of the present invention provides a test method suitable for cascaded converter sub-modules under the nearest level approximation modulation.
  • the method is based on the above-mentioned cascaded converter multi-sub-module test circuit or the above
  • the cascaded converter sub-module test system adopts the current control method of the above-mentioned cascaded converter sub-module test system to test the cascaded converter sub-module.
  • the present invention has the following beneficial effects:
  • the test circuit of the cascaded converter with multiple sub-modules provided by the present invention, wherein the first tested module group structure is a symmetrical bridge arm structure, and each tested bridge arm contains a plurality of tested sub-modules connected in series
  • the module can realize the simultaneous simulation of multiple sub-modules in the cascaded converter under rectification and inverter operating conditions.
  • the series-type tested sub-modules are easy to expand, which significantly improves test efficiency and reduces test costs.
  • the two tested bridge arms contain the same number of tested sub-modules, and the tested bridge arms are connected in reverse series.
  • the structure ensures that the DC components in the capacitor voltage of the tested sub-module inside the tested bridge arm cancel each other out, which significantly reduces the requirements for the DC voltage in the test circuit.
  • this circuit can flexibly configure and test the corresponding working conditions by changing the output current of the current generator and the number of tested sub-modules, which improves the flexibility of the experiment.
  • the first tested module group structure is a reverse series connection structure, and each test unit includes two reverse series connections
  • the tested sub-module can realize the simultaneous simulation of the same sub-module in the cascaded converter under the two operating conditions of rectification and inverter.
  • several series-connected test units can realize simultaneous testing of multiple sub-modules.
  • the series-connected test unit is easy to expand, which significantly improves test efficiency and reduces test costs. Further, this kind of test circuit of cascaded converter multi-submodule based on reverse series connection structure.
  • the basic structure of the reverse series connection of two submodules under test in the same test unit ensures the capacitance of the two submodules under test.
  • the working conditions corresponding to the test can be flexibly configured by changing the output current of the current generator and the number of tested sub-modules, which improves the flexibility of the experiment.
  • the control system for the test circuit of the cascaded converter with multiple sub-modules can generate the input current of the sub-module under test that is the same as the actual operating state according to the current generator and the current controller; and through voltage control The controller controls the capacitor voltage and switching status of the sub-module under test, and generates the same capacitor voltage as the actual operating state of the sub-module under test, so as to realize the control of multiple sub-modules in the cascaded converter under rectification and inverter operation conditions. Simultaneous simulation can ensure the accuracy of the test and improve the test efficiency; the working conditions of the test can be flexibly configured by changing the output current of the current generator and the number of tested sub-modules, which improves the flexibility of the experiment.
  • the current control method of the cascaded converter sub-module test system provided by the present invention generates the feedforward voltage through calculation or sampling, and compensates the feedforward voltage to the current controller. Due to the generated forward voltage The feed voltage changes synchronously with the on-off state of the sub-module under test. Therefore, it can better cancel the pulse voltage interference of the module group under test caused by the nearest level approach modulation, avoid the current distortion caused by the pulse voltage, and The method does not need to add additional auxiliary circuits, thereby reducing the complexity of control, saving the manufacturing cost of the operating condition simulation system, and is a valuable technical improvement.
  • FIG. 1 is a topological structure diagram of a test circuit of a cascaded converter multi-submodule using a symmetrical bridge arm structure to be tested in an embodiment of the present invention
  • FIG. 2 is a topological structure diagram of a test circuit of a cascaded converter with multiple sub-modules of a tested module using a reverse series connection structure in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a first topology structure of a current generator in a test circuit of multiple sub-modules of a cascaded converter in an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a second topology structure of a current generator in a test circuit of multiple sub-modules of a cascaded converter in an embodiment of the present invention
  • FIG. 5 is a schematic diagram of the first topology structure of the tested bridge arm in the first topology structure of the test circuit of the multi-submodule cascade converter in an embodiment of the present invention
  • FIG. 6 is a schematic diagram of the second topology structure of the tested bridge arm in the first topology structure of the test circuit of the multi-submodule cascade converter in an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a first topology structure of a tested unit in a test circuit of a cascaded converter with multiple sub-modules of the tested module using a reverse series connection structure in an embodiment of the present invention
  • FIG. 8 is a schematic diagram of a second topology structure of a tested unit of a test circuit of a cascade converter with multiple sub-modules of the tested module using a reverse series connection structure in an embodiment of the present invention
  • Figure 9 is a schematic diagram of a cascaded converter sub-module test system in an embodiment of the present invention.
  • FIG. 10 is a schematic block diagram of the first method of generating a feedforward voltage in a current control method in an embodiment of the present invention.
  • FIG. 11 is a schematic block diagram of the second method of generating feedforward voltage in the current control method in an embodiment of the present invention.
  • Fig. 12 is a schematic block diagram of a current controller in a cascaded converter sub-module test system according to an embodiment of the present invention
  • FIG. 13 is a schematic block diagram of the effect of feedforward voltage compensation according to an embodiment of the present invention.
  • FIG. 14 is a schematic block diagram of an implementation of a voltage controller in a cascaded converter sub-module test system according to an embodiment of the present invention.
  • a test circuit for a cascaded converter with multiple sub-modules with a symmetrical bridge arm structure provided by the present invention.
  • the cascaded converters that can be simulated include but are not limited to half bridges, Full-bridge modular multilevel converter (MMC) and cascaded H-bridge converter (CHB).
  • MMC Full-bridge modular multilevel converter
  • CHB cascaded H-bridge converter
  • FIG. 1 is a schematic structural diagram of a single-phase test circuit of a cascaded converter sub-module based on a symmetrical bridge arm structure according to an embodiment of the present invention; as shown in FIG. 1, it includes: a current generator 1 and a tested module
  • the tested module group includes two tested bridge arms 201, the current generator 1 provides test current to the two tested bridge arms 201, and the structure of the two tested bridge arms 201 may be the same or different;
  • the arms 201 are connected in reverse series.
  • Each bridge arm 201 under test includes N submodules under test connected in series; when the bridge arm under test 201 receives the test current sent by the current generator 1, the bridge arm under test 201 tests the voltage signal of the submodule under test, or Test the voltage signal and current signal of the sub-module under test.
  • the tested bridge arm 201 and its internal tested sub-modules can be arranged in any order in the test circuit without changing the electrical connection relationship; two tested bridge arms 201 internal tested sub-modules connected in reverse series
  • the DC components of the capacitor voltage are in opposite directions and can cancel each other.
  • the tested module group includes two tested bridge arms with the same structure, the number of tested sub-modules in the two tested bridge arms is the same, and the DC voltage components of all tested sub-modules are the same.
  • the current generator 1 is used to generate a test current and is mainly composed of a single-phase converter and its corresponding outlet filter; wherein the upper end of the output of the single-phase converter is connected to the input port of the outlet filter. Further, the upper output end of the current generator 1 is connected to the input end of the second tested bridge arm 201, and the lower output end is connected to the input end of the first tested bridge arm 201 for generating flow through two bridge arms under test.
  • the test current is generated by the current generator 1, and the two tested bridge arms 201 are used to simulate the multiple tested sub-modules in the actual cascaded converter under rectification and inverter conditions at the same time, which significantly reduces the DC voltage requirements and improve test efficiency.
  • the current generator 1 has at least one set of output ports at both ends, and the output current i a corresponds to the current of the bridge arm where the submodule of the actual cascade converter is located.
  • the single-phase converter can use any two-level and multi-level circuit topologies including but not limited to, specifically, the half-bridge converter as shown in Figure 3; the full-bridge converter as shown in Figure 4
  • the outlet filter can use any filter including but not limited to L, LC, LCL type filters; the tested sub-module in the tested bridge arm 201 can correspond to the upper and lower phases of the actual converter
  • the topology of the tested bridge arm 201 includes, but is not limited to, the topological structure composed of half-bridge and full-bridge sub-modules shown in FIG.
  • the circuit topology of Figure 5 is: a plurality of half-bridge converters connected in series in the forward direction and their parallel capacitors.
  • the circuit topology shown in Figure 6 multiple full-bridge converters connected in series in the forward direction and their parallel capacitors.
  • the single-phase test circuit for sub-modules of cascaded converters based on the reverse series connection structure proposed in the above embodiments of the present invention can simulate the operating conditions of any sub-modules of the cascaded converters and realize multiple sub-modules Simultaneous testing under a variety of working conditions, and effectively lower the test DC voltage requirements, save test costs and improve test efficiency.
  • cascaded converter multi-submodule test circuit based on the reverse series connection structure provided by the present invention.
  • the cascaded converters that can be simulated include but Not limited to half-bridge, full-bridge modular multilevel converters (MMC) and cascaded H-bridge converters (CHB).
  • MMC full-bridge modular multilevel converters
  • CHB cascaded H-bridge converters
  • FIG. 2 is a schematic structural diagram of a test circuit for multiple sub-modules of a cascaded converter based on a reverse series connection structure according to an embodiment of the present invention.
  • it may include: a current generator 1 and a passive Test module group, the current generator 1 provides test current to the tested module group; among them, the tested module group includes one or more tested units 202, and each tested unit 202 includes two tested sub-modules connected in reverse series
  • the tested units 202 are in a series relationship; the DC components of the capacitor voltage of the two tested sub-modules connected in reverse series are opposite in direction and equal in magnitude; the tested module group and its internal tested sub-modules do not change the electrical connection relationship Under the premise, the test circuit can be arranged in any order.
  • the tested unit 202 When the tested unit 202 receives the test current sent by the current generator 1, the tested unit 202 tests the voltage signal of the tested sub-module, or tests the voltage signal and current signal of the tested sub-module.
  • Two sub-modules under test in reverse series in each tested unit 202 simulate various working conditions such as cascade converter rectification or inverter operation; the capacitance voltage of two sub-modules under test connected in reverse series
  • the direct current components are in opposite directions and can cancel each other out.
  • the units under test 202 are connected in series.
  • the current generator 1 is used to generate a test current, and is mainly composed of a single-phase converter and its corresponding outlet filter; the upper end of the output of the single-phase converter is connected to the input port of the outlet filter.
  • the output terminal of the current generator 1 is connected to a number of units under test 202 connected in series, and is used to generate a test current flowing through the sub-module under test inside the unit under test 202; the input terminal of the unit under test 202 is connected to the current generator 1
  • the connection is used to receive the test current and output the capacitance voltage signal of the sub-module under test in the internal tested unit 202 to the outside; the test current is generated by the current generator 1, and the actual cascaded converter is realized through the tested unit 202
  • Simultaneous simulation of multiple tested sub-modules in a variety of operating conditions significantly reduces the requirements for DC voltage and improves test efficiency.
  • the current generator 1 has at least one set of output ports at both ends, and the output current i a corresponds to the current of the bridge arm where the submodule of the actual cascade converter is located.
  • the single-phase converter can use any two-level and multi-level circuit topologies including but not limited to, specifically, the half-bridge converter as shown in Figure 3; the full-bridge converter as shown in Figure 4
  • the outlet filter can use any filter including but not limited to L, LC, LCL type filters; the tested sub-module in the tested unit 202 can correspond to the upper and lower bridges of each phase of the actual converter Arm sub-module.
  • the topological structure of the sub-module under test includes, but is not limited to, the topological structure composed of half-bridge and full-bridge sub-modules as shown in Fig. 7 and Fig. 8.
  • the circuit topology of Figure 7 is: two half-bridge converters connected in reverse series and their parallel capacitors.
  • the circuit topology of Figure 8 is: two full-bridge converters connected in reverse series and their parallel capacitors.
  • the cascaded converter sub-module test circuit based on the reverse series connection structure proposed by the above-mentioned embodiment of the present invention can simulate the operating conditions of any sub-module of the cascaded converter, and realize that multiple sub-modules can be used in multiple sub-modules. Simultaneous testing under various working conditions, and effectively lower the test DC voltage requirements, save test costs and improve test efficiency.
  • Fig. 9 is a schematic diagram of a cascaded converter sub-module test system provided in another embodiment of the present invention.
  • the cascaded converters that can be simulated by this cascaded converter submodule test system include but are not limited to half-bridge, full-bridge modular multilevel converters (MMC) and cascaded H-bridge converters ( CHB).
  • the cascaded converter sub-module test system in this embodiment includes: current generator 1, tested module group 2, cascaded converter system parameter model 3, current controller 4, voltage Controller 5.
  • the current generator 1 provides the test current to the tested module group 2; the tested module group 2 includes one or more tested bridge arms, and each tested bridge arm contains one or more tested sub-modules connected in series.
  • the bridge arms are in a reverse series relationship; or, the tested module group 2 includes one or more tested units, and each tested unit includes two tested sub-modules connected in reverse series, and the tested units are connected in series.
  • the tested module group 2 when the tested module group 2 receives the current sent by the current generator, the tested module group 2 outputs the voltage signal of the tested sub-module; the cascaded converter system parameter model 3 sends the current controller 4 and the voltage controller 5 Output current and voltage reference signals corresponding to the system parameters and operating conditions of the actual cascade converter; the current controller 4 controls the test current generated by the current generator and generates the control signal required by the current generator 1 ; The voltage controller 5 controls the capacitor voltage of the tested sub-module in the tested module group 2 and generates the switch control signal of the tested sub-module in the tested module group 2.
  • the current generator 1 and the tested module group 2 constitute the test circuit of the cascaded converter with multiple sub-modules in the embodiment shown in Figures 1 and 2; the cascaded converter system parameter model 3.
  • Current The controller 4 and the voltage controller 5 constitute a control system for the test circuit of the multi-sub-module of the cascade converter, thereby forming a complete sub-module test system of the cascade converter.
  • the output terminal of the current generator 1 is connected to the upper end of the tested module group 2 for generating a flow through the tested module group 2 Test current of the internal tested sub-module.
  • the input terminal is connected with the current generator 1 to receive the test current, and output the capacitance voltage signal of the internal tested sub-module to the voltage controller 5.
  • the system parameter model of the cascade converter 3 generates reference current and voltage signals according to the system parameters and operating conditions of the actual cascade converter for simulating actual operating conditions, and outputs the reference current and voltage signals to the current control respectively
  • the device 4 and the voltage controller 5 serve as the corresponding target current signal and target voltage signal.
  • the current controller 4 receives the reference current signal output by the cascade converter system parameter model 3, and controls the switching pulses of each device in the current generator to make the output current of the current generator 1 match the system parameters of the cascade converter
  • the reference current output by Model 3 is approximately the same.
  • the voltage controller 5 collects the current signal of the output current of the current generator 1, the capacitance voltage signal of each sub-module under test output by the tested module group 2, and the average capacitance voltage output by the system parameter model 3 of the cascade converter.
  • Module reference voltage (reference voltage signal), which generates the control signal of each tested sub-module in the tested module group 2, so that the capacitance voltage of each tested sub-module in the tested module group 2 is the same as that required in the actual cascaded converter
  • the capacitor voltages of the simulated sub-modules are approximately the same.
  • the output terminal of the current generator 1 is connected to the module group 2 under test for generating a test current, which includes a single-phase converter and its corresponding filter.
  • the specific structure of the tested module group 2 is the same as in the embodiment shown in Figs. 1-8.
  • the voltage controller 5 may include: a capacitor voltage equalization module 51 and a switch modulation module 52; wherein: the capacitor voltage equalization module 51 includes an averaging component, a sign judgment component, an adder, a multiplier, and PI controller, the averaging component passes through the output of the adder and the symbol judging component is connected in series with the PI controller after passing through the multiplier; the switch modulation module 52 includes carrier comparison and sorting algorithms. Further, the input of the capacitor voltage equalization module 51 includes the current signal of the output current of the current generator 1, the capacitor voltage signal of the internal tested sub-modules output by the tested module group 2 and the output of the cascade converter system parameter model 3 module.
  • the reference voltage signal includes the average capacitor voltage and the reference voltage of the sub-module; the capacitor voltage equalization module outputs the target voltage signal of the tested module group 2; the switch modulation module adopts the carrier comparison or sorting algorithm and is generated according to the capacitor voltage equalization module
  • the target voltage signal determines the number of tested sub-modules to be input, and controls the switching state of each tested sub-module in the tested module group 2 according to the current signal of the output current of the current generator 1.
  • the system parameter model 3 of the cascade converter is used to simulate the electrical characteristics of the actual system according to the system and operating parameters of the cascade converter.
  • the current controller 4 and the voltage controller 5 are respectively used for current control calculations and voltage control calculations.
  • FIG. 14 is a schematic block diagram of an implementation of a voltage controller in a cascaded converter sub-module test system according to an embodiment of the present invention.
  • the schematic block diagram of the voltage controller 5 includes but is not limited to the structure shown in FIG. 14.
  • the voltage controller 5 is composed of a capacitor voltage equalization module 51 and a switch modulation module 52.
  • the capacitor voltage equalization module 51 collects the current signal of the output current of the current generator 1, the capacitor voltage signal of the internal sub-modules under test output by the tested module group 2, and the average capacitor voltage output by the system parameter model 3 of the cascade converter.
  • the sub-module refers to the voltage, and generates the synthesized reference voltage signal (ie, the target voltage signal) of the test bridge arm 1 and the test bridge arm 2 in the tested module group 2.
  • the switch modulation module 52 adopts a voltage modulation method to determine the pulse signal of each tested sub-module in the tested module based on the set carrier waveform and the target voltage signal generated by the capacitor voltage equalization module, such as carrier phase shift modulation; or
  • the capacitor voltage sorts the tested sub-modules, and determines the pulse signal of each tested sub-module in the tested module based on the direction of the test current, such as the nearest level approach modulation.
  • the capacitor voltage of the tested sub-module in the tested module is the same as the capacitor voltage of the sub-module that needs to be simulated in the actual cascade converter.
  • the switch modulation module 52 uses an optional carrier comparison or sorting algorithm to determine the number of tested sub-modules in the tested module group 2 according to the target voltage signal generated by the capacitor voltage equalization module, and according to the current output of the current generator 1
  • the current signal controls the switching status of each tested sub-module in the tested module group 2.
  • the voltage controller 5 performs closed-loop control on the capacitor voltage of the tested sub-module in the tested module group 2, and the voltage equalization module 51 compares the capacitor voltage of the tested sub-module in the first test bridge arm and the second test bridge arm.
  • the average value Vavg1 and Vavg2 are respectively compared with the reference capacitor voltage signals V ref1 and V ref2 output by the cascaded converter system parameter model module to obtain the capacitance voltage difference and the direction of the current generator output current is multiplied by the ratio.
  • the integral regulator (optional) is superimposed with the voltage reference signals u ref1 and u ref2 output by the cascaded converter system parameter model module as the input signal of the switch modulation module 52, respectively used to generate the first tested bridge
  • the modulation waves of the first test bridge arm and the second test bridge arm are obtained according to the following formula:
  • K p is the proportional control coefficient of the voltage controller
  • K i is the integral control coefficient of the voltage controller
  • sign represents the sign function, used to extract the direction of the current generator 1 output current i a , u ref1* and u ref2 * Respectively the modulation waves of the first test bridge arm and the second test bridge arm.
  • a current control method of the cascaded converter sub-module test system in the above-mentioned embodiment is provided, so as to realize the control of the pulse voltage versus current of the tested module caused by the nearest level approximation modulation. Suppression of output waveform interference; specifically, by compensating the feedforward voltage in the current controller, offsetting the pulse voltage interference of the tested module caused by the nearest level approach modulation.
  • the current control method in the current controller 4 adopts proportional integral resonance control, and the modulation method of the output voltage adopts sinusoidal pulse width modulation.
  • the current controller 4 After the current controller 4 receives the test current reference signal, the test current signal, and the feedforward voltage signal, it outputs a switching sequence to control the current generator 1 to output the required current.
  • the test current in the operating condition simulation system is the same as the bridge arm current in the simulated actual cascade converter system.
  • the specific working process of the current controller 4 is: the current controller 4 inputs the difference between the read reference current signal of the bridge arm and the calculated or sampled feedforward voltage into the proportional integral resonance controller, and then reads the previous The feed voltage signal is compensated to the output terminal of the proportional integral resonance controller, and finally, according to the compensated modulation voltage, a corresponding switching sequence is generated through sinusoidal pulse width modulation to control the current generator 1.
  • the current control method of the cascaded sub-module operating condition simulation system applicable to the nearest level approach modulation compensates the tested module caused by the nearest level approach modulation by compensating the feedforward voltage in the current controller Group 2 port pulse voltage interference; by compensating the feedforward voltage that changes synchronously with the pulse voltage of the tested module group 2 port to the output terminal of the proportional integral resonant regulator in the current controller, thereby canceling the test module group 2 port
  • the interference caused by pulse voltage avoids current distortion caused by pulse voltage interference.
  • FIG. 10 is a schematic block diagram of the first method of generating a feedforward voltage in a current control method in an embodiment of the present invention.
  • the feedforward voltage used for compensation is generated in either of the following two ways.
  • the feedforward voltage generation method 1 is adopted, that is, by calculating the difference between the number of input sub-modules in the inverter-type under-test sub-module group and the rectification-type under-test sub-module group, and combining the individual sub-modules
  • the capacitor voltage of the module generates the feedforward voltage, and the process of the feedforward voltage compensation through this method is shown in Figure 10.
  • the feedforward voltage generation method is specifically as follows: first, read the on and off states of all tested sub-modules in the tested module 2 at the next moment, the on state is recorded as 1, the off state is recorded as 0; The difference between the sum of the on-off states of the tested sub-modules in the inverter state and the sum of the on-off states of all the tested sub-modules in the rectification state; finally, the difference of the sum of the on-off states is multiplied by the voltage of a single sub-module , You can generate the feedforward voltage required for current control at the next moment.
  • the feedforward voltage generation method can be expressed by the following formula:
  • u'DUT is the feedforward voltage used for compensation
  • U c is the DC component of the sub-module capacitor voltage
  • n inv is the input number of the measured sub-module in the inverter state at the next moment
  • n rec is the next The number of input sub-modules in the rectification state at any time.
  • the capacitor voltage of a single submodule required to generate the feedforward voltage is obtained through a cascaded converter system parameter model, or it can also be obtained by sampling the capacitor voltage of a single submodule.
  • the second feedforward voltage generation method is adopted, as shown in FIG. 11, which is a schematic block diagram of the second feedforward voltage generation method in the current control method in an embodiment of the present invention.
  • This method generates a feedforward voltage by sampling the port voltage signal of the tested module group 2 and low-pass filtering the sampled voltage signal, and the process of performing feedforward voltage compensation by this method is shown in Figure 11.
  • the feedforward voltage generation method is specifically as follows: first, the port voltage sampler 6 samples the port pulse voltage signal of the port 2 of the tested module group and the voltage difference signal at both ends of the current generator 1; then, the sampled voltage signal is passed low Pass filter 7 performs low-pass filtering to filter out the sampling error caused by the switch dead zone; finally, the voltage signal after low-pass filtering is used as the feedforward voltage.
  • the feedforward voltage generation method can be expressed by the following formula:
  • u'DUT is the feedforward voltage used for compensation
  • u DUT is the port voltage sampled by the port voltage sampler
  • ⁇ 0 is the cut-off frequency of the low-pass filter
  • s is the complex variable in the transfer function.
  • the cut-off frequency of the low-pass filter used for low-pass filtering the sampled voltage signal is selected to be 1/10 to 1/100 of the high-frequency voltage pulse frequency caused by the switch dead zone ;
  • the low-pass filter used for low-pass filtering the sampled voltage signal is realized by an analog circuit or a digital circuit.
  • the switch dead zone will cause the voltage signal at both ends of the sub-module group to be tested to generate high-frequency voltage pulses.
  • This type of high-frequency pulse pulse Wide and narrow has little interference to the current controller, but if these high-frequency voltage pulses are sampled and compensated to the current controller, it will be due to the delay between the compensated high-frequency pulse voltage and the actual high-frequency pulse voltage.
  • causes greater interference to the current controller so after sampling the voltage across the sub-module group to be tested, the sampled signal is low-pass filtered through the low-pass filter 7 to eliminate the high-frequency pulse voltage in the compensation voltage .
  • the feedforward voltage is compensated in the current controller 4 to cancel the pulse voltage interference at the 2 ports of the tested module group caused by the nearest level approach modulation.
  • the current control method can be expressed as: compensating the obtained feedforward voltage signal to the output terminal of the proportional integral resonant regulator in the current controller 4, and finally performing sinusoidal pulse width modulation according to the compensated regulator output signal to output the corresponding
  • the switch sequence is used to control the current generator 1.
  • the control process is shown in Figure 12.
  • the entire control process can be expressed as:
  • i load is the test current signal
  • ⁇ i is the difference between the test current reference value and the test current signal
  • u PIR is the output value of the proportional integral resonant regulator
  • u'DUT feedforward voltage signal U m is the modulation voltage of the current generator
  • ⁇ 1 is the current frequency one
  • ⁇ 2 is the current frequency two
  • K Pi is the proportional control coefficient of the current controller
  • K Ii is the integral control coefficient of the current controller
  • K ri1 is the current
  • K ri2 is the resonance control coefficient of the current controller corresponding to power frequency two.
  • the constructed operating condition simulation system is used to simulate the operating conditions of the sub-modules in the actual cascaded converter, so that the electrical characteristics of the tested module group 2 in the operating condition simulation system are cascaded with the actual The sub-modules in the cascaded converter are the same, so the working condition of the sub-modules in the actual cascaded converter can be evaluated through the built working condition simulation system.
  • the voltage modulation method of the operating condition simulation system of the cascaded converter sub-module provided can adopt but not limited to the nearest level approximation modulation method and the carrier phase shift modulation method, which can be simulated but not Limited to cascaded converters
  • the simulated sub-module structure includes but not limited to half-bridge, full-bridge modular multilevel converter (MMC) and cascaded H-bridge converter (CHB).
  • the feedforward voltage is generated by calculation or sampling, and the feedforward voltage is compensated to the current controller to generate the feedforward voltage. Since the generated feedforward voltage changes synchronously with the on-off state of the sub-module under test, it can better offset the pulse voltage interference at the 2 ports of the tested module group caused by the nearest level approaching modulation, and avoid current due to pulse voltage The method does not need to add additional auxiliary circuits, thereby reducing the complexity of control and saving the manufacturing cost of the working condition simulation system, which is a very valuable technical improvement.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

一种级联型变流器多子模块的测试电路，其中，电流发生器（1）向被测试模块组（2）提供测试电流；被测试模块组（2）包含由多个被测子模块组成的串联连接的两个被测试桥臂（201），或，被测试模块组（2）由一个或多个串联连接的被测试单元（202）组成，每个被测试单元（202）包括两个反向串联的被测子模块。还提供了一种级联型变流器子模块测试系统，测试系统的电流控制方法以及适用于最近电平逼近调制下的级联型变流器子模块的测试方法。可实现级联型变流器子模块在整流、逆变运行模式下的工况模拟，能实现对多个子模块的同时测试。被测子模块反向串接的结构能够抵消电容电压中的直流分量，极大降低测试所需供电电压的要求。

Description

级联型变流器多子模块的测试电路、系统及其控制方法 技术领域
本发明涉及电力电子技术领域，具体地，涉及级联型变流器多子模块的测试电路、测试系统及其控制方法。
背景技术
Cascaded H-Bridge(CHB)，ModularMultiLevelConverter(MMC)等级联型变流器由子模块级联构成，其自身结构使得其便于拓展，尤其在高电压、大容量的运行场景下具备良好前景。随着级联型变流器容量和电压等级的不断提升，级联变流器在运行过程中可靠性的评估和检测受到了越来越广泛的关注。早期为了对级联型变流器进行可靠性的评估和检测，往往需要搭建完整的级联变流器系统，但由于级联型变流器的可靠性主要取决于级联型变流器子模块的可靠性，因此通过级联变流器子模块工况模拟测试电路来评估级联系统的可靠性，成为了更加高效且节约成本的方法。由于子模块的运行特性与变流器密切相关，为了确保变流器的长期可靠运行，对子模块在实际工况中的运行特性进行测试具有重要的意义。
然而现有的测试平台测试工况和控制模式较为单一，由于供电直流电压的限制，无法实现对多个子模块的同时测试，供电要求较高，测试效率低下。因此，需要一种简单、可靠的测试电路用来准确模拟被测子模块在实际系统中的运行工况，并实现多个子模块在多种工况下的同时测试，并降低对测试直流电压的要求，以提高测试效率。
另外，目前级联型变流器的调制方法主要为最近电平逼近调制法。在该调制方法下，级联型变流器子模块输出的脉冲电压具有脉冲幅值大，脉宽较宽等的特点，子模块可能会长时间的开通或关断，这使得被测试模块脉冲电压对电流控制器产生了较大干扰，导致电流控制器难以稳定地控制电流。
比如，专利号为ZL201910083488.1、ZL201910083490.9的中国发明专利，能够实现对级联型变流器任意子模块的运行工况模拟，但是运行于不同工况的子模块在测试电路中相互耦合增加了控制难度，同时无法抑制由最近电平逼近调制导致的电压脉冲干扰。也就是说，在传统的级联变流器子模块工况模拟测试电路中，缺少有效方法来抑制由最近电平逼近调制导致的电压脉冲干扰。为了消除子模块输出脉冲电压的影响，本领域通常通过添加额外的辅助电路，并控制辅助电路与子模块协同运行，从而抵消子模块脉冲电压对电流控制器带来的干扰。但额外 的控制电路增加了控制的复杂性以及模拟测试电路的制造成本，且由开关死区导致的控制延时将导致辅助电路与脉冲电压的同步性降低，进而导致辅助电路无法很好地抵消脉冲电压的干扰。因此，本领域亟需一种更简便，更节约成本的级联变流器子模块工况模拟技术和对应的电流控制方法。
发明内容
针对现有技术中的缺陷，本发明的目的是提供一种级联型变流器多子模块的测试电路及其控制方法。
本发明的第一方面，提供一种级联型变流器多子模块的测试电路，包括：电流发生器和被测试模块组，所述电流发生器向所述被测试模块组提供测试电流；其中所述被测试模块采用以下任一种构成形式：
-所述被测试模块组包括两个被测试桥臂，每个被测试桥臂包含若干串联连接的被测子模块，两个被测试桥臂之间呈反向串联连接结构；两个被测试桥臂中的被测子模块分别模拟级联型变流器整流和/或逆变的运行工况；两个被测试桥臂结构相同或不相同；
-所述被测试模块组包括一个或多个被测试单元，被测试单元之间呈串联关系；每个所述被测试单元包括两个反向串联的被测子模块，两个反向串联连接的被测子模块分别模拟级联型变流器整流或逆变的运行工况；两个反向串联连接的被测子模块的电容电压直流分量方向相反，大小相等；
所述被测试模块组及其内部被测子模块在不改变电气连接关系的前提下，在测试电路中能够按照任意顺序进行排列；当所述被测试模块接收到所述电流发生器发送的测试电流时，所述被测试模块模拟所述级联变流器子模块的电压信号，或者模拟所述级联变流器子模块的电压信号和电流信号。
可选地，所述电流发生器包括：单相变流器和滤波器；其中：
当所述被测试模块组包括两个结构相同的被测试桥臂时，所述单相变流器的第一端与所述滤波器的输入端连接，所述滤波器输出端与串联的第二个被测试桥臂的输入端相连，所述单相变流器的第二端与串联的第一个被测试桥臂的输入端相连，且所述第一个被测试桥臂的输出端与所述第二个被测试桥臂的输出端连接；所述单相变流器、滤波器、第一个被测试桥臂、第二个被测试桥臂的串联顺序可以任意改变；
当所述被测试模块组包括一个或多个被测试单元时，所述单相变流器的第一端与所述滤波器的输入端连接，所述滤波器输出端与串联的所述被测试单元的第一输入端相连，所述单相变流器的第二端与串联的所述被测试单元的第二输入端相连；所述单相变流器、滤波器、被测试 单元的串联顺序可以任意改变。
可选地，所述被测子模块包括：桥式电路和电容器，所述桥式电路和所述电容器并联。
可选地，所述桥式电路包括半桥型电路或全桥型电路；所述滤波器包括L型滤波器、CL型滤波器、LC型滤波器、LCL型滤波器中任一类型。
可选地，所述被测子模块对应实际级联型变流器中的子模块，所述电流发生器生成的电流对应所述被测子模块在实际级联型变流器中所在桥臂的电流，或相电流；所述测试电流包括：所述级联型变流器各相的上、下桥臂电流，或者各相的电流。
本发明的第二方面，提供一种级联型变流器子模块测试系统，包括：电流发生器，被测试模块组，级联变流器系统参数模型，电流控制器，电压控制器；
所述电流发生器，用于向所述被测试模块组提供特定的测试电流；
所述被测试模块组包括一个或多个被测试桥臂，每个被测试桥臂包含一个或多个串联连接的被测子模块，所述被测试桥臂之间呈反向串联关系；或者，所述被测试模块组包括一个或多个被测试单元，每个所述被测试单元包括两个反向串联的被测子模块，所述被测试单元之间呈串联关系；当所述被测试模块组接收到所述电流发生器发送的电流时，所述被测试模块组输出所述被测子模块的电压信号；
级联变流器系统参数模型，用于向电流控制器和电压控制器输出与实际级联型变流器的系统参数及运行工况相对应的电流和电压参考信号；
电流控制器，用于控制所述电流发生器生成的测试电流，以及生成电流发生器所需的控制信号；
电压控制器，用于控制所述被测试模块组中被测子模块的电容电压，以及生成被测试模块中被测子模块的开关控制信号。
可选地，所述电流控制器，具体完成以下一种或两种控制：
-根据测试电流信号及所述级联变流器系统参数模型输出的参考电流信号共同生成所述电流发生器的控制信号，并通过控制信号调节所述电流发生器输出的测试电流，使得所述电流发生器输出的测试电流与所述级联变流器系统参数模型输出的参考电流信号相同；
-采集单相电流发生器的输出测试电流i a以及级联变流器系统参数模型输出的参考电流i a.ref，计算输出测试电流i a与参考电流i a.ref之间的电流差值，并将所述电流差值通过比例-积分-谐振控制器生成电流发生器输出电压参考值u a,参考电压u a经过脉宽调制之后作为电流发生器内开关器件的控制信号。
可选地，所述电压控制器，根据所述被测试模块组输出的内部各被测子模块的电容电压 信号及所述级联变流器系统参数模型输出的参考电压信号，生成各被测子模块中开关器件的控制信号，以使得所述被测试模块内部各被测子模块的电容电压保持平衡，并且各被测子模块的电容电压与实际级联型变流器中需要模拟的子模块的电容电压相同。
可选地，所述电压控制器包括：电容均压模块和开关调制模块；其中：
所述电容均压模块，根据所述电流发生器输出的测试电流、所述被测试模块组输出的内部各被测子模块的电容电压、所述级联变流器系统参数模型输出的参考电压信号，生成所述被测试模块的目标电压信号；其中，所述参考电压信号包括平均电容电压和子模块参考电压；
所述开关调制模块，根据所述电容均压模块生成的目标电压信号，确定投入被测子模块个数，并根据所述电流发生器输出的测试电流信号控制所述被测试模块中各被测子模块的投切状态。
可选地，所述电容均压模块包括求取平均值元件、符号判断元件、加法器、乘法器以及PI控制器，其中，所述取平均值元件通过加法器的输出端与符号判断元件连接，并通过乘法器后与PI控制器串联连接；
所述电容均压模块，对所述被测试模块中被测子模块的电容电压进行闭环控制，所述闭环控制的策略如下：
将所述被测试桥臂中被测子模块电容电压的平均值V avg1与V avg2分别与级联变流器系统参数模型输出的参考电容电压信号V ref1与V ref2作差，得到电容电压差值；
将所述电容电压差值分别与电流发生器输出的测试电流信号的方向相乘，经过比例-积分控制器后再与级联变流器系统参数模型输出的电压参考信号u ref1与u ref2叠加，作为所述开关调制模块的输入信号；电容均压模块输出信号确定下一开关周期投入子模块数量；
所述开关调制模块采用电压调制方法，基于设定载波波形及所述电容均压模块生成的目标电压信号确定被测试模块中各被测子模块的脉冲信号，或根据电容电压对被测子模块进行排序，结合测试电流方向确定被测试模块中各被测子模块的脉冲信号，以使得所述被测试模块中被测子模块的电容电压与实际级联型变流器中需要模拟的子模块电容电压相同。
本发明的第三方面，提供一种级联型变流器子模块测试系统的电流控制方法，用于实现对由最近电平逼近调制导致的被测试模块脉冲电压对电流输出波形干扰的抑制；具体为，通过在电流控制器内补偿前馈电压，抵消由最近电平逼近调制导致的被测试模块脉冲电压干扰；其中：
用于补偿的所述前馈电压通过以下任意一种方式生成：
-第一种方式：计算处于逆变状态的被测子模块投入数目与处于整流状态的被测子模块投 入数目的差值，并结合单个子模块的电容电压，从而生成前馈电压；
-第二种方式：首先，通过电压采样器采样被测试模块的端口脉冲电压信号；再对采样得到的电压信号进行低通滤波，以滤除由开关死区导致的采样误差；最后，将低通滤波后的电压信号作为前馈电压；
将与被测试模块端口脉冲电压同步变化的前馈电压补偿至电流控制器中比例积分谐振调节器的输出端，从而抵消由被测试模块端口脉冲电压带来的干扰，避免了由脉冲电压干扰导致的电流畸变。
可选地，该方法适用于处于最近电平逼近调制下的级联型变流器子模块测试系统的电流控制；或者，应用于载波移相调制下的级联型变流器子模块测试系统的电流控制。
本发明第四方面，提供一种适用于最近电平逼近调制下的级联型变流器子模块的测试方法，该方法基于上述的级联型变流器多子模块的测试电路或上述的级联型变流器子模块测试系统，采用上述的级联型变流器子模块测试系统的电流控制方法，对级联型变流器子模块进行测试。
与现有技术相比，本发明具有如下的有益效果：
1、本发明提供的级联型变流器多子模块的测试电路，其中第一种被测试模块组结构是一种对称桥臂结构，每一个被测试桥臂包含多个串联的被测子模块，能够实现对级联型变流器中多个子模块在整流、逆变运行工况的同时模拟，串联型的被测子模块便于拓展，显著提高了测试效率，降低测试成本。进一步的，这种基于对称桥臂结构的级联型变流器多子模块的测试电路中，两个被测试桥臂包含数量相同的被测子模块，被测试桥臂之间反向串接的结构确保了被测试桥臂内部被测子模块电容电压中的直流分量相互抵消，显著降低了对测试电路中直流电压的要求。另外，这种电路可以通过改变电流发生器的输出电流及被测子模块的数量灵活地配置测试对应的工况条件，提高了实验的灵活性。
2、本发明提供的级联型变流器多子模块的测试电路中，其中第一种被测试模块组结构是一种反向串接结构，其每一个测试单元包含两个反向串接的被测子模块，能够实现对级联型变流器中同一子模块在整流、逆变两种运行工况的同时模拟。另外，若干串联连接测试单元能够实现多个子模块的同时测试，串联型的测试单元便于拓展，显著提高了测试效率，降低测试成本。进一步的，这种基于反向串接结构的级联型变流器多子模块的测试电路同一测试单元中两个被测子模块反向串接的基本结构确保了两个被测子模块电容电压中的直流分量相互抵消，显著降低了对测试电路中直流电压的要求。另外，可以通过改变电流发生器的输出电流及被测子模块的数量灵活地配置测试对应的工况条件，提高了实验的灵活性。
3、本发明提供的级联型变流器多子模块的测试电路的控制系统，可以根据电流发生器、电流控制器，产生与实际运行状态相同的待测子模块输入电流；并且通过电压控制器控制被测子模块的电容电压以及投切状态，产生与实际运行状态相同的待测子模块电容电压，从而实现对级联型变流器中多个子模块在整流、逆变运行工况的同时模拟，在确保测试的准确性提高测试效率；可以通过改变电流发生器的输出电流及被测子模块的数量灵活地配置测试对应的工况条件，提高了实验的灵活性。
4、本发明提供的级联型变流器子模块测试系统的电流控制方法，通过计算或采样的方式生成了前馈电压，并将前馈电压补偿到了电流控制器中，由于所生成的前馈电压与待测子模块的通断状态同步变化，因此，可较好抵消由最近电平逼近调制所导致的被测试模块组端口脉冲电压干扰，避免了电流因脉冲电压而导致的畸变，且该方法无需增加额外的辅助电路，从而降低了控制的复杂性，节约了工况模拟系统的制造成本，是极具价值的技术改进。
附图说明
图1为本发明一实施例中采用对称桥臂结构被测试模块的级联型变流器多子模块的测试电路的拓扑结构图；
图2为本发明一实施例中采用反向串接结构被测试模块的级联型变流器多子模块的测试电路的拓扑结构图；
图3为本发明一实施例中级联型变流器多子模块的测试电路中电流发生器的第一种拓扑结构示意图；
图4为本发明一实施例中级联型变流器多子模块的测试电路中电流发生器的第二种拓扑结构示意图；
图5为本发明一实施例中的级联型变流器多子模块的测试电路的第一种拓扑结构中被测试桥臂的第一种拓扑结构示意图；
图6为本发明一实施例中的级联型变流器多子模块的测试电路的第一种拓扑结构中被测试桥臂的第二种拓扑结构示意图；
图7为本发明一实施例中采用反向串接结构被测试模块的级联型变流器多子模块的测试电路中被测试单元的第一种拓扑结构示意图；
图8为本发明一实施例中采用反向串接结构被测试模块的级联型变流器多子模块的测试电路的被测试单元的第二种拓扑结构示意图；
图9为本发明一实施例中的级联型变流器子模块测试系统的原理图；
图10为本发明一实施例中的电流控制方法中前馈电压生成方式一的示意性框图；
图11为本发明一实施例中的电流控制方法中前馈电压生成方式二的示意性框图；
图12为本发明一实施例的级联型变流器子模块测试系统中电流控制器的示意性框图；
图13为本发明一实施例的前馈电压补偿效果示意性框图；
图14为本发明一实施例的级联型变流器子模块测试系统中电压控制器实现方式的示意性框图。
图中：电流发生器1，被测试模块组2，被测试桥臂201，被测试单元202，级联变流器系统参数模型3，电流控制器4，电压控制器5，电容均压模块51，开关调制模块52，端口电压采样器6，低通滤波器7。
具体实施方式
下面结合具体实施例对本发明进行详细说明。以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。应当指出的是，对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进。这些都属于本发明的保护范围。
参照图1、3～6所示，为本发明提供的一种对称桥臂结构的级联型变流器多子模块的测试电路，可模拟的级联变流器包括但不限于半桥、全桥型模块化多电平变流器(MMC)以及级联H桥型变流器(CHB)。
具体地，图1为本发明一实施例的基于对称桥臂结构的级联型变流器子模块单相测试电路的结构示意图；如图1所示，包括：电流发生器1和被测试模块组，被测试模块组包括两个被测试桥臂201，电流发生器1向两个被测试桥臂201提供测试电流，两个被测试桥臂201结构可以相同，也可以不相同；被测试桥臂201之间为反向串联连接。每个被测试桥臂201包括N个串联的被测子模块；当被测试桥臂201接收到电流发生器1发送的测试电流时，被测试桥臂201测试被测子模块的电压信号，或者测试被测子模块的电压信号和电流信号。被测试桥臂201及其内部被测子模块在不改变电气连接关系的前提下，在测试电路中能够按照任意顺序进行排列；两个反向串联连接的被测试桥臂201内部被测子模块电容电压直流分量方向相反，并且能够相互抵消。在一优选方式中，当被测试模块组包括两个结构相同的被测试桥臂时，两个被测试桥臂中被测子模块数目相同，所有被测子模块直流电压分量大小相等。
较佳地，电流发生器1用于生成测试电流，主要由单相变流器及其对应的出口滤波器构成；其中，单相变流器输出上端与出口滤波器输入端口相连接。进一步的，电流发生器1的输出上端与第二个被测试桥臂201的输入端相连接，输出下端与第一个被测试桥臂201的输入端相连接，用于生成流经两个被测试桥臂201内部被测子模块的测试电流；两个被测试桥臂201的输入端分别电流发生器1相连接用于接收测试电流，并将内部被测子模块的电容电压信号输出至外部； 通过电流发生器1产生测试电流，并通过两个被测试桥臂201实现对实际级联型变流器中多个被测子模块在整流、逆变工况下的同时模拟，显著降低对直流电压的要求，并提高测试效率。
较佳地，上述实施例中，电流发生器1具有至少一组两端的输出端口，输出的电流i a对应实际级联型变流器被测子模块所在桥臂的电流，电流发生器1中的单相变流器可以采用包括但不限于任意两电平及多电平电路拓扑结构，具体地，如图3所示的半桥型变流器；如图4所示的全桥型变流器；出口滤波器可以采用包括但不限于L、LC、LCL型滤波器在内的任意滤波器；被测试桥臂201中的被测子模块可以对应实际变流器各相的上、下桥臂子模块，被测试桥臂201的拓扑结构包括但不限于图5、图6所示的由半桥及全桥子模块组成的拓扑结构。图5的电路拓扑结构为：多个正向串联连接的半桥型变流器及其并联电容器。图6所示的电路拓扑：多个正向串联连接的全桥型变流器及其并联电容器。
本发明上述实施例提出的基于反向串接结构的级联型变流器子模块单相测试电路，可以实现对级联型变流器任意子模块的运行工况模拟，并且实现多个子模块在多种工况下的同时测试，并有效较低测试直流电压要求，节省测试成本并提升测试效率。
参照图2～4和7～8所示，为本发明提供的另一种基于反向串接结构的级联型变流器多子模块的测试电路，可模拟的级联变流器包括但不限于半桥、全桥型模块化多电平变流器(MMC)以及级联H桥型变流器(CHB)。
具体地，图2为本发明一实施例的基于反向串接结构的级联型变流器多子模块的测试电路的结构示意图，如图2所示，可以包括：电流发生器1和被测试模块组，电流发生器1向被测试模块组提供测试电流；其中，被测试模块组包括一个或多个被测试单元202，每个被测试单元202包括两个反向串联的被测子模块；被测试单元202之间呈串联关系；两个反向串联连接的被测子模块的电容电压直流分量方向相反，大小相等；被测试模块组及其内部被测子模块在不改变电气连接关系的前提下，在测试电路中能够按照任意顺序进行排列。当被测试单元202接收到电流发生器1发送的测试电流时，被测试单元202测试被测子模块的电压信号，或者测试被测子模块的电压信号和电流信号。每个被测试单元202中两个反向串联的被测子模块，分别模拟级联型变流器整流或逆变运行等多种工况；两个反向串联连接的被测子模块电容电压直流分量方向相反，并且能够相互抵消。
具体地，参见图2，被测试单元202之间为串联连接。其中，电流发生器1用于生成测试电流，主要由单相变流器及其对应的出口滤波器构成；单相变流器输出上端与出口滤波器输入端口相连接。电流发生器1的输出端与若干串联连接的被测试单元202相连接，用于生成流经被测试单元202内部被测子模块的测试电流；被测试单元202，输入端与电流发生器1相连接用于接 收测试电流，并将内部被测试单元202中被测子模块的电容电压信号输出至外部；通过电流发生器1产生测试电流，并通过被测试单元202实现对实际级联型变流器中多个被测子模块在多种运行工况下的同时模拟，显著降低对直流电压的要求，并提高测试效率。
较佳地，上述实施例中，电流发生器1具有至少一组两端的输出端口，输出的电流i a对应实际级联型变流器被测子模块所在桥臂的电流，电流发生器1中的单相变流器可以采用包括但不限于任意两电平及多电平电路拓扑结构，具体地，如图3所示的半桥型变流器；如图4所示的全桥型变流器；出口滤波器可以采用包括但不限于L、LC、LCL型滤波器在内的任意滤波器；被测试单元202中的被测子模块可以对应实际变流器各相的上、下桥臂子模块。被测子模块的拓扑结构包括但不限于图7、图8所示的由半桥及全桥子模块组成的拓扑结构。图7的电路拓扑为：两个反向串联连接的半桥型变流器及其并联电容器。图8的电路拓扑为：两个反向串联连接的全桥型变流器及其并联电容器。
本发明上述实施例提出的基于反向串接结构的级联型变流器子模块测试电路，可以实现对级联型变流器任意子模块的运行工况模拟，并且实现多个子模块在多种工况下的同时测试，并有效较低测试直流电压要求，节省测试成本并提升测试效率。
图9为本发明另一实施例中提供的级联型变流器子模块测试系统的原理图。该级联型变流器子模块测试系统可模拟的级联变流器包括但不限于半桥、全桥型模块化多电平变流器(MMC)以及级联H桥型变流器(CHB)。
参见图9所示，该实施例中的级联型变流器子模块测试系统包括：电流发生器1，被测试模块组2，级联变流器系统参数模型3，电流控制器4，电压控制器5。电流发生器1向被测试模块组2提供测试电流；被测试模块组2包括一个或多个被测试桥臂，每个被测试桥臂包含一个或多个串联连接的被测子模块，被测试桥臂之间呈反向串联关系；或者，被测试模块组2包括一个或多个被测试单元，每个被测试单元包括两个反向串联的被测子模块，被测试单元之间呈串联关系；当被测试模块组2接收到电流发生器发送的电流时，被测试模块组2输出被测子模块的电压信号；级联变流器系统参数模型3向电流控制器4和电压控制器5输出与实际级联型变流器的系统参数及运行工况相对应的电流和电压参考信号；电流控制器4控制电流发生器生成的测试电流，以及生成电流发生器1所需的控制信号；电压控制器5控制被测试模块组2中被测子模块的电容电压，以及生成被测试模块组2中被测子模块的开关控制信号。
以上实施例中电流发生器1、被测试模块组2构成如上图1、2所示实施例中的级联型变流器多子模块的测试电路；级联变流器系统参数模型3、电流控制器4、电压控制器5构成对级联型变流器多子模块的测试电路的控制系统，从而形成一个完整的级联型变流器子模 块测试系统。
具体的，如图9所示，上述实施例的级联型变流器子模块测试系统中，电流发生器1输出端与被测试模块组2上端相连接，用于生成流经被测试模块组2内部被测子模块的测试电流。被测试模块组2，输入端与电流发生器1相连接用于接收测试电流，并将内部被测子模块的电容电压信号输出至电压控制器5。级联变流器的系统参数模型3根据实际级联型变流器的系统参数及运行工况生成参考电流、电压信号用于模拟实际工况，并将参考电流、电压信号分别输出至电流控制器4和电压控制器5作为相应的目标电流信号和目标电压信号。电流控制器4接收级联变流器系统参数模型3输出的参考电流信号，并通过控制电流发生器中各器件的开关脉冲，使得电流发生器1的输出电流与级联变流器的系统参数模型3输出的参考电流近似相同。电压控制器5采集电流发生器1输出电流的电流信号、被测试模块组2输出的内部各被测子模块的电容电压信号和级联变流器的系统参数模型3输出的平均电容电压与子模块参考电压(参考电压信号)，生成被测试模块组2中各被测子模块的控制信号，使得被测试模块组2内部各被测子模块的电容电压与实际级联型变流器中需要模拟的子模块的电容电压近似相同。
上述实施例中，电流发生器1的输出端与被测试模块组2相连，用于生成测试电流，其包括单相变流器及其对应的滤波器。被测试模块组2的具体结构与图1～8所示实施例中相同。
较佳地，上述实施例中，电压控制器5可以包括：电容均压模块51及开关调制模块52；其中：电容均压模块51包括取平均值元件、符号判断元件、加法器、乘法器及PI控制器，取平均值元件经过加法器的输出端和符号判断元件经过乘法器后与PI控制器串联连接；开关调制模块52包括载波比较和排序算法。进一步的，电容均压模块51的输入包括电流发生器1输出电流的电流信号、被测试模块组2输出的内部各被测子模块的电容电压信号以及级联变流器系统参数模型3模块输出的参考电压信号，参考电压信号包括平均电容电压与子模块参考电压；电容均压模块输出被测试模块组2的目标电压信号；开关调制模块采用载波比较或排序算法，根据电容均压模块生成的目标电压信号确定投入被测子模块个数，并根据电流发生器1输出电流的电流信号控制被测试模块组2中各被测子模块的投切状态。
在本发明部分实施例中，级联变流器的系统参数模型3用于根据级联型变流器的系统及运行参数模拟实际系统的电气特征，电流控制器4、电压控制器5分别用于电流控制运算与电压控制运算。
图14为本发明一实施例的级联型变流器子模块测试系统中电压控制器实现方式的示意性框图。在本实施例中，电压控制器5的示意性框图包括但不限于图14所示的结构。电压控制器5中由电容均压模块51及开关调制模块52共同构成。电容均压模块51采集电流发生 器1输出电流的电流信号、被测试模块组2输出的内部各被测子模块的电容电压信号和级联变流器的系统参数模型3输出的平均电容电压与子模块参考电压，并生成被测试模块组2中测试桥臂1及测试桥臂2的合成参考电压信号(即目标电压信号)。
作为一个优选，开关调制模块52采用电压调制方法，基于设定载波波形及电容均压模块生成的目标电压信号确定被测试模块中各被测子模块的脉冲信号，如载波移相调制；或根据电容电压对被测子模块进行排序，结合测试电流方向确定被测试模块中各被测子模块的脉冲信号，如最近电平逼近调制。从而使得被测试模块中被测子模块的电容电压与实际级联型变流器中需要模拟的子模块电容电压相同。
具体的，开关调制模块52采用可选的载波比较或排序算法根据电容均压模块生成的目标电压信号确定投入被测试模块组2中被测子模块个数，并根据电流发生器1输出电流的电流信号控制被测试模块组2中各被测子模块的投切状态。具体的，电压控制器5对被测试模块组2中被测子模块的电容电压进行闭环控制，电压均压模块51将第一测试桥臂及第二测试桥臂中被测子模块电容电压的平均值V avg1与V avg2分别与级联变流器系统参数模型模块输出的参考电容电压信号V ref1与V ref2作差得到电容电压差值分别与电流发生器输出电流的方向相乘，经过比例-积分调节器(可选)再与级联变流器系统参数模型模块输出的电压参考信号u ref1与u ref2叠加后，作为开关调制模块52的输入信号，分别用于生成第一被测试桥臂及第二被测试桥臂中被测子模块的脉冲信号，从而使被测试模块组2中被测子模块的电容电压与实际级联型变流器中需要模拟的子模块电容电压相同。
具体的，第一测试桥臂及第二测试桥臂的调制波按照如下公式得到：
Figure PCTCN2020103857-appb-000001
式中：K p为电压控制器的比例控制系数，K i为电压控制器的积分控制系数，sign表示符号函数，用于提取电流发生器1输出电流i a的方向，u ref1*与u ref2*分别为第一测试桥臂及第二测试桥臂的调制波。
在本发明另一实施例中，提供了一种上述实施例中的级联型变流器子模块测试系统的电流控制方法，实现对由最近电平逼近调制导致的被测试模块脉冲电压对电流输出波形干扰的抑制；具体为，通过在电流控制器内补偿前馈电压，抵消由最近电平逼近调制导致的被测试模块脉冲电压干扰。
作为一优选实施例，电流控制器4中的电流控制方法采用比例积分谐振控制，输出电压的 调制方法采用正弦脉宽调制。
作为一优选实施例，电流控制器4接收测试电流参考信号、测试电流信号以及前馈电压信号后，输出开关序列，以控制电流发生器1输出所需的电流。从而使得工况模拟系统中的测试电流与所模拟的实际级联型变流器系统中的桥臂电流相同。电流控制器4具体的工作过程为：电流控制器4将读取到的桥臂参考电流信号与计算或采样得到的前馈电压的差值输入比例积分谐振控制器，再将读取到的前馈电压信号补偿到比例积分谐振控制器的输出端，最后根据补偿后的调制电压，通过正弦脉宽调制生成对应的开关序列，以控制电流发生器1。
本发明实施例提供的适用最近电平逼近调制的级联型子模块工况模拟系统的电流控制方法，通过在电流控制器内补偿前馈电压，抵消由最近电平逼近调制导致的被测试模块组2端口的脉冲电压干扰；通过将与被测试模块组2端口脉冲电压同步变化的前馈电压补偿至电流控制器中比例积分谐振调节器的输出端，从而抵消了由被测试模块组2端口脉冲电压带来的干扰，避免了由脉冲电压干扰导致的电流畸变。
图10为本发明一实施例中的电流控制方法中前馈电压生成方式一的示意性框图。用于补偿的前馈电压通过以下两种方式中任一种生成。
具体的，在一实施例中，采用前馈电压生成方法一，即：通过计算逆变型待测子模块组与整流型待测子模块组中投入子模块数目的差值，并结合单个子模块的电容电压，从而生成前馈电压，通过该方法进行前馈电压补偿的过程如图10所示。该前馈电压生成方法具体为，首先，读取下一时刻被测试模块2中所有被测子模块的开通关断状态，开通状态记为1，关断状态记为0；之后，计算所有处于逆变状态的被测子模块通断状态之和与所有处于整流状态的被测子模块通断状态之和的差值；最后，令通断状态之和的差值乘以单个子模块的电压，即可生成下一时刻电流控制所需的前馈电压。该前馈电压生成方法可用以下公式表示：
u' DUT＝U c×(n inv-n rec)
式中，u' DUT为用于补偿的前馈电压，U c为子模块电容电压的直流分量，n inv为下一时刻处于逆变状态的被测子模块的投入数目，n rec为下一时刻处于整流状态的被测子模块的投入数目。
可选地，前馈电压生成方法一中，生成前馈电压所需的单个子模块电容电压通过级联变流器系统参数模型得到，或者，也可以通过采样单个子模块的电容电压得到。
在另一实施例中，采用前馈电压生成方法二，如图11，为本发明一实施例中的电流控制方法中前馈电压生成方式二的示意性框图。该方法通过采样被测试模块组2的端口电压信号，并对采样得到的电压信号进行低通滤波，从而生成前馈电压，通过该方法进行前馈电压补偿的过程如图11所示。该前馈电压生成方法具体为：首先，通过端口电压采样器6采样被测试模 块组2端口的端口脉冲电压信号，电流发生器1两端的电压差信号；再对采样得到的电压信号，通过低通滤波器7，进行低通滤波，以滤除由开关死区导致的采样误差；最后，将低通滤波后的电压信号作为前馈电压。该前馈电压生成方法可用以下公式表示：
Figure PCTCN2020103857-appb-000002
式中，u' DUT为用于补偿的前馈电压，u DUT为端口电压采样器采样所得的端口电压，ω 0为低通滤波器的截止频率，s为传递函数中的复变量。
上述前馈电压生成方法二中，对采样得到的电压信号进行低通滤波所采用的低通滤波器的截止频率选为由开关死区导致的高频电压脉冲频率的1/10至1/100；对采样得到的电压信号进行低通滤波所采用的低通滤波器通过模拟电路或数字电路的方式实现。
在级联型变流器子模块工况模拟系统采用最近电平逼近调制法时，开关死区会导致待测子模块组两端的电压信号产生高频的电压脉冲，这类高频脉冲的脉宽极窄对电流控制器的干扰很小，但如果将这些高频的电压脉冲采样并补偿到电流控制器，反而会由于补偿的高频脉冲电压与实际高频脉冲电压存在的延时，而对电流控制器造成更大的干扰，因此在采样得到待测子模块组两端电压后，通过低通滤波器7对采样得到的信号进行低通滤波，从而在补偿电压内消除高频脉冲电压。
本发明实施例提供的电流控制方法，通过在电流控制器4内补偿前馈电压，抵消由最近电平逼近调制导致的被测试模块组2端口的脉冲电压干扰。具体地，电流控制方法可表述为，将所得的前馈电压信号补偿到电流控制器4中比例积分谐振调节器的输出端，最后根据补偿后的调节器输出信号进行正弦脉宽调制输出相应的开关序列，用于控制电流发生器1，控制过程如图12所示。整个控制过程可用公式表达为：
Figure PCTCN2020103857-appb-000003
其中，
Figure PCTCN2020103857-appb-000004
为流入子模块的测试电流参考值，i load为测试电流信号，Δi为测试电流参考值与测试电流信号的差值，u PIR为比例积分谐振调节器的输出值，u' DUT前馈电压信号，u m为电流发生器的调制电压，ω 1为电流频率一，ω 2电流频率二，K Pi为电流控制器的比例控制系数，K Ii为电流控制器的积分控制系数，K ri1为电流控制器的对应电流频率一的谐振控制系数，K ri2为电流控制器的对应电力频率二的谐振控制系数。
整个桥臂电流控制环路的框图如图13所示，可以明显看出再加入补偿电压后，被测试模块组2两端脉冲电压对电流控制环的影响被补偿电压抵消，因此可以抑制脉冲电压的干扰，从而使得系统输出的桥臂电流稳定地追踪参考电流。
在本发明部分实施例中，所搭建的工况模拟系统用于模拟实际级联型变流器中子模块的工作状况，使得工况模拟系统中被测试模块组2的电气特性与实际级联型变流器中的子模块相同，从而可以通过所搭建的工况模拟系统来评估实际级联型变流器中子模块的工况。
在本发明部分实施例中，所提供的级联型变流器子模块的工况模拟系统的电压调制方法可采用但不限于最近电平逼近调制法以及载波移相调制法，可模拟但不限于的级联变流器，所模拟的子模块结构包括但不限于半桥、全桥型模块化多电平变流器(MMC)以及级联H桥型变流器(CHB)。
本发明上述实施例提供的电流控制方法，通过计算或采样的方式生成了前馈电压，并将前馈电压补偿到了电流控制器中，生成前馈电压的方法。由于所生成的前馈电压与待测子模块的通断状态同步变化，因此，可较好抵消由最近电平逼近调制所导致的被测试模块组2端口脉冲电压干扰，避免了电流因脉冲电压而导致的畸变，且该方法无需增加额外的辅助电路，从而降低了控制的复杂性，节约了工况模拟系统的制造成本，是极具价值的技术改进。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变化或修改，这并不影响本发明的实质内容。在不冲突的情况下，本申请的实施例和实施例中的特征可以任意相互组合。

Claims (20)

  1. 一种级联型变流器多子模块的测试电路，其特征在于，包括：电流发生器和被测试模块组，所述电流发生器向所述被测试模块组提供测试电流；其中所述被测试模块采用以下任一种构成形式：
    -所述被测试模块组包括两个被测试桥臂，每个被测试桥臂包含若干串联连接的被测子模块，两个被测试桥臂之间呈反向串联连接结构；两个被测试桥臂中的被测子模块分别模拟级联型变流器整流和/或逆变的运行工况；两个被测试桥臂结构相同或不相同；
    -所述被测试模块组包括一个或多个被测试单元，被测试单元之间呈串联关系；每个所述被测试单元包括两个反向串联的被测子模块，两个反向串联连接的被测子模块分别模拟级联型变流器整流或逆变的运行工况；两个反向串联连接的被测子模块的电容电压直流分量方向相反，大小相等；
    所述被测试模块组及其内部被测子模块在不改变电气连接关系的前提下，在测试电路中能够按照任意顺序进行排列；当所述被测试模块接收到所述电流发生器发送的测试电流时，所述被测试模块模拟所述级联变流器子模块的电压信号，或者模拟所述级联变流器子模块的电压信号和电流信号。
  2. 根据权利要求1所述的级联型变流器多子模块的测试电路，其特征在于，所述电流发生器包括：单相变流器和滤波器；其中：
    当所述被测试模块组包括两个结构相同的被测试桥臂时，所述单相变流器的第一端与所述滤波器的输入端连接，所述滤波器输出端与串联的第二个被测试桥臂的输入端相连，所述单相变流器的第二端与串联的第一个被测试桥臂的输入端相连，且所述第一个被测试桥臂的输出端与所述第二个被测试桥臂的输出端连接；所述单相变流器、滤波器、第一个被测试桥臂、第二个被测试桥臂的串联顺序可以任意改变；
    当所述被测试模块组包括一个或多个被测试单元时，所述单相变流器的第一端与所述滤波器的输入端连接，所述滤波器输出端与串联的所述被测试单元的第一输入端相连，所述单相变流器的第二端与串联的所述被测试单元的第二输入端相连；所述单相变流器、滤波器、被测试单元的串联顺序可以任意改变。
  3. 根据权利要求1所述的级联型变流器多子模块的测试电路，其特征在于，所述被测子模块包括：桥式电路和电容器，所述桥式电路和所述电容器并联。
  4. 根据权利要求3所述级联型变流器多子模块的测试电路，其特征在于，所述桥式电路 包括半桥型电路或全桥型电路；所述滤波器包括L型滤波器、CL型滤波器、LC型滤波器、LCL型滤波器中任一类型。
  5. 根据权利要求1所述的级联型变流器多子模块的测试电路，其特征在于，所述被测子模块对应实际级联型变流器中的子模块，所述电流发生器生成的电流对应所述被测子模块在实际级联型变流器中所在桥臂的电流，或相电流；所述测试电流包括：所述级联型变流器各相的上、下桥臂电流，或者各相的电流。
  6. 根据权利要求1所述的级联型变流器多子模块的测试电路，其特征在于，所述被测试模块组包括两个结构相同的被测试桥臂时，两个被测试桥臂中被测子模块数目相同，所有被测子模块直流电压分量大小相等。
  7. 一种级联型变流器子模块测试系统，其特征在于，包括：电流发生器，被测试模块组，级联变流器系统参数模型，电流控制器，电压控制器；
    所述电流发生器，用于向所述被测试模块组提供特定的测试电流；
    所述被测试模块组包括一个或多个被测试桥臂，每个被测试桥臂包含一个或多个串联连接的被测子模块，所述被测试桥臂之间呈反向串联关系；或者，所述被测试模块组包括一个或多个被测试单元，每个所述被测试单元包括两个反向串联的被测子模块，所述被测试单元之间呈串联关系；当被测试模块组接收到所述电流发生器发送的电流时，所述被测试模块组输出所述被测子模块的电压信号；
    级联变流器系统参数模型，用于向电流控制器和电压控制器输出与实际级联型变流器的系统参数及运行工况相对应的电流和电压参考信号；
    电流控制器，用于控制所述电流发生器生成的测试电流，以及生成电流发生器所需的控制信号；
    电压控制器，用于控制所述被测试模块组中被测子模块的电容电压，以及生成被测试模块中被测子模块的开关控制信号。
  8. 根据权利要求7所述的级联型变流器子模块测试系统，其特征在于，所述电流控制器，具体完成以下一种或两种控制：
    -根据测试电流信号及所述级联变流器系统参数模型输出的参考电流信号共同生成所述电流发生器的控制信号，并通过控制信号调节所述电流发生器输出的测试电流，使得所述电流发生器输出的测试电流与所述级联变流器系统参数模型输出的参考电流信号相同；
    -采集单相电流发生器的输出测试电流i a以及级联变流器系统参数模型输出的参考电流i a.ref，计算输出测试电流i a与参考电流i a.ref之间的电流差值，并将所述电流差值通过比例-积分-谐振 控制器生成电流发生器输出电压参考值u a,参考电压u a经过脉宽调制之后作为电流发生器内开关器件的控制信号。
  9. 根据权利要求7所述的级联型变流器子模块测试系统，其特征在于，所述电压控制器，根据所述被测试模块组输出的内部各被测子模块的电容电压信号及所述级联变流器系统参数模型输出的参考电压信号，生成各被测子模块中开关器件的控制信号，以使得所述被测试模块内部各被测子模块的电容电压保持平衡，并且各被测子模块的电容电压与实际级联型变流器中需要模拟的子模块的电容电压相同。
  10. 根据权利要求9所述的级联型变流器子模块测试系统，其特征在于，所述电压控制器包括：电容均压模块和开关调制模块；其中：
    所述电容均压模块，根据所述电流发生器输出的测试电流、所述被测试模块组输出的内部各被测子模块的电容电压、所述级联变流器系统参数模型输出的参考电压信号，生成所述被测试模块的目标电压信号；其中，所述参考电压信号包括平均电容电压和子模块参考电压；
    所述开关调制模块，根据所述电容均压模块生成的目标电压信号，确定投入被测子模块个数，并根据所述电流发生器输出的测试电流信号控制所述被测试模块中各被测子模块的投切状态。
  11. 根据权利要求10所述的级联型变流器子模块测试系统，其特征在于，所述电容均压模块包括求取平均值元件、符号判断元件、加法器、乘法器以及PI控制器，其中，所述取平均值元件通过加法器的输出端与符号判断元件连接，并通过乘法器后与PI控制器串联连接；
    所述电容均压模块，对所述被测试模块中被测子模块的电容电压进行闭环控制，所述闭环控制的策略如下：
    将所述被测试桥臂中被测子模块电容电压的平均值V avg1与V avg2分别与级联变流器系统参数模型输出的参考电容电压信号V ref1与V ref2作差，得到电容电压差值；
    将所述电容电压差值分别与电流发生器输出的测试电流信号的方向相乘，经过比例-积分控制器后再与级联变流器系统参数模型输出的电压参考信号u ref1与u ref2叠加，作为所述开关调制模块的输入信号；电容均压模块输出信号确定下一开关周期投入子模块数量；
    所述开关调制模块采用电压调制方法，基于设定载波波形及所述电容均压模块生成的目标电压信号确定被测试模块中各被测子模块的脉冲信号，或根据电容电压对被测子模块进行排序，结合测试电流方向确定被测试模块中各被测子模块的脉冲信号，以使得所述被测试模块中被测子模块的电容电压与实际级联型变流器中需要模拟的子模块电容电压相同。
  12. 根据权利要求7所述的级联型变流器子模块测试系统，其特征在于，所述级联变流 器系统参数模型输出的参考电流信号和参考电压信号的生成方式包括以下任一方式：
    方式一：与实际级联型变流器系统参数及运行工况相同的仿真系统中得到仿真数据；
    方式二：实际级联型变流器运行过程中记录的数据；
    方式三：根据实际级联型变流器系统参数及运行工况计算得到的等效数据。
  13. 一种级联型变流器子模块测试系统的电流控制方法，其特征在于，通过以下控制方法，实现对由最近电平逼近调制导致的被测试模块脉冲电压对电流输出波形干扰的抑制；具体为，通过在电流控制器内补偿前馈电压，抵消由最近电平逼近调制导致的被测试模块脉冲电压干扰；其中：用于补偿的所述前馈电压通过以下任意一种方式生成：
    -第一种方式：计算处于逆变状态的被测子模块投入数目与处于整流状态的被测子模块投入数目的差值，并结合单个子模块的电容电压，从而生成前馈电压；
    -第二种方式：首先，通过电压采样器采样被测试模块的端口脉冲电压信号；再对采样得到的电压信号进行低通滤波，以滤除由开关死区导致的采样误差；最后，将低通滤波后的电压信号作为前馈电压；
    将与被测试模块端口脉冲电压同步变化的前馈电压补偿至电流控制器中比例积分谐振调节器的输出端，从而抵消由被测试模块端口脉冲电压带来的干扰，避免了由脉冲电压干扰导致的电流畸变。
  14. 根据权利要求13所述的电流控制方法，其特征在于，该方法适用于处于最近电平逼近调制下的级联型变流器子模块测试系统的电流控制；或者，应用于载波移相调制下的级联型变流器子模块测试系统的电流控制。
  15. 根据权利要求13所述的电流控制方法，其特征在于，所述第一种方式中生成前馈电压，包括：
    首先，读取下一时刻被测试模块中所有被测子模块的开通关断状态，开通状态记为1，关断状态记为0；
    之后，计算所有处于逆变状态的被测子模块通断状态之和与所有处于整流状态的被测子模块通断状态之和的差值；
    最后，令通断状态之和的差值乘以单个子模块的电压，即可生成下一时刻电流控制所需的前馈电压。
  16. 根据权利要求13所述的电流控制方法，其特征在于，所述第一种方式中，所生成的前馈电压通过公式表示为：
    u' DUT＝U c×(n inv-n rec)
    式中，u' DUT为用于补偿的前馈电压，U c为子模块电容电压的直流分量，n inv为下一时刻处于逆变状态的被测子模块的投入数目，n rec为下一时刻处于整流状态的被测子模块的投入数目；
    所述第二种方式中，所生成的前馈电压通过公式表示为：
    Figure PCTCN2020103857-appb-100001
    式中，u' DUT为用于补偿的前馈电压，u DUT为端口电压采样器采样所得的端口电压，ω 0为低通滤波器的截止频率，s为传递函数中的复变量。
  17. 根据权利要求16所述的电流控制方法，其特征在于，所述第一种前馈电压生成方式中，生成前馈电压所需的单个子模块电容电压通过级联变流器系统参数模型得到，或，通过采样单个子模块的电容电压得到。
  18. 根据权利要求13所述的电流控制方法，其特征在于，所述第二种方式中，对采样得到的电压信号进行低通滤波所采用的低通滤波器的截止频率选为由开关死区导致的高频电压脉冲频率的1/10至1/100；低通滤波器采用模拟电路或数字电路实现。
  19. 根据权利要求13-18任一项所述的电流控制方法，其特征在于，在电流控制器内补偿前馈电压，抵消被测试模块端口的脉冲电压干扰的方法，包括如下控制过程：
    Figure PCTCN2020103857-appb-100002
    式中，
    Figure PCTCN2020103857-appb-100003
    为测试电流参考值，i arm为电流发生器发送的测试电流，Δi为测试电流参考值与测试电流的差值，u PIR为比例积分谐振调节器的输出值，u' DUT为用于补偿的前馈电压，u m为电流发生器的调制电压，ω 1为电流频率一，ω 2电流频率二，K Pi为电流控制器的比例控制系数，K Ii为电流控制器的积分控制系数，K ri1为电流控制器对应电流频率一的谐振控制系数，K ri2为电流控制器对应电流频率二的谐振控制系数，s为传递函数中的复变量。
  20. 一种适用于最近电平逼近调制下的级联型变流器子模块的测试方法，其特征在于，基于权利要求1-6任一项所述的级联型变流器多子模块的测试电路或权利要求7-12任一项所述的级联型变流器子模块测试系统，通过权利要求13-19任一项级联型变流器子模块测试系统的电流控制方法，对级联型变流器子模块进行测试。
PCT/CN2020/103857 2019-07-23 2020-07-23 级联型变流器多子模块的测试电路、系统及其控制方法 WO2021013229A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/283,566 US11899067B2 (en) 2019-07-23 2020-07-23 Testing circuit, system and control method for multiple submodules of cascaded converter

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN201910665460.9A CN110426649B (zh) 2019-07-23 2019-07-23 级联型变流器子模块的单相测试方法及系统
CN201910665459.6A CN110488114A (zh) 2019-07-23 2019-07-23 基于反向串接结构的级联型变流器子模块测试电路
CN201910668891.0 2019-07-23
CN201910668891.0A CN110488115B (zh) 2019-07-23 2019-07-23 基于对称桥臂结构的级联型变流器子模块单相测试电路
CN201910665459.6 2019-07-23
CN201910665460.9 2019-07-23

Publications (1)

Publication Number Publication Date
WO2021013229A1 true WO2021013229A1 (zh) 2021-01-28

Family

ID=74193136

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/103857 WO2021013229A1 (zh) 2019-07-23 2020-07-23 级联型变流器多子模块的测试电路、系统及其控制方法

Country Status (2)

Country Link
US (1) US11899067B2 (zh)
WO (1) WO2021013229A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021159219A1 (en) * 2020-02-14 2021-08-19 Ecole De Technologie Superieure Three-phase multilevel electric power converter
US11682968B2 (en) * 2020-04-09 2023-06-20 Virginia Tech Intellectual Properties, Inc. Control of power converters having integrated capacitor blocked transistor cells
CN115166574B (zh) * 2022-05-19 2024-03-29 江苏省电力试验研究院有限公司 适用于直流漏电流监测的监测方法及系统

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103675539A (zh) * 2013-11-27 2014-03-26 广州智光电气股份有限公司 一种级联式储能变流器检测平台及其控制方法
CN103701350A (zh) * 2014-01-13 2014-04-02 清华大学 低频工况下模块化多电平变流器电容电压波动抑制方法
WO2018179145A1 (ja) * 2017-03-29 2018-10-04 東芝三菱電機産業システム株式会社 電力変換装置およびそのテスト方法
CN109188156A (zh) * 2018-11-06 2019-01-11 威凡智能电气高科技有限公司 一种高压直挂储能变流器模块化测试平台及测试电路
CN109324243A (zh) * 2018-09-06 2019-02-12 上海交通大学 一种级联型变流器子模块的工况模拟测试系统及测试方法
CN109709434A (zh) * 2019-01-29 2019-05-03 上海交通大学 级联型变流器多子模块多工况模拟的测试电路
CN109709363A (zh) * 2019-01-29 2019-05-03 上海交通大学 级联型变流器多子模块多工况模拟装置的控制方法及系统
CN110426649A (zh) * 2019-07-23 2019-11-08 上海交通大学 级联型变流器子模块的单相测试方法及系统
CN110488115A (zh) * 2019-07-23 2019-11-22 上海交通大学 基于对称桥臂结构的级联型变流器子模块单相测试电路
CN110488114A (zh) * 2019-07-23 2019-11-22 上海交通大学 基于反向串接结构的级联型变流器子模块测试电路
CN110850194A (zh) * 2019-10-15 2020-02-28 上海交通大学 一种级联型变流器子模块的工况模拟测试电路及方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101707443B (zh) * 2009-11-20 2013-05-08 中国电力科学研究院 一种新型电力电子变压器
WO2012099176A1 (ja) * 2011-01-18 2012-07-26 国立大学法人東京工業大学 電力変換器およびその制御方法
CN102565579B (zh) 2011-12-16 2014-03-12 中电普瑞科技有限公司 一种换流链运行试验装置及控制方法
CN103199682A (zh) * 2013-03-01 2013-07-10 南方电网科学研究院有限责任公司 基于mmc的柔性直流输电换流器谐波及损耗计算方法
CN105337519B (zh) * 2015-11-18 2018-05-01 阳光电源股份有限公司 级联多电平变换器的自检系统及自检方法
CN105553314A (zh) * 2015-12-21 2016-05-04 哈尔滨工业大学 基于三电平子模块和两电平子模块的混合型模块化多电平换流器拓扑结构
CN107645249A (zh) * 2016-07-21 2018-01-30 申茂军 一种基于载波移相调制的多电平变换器变频运行控制方法
CN107070289B (zh) * 2017-01-03 2019-05-24 武汉大学 一种模块化多电平结构的冲击电压产生装置及其方法
CN107863889B (zh) * 2017-11-29 2019-11-22 中国电力科学研究院 一种电网扰动装置
CN113994584B (zh) * 2018-01-25 2023-12-22 奥克兰联合服务有限公司 多电平模块化变换器
CN108539723B (zh) * 2018-05-07 2019-11-12 福州大学 一种分相分压式级联h桥柔性限流装置及其控制方法
JP6545425B1 (ja) * 2018-12-25 2019-07-17 三菱電機株式会社 電力変換装置
US12081112B2 (en) * 2019-12-25 2024-09-03 Mitsubishi Electric Corporation Power conversion device
CN113765427A (zh) * 2020-06-03 2021-12-07 台达电子企业管理（上海）有限公司 模块化多电平变换器系统及其电压检测方法、开路故障诊断方法
CN115347805A (zh) * 2021-05-12 2022-11-15 台达电子企业管理（上海）有限公司 供电装置及其控制方法、三相供电系统及其控制方法
US11611289B2 (en) * 2021-07-19 2023-03-21 Virginia Tech Intellectual Properties, Inc. Hybrid modular multilevel converter topologies using half-bridge submodules
CN215297543U (zh) * 2021-07-28 2021-12-24 中国三峡建工(集团)有限公司 一种级联型mmc柔直换流阀功率子模块试验装置
CN115128317A (zh) * 2022-06-21 2022-09-30 上海交通大学 级联结构电流发生器、变流器子模块测试电路和控制系统

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103675539A (zh) * 2013-11-27 2014-03-26 广州智光电气股份有限公司 一种级联式储能变流器检测平台及其控制方法
CN103701350A (zh) * 2014-01-13 2014-04-02 清华大学 低频工况下模块化多电平变流器电容电压波动抑制方法
WO2018179145A1 (ja) * 2017-03-29 2018-10-04 東芝三菱電機産業システム株式会社 電力変換装置およびそのテスト方法
CN109324243A (zh) * 2018-09-06 2019-02-12 上海交通大学 一种级联型变流器子模块的工况模拟测试系统及测试方法
CN109188156A (zh) * 2018-11-06 2019-01-11 威凡智能电气高科技有限公司 一种高压直挂储能变流器模块化测试平台及测试电路
CN109709434A (zh) * 2019-01-29 2019-05-03 上海交通大学 级联型变流器多子模块多工况模拟的测试电路
CN109709363A (zh) * 2019-01-29 2019-05-03 上海交通大学 级联型变流器多子模块多工况模拟装置的控制方法及系统
CN110426649A (zh) * 2019-07-23 2019-11-08 上海交通大学 级联型变流器子模块的单相测试方法及系统
CN110488115A (zh) * 2019-07-23 2019-11-22 上海交通大学 基于对称桥臂结构的级联型变流器子模块单相测试电路
CN110488114A (zh) * 2019-07-23 2019-11-22 上海交通大学 基于反向串接结构的级联型变流器子模块测试电路
CN110850194A (zh) * 2019-10-15 2020-02-28 上海交通大学 一种级联型变流器子模块的工况模拟测试电路及方法

Also Published As

Publication number Publication date
US11899067B2 (en) 2024-02-13
US20210389376A1 (en) 2021-12-16

Similar Documents

Publication Publication Date Title
CN105790626B (zh) 谐振型功率转换电路及控制谐振型功率转换电路的方法
WO2021013229A1 (zh) 级联型变流器多子模块的测试电路、系统及其控制方法
CN107612409B (zh) 带偏磁控制的精简矩阵变换器模型预测控制方法
CN109709363B (zh) 级联型变流器多子模块多工况模拟装置的控制方法及系统
CN111965468B (zh) 适用nlc的级联型子模块工况模拟系统的电流控制方法
CN107204720A (zh) 一种交直流变换电路、交直流变换器及其控制方法
CN117630668B (zh) 基于对称模块组的高压直挂储能模块测试系统和控制方法
CN107046374A (zh) 一种模块化多电平变换器子模块电容电压均衡控制方法
CN106452142B (zh) 一种适用于模块化多电平变换器的改进调制策略
CN102130572B (zh) 一种三相整流桥直流侧并联型有源电力滤波器
Djerboub et al. Particle swarm optimization trained artificial neural network to control shunt active power filter based on multilevel flying capacitor inverter
CN112532059A (zh) 一种交错并联llc的均流控制方法
CN110488115B (zh) 基于对称桥臂结构的级联型变流器子模块单相测试电路
CN114285071A (zh) 用于并网变流器稳定性测试的电网模拟器及测试装置
CN102684204A (zh) 一种级联式statcom直流侧电容电压平衡控制方法
CN114977747B (zh) 一种谐振滤波器、级联型变流器子模块测试电路及控制
CN110426649A (zh) 级联型变流器子模块的单相测试方法及系统
CN109067147B (zh) 级联型变流器子模块电容电压扰动量及不平衡度提取方法
CN109004844B (zh) 串联阻抗源变换器的光储协调与输出均压综合控制方法
CN112701725A (zh) 一种混合导通模式的并网逆变器
CN113176428B (zh) 级联型变流器工况模拟的电流畸变消除系统及方法
CN108880307A (zh) 一种无需电流信号的子模块电容电压均衡控制方法
CN109039124A (zh) 基于移相空间矢量调制的mmc电容电压均衡控制方法
CN114362549A (zh) 基于非隔离型背靠背拓扑的级联多电平变流器及其控制策略
CN202772582U (zh) 一种级联式statcom直流侧电容电压平衡控制电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20843765

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20843765

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 22.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20843765

Country of ref document: EP

Kind code of ref document: A1