WO2020135209A1 - Method for reducing bank conflicts - Google Patents

Abstract

A method for reducing bank conflicts, comprising: determining binary addresses of a plurality of pieces of data to which a bank conflict occurs when a memory comprising N banks is accessed in parallel; determining a shift step, the shift step representing the number of banks in which data has been moved and being a value represented by n bits selected from a binary address of data in the memory, where N=2^n; after the data in the memory is moved by a shift step, the data, to which a bank conflict occurs, no longer being located in the same bank; and moving the data in the memory by the shift step, the row address values in the banks of the data in the memory being unchanged. According to the method, data, to which a conflict might occur, during access is no longer located in the same bank, thereby reducing bank conflicts and improving the memory performance.

Description

Method for reducing memory conflict Technical field

The invention relates to a method for reducing memory bank conflicts, which belongs to the technical field of memory.

Background technique

Recently, as the demands on the processor's ability to process data have increased, some processors have been designed to access memory in parallel. In the case where the memory has multiple banks, the processor can simultaneously access multiple banks at the same time without conflict.

However, in some cases, the processor may need to access data stored in the same memory bank in parallel. Under normal circumstances, the address of the data in the memory is fixed, and a bank conflict will occur at this time. That is, these data located in the same memory bank must be accessed one by one. For example, in the memory example shown in FIG. 3, each column represents a memory bank, that is, the memory has 8 memory banks of Bank 0, ..., Bank 7, and if multiple addresses in the same memory bank are accessed Data, for example, click 0,8,16,24 in Bank 0, as shown in gray in Figure 3, then it must use multiple cycles to access Bank 0 one by one, resulting in reduced memory performance.

Summary of the invention

The object of the present invention is to provide a solution for reducing memory bank conflicts in the LSU (Load/Store, Unit, Access Unit) micro-architecture design of a processor to improve memory performance.

The first aspect of the present invention provides a method for reducing memory bank conflicts, including:

Determine the binary addresses of multiple data that will cause bank conflicts when accessing the memory containing N banks in parallel;

Determine the shift step size. The shift step size indicates the number of memory banks in which the data in the memory bank will be moved. It is the value represented by n bits selected from the binary address of the data in the memory, where N=2^n, Moreover, both N and n are natural numbers; and after the data in the memory is moved by their respective shift steps, multiple data in which a bank conflict occurs will no longer be in the same bank; and

The data in the memory is moved according to the shift step, wherein the row address value of the data in the memory within the memory bank is unchanged.

Through address conversion, the present invention makes data that may conflict during access no longer in the same storage body, reduces storage body conflicts, and improves memory performance.

Further, the shift steps of the multiple data in which the bank conflict occurs are different from each other, so that after the data in the memory is moved by the shift step, the multiple data in which the bank conflict occurs will be respectively located in different banks. By moving all the conflicting data to different storage bodies, all conflicts are eliminated as much as possible, and the performance of the memory is fully improved.

Further, the n bits selected from the binary address of the data in the memory may be consecutive n bits. Alternatively, the n bits selected from the binary address of the data in the memory may also be discontinuous n bits. More specifically, the line spacing of multiple data in which a bank conflict occurs can be represented by 2^i+j, where i and j are natural numbers, and 0≤j<2^i; when j=0, the shift step size It may be a value represented by consecutive n bits from the n+i bit of the binary address of the data in the memory to the higher bit direction. When j≠0, the shift step size can be the value represented by consecutive n bits from the n+i or n+i+1 bit of the binary address of the data in the memory, or the data in the memory The value represented by the discontinuous n bits in the binary address of. The choice of these different shift steps depends on the specific circumstances of the memory bank conflict and the configuration of the software.

Further, the storage space of the memory can be divided into multiple pages, and multiple sets of registers are provided to configure the pages to determine the shift step size for each page, and the number of registers is less than or equal to the number of pages. Further, when the number of registers is smaller than the number of pages, each register can be mapped to multiple pages in a TLB manner.

A second aspect of the present invention provides a device for reducing memory bank conflicts, including:

The bank conflict determination unit is configured to determine a binary address of a plurality of data in which bank conflicts occur when parallel access is made to a memory containing N banks;

The shift step determination unit is configured such that after the data in the memory is moved by its respective shift step, multiple data in which a bank conflict occurs will no longer be located in the same bank, where the shift step indicates storage The number of banks in which the data in the volume will be moved is the value represented by n bits selected from the binary address of the data in the memory, where N = 2^n, and both N and n are natural numbers; and

The shift unit is configured to shift the data in the memory according to a shift step, wherein the row address value of the data in the memory within the memory bank is unchanged.

Further, the shift step determination unit is further configured that the shift steps of a plurality of data in which a bank conflict occurs are different from each other, so that after the data in the memory is shifted by the shift step, there are many bank conflicts The data will be located in different memory banks.

Further, the n bits selected from the binary address of the data in the memory may be consecutive n bits. Alternatively, the n bits selected from the binary address of the data in the memory may also be discontinuous n bits, and the shift step size of the data in which the bank conflict occurs may be completely different.

Further, the shift step determination unit may be further configured to divide the storage space of the memory into multiple pages, and provide multiple sets of registers to configure pages to select shift steps for each page, and the number of registers is less than or equal to The number of pages. Further, when the number of registers is less than the number of pages, each register is mapped to multiple pages in a TLB manner.

A third aspect of the present invention provides a processor. The processor includes a memory having a plurality of storage bodies and the device provided by the foregoing second aspect or any implementation manner of the second aspect.

A fourth aspect of the present invention provides an electronic device. The electronic device may be various computers, servers, or various mobile devices, including the processor provided in the foregoing fourth aspect or any implementation manner of the fourth aspect.

A fifth aspect of the present invention provides a computer program product, the computer program product includes program code, and when the computer program product is executed by a controller, the controller executes the foregoing first aspect or any implementation manner of the first aspect The method provided.

The present invention performs a shift operation by simply extracting a few bits in the address of the data stored in the memory, moves the data that may conflict to different memory banks, reduces or eliminates the memory bank conflicts, and improves the memory performance.

BRIEF DESCRIPTION

FIG. 1 is a flowchart of a method for reducing memory bank conflict according to an embodiment of the present invention.

2 is a schematic diagram of a system capable of reducing memory bank conflicts according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a memory having eight memory banks according to an embodiment of the present invention.

4 is a schematic diagram of a memory after using address [5:3] to move data in a memory according to an embodiment of the present invention.

5 is a schematic diagram of a memory after using address [6:4] to move data in a memory according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a memory after using values represented by bits 6, 5, and 3 of an address as shift steps to move data in a memory according to an embodiment of the present invention.

7 is a schematic diagram of hardware implementation of memory address reorganization according to an embodiment of the present invention.

detailed description

The present invention will be further described below with reference to specific embodiments and drawings. It can be understood that the specific embodiments described herein are only for explaining the present invention, rather than limiting the present invention. In addition, in order to facilitate description, the drawings only show parts, but not all structures or processes related to the present invention.

Memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) may include multiple banks, and devices such as processors may independently access multiple banks. When a processor needs to access data stored in the same memory bank in parallel, a memory bank conflict occurs. The present invention uses address conversion to move data that may be in conflict to different memory banks, thereby reducing memory bank conflicts.

According to an embodiment of the present invention, a method for reducing memory bank conflict is provided. As shown in FIG. 1, the method includes the following steps:

First, in step S101, a binary address of a plurality of data in which a bank conflict occurs when parallel access to a memory including multiple banks is determined. For example, as shown in FIG. 3, in the memory 300 having eight banks Bank 0, Bank 1, ..., Bank 7, under normal circumstances, data in eight banks can be accessed in parallel through 8 addresses There will be no conflict. However, if you click on multiple data stored in the same memory bank at the same time, for example, click on the four addresses 0,8,16,24 in Bank 0 at the same time, as shown in gray in Figure 3, a bank conflict will occur. When you need to access the data at 0, 8, 16, and 24 at the same time, 0, 8, 16, and 24 are the locations where memory bank conflicts will occur.

Subsequently, in step S102, a shift step size is determined. The shift step size indicates the number of memory banks in which data in the memory bank is moved, that is, several memory banks in which the data will be moved, which is selected from the binary addresses of the data in the memory The value represented by the n bits of, where N=2^n, and both N and n are natural numbers; and, after the data in the memory is shifted by the shift step, the data in which the bank conflict occurs will no longer be in the same bank Medium; and Step S103, the data in the memory is moved according to the shift step, wherein the row address value of the data in the memory within the memory bank is unchanged.

For example, for the memory 300 shown in FIG. 3, the conflicting data 0, 8, 16, 24 can be transferred in shift steps so that they are located in different memory banks. The memory 300 includes 8 memory banks (that is, N=8). For each data stored in it, a maximum of 7 banks need to be moved, and a minimum of 0 banks need to be moved. Then, a three-bit address can be used to represent the shift step Therefore, 3 bits can be selected from the address of the data stored in the memory to represent the shift step size (ie, n=3). For example, according to an embodiment of the present invention, the value represented by the consecutive 3 bits from the third bit of the address to the higher bit direction can be used as the shift step, that is, the address [5:3] is taken to move the memory Data, that is, take the 5th to 3rd bits of the address of the data stored in the memory (in the address representation, the lowest bit of the rightmost side is usually taken as the 0th bit, and it is sequentially increased to the left. All expressed in this way), according to the three-bit value to move the data in the memory. Then, in the memory 300, the shift steps of the first line of data 0-7 are all 000, that is, the first line of data does not move; the shift steps of the second line of data 8-15 are all 001, that is, move One bit; in the same way, the shift step of the remaining data can be obtained. In this embodiment, the conflicting data of the sending memory bank is moved to a different memory bank, but the row address value of the data inside the memory bank has not changed, that is, from the perspective of the figure, the data are all in the same row Medium shift, because the shift step only changes the decoding of the memory bank, and does not change the decoding of the row address inside the memory bank.

After shifting in the above manner, the results shown in Figure 4 can be obtained. The data 0, 8, 16, 24 in the memory are moved to different banks Bank 0, Bank 1, Bank 2, Bank 3, etc. The processor can access 0, 8, 16, 24 in parallel in one cycle. In FIG. 4, only the row where the data of the bank conflict occurs is schematically shown, and the remaining rows are omitted.

As can be seen from the comparison between Figure 3 and Figure 4, after moving the data in the above manner, the memory bank conflict is eliminated, and the data at 0, 8, 16, 24 can be accessed in parallel in the same cycle, which improves Memory performance.

It should be noted that the above shift step selection can be flexibly configured according to different data access requirements. For example, in another embodiment, there are 8 banks for the memory 300 which is also similar to FIG. 3 Memory, assuming that the data at Bank 0, 0, 16, 32, 48 conflicts, in order to move the above data to different memory banks, you can use the consecutive 3 bits from the fourth bit of the address to the higher bit direction The value is used as the shift step, that is, the value represented by the address [6:4] is used as the shift step to move the data in the memory. The shift steps of the data at 0, 16, 32, 48 are 000 , 001, 010, and 011, so that the data at 0, 16, 32, and 48 will be moved to banks Bank 0, Bank 1, Bank 2, Bank 3, respectively. The result after the shift is shown in Figure 5.

In addition, in the above two examples, all the conflicting data have been moved to different memory banks, but this is only a preferred embodiment of the present invention. In some cases, all conflicts may not be removed. The data is moved to different memory banks separately, but only part of the conflicted data is moved to different memory banks to eliminate part of the conflict. For example, in the memory shown in Figure 3, it is assumed that the data at 0, 8, 16, 24 needs to be accessed at the same time. In addition to the above address [5:3] to move the data in the memory, the address [6 : 4] to move the data in the memory, that is, the shift steps of the four conflicting data are 000, 000, 001, and 001. The result after the movement is the same as that in FIG. 5. At this time, the memory conflict The data at 0, 8, 16, 24 were moved to Bank 0, Bank 0, Bank 1, Bank 1, respectively, so that access to such four data was reduced from four cycles to two cycles, which also reduced the memory bank The conflict improves memory performance to a certain extent.

The above embodiment shows a case where several consecutive bits in the address of the data stored in the memory are selected to represent the shift step size. In addition, it is also possible to select a few consecutive bits in the address as the shift step.

For example, in the example of the memory with 8 banks shown in FIG. 3, in one embodiment, if the conflicting data is the data at 8, 16, 32 in Bank 0, in order to transfer the above data to In different memory banks, you can select the data consisting of the sixth, fifth, and third bits of the address as the shift step, and move the data to the banks Bank 1, Bank 0, Bank 2, respectively, and obtain the results shown in Figure 6. Fig. 6 only schematically shows some rows, and the remaining rows are omitted. Similarly, in some embodiments, the data consisting of bits 5, 4, and 2 of the address may also be selected as the shift step, or the data consisting of bits 6, 3, and 1 may be selected as the shift step, etc., These different choices depend on different memory conflicts caused by different data access requirements or different software configurations.

Although the different choices for the shift step size depend on different memory conflicts caused by different data access requirements or different software configurations. However, there are certain rules to follow when choosing. For example, in the case where a plurality of data in which a bank conflict occurs are equidistant, the line spacing of the conflicting data (in the present invention, the line spacing represents the difference between the line address values of the two data) can be expressed as 2^i+j, Among them, i and j are natural numbers, and 0≤j<2^i. At this time, in different cases, the shift step size can be selected in the following manner.

When j=0, the shift step size can be selected as the value represented by consecutive n bits from the n+i bit of the binary address of the data in the memory to the higher bit direction. For example, in the memory bank conflict example shown in FIG. 3, the line spacing of the data at 0, 8, 16, 24 is 1, that is, i=0, j=0, then select the consecutive n+i=3 consecutive 3 (n=3) bits, that is, address [5:3] to move the data in the memory, which can effectively eliminate the memory bank conflict; again, as shown in FIG. 5, the conflict data 0, 16, 32, 48 are moved to For examples in different memory banks, the line spacing of conflicting data is 2, that is, i=1, j=0, then you can select consecutive 3 (n=3) bits from n+i=4, which is the address [6: 4] To move the data in the memory, it can also effectively eliminate memory conflicts. When j≠0, the shift step size can be the value represented by consecutive n bits from the n+i or n+i+1 bit of the binary address of the data in the memory, or the value in the memory The value represented by discrete n bits in the binary address of the data. For example, also using the example of a memory with 8 banks shown in FIG. 3, assuming that the bank conflict data is 0,24,48, the line spacing is 3, that is, i=1, j=1, then you can Select consecutive 3 (n=3) bits from n+i=4, that is, address[6:4] to move the data in the memory. At this time, the shift steps of the data at 0, 24, 48 are respectively 000, 001, 011, the data will be moved to the bank Bank 0, Bank 1, Bank 3, which can effectively eliminate the bank conflict; you can also choose the n + i + 1 = 5 consecutive 3 (n = 3 ) Bits, that is, address [7:5] to move the data in the memory, at this time, the shift steps of the data at 0, 24, 48 are 000, 000, and 001, respectively, and the data is moved to the bank Bank 0 , Bank0, Bank1, effectively reduce the bank conflict; you can also select a few consecutive bits, as long as you can remove the data of the bank conflict from the same bank.

It should be noted that the above selection method of the shift step when the line spacing of conflicting data is represented by 2^i+j is only an example, and is intended to illustrate a possible implementation of the present invention, and does not constitute a limitation on the present invention. For those skilled in the art, according to the idea of the present invention, n bits in the address can be selected as a shift step in various ways.

Meanwhile, although an example of a memory including 8 memory banks is shown in FIGS. 3-5, those skilled in the art should understand that the number of memory banks and the structure of the memory shown here are only for convenience of explanation, and It does not constitute a limitation on the present invention. The present invention can also be applied to memories with different numbers of banks of 4, 16, 32, etc. In memories with different numbers of banks, addresses with different numbers of bits can be selected as shift data, for example, in In a memory with 32 banks, when a bank conflict occurs, 5 bits of the address can be selected as shift data, and the value represented by the selected 5 bits can be used to move the conflicted data to different banks, thereby reducing Memory conflict.

The following describes a hardware implementation example of memory address reorganization according to an embodiment of the present invention with reference to FIG. 7.

According to an embodiment of the present invention, it is assumed that the memory is divided into N memory banks. In general, N usually takes an exponent of 2, such as 2, 4, 8, 16, 32, etc., that is, N = 2^n to avoid resources Wasted, but in some extreme cases, other values can also be taken.

Generally, n bits can be selected from the memory address to decode the bank selection. For example, as shown in FIG. 7, this signal can be named bank_sel (ie, bank_sel is the n-bit selected from the address). Without the present invention, the value of Bank_sel can directly select the memory bank to be accessed, for example, bank_sel=0 means Bank 0, bank_sel=1 means Bank 1, and so on.

In an embodiment according to the present invention, a shift step can be added to bank_sel, which can be represented by shift_sel. As shown in FIG. 7, for each row of such a memory with N banks, there will be N A possible shift situation (0, 1, 2, ..., N-1), that is, the value of shift_sel may be 0...N-1. Then, the choice of memory bank is determined jointly by bank_sel and shift_sel. For example, bank_sel+shift_sel=0 means Bank 0, bank_sel+shift_sel=1 means Bank 1, and so on.

Thus, as shown in FIG. 7, a 5-bit field address can be defined, including bank selection (bank_sel), shift step (shift_sel), byte offset (offset), and 2-bit field index (index_h And index_l) to generate decoded signals. Among them, bank selection (bank_sel) and shift step (shift_sel) are used to decode bank selection, as described above; row indexes (index_h and index_l) are used to index specific rows of the bank, that is, used to index data in The row address inside the memory bank; the byte offset (offset) is used to index the offset within a memory bank. For example, if the memory bank width is 4 bytes, the byte offset (offset) should be 2 bits. The position of each field can be configured by software. For example, whether shift_sel and bank_sel are adjacent can be configured by software. If they are not adjacent, as shown in FIG. 7, for example, the width of index_l can also be configurable .

After the hardware is configured, the key is how to obtain the shift step shift_sel.

According to an embodiment of the present invention, a simple method is to select another n bits in the address as shift_sel according to data access requirements. Both the bank_sel bit and the shift_sel bit can be any n bits in the address. For example, they can be the same n bits in the address, or some bits overlap. The software configuration can select the n-bit in the address as shift_sel according to the application scenario. Of course, if you don't want to move, you can also configure a value that means no movement. As mentioned earlier, they can be consecutive n bits in the address or discontinuous n bits.

Another more complex but more flexible method is to select different bits as shift_sel in different address spaces.

For example, in some embodiments, the storage space of the memory may be divided into multiple pages (page), for example, divided into Page 1, Page 2, Page 3... Each page may have n KB (or other) space , You can provide multiple sets of registers to configure these pages, so as to define a different shift mode for each page. For example, you can choose to use the address [5:3] in Page 1 to move the data in the memory, choose the address [6:4] in Page 2 to move the data in the memory, and select the first address in Page 3 5, 4, 2 bits to move the data in the memory and so on.

If possible, a set of registers can be allocated for each page. However, in some cases, the number of register groups may be smaller than the number of address pages, that is, a group of register groups may be configured to be mapped to different pages in a TLB manner, thereby saving registers. This method is actually a special TLB (Translation Lookaside Buffer, translation bypass buffer). Traditionally, TLB is generally used to convert a virtual address to a physical address, but here, a TLB can be provided to transfer the data in the memory from one memory bank to another memory bank in different shift modes on different pages.

In the memory space divided into a plurality of pages, the size of each page may be an index of 2, that is, M=2^m. Then, the address in one page can be represented by m bits. Assuming that the entire address has k bits, other k-m bit addresses may constitute page addresses. You can define multiple sets of configuration registers, and use these multiple sets of configuration registers as TLB. When accessing the memory, the page address of the accessed address is compared with the page addresses in all configuration register groups. If an identical value is found, then the group configuration can be used to select shift_sel; and if the same value is not found, Then the hardware will request an interrupt from the software to request the software to fill or replace the TLB, or automatically replace the TLB entry with the software pre-configured value in the second TLB. The software must ensure that no two or more register bank configurations correspond to the same page. In this way, a large number of page address spaces can be configured with a relatively small number of register groups, and the addresses can be converted from one memory bank to another in different shift modes in different page address spaces.

The above hardware implementation is only used as an example to illustrate the idea of the present invention, and the specific configuration therein does not constitute a limitation to the present invention, and the present invention can be implemented in various suitable ways.

According to another embodiment of the present invention, there is also provided a system, which can be implemented in a processor, as shown in FIG. 2, that is, the processor may include a memory 20 having multiple memory banks and reduce memory bank conflicts的装置10。 The device 10. Among them, the device 10 includes a bank conflict determination unit 101 configured to determine the binary address of data that will cause bank conflict when parallel access to a memory containing N banks is performed; the shift step determination unit 103 is configured as After the data in the memory is moved in shift steps, the data in which the memory bank conflicts will no longer be in the same memory bank, where the shift step indicates the number of memory banks in which the data in the memory bank is moved. The value represented by the n bits selected in the binary address of the data in which N=2^n; and the shift unit 105 is configured to move the data in the memory according to the shift step, wherein the data in the memory is stored The row address value inside the bank remains unchanged; the device 10 can execute the method shown in FIG. 1 to reduce bank conflicts.

Here, it is particularly noted that the units mentioned in various embodiments of the present invention are logical units. Physically, a logical unit may be a physical unit, or may be a part of a physical unit, or may be multiple The combination of physical units is implemented. The physical implementation of these logical units is not the most important. The combination of functions implemented by these logical units is the key to solving the technical problems proposed by the present invention. In addition, in order to highlight the innovative part of the present invention, units that are not closely related to solving the technical problems proposed by the present invention are not introduced in the embodiments of the present invention, which does not mean that there are no other units in the embodiments.

According to another embodiment of the present invention, there is also provided an electronic device, including the processor as described above, such a computing device may be various computing devices, such as laptop computers, desktop computers, workstations, personal digital Assistants, servers, blade servers, mainframes, and other suitable computers; or various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, portable digital assistants (PDAs), portable game consoles, handheld computers, or tablet computers Etc.; or various smart devices, such as various wearable smart devices, smart home appliances, etc.

The embodiments of the present invention have been described in detail above in conjunction with the drawings, but the use of the technical solutions of the present invention is not limited to the various applications mentioned in the embodiments of this patent, and various structures and modifications can be easily referred to the technical solutions of the present invention Implemented in order to achieve the various beneficial effects mentioned in this article. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes made without departing from the gist of the present invention shall fall within the scope of the patent of the present invention.

Claims (14)

A method for reducing memory bank conflicts, which includes: Determine the binary addresses of multiple data that will cause bank conflicts when accessing the memory containing N banks in parallel; Determine the shift step size, which indicates the number of memory banks in which data in the memory bank will be moved, and is a value represented by n bits selected from the binary address of the data in the memory, where N=2^n, and both N and n are natural numbers; and after the data in the memory is moved by the respective shift steps, the multiple data in which the bank conflict occurs will no longer be in the same storage In the body; and The data in the memory is moved according to the shift step, wherein the row address value of the data in the memory inside the memory bank is unchanged. The method for reducing memory bank conflict according to claim 1, wherein: The shift steps of the plurality of data in the memory bank conflict are different from each other, so that after the data in the memory is moved by the shift step, the plurality of data in the memory bank conflict will be located at In different memory banks. The method for reducing memory bank conflict according to claim 1, wherein: The line spacing of the multiple data in which the memory bank conflict occurs is 2^i+j, where i and j are natural numbers, and 0≤j<2^i; When j=0, the shift step size is a value represented by consecutive n bits from the n+ith bit of the binary address of the data in the memory toward the higher bit direction. The method for reducing memory bank conflict according to claim 1, wherein: The line spacing of the multiple data in which the memory bank conflict occurs is 2^i+j, where i and j are natural numbers, and 0≤j<2^i; When j≠0, the shift step size is the value represented by consecutive n bits from the n+i or n+i+1 bit of the binary address of the data in the memory to the higher bit direction, or The value represented by discrete n bits in the binary address of the data in the memory. The method for reducing memory bank conflict according to any one of claims 1 to 4, wherein: The storage space of the memory is divided into multiple pages, and multiple sets of registers are provided to configure the pages to determine the shift step size for each page, and the number of registers is less than or equal to the number of pages. The method for reducing memory bank conflict according to claim 5, wherein: When the number of the registers is smaller than the number of pages, each register is mapped to multiple pages in a TLB manner. A device for reducing memory bank conflicts is characterized by comprising: The bank conflict determination unit is configured to determine a binary address of a plurality of data where bank conflicts occur when parallel access is made to a memory containing N banks; The shift step determination unit is configured to move the data in the memory with the respective shift steps, the multiple data in which the bank conflict occurs will no longer be located in the same bank, wherein, The shift step represents the number of memory banks to which data in the memory bank will be moved, and is a value represented by n bits selected from the binary address of the data in the memory, where N=2^n, And N and n are both natural numbers; and The shift unit is configured to move the data in the memory according to the shift step, wherein the row address value of the data in the memory inside the memory bank is unchanged. The apparatus for reducing memory bank conflict according to claim 7, wherein the shift step determination unit is further configured that the shift steps of the plurality of data in which the memory bank conflict occurs are different from each other After the data in the memory is moved by the shift step, the multiple data in which the bank conflict occurs will be located in different banks. The apparatus for reducing memory bank conflict according to claim 7, wherein: The line spacing of the multiple data in which the memory bank conflict occurs is 2^i+j, where i and j are natural numbers, and 0≤j<2^i; When j=0, the shift step size is a value represented by consecutive n bits from the n+ith bit of the binary address of the data in the memory toward the higher bit direction. The apparatus for reducing memory bank conflict according to claim 7, wherein: The line spacing of the multiple data in which the memory bank conflict occurs is 2^i+j, where i and j are natural numbers, and 0≤j<2^i; When j≠0, the shift step size is the value represented by consecutive n bits from the n+i or n+i+1 bit of the binary address of the data in the memory to the higher bit direction, or The value represented by discrete n bits in the binary address of the data in the memory. The apparatus for reducing memory conflict according to any one of claims 7-10, characterized in that The shift step determination unit is further configured to divide the storage space of the memory into multiple pages, and provide multiple sets of registers to configure the pages to determine the shift step size for each page, the register The number of is less than or equal to the number of pages. The apparatus for reducing memory bank conflict according to claim 11, wherein: When the number of the registers is smaller than the number of pages, each register is mapped to multiple pages in a TLB manner. A processor, characterized in that it includes a memory having a plurality of memory banks and a device for reducing memory bank conflicts according to claims 7-12. An electronic device characterized by comprising the processor according to claim 13.

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