CN109710309A - Methods to reduce bank conflicts - Google Patents
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Abstract
The present invention relates to a kind of methods for reducing bank conflict, carry out the binary address for multiple data that bank conflict can occur when concurrent access to the memory comprising N number of memory bank including determining；Determine shift step, it is value represented by the position n that selects from the binary address of the data in memory which, which indicates the memory bank number that is moved of data in memory bank, wherein N=2^n；Also, after the data in memory are with shift step movement, the data that bank conflict occurs be will not be positioned in same memory bank；And according to the data in shift step mobile memory, wherein row address value of the data in memory in memory bank is constant.The present invention is no longer at the data that may be clashed when access in same memory bank, reduces bank conflict, improves memory performance.
Description
Technical field
The present invention relates to a kind of methods for reducing bank conflict, belong to memory technology field.
Background technique
Recently, with the raising of the requirement of the ability of the processing data to processor, some processors are had been designed to
Concurrent access memory.In the case where memory has multiple memory banks (Bank), processor can be simultaneously to multiple storages
Body concurrent access is without clashing.
However, in some cases, processor may need concurrent access to be stored in the data in same memory bank, just
In normal situation, the address of data is fixed in memory, and bank conflict (bank conflict) will occur at this time, that is,
These data in same memory bank must be accessed one by one.For example, in memory example as shown in Figure 3, Mei Yilie
A memory bank is represented, i.e., there are Bank 0 ..., 8 memory banks of Bank 7, if accessing in the same memory bank in the memory
Multiple addresses data, such as 0,8,16,24 are clicked in Bank 0, if gray scale is shown in Fig. 3, then it must be with multiple
Period accesses Bank 0 one by one, and internal memory performance is caused to reduce.
Summary of the invention
It is an object of the invention to the designs of the micro-architecture of the LSU (Load/Store Unit, access unit) in processor
In, a kind of reduction bank conflict scheme is provided, to improve memory performance.
The first aspect of the present invention provides a kind of method for reducing bank conflict, comprising:
It determines and multiple data that bank conflict can occur when concurrent access is carried out to the memory comprising N number of memory bank
Binary address；
Determine shift step, shift step indicates that the data in memory bank are from memory by by mobile memory bank number
In data binary address in value represented by the position n that selects, wherein N=2^n, and N and n are natural number；Also, it deposits
After data in reservoir are moved with respective shift step, multiple data that bank conflict occurs will not be positioned at same deposit
Chu Tizhong；And
According to the data in shift step mobile memory, wherein row address of the data in memory inside memory bank
It is worth constant.
The present invention is no longer at the data that may be clashed when access in same memory bank, is subtracted by address mapping
Lack bank conflict, improves memory performance.
Further, the shift step that multiple data of bank conflict occur is all different each other, so that in memory
After data are with shift step movement, multiple data that bank conflict occurs will be located in different memory banks.Pass through
All data clashed are moved respectively in different bank, eliminate all conflicts as far as possible, sufficiently improve storage
The performance of device.
Further, the position n selected from the binary address of the data in memory can be n continuous.It may be selected
Ground, the position n selected from the binary address of the data in memory are also possible to n discontinuous.More specifically, depositing
The line-spacing of multiple data for storing up body conflict can be indicated with 2^i+j, wherein i and j is natural number, and 0≤j < 2^i；In j=0
When, shift step can be from the n-th+i of the binary address of the data in memory to continuous n of high-order direction
Represented value.In j ≠ 0, shift step can be the n-th+i or n+i+1 of the binary address of the data from memory
It rises to n institute discontinuous in the binary address of value represented by continuous n of high-order direction or the data in memory position
The value of expression.The selection of these different shift steps depends on the concrete condition of bank conflict and the configuration of software.
Further, it is possible to which the memory space of memory is divided into multiple pages, multiple groups register is provided to configure the page
To determine that shift step, the quantity of register are less than or equal to the quantity of the page respectively for each page.Further, it is depositing
When the quantity of device is less than the quantity of the page, each register mappings can be made to multiple pages in a manner of TLB.
The second aspect of the present invention provides a kind of device for reducing bank conflict, comprising:
Bank conflict determination unit is configured to determine to the memory progress concurrent access comprising N number of memory bank
When can occur bank conflict multiple data binary address；
Shift step determination unit, after being configured as making the data in memory to move with respective shift step, hair
Multiple data of raw bank conflict will not be positioned in same memory bank, wherein shift step indicates the data in memory bank
It will, by mobile memory bank number, be value represented by the position n that is selected from the binary address of the data in memory, wherein N
=2^n, and N and n are natural number；With
Shift unit is configured as according to the data in shift step mobile memory, wherein the number in the memory
It is constant according to the row address value inside memory bank.
Further, shift step determination unit is configured to, and the displacement of multiple data of bank conflict occurs
Step-length is all different each other, and after moving the data in memory with shift step, multiple data of bank conflict occur
It will be located in different memory banks.
Further, the position n selected from the binary address of the data in memory can be n continuous.It may be selected
Ground, the position n selected from the binary address of the data in memory be also possible to it is n discontinuous, and occur memory bank punching
The shift step of prominent data can be entirely different.
Further, shift step determination unit can be configured to, and the memory space of memory is divided into more
A page provides multiple groups register to configure the page to select shift step respectively for each page, and the quantity of register is small
In or equal to the page quantity.Further, when the quantity of register is less than the quantity of the page, each deposit is made in a manner of TLB
Device is mapped to multiple pages.
The third aspect of the present invention provides a kind of processor, the processor include have the memory of multiple memory banks with
And the device such as the offer of any implementation of aforementioned second aspect or second aspect.
The fourth aspect of the present invention provides a kind of electronic equipment, which can be various computers, server
Or various mobile devices, the processor provided including any implementation of such as aforementioned fourth aspect or fourth aspect.
The fifth aspect of the present invention provides a kind of computer program product, which includes program generation
Code, when the computer program product is executed by a controller, which executes any of aforementioned first aspect or first aspect
The method that implementation provides.
Several in address of the present invention by simply extracting data stored in memory carry out shifting function, will
The data that may be clashed are moved in different bank, reduce or eliminate bank conflict, improve memory performance.
Detailed description of the invention
Fig. 1 is the flow chart of the method for the reduction bank conflict of embodiment according to the present invention.
Fig. 2 is the schematic diagram of the system that can reduce bank conflict of embodiment according to the present invention.
Fig. 3 is the memory schematic diagram with eight memory banks of embodiment according to the present invention.
Fig. 4 is being shown using the memory after the data in address [5:3] mobile memory for embodiment according to the present invention
It is intended to.
Fig. 5 is being shown using the memory after the data in address [6:4] mobile memory for embodiment according to the present invention
It is intended to.
Fig. 6 is that value represented by the 6th, 5,3 for using address of embodiment according to the present invention is moved as shift step
The memory schematic diagram after data in dynamic memory.
Fig. 7 is the hardware realization schematic diagram of the storage address recombination of embodiment according to the present invention.
Specific embodiment
The present invention will be further described with attached drawing combined with specific embodiments below.It is understood that described herein
Specific embodiment is of the invention just for the sake of explaining, rather than limitation of the invention.In addition, for ease of description, in attached drawing only
Show part related to the present invention and not all structure or process.
The memory devices of dynamic random access memory (DRAM) or static random access memory (SRAM) etc.
It may include multiple memory banks (Bank), the equipment such as processor can carry out independent access to multiple memory banks.It is needed in processor
When concurrent access being wanted to store the data in same memory bank, it may occur that bank conflict, the present invention, can by address mapping
The data that can be clashed are moved in different bank, to reduce bank conflict.
According to one embodiment of present invention, a kind of method for reducing bank conflict is provided, as shown in Figure 1, including
Following steps:
Firstly, step S101, memory bank can be occurred when carrying out concurrent access to the memory comprising multiple memory banks by determining
The binary address of multiple data of conflict.For example, as shown in Figure 3, there are eight memory bank Bank 0, Bank
In the memory 300 of 1 ..., Bank 7, under normal circumstances, the data in 8 address concurrent accesses, eight memory banks can be passed through
Without clashing.However, if click multiple data for being stored in the same memory bank simultaneously, such as click simultaneously
Four addresses 0 in Bank0,8,16,24, as shown in grey in Fig. 3, i.e., bank conflict can occur, need while accessing
When data at 0,8,16,24,0,8,16,24 is the position that bank conflict can occur.
Then, step S102 determines that shift step, shift step indicate the memory bank that the data in memory bank are moved
Number, i.e. data will be by the several memory banks of movement, it is represented by the position n that selects from the binary address of the data in memory
Value, wherein N=2^n, and N and n are natural number；Also, it after the data in memory are with shift step movement, deposits
The data of storage body conflict will not be positioned in same memory bank；And step S103, according in shift step mobile memory
Data, wherein row address value of the data in memory inside memory bank is constant.
For example, for the memory 300 shown in Fig. 3, can will be clashed with shift step 0,8,16,24 turns of data
It moves, them is made to be located at different memory banks.Memory 300 includes 8 memory banks (i.e. N=8), for the every number wherein stored
For, mobile 7 Bank are at most needed, at least need mobile 0 Bank, then can indicate displacement step with three bit address
It is long, therefore, 3 can be selected from the address of the data stored in memory to indicate shift step (i.e. n=3).For example, root
According to one embodiment of the present of invention, can be used from the 3rd of address to value conduct represented by continuous 3 of high-order direction
Shift step, that is, address [5:3] is taken to carry out the data in mobile memory, that is, the address of the data stored in access to memory
In the 5th to the 3rd (address expression in, it is incremented by successively to the left usually using the lowest order of the rightmost side as the 0th, below
The digit of address indicates in this way), carry out the data in mobile memory according to this three value.So, in memory 300
In, the shift step of the first row data 0-7 is 000, i.e. the first row data do not move；The shift step of second row data 8-15
It is 001, that is, one mobile；Similarly, the shift step of other remaining data can be obtained.In the present embodiment, memory bank punching is sent
Prominent data have been moved in different bank, but row address value of the data inside memory bank does not change,
From the point of view of indicating from attached drawing, data are all to move in the same row, because shift step only changes the decoding of memory bank, and
The decoding of the row address inside memory bank can't be changed.
It is available shown in Fig. 4 as a result, the data 0,8,16,24 in memory are divided after shifting in the manner described above
Be not moved to different memory bank Bank 0, Bank 1, Bank 2, in Bank 3, in this way, processor can be in a week
It is interim to concurrently access 0,8,16,24.In Fig. 4, the row where the data that bank conflict occurs only is schematically illustrated,
Remaining row is omitted.
After it can be seen that in the comparison of Fig. 3 and Fig. 4 through above-mentioned mode mobile data, bank conflict is eliminated,
Data at 0,8,16,24 can be accessed concurrently in the same period, improve memory performance.
It should be noted that the selection of the above shift step be can according to different data access demands flexible configuration
, for example, in another embodiment, for the memory with 8 memory banks for the memory 300 being also similarly in Fig. 3,
Assuming that 0 in Bank 0, the data at 16,32,48 are clashed, can be in order to which above data is moved to different bank
Use to value represented by continuous 3 of high-order direction as shift step from the 4th of address, that is, take address [6:
4] value represented by comes the data in mobile memory, the shift step difference of the data at 0,16,32,48 as shift step
Be 000,001,010,011, thus the data at 0,16,32,48 will be moved respectively to memory bank Bank 0, Bank 1,
In Bank2, Bank 3, the result after displacement is as shown in Figure 5.
In addition, all colliding datas have all been individually displaced in different memory banks in two examples above, but
It is that this is that a kind of more excellent embodiment of the invention can not also all distinguish all colliding datas in some cases
It is moved in different bank, and only part colliding data is moved in different bank, eliminate part and conflict.For example,
In memory shown in Fig. 3, it is assumed that the data at 0,8,16,24 are needed while accessing, in addition to above-mentioned takes address [5:3] to come
Other than data in mobile memory, address [6:4] can also be taken to carry out the data in mobile memory, i.e., four clash
The shift step of data is respectively 000,000,001,001, and the result obtained after mobile is identical as Fig. 5, at this point, memory bank occurs
Data at 0, the 8,16,24 of conflict be individually displaced Bank 0, Bank 0, Bank 1, in Bank 1 so as in this way
The access of four data is two periods from four cycle reductions, equally reduces bank conflict, improves to a certain extent
Memory performance.
Above embodiment shows continuous several in the address for selecting data stored in memory to indicate
The case where shift step.In addition to this, discontinuous several be can choose in address also as shift step.
For example, in the example of the memory with 8 memory banks shown in Fig. 3, in one embodiment, if rushing
Prominent data are 8 in Bank 0, and the data at 16,32 can choose in order to which above data to be transferred in different bank
The data of 6th, 5,3 composition of address move the data into memory bank Bank 1, Bank0, Bank as shift step respectively
In 2, obtain as shown in FIG. 6 as a result, Fig. 6 only schematically illustrates part row, remaining row is omitted.Equally, in some realities
It applies in mode, also can choose the data of the 5th, 4,2 composition of address as shift step, or can choose 6,3,1
For the data of composition as shift step etc., it is different that these different selections depend on different data access demand brings
Bank conflict or different software configurations.
Although the different selections for shift step depend on different data access demand bring different banks
Conflict or different software configurations.But there can also be certain rule that can follow in selection.For example, memory bank occurs
Multiple data of conflict are in equidistant situation, and (in the present invention, line-spacing indicates the row ground of two data to the line-spacing of colliding data
Difference between the value of location) it can be indicated with 2^i+j, wherein i and j is natural number, and 0≤j < 2^i, at this point, in varied situations,
Shift step can be selected in the following manner.
In j=0, shift step can choose for from the n-th+i of the binary address of the data in memory to
Value represented by continuous n of high-order direction.For example, in bank conflict example shown in Fig. 3, at 0,8,16,24
The line-spacing of data is 1, that is, i=0, j=0, then continuous 3 positions (n=3) that the n-th+i=3 of selection rises, i.e. address [5:3] are moved
Data in dynamic memory, can effectively eliminate bank conflict；For another example, shown in fig. 5 by 0,16,32,48 points of colliding data
The example not being moved in different memory banks, the line-spacing of colliding data are 2, that is, i=1, j=0, then can choose n-th
The data in mobile memory are carried out in continuous 3 positions (n=3) that+i=4 rises, i.e. address [6:4], also can effectively eliminate memory bank punching
It is prominent.And in j ≠ 0, shift step can be from the n-th+i or n+i+1 of the binary address of the data in memory to
In the binary address of value represented by continuous n of high-order direction or the data in memory it is n discontinuous represented by
Value.For example, also with the example of the memory with 8 memory banks shown in Fig. 3, it is assumed that the data of bank conflict occur
It is 0,24,48, then line-spacing is 3, that is, i=1, j=1, then can choose the n-th+i=4 continuous 3 positions (n=3), i.e. address
[6:4] carrys out the data in mobile memory, at this point, the shift step of the data at 0,24,48 is respectively 000,001,011, number
According to will be individually displaced memory bank Bank 0, Bank 1, in Bank 3, can effectively eliminate bank conflict；It can also select
Continuous 3 positions (n=3) that the n-th+i+1=5 rises are selected, i.e., address [7:5] carrys out the data in mobile memory, at this point, at 0,24,48
The shift steps of data be respectively 000,000,001, data are individually displaced memory bank Bank 0, Bank 0, Bank 1
In, effectively reduce bank conflict；Also can choose it is several discontinuous, as long as can be the data of generation bank conflict
It is removed from same memory bank.
It should be noted that the selection mode of the shift step when line-spacing above with respect to colliding data is indicated with 2^i+j
It is merely illustrative, it is intended to illustrate a kind of possible embodiment of the invention, is not construed as limiting the invention, for
For those skilled in the art, it can adopt according to the thought of the present invention and select the position n in address as displacement in various manners
Step-length.
Meanwhile although the example of the memory including 8 memory banks, those skilled in the art are shown in figs. 3-5
It should be appreciated that the quantity of memory bank shown here and the structure of memory are used for the purpose of facilitating explanation, and do not constitute
Limitation of the present invention.The present invention can be applied equally in the memory of the memory bank with 4,16,32 etc. different numbers,
In the memory of the memory bank with different number, the address of not isotopic number can choose as shifted data, for example,
In memory with 32 memory banks, when bank conflict occurs, 5 in address can be chosen as shifted data, used
The data clashed are moved in different bank by the value for 5 expressions chosen, to reduce bank conflict.
Illustrate the hardware realization example of the storage address recombination of embodiment according to the present invention below with reference to Fig. 7.
According to one embodiment of present invention, it is assumed that memory is divided into N number of memory bank, and in general, N usually takes 2
Index, such as 2,4,8,16,32 etc., i.e. N=2^n can also take it to avoid the wasting of resources, but in some extreme environments
He is worth.
In general, n can be selected to carry out decoded bank selection from storage address.For example, as shown in fig. 7, can incite somebody to action
This signal is named as bank_sel (that is, bank_sel is the position n selected from address).In the absence of the present invention,
The value of Bank_sel can directly select the memory bank to be accessed, for example, bank_sel=0 indicates Bank 0, bank_sel=1
Indicate Bank 1 etc..
In an embodiment according to the present invention, shift step can be added to bank_sel, shift step can be used
Shift_sel is indicated, as shown in fig. 7, can all have N kind may every a line of such memory with N number of memory bank
Displacement situation (0,1,2 ..., N-1), that is, the value of shift_sel can be 0...N-1.So, the selection of memory bank just by
Bank_sel and shift_sel is codetermined.For example, bank_sel+shift_sel=0 indicates Bank 0, bank_sel+
Shift_sel=1 indicates Bank 1 etc..
As a result, as shown in fig. 7, the address of 5 bit fields can be defined, including bank selection (bank_sel), displacement
The line index (index_h and index_l) of step-length (shift_sel), byte offset (offset) and 2 bit fields, to generate
Decoded signal.Wherein, bank selection (bank_sel) and shift step (shift_sel) are selected for decoded bank, such as
It is upper described；Line index (index_h and index_l) is used to index the particular row of memory bank, i.e., is storing for index data
The row address in internal portion；Byte offset (offset) is for indexing the intracorporal offset of storage, for example, if memory bank is wide
Degree is 4 bytes, then byte offset (offset) should be 2.The position of each bit field can be configured by software, for example, can be with
It is whether adjacent that shift_sel and bank_sel is configured by software, if it is non-conterminous, such as situation as shown in Figure 7, this
When, the width of index_l is also possible to configurable.
After hardware configuration is good, it is important to how to obtain shift step shift_sel.
According to an embodiment of the invention, a kind of simple method is according to other in data access demand selection address
N are used as shift_sel.Bank_sel and shift_sel can be any n in address.For example, they can be with
It is n identical in address, or there are some overlappings.The position n in address can be selected as by software configuration according to application scenarios
shift_sel.Certainly, if being not desired to move, the value for meaning not move can also be configured.As previously mentioned, they can be with
Be it is n continuous in address, be also possible to n discontinuous.
Another more complicated but also more flexible method is to select different positions as shift_ in different address spaces
sel。
For example, in some embodiments, the memory space of memory can be divided into multiple pages (page), such as draw
It is divided into Page 1, each page of Page 2, Page 3 ... there can be the space of n KB (or other), can provide multiple groups and post
Storage configures these pages, to define different displacement modes respectively for each page.For example, can be selected in Page 1
The data come in mobile memory using address [5:3] are selected, select to come in mobile memory using address [6:4] in Page 2
Data, in Page 3 select using address the 5th, 4,2 data etc. come in mobile memory.
If that can be respectively each page with one group of register if.But in some cases, register group
Quantity can be less than the quantity of the address page, that is to say, that can be configured to be mapped to not in a manner of TLB by one group of register group
The same page, to save register.This mode is actually a special TLB (Translation Lookaside
Buffer, translation bypass buffering).Traditionally, TLB is generally used for being converted to virtual address into physical address, but herein, it can
To provide TLB to take different displacement modes to be transferred to the data in memory separately from a memory bank in the different pages
In one memory bank.
In the storage space for being divided into multiple pages, every page of size can be 2 index, that is, M=2^m.That
, the address in one page can be indicated with m.Assuming that entire address has k, then other k-m bit address are with may be constructed the page
Location.Multiple groups configuration register can be defined, and using this multiple groups configuration register as TLB.When accessing memory, it will be accessed
The page address of address be compared with the page address in all configuration register groups, if finding an identical value,
It so can be used group configuration to select shift_sel；And if not finding identical value, hardware will be into software request
It is disconnected, to require software to fill or replace TLB, or TLB entry is replaced automatically using the software pre-configured value in the 2nd TLB.It is soft
Part must assure that be not in that the configuration of two or more register groups corresponds to the same page.In this way, with small number of deposit
Device group can configure a large amount of page address spaces, realize ground in different page address spaces with different displacement modes
Location is transformed into another memory bank from a memory bank.
Hardware above, which is realized, merely exemplary illustrates that thought of the invention, concrete configuration therein are not constituted to this hair
Bright limitation, the present invention can by it is various it is suitable in a manner of implement.
According to another embodiment of the invention, a kind of system is additionally provided, which can realize in the processor, such as
Shown in Fig. 2, that is, processor may include the memory 20 with multiple memory banks and the device 10 for reducing bank conflict.
Wherein, device 10 includes bank conflict determination unit 101, is configured to determine that and carries out to the memory comprising N number of memory bank
The binary address of the data of bank conflict can occur when concurrent access；Shift step determination unit 103 is configured as making to deposit
After data in reservoir are moved with shift step, the data that bank conflict occurs be will not be positioned in same memory bank,
In, it is the binary address of the data from memory that shift step, which indicates the memory bank number that the data in memory bank are moved,
Value represented by the position n of middle selection, wherein N=2^n；With shift unit 105, it is configured as according to shift step mobile memory
In data, wherein row address value of the data in memory inside memory bank is constant；Device 10 can execute as shown in Figure 1
Reduction bank conflict method.
Here, illustrating, each unit mentioned in various embodiments of the invention is all logic unit, physically, one
A logic unit can be a physical unit, be also possible to a part of a physical unit, can also be with multiple physics lists
Member combination realize, the Physical realization of these logic units itself be not it is most important, these logic units are realized
The combination of function be only the key for solving technical problem proposed by the invention.In addition, in order to protrude innovation portion of the invention
Point, there is no draw the unit less close with technical problem relationship proposed by the invention is solved in various embodiments of the present invention
Enter, this does not indicate that there is no other units in each embodiment.
According to another embodiment of the invention, a kind of electronic equipment, including foregoing processor are additionally provided, this
Kind, which calculates equipment, can be various calculating equipment, such as laptop computer, desktop computer, work station, personal digital assistant, service
Device, blade server, mainframe and other computers appropriate；Or various forms of mobile devices, such as individual digital help
Reason, cellular phone, smart phone, portable digital-assistant (PDA), portable game machine, palm PC or tablet computer etc.；Or
The various smart machines of person, various wearable smart machines, intelligent appliance etc..
The embodiment of the present invention is elaborated above in conjunction with attached drawing, but the use of technical solution of the present invention is not only
The various applications referred in this patent embodiment are confined to, various structures and modification can be with reference to technical solution of the present invention easily
Ground is implemented, to reach various beneficial effects mentioned in this article.Within the knowledge of a person skilled in the art,
The various change made without departing from the purpose of the present invention should all belong to the invention patent covering scope.
Claims (14)
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| CN201811580102.XA CN109710309B (en) | 2018-12-24 | 2018-12-24 | Method for reducing memory bank conflict |
| PCT/CN2019/126552 WO2020135209A1 (en) | 2018-12-24 | 2019-12-19 | Method for reducing bank conflicts |
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| CN201811580102.XA CN109710309B (en) | 2018-12-24 | 2018-12-24 | Method for reducing memory bank conflict |
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| CN109710309B (en) | 2021-01-26 |
| WO2020135209A1 (en) | 2020-07-02 |
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