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WO2020054214A1 - Dispositif de génération d'informations d'instruction d'inspection, système d'inspection de substrat, procédé de génération d'informations d'instruction d'inspection et programme de génération d'informations d'instruction d'inspection - Google Patents

Dispositif de génération d'informations d'instruction d'inspection, système d'inspection de substrat, procédé de génération d'informations d'instruction d'inspection et programme de génération d'informations d'instruction d'inspection Download PDF

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Publication number
WO2020054214A1
WO2020054214A1 PCT/JP2019/028270 JP2019028270W WO2020054214A1 WO 2020054214 A1 WO2020054214 A1 WO 2020054214A1 JP 2019028270 W JP2019028270 W JP 2019028270W WO 2020054214 A1 WO2020054214 A1 WO 2020054214A1
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WO
WIPO (PCT)
Prior art keywords
conductive
instruction information
inspection
wiring
inspection instruction
Prior art date
Application number
PCT/JP2019/028270
Other languages
English (en)
Japanese (ja)
Inventor
雅也 椹木
Original Assignee
日本電産リード株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電産リード株式会社 filed Critical 日本電産リード株式会社
Priority to JP2020546728A priority Critical patent/JP7352840B2/ja
Priority to KR1020217011041A priority patent/KR102707838B1/ko
Priority to CN201980060230.8A priority patent/CN112689769B/zh
Publication of WO2020054214A1 publication Critical patent/WO2020054214A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits

Definitions

  • the present invention relates to an inspection instruction information generating apparatus that generates inspection instruction information for instructing an inspection position when inspecting a substrate, a substrate inspection system that performs an inspection using the inspection instruction information, an inspection instruction information generating method, and The present invention relates to an inspection instruction information generation program.
  • a substrate provided with a conductor that spreads in a plane (hereinafter, referred to as a plane conductor)
  • conductive portions such as pads, bumps, and wiring on the surface of the substrate and the plane conductor are electrically connected in the thickness direction of the substrate.
  • a board with a connected structure.
  • FIG. 22 is a conceptual schematic diagram showing a multi-layer substrate WB which is an example of a substrate provided with a planar conductor IP which is a conductor pattern which spreads planarly in an inner layer of the substrate.
  • the multilayer substrate WB shown in FIG. 22 has conductive portions PA and PB such as pads and wiring patterns provided on the substrate surface BS.
  • the conductive portions PA and PB are electrically connected to the planar conductor IP by vias RA and RB.
  • the planar conductor IP corresponds to the planar conductor.
  • a printed wiring board is laminated on both sides of a conductive metal plate as a base, and the formed substrate is peeled off from the base metal plate to form two printed wiring boards.
  • a method of forming a substrate There is a method of forming a substrate.
  • the substrate before the substrate is separated from the base metal plate (hereinafter, referred to as an intermediate substrate) has an aspect in which the metal plate is sandwiched between two substrates. .
  • Such an intermediate substrate is also called a carrier substrate.
  • FIG. 23 is a conceptual schematic diagram showing an example of such an intermediate substrate MB.
  • a substrate WB1 is provided on one surface of a metal plate MP
  • a substrate WB2 is provided on the other surface of the metal plate MP.
  • conductive portions PA1, PB1,..., PF1 such as pads and wiring patterns are provided on the substrate surface BS1 of the substrate WB1.
  • Conductive portions PA2, PB2,..., PF2 such as pads and wiring patterns are provided on a contact surface BS2 of the substrate WB1 with the metal plate MP.
  • the metal plate MP is, for example, a conductive metal plate having a thickness of about 1 mm to 10 mm.
  • the conductive portions PA1 to PF1 are electrically connected to the conductive portions PA2 to PF2 through vias RA to RF. Since the conductive portions PA2 to PF2 are in close contact with and conductive to the metal plate MP, the conductive portions PA1 to PF1 are electrically connected to the metal plate MP by the vias RA to RF.
  • the conductive part PA1 and the via RA form a pair, the conductive part PB1 and the via RB form a pair, and the conductive part and the via respectively form a pair.
  • the substrate WB2 has the same configuration as the substrate WB1, and a description thereof will be omitted.
  • the metal plate MP corresponds to a planar conductor.
  • the resistance values Ra, Rb of the vias RA, RB may be measured.
  • the resistance of the equivalent resistance of the planar conductor IP is represented by R1 to R4.
  • a measurement current I flows between the conductive portions PA1 and PB1, and a voltage V generated between the conductive portions PA1 and PB1. Is measured, and the resistance value is calculated as V / I.
  • V / I on the current path from the conductive part PA1 in the conductive portion PB1, two locations via RA, the resistance value of the RB Ra, and Rb, the resistance value R 1 of the sheet conductor IP resistor R1 Is obtained.
  • the conductive portions PA1 to PE1 are described in a straight line for the sake of space. However, in an actual substrate, the conductive portions PA1 to PE1 are two-dimensionally distributed on the substrate surface. Therefore, resistance against the electric current I 1 by selecting the pair of conductive parts PA1, PC1 for the measurement, the electric current I 2 to select another pair of conductive portions PB1, PD1, the current I 1, I 2 The current paths may overlap.
  • the inspection must be performed one by one between the pair of conductive parts so that the measurement current does not overlap, and the inspection time of the entire substrate increases.
  • An object of the present invention is to provide an inspection instruction information generating apparatus that generates inspection instruction information indicating an inspection location where the inspection time of a substrate can be easily reduced, a board inspection system including the inspection instruction information generating apparatus, and an inspection instruction information generating method. And an inspection instruction information generation program.
  • a conductor layer that is a layer provided with a conductive planar conductor that spreads in a plane, a substrate surface provided with a plurality of conductive portions, and the conductor layer A wiring layer which is a layer laminated between the substrate surface, a via connecting the wiring of the wiring layer and the plurality of conductive portions, and a wiring of the wiring layer and a planar conductor of the conductive layer.
  • a storage section for storing conductive structure information indicating how the planar conductor, the conductive section, the wiring, and the via are electrically connected to each other on a substrate including a via to be connected, and a wiring in the wiring layer
  • the conductive parts are selected as a first selected conductive part from each of the groups, and the selected plurality is selected.
  • the information indicating the first selected conductive part of the pair And an inspection instruction information generating unit for executing a test instruction information generating process of recording a test instruction information.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first A step of detecting a voltage between the selected conductive parts and inspecting vias and wiring of a current path between the first selected conductive parts of each pair based on the current and the voltage.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first Detecting a voltage between the selected conductive portions, and testing vias and wiring of a current path between each pair of the first selected conductive portions based on the current and the voltage; (c2) the test instruction information Between the second selected conductive portions forming a pair, the first current supply process performs a second current supply process of flowing current in a non-parallel manner, and the voltage between the paired second selected conductive portions is And based on the detected current and voltage, Via the current path between the conductive portion and executes the step of examining the wiring.
  • a board inspection system includes the above-described inspection instruction information generation device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit (C1) a first current flowing between a pair of first selected conductive portions with respect to a plurality of pairs of first selected conductive portions indicated by the inspection instruction information for each of the wiring layers in the order indicated by the information; The supply process is performed in parallel, the voltage between the pair of first selected conductive units is detected, and based on the current and the voltage, the via of the current path between the pair of first selected conductive units and A step of inspecting the wiring is performed, and if the result of the inspection in the step (c1) is defective, the step (c1) is not performed on the wiring layer having the next or subsequent order.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first Detecting a voltage between the selected conductive parts, and inspecting vias and wiring of a current path between the pair of first selected conductive parts based on the current and the voltage, and performing the step (c1).
  • the inspection instruction information generating method may further include a conductive layer that is a layer provided with a conductive planar conductor that spreads in a plane, a substrate surface provided with a plurality of conductive portions, and the conductive layer.
  • a wiring layer that is a layer laminated between a layer and the substrate surface; a via that connects the wiring of the wiring layer to the plurality of conductive parts; a wiring of the wiring layer and a planar conductor of the conductor layer
  • the wiring of the wiring layer is formed based on conductive structure information indicating how the planar conductor, the conductive portion, the wiring, and the via are electrically connected to each other on the substrate including a via that connects the wiring layer and the via.
  • a pair of the conductive portions is selected as a first selected conductive portion from each of the groups, and the selected plural pairs of the first selected conductive portions are selected.
  • Information as inspection instruction information. Including inspection instruction information generation step of executing the test instruction information generating process.
  • FIG. 1 is a schematic diagram conceptually showing a configuration of a board inspection system 1 according to an embodiment of the present invention.
  • FIG. 2 is a block diagram illustrating an example of an electrical configuration of a measurement unit illustrated in FIG. 1. It is sectional drawing which shows an example of the board
  • FIG. 2 is a plan view illustrating an example of a substrate to be inspected. 4 illustrates an example of conductive structure information D1 ′ obtained by simplifying the conductive structure information D1 of the substrate B illustrated in FIG. 3.
  • 6 is a diagram illustrating conductive structure information D1 ′′ that is obtained by expressing the conductive structure information D1 ′ illustrated in FIG. 5 in a tree structure.
  • 4 is a flowchart illustrating an example of an inspection instruction information generating method according to an embodiment of the present invention and an operation of an inspection instruction information generating apparatus using the inspection instruction information generating method.
  • 4 is a flowchart illustrating an example of an inspection instruction information generating method according to an embodiment of the present invention and an operation of an inspection instruction information generating apparatus using the inspection instruction information generating method.
  • 4 is a flowchart illustrating an example of an inspection instruction information generating method according to an embodiment of the present invention and an operation of an inspection instruction information generating apparatus using the inspection instruction information generating method.
  • 4 is a flowchart illustrating an example of a board inspection method according to an embodiment of the present invention and an operation of a board inspection apparatus using the board inspection method.
  • FIG. 5 is a flowchart illustrating an example of a first step in a test instruction information generating method according to an embodiment of the present invention. It is a flowchart which shows an example of the process regarding the branch connected to the root node in the test
  • FIG. 7 is an explanatory diagram illustrating another example of the conductive structure information D1 ′′ illustrated in FIG. 6.
  • FIG. 4 is an explanatory diagram illustrating another example of the substrate illustrated in FIG. 3.
  • FIG. 9 is an explanatory diagram in a table format showing an example of inspection instruction information;
  • 3 is a flowchart illustrating an example of an operation of the substrate inspection device illustrated in FIG. 3 is a flowchart illustrating an example of an operation of the substrate inspection device illustrated in FIG. 3 is a flowchart illustrating an example of an operation of the substrate inspection device illustrated in FIG.
  • It is a conceptual schematic diagram which shows an example of the board
  • 23 is an explanatory diagram for describing a measuring method for measuring a resistance value of a via and a planar conductor IP of the multilayer substrate WB illustrated in FIG. 22.
  • FIG. 22 is an explanatory
  • the board inspection system 1 shown in FIG. 1 includes an inspection instruction information generation device 3 and a board inspection device 2.
  • the inspection instruction information generating device 3 shown in FIG. 1 includes an inspection instruction information generating unit 31 and a storage unit 32.
  • the inspection instruction information generating apparatus 3 is configured using a computer such as a personal computer, for example, and executes a predetermined arithmetic processing (CPU (Central Processing Unit)), a RAM for temporarily storing data (Random Access Memory), A non-volatile storage device such as an HDD (Hard Disk Drive) and / or a flash memory, a communication circuit, and peripheral circuits thereof are provided.
  • the inspection instruction information generating device 3 functions as the inspection instruction information generating unit 31 by executing the inspection instruction information generating program according to the embodiment of the present invention stored in, for example, a nonvolatile storage device.
  • the storage unit 32 is configured using, for example, the above-described nonvolatile storage device.
  • the storage unit 32 stores the conductive structure information D1.
  • the conductive structure information D1 may be transmitted from the outside to the inspection instruction information generating device 3 via, for example, a communication circuit (not shown), and the transmitted conductive structure information D1 may be stored in the storage unit 32.
  • a communication circuit not shown
  • the conductive structure information D1 may be stored in the storage unit 32.
  • the conductive structure information D1 can be stored in the storage unit 32.
  • the conductive structure information D1 is information indicating how the planar conductor IP, the conductive portion P, the wiring W of each wiring layer L, and the via V of the substrate B described later are conductively connected.
  • As the conductive structure information D1 for example, so-called Gerber data used in the manufacture of a substrate and / or a netlist can be used.
  • the inspection instruction information generating unit 31 generates inspection instruction information D2 for instructing the board inspection apparatus 2 on a pair of conductive parts P to which a current is to flow for inspection based on the conductive structure information D1.
  • the inspection instruction information generating unit 31 may transmit the inspection instruction information D2 to the board inspection apparatus 2 via a communication circuit (not shown), for example.
  • the inspection instruction information generation unit 31 may write the inspection instruction information D2 on a storage medium. Then, the user may cause the board inspection apparatus 2 to read the inspection instruction information D2 from the storage medium. Details of the operation of the inspection instruction information generation unit 31 will be described later.
  • the board inspection apparatus 2 shown in FIG. 1 is an apparatus for inspecting a board B which is an inspection target board to be inspected.
  • the substrate B is, for example, an intermediate substrate or a multilayer substrate, and includes a printed wiring substrate, a film carrier, a flexible substrate, a ceramic multilayer wiring substrate, a semiconductor substrate such as a semiconductor chip and a semiconductor wafer, a package substrate for a semiconductor package, a liquid crystal display and a plasma display. Electrode plate, an intermediate substrate in the process of manufacturing these substrates, or a so-called carrier substrate.
  • the multilayer board WB shown in FIG. 22 and the intermediate board MB shown in FIG. 23 correspond to an example of the board B which is the board to be inspected.
  • the board inspection apparatus 2 shown in FIG. In the internal space of the housing 112, the substrate fixing device 110, the measuring unit 121, the measuring unit 122, the moving mechanism 125, and the control unit 20 are mainly provided.
  • the substrate fixing device 110 is configured to fix the substrate B at a predetermined position.
  • the measuring unit 121 is located above the substrate B fixed to the substrate fixing device 110.
  • the measurement unit 122 is located below the substrate B fixed to the substrate fixing device 110.
  • the measurement units 121 and 122 include measurement jigs 4U and 4L for bringing the probe into contact with a plurality of conductive units provided on the substrate B.
  • a plurality of probes Pr are attached to the measuring jigs 4U and 4L.
  • the measurement jigs 4U and 4L arrange and hold a plurality of probes Pr so as to correspond to the arrangement of the conductive parts to be measured provided on the surface of the substrate B.
  • the moving mechanism 125 appropriately moves the measuring units 121 and 122 in the housing 112 in accordance with a control signal from the control unit 20, and brings the probes Pr of the measuring jigs 4U and 4L into contact with each conductive unit of the substrate B.
  • the board inspection apparatus 2 may include only one of the measurement units 121 and 122, and the board B may be provided with a conductive unit on only one side. In addition, the board inspection apparatus 2 may perform measurement on both sides of the board to be inspected by using either one of the measurement units to turn the board to be inspected upside down.
  • the control unit 20 includes, for example, a CPU (Central Processing Unit) that executes predetermined arithmetic processing, a RAM (Random Access Memory) that temporarily stores data, and a ROM (Read Only Memory) that stores a predetermined control program. , A non-volatile storage unit 22 such as a hard disk drive (HDD), and peripheral circuits thereof.
  • the control unit 20 functions as the inspection processing unit 21 by executing, for example, a control program stored in the storage unit 22.
  • the measurement unit 121 shown in FIG. 2 includes a scanner unit 13, a plurality of measurement blocks 12, and a plurality of probes Pr.
  • the measuring section 122 is configured in the same manner as the measuring section 121, and thus the description thereof is omitted.
  • the measurement block 12 includes power supply units CS and CM, and a voltage detection unit VM.
  • the power supply units CS and CM are constant current circuits that output a current I according to a control signal from the control unit 20.
  • the power supply unit CS allows the current I to flow in a direction to be supplied to the scanner unit 13, and the power supply unit CM allows the current I to flow in a direction drawn from the scanner unit 13.
  • the voltage detection unit VM is a voltage detection circuit that measures a voltage and transmits the voltage value to the control unit 20.
  • the scanner unit 13 is a switching circuit configured using switching elements such as a transistor and a relay switch.
  • the scanner unit 13 includes current terminals + F and -F for supplying a current I for resistance measurement to the substrate B, and a voltage detection terminal + S and a voltage detection terminal + S for detecting a voltage generated between the conductive parts of the substrate B due to the current I. -S corresponding to the plurality of measurement blocks 12. Further, a plurality of probes Pr are electrically connected to the scanner unit 13.
  • the scanner unit 13 switches the connection relationship between the current terminals + F, -F and the voltage detection terminals + S, -S and the plurality of probes Pr according to a control signal from the control unit 20.
  • the power supply unit CS has one output terminal connected to the circuit ground and the other end connected to the current terminal + F.
  • the power supply section CM has one output terminal connected to the circuit ground and the other end connected to the current terminal -F.
  • the voltage detection unit VM has one end connected to the voltage detection terminal + S and the other end connected to the voltage detection terminal -S.
  • the scanner unit 13 is capable of electrically connecting the current terminals + F, -F and the voltage detection terminals + S, -S to an arbitrary probe Pr.
  • the scanner unit 13 allows the current I to flow between any of the conductive parts that the probe Pr is in contact with, and detects the voltage V generated between the conductive parts in accordance with the control signal from the control unit 20. It is made possible to measure by VM.
  • the power supply units CS and CM only need to be able to pass the current I to the substrate B via the scanner unit 13, and are not limited to an example in which one ends of the power supply units CS and CM are connected to the circuit ground.
  • the current loop may be formed by connecting one end of the power supply unit CS and one end of the power supply unit CM.
  • control unit 20 outputs a control signal to the scanner unit 13 to cause the plurality of power units CS and CM to cause the current I to flow between an arbitrary plurality of pairs of probes Pr, and an arbitrary plurality of pairs of probes Pr.
  • the voltage between them can be detected by the plurality of voltage detection units VM.
  • FIG. 3 also serves as an explanatory diagram illustrating the conductive structure information D1 of the substrate B.
  • the conductive structure information D1 is not necessarily data represented by an image, but in the following description, the structure represented by the conductive structure information D1 will be described with reference to the drawings for easy understanding.
  • the board B shown in FIG. 3 is a multilayer board in which five boards B1 to B5 are stacked.
  • One surface of the substrate B is a substrate surface F1
  • the other surface is a substrate surface F2.
  • the boundary between the substrates B1 and B2 is the wiring layer L1
  • the boundary between the substrates B2 and B3 is the wiring layer L2
  • the boundary between the substrates B3 and B4 is the conductor layer Lc
  • the boundary between the substrates B4 and B5 is the wiring layer L4.
  • Conductive portions P1 to P7 are provided on the substrate surface F1, and conductive portions P11 to P17 are provided on the substrate surface F2.
  • the conductive portions P1 to P7 and P11 to P17 are inspection points, such as pads, bumps, wirings, and electrodes, to which the probe Pr contacts.
  • the conductor layer Lc is provided with a planar conductor IP that is a conductor that spreads in a planar or mesh shape.
  • the wiring layer L1 is provided with wirings W11 and W12
  • the wiring layer L2 is provided with wirings W21 and W22
  • the wiring layer L4 is provided with wirings W41, W42 and W43 and the wirings W44 and W45.
  • the planar conductor IP may have a shape of a single sheet, that is, a shape that spreads in a planar shape, and a conductor pattern such as wiring is combined in a regular or irregular mesh shape (mesh shape) to form a single layer.
  • the conductor may have a shape that spreads in a plane as a whole.
  • FIG. 3 illustrates an example in which the planar conductor IP extends over substantially the entire area of the substrate B, but the planar conductor IP is not necessarily limited to an example that extends over substantially the entire area of the substrate B.
  • the planar conductor IP may be provided only in a partial region of the substrate B.
  • the wiring W may be provided in a region of the conductor layer Lc where the planar conductor IP of the substrate B is not provided.
  • the substrate B shown in FIG. 4 includes a planar conductor IPa and a planar conductor IPd which are electrically separated from each other.
  • the planar conductor IPa is used, for example, as an analog ground
  • the planar conductor IPd is used, for example, as a digital ground.
  • the substrate B may include a plurality of planar conductors IP insulated from each other.
  • the wirings W41, W42, and W43 are a single wiring in which the wiring W41, the wiring W42, and the wiring W43 of the wiring layer L4 are continuous, but for convenience of description, each part of the single wiring W41, W42, and W43 is wired. These are referred to as W41, a wiring W42, and a wiring W43.
  • the wirings W44 and W45 are a single wiring in which the wiring W44 and the wiring W45 are continuous, and the wiring W44 and the wiring W45 are parts of the single wirings W44 and W45, respectively.
  • the substrate B is provided with vias V11 to V17 penetrating the substrate B1, the vias V21 to V27 penetrating the substrate B2, the vias V31 to V36 penetrating the substrate B3, and penetrating the substrate B4. Vias V41 to V45 are provided, and vias V51 to V57 penetrating the substrate B5 are provided.
  • the conductive structure information stored in the storage unit 22 includes the conductive units P1 to P7, P11 to P17, wirings W11, W12, W21, W22, W41 to W45, vias V11 to V17, V21 to V27, V31 to V36, V41 to V45, V51 to V57, and information indicating how the planar conductor IP is conductively connected, for example, information indicating the connection relationship illustrated in FIG.
  • conductive portions such as the conductive portions P1 to P7 and P11 to P17 are collectively referred to as a conductive portion P
  • wires such as the wires W11, W12, W21, W22, and W41 to W45 are collectively referred to as a wire W.
  • V11 to V17, V21 to V27, V31 to V36, V41 to V45, V51 to V57, and the like are collectively referred to as a via V
  • the wiring layers L1, L2, and L4 are collectively referred to as a wiring layer L.
  • Each conductive part P is conductively connected to the planar conductor IP via the via V and the wiring W.
  • the wiring structure in which each conductive portion P is conductively connected to the planar conductor IP is generally used for connecting a circuit ground or a power supply pattern.
  • the substrate B may include wiring, pads, and the like that are not connected to the circuit ground and the power supply pattern.
  • each probe Pr of the measuring section 121 is brought into contact with the conductive sections P1 to P7 by the moving mechanism 125, and each probe Pr of the measuring section 122 is brought into contact with the conductive sections P11 to P17. Touched.
  • the measuring units 121 and 122 allow the current I to flow between any pair of conductive parts P and detect the voltage between the pair of conductive parts P.
  • the measuring units 121 and 122 may contact a current supply probe Pr and a voltage measurement probe Pr with one conductive portion P for resistance measurement by a so-called four-terminal resistance measurement method.
  • a current supply probe Pr and a voltage measurement probe Pr may contact a current supply probe Pr and a voltage measurement probe Pr with one conductive portion P for resistance measurement by a so-called four-terminal resistance measurement method.
  • one probe Pr serving both as a current supply and a voltage measurement may be brought into contact with one conductive part P.
  • the inspection processing unit 21 controls the measurement units 121 and 122 so that one of the pair of conductive units P selected as described later is supplied with the current I from the power supply unit CS (see FIG. 2), and the other is.
  • the current I is drawn from the power supply unit CM (see FIG. 2) to supply the current I between the conductive parts P and detect the voltage between the conductive parts P.
  • the substrate B To inspect.
  • the inspection processing unit 21 can perform a resistance measurement by a four-terminal resistance measurement method or a two-terminal resistance measurement method based on the current and the voltage, and can inspect the substrate B based on the resistance value.
  • the inspection processing unit 21 controls the measuring units 121 and 122 to perform the current supply and the voltage detection is simply described as the inspection processing unit 21 supplying the current and detecting the voltage. I do. Details of the operation of the inspection processing unit 21 will be described later.
  • FIGS. 5 and 6 are explanatory diagrams showing an example of the conductive structure information D1 changed in the process of executing the inspection instruction information generating method when generating the inspection instruction information corresponding to the substrate B shown in FIG.
  • FIGS. 5 to 14 the operation of the inspection instruction information generating device 3 that executes the inspection instruction information generating method based on the inspection instruction information generating program according to one embodiment of the present invention will be described.
  • the inspection instruction information generating unit 31 performs a process of simplifying the connection structure indicated by the conductive structure information D1 as a pre-process before grouping the conductive units P of the substrate B. Specifically, when the wirings W of the plurality of wiring layers L are connected in parallel, the inspection instruction information generation unit 31 places the wirings W connected in parallel to the substrate surface F1 of the respective wirings W most.
  • the conductive structure information D1 is duplicated and changed so as to replace with the close wiring W, and the conductive structure information D1 'is generated (step S1: (d) step).
  • the wirings W11 and W21 of the plurality of wiring layers L1 and L2 are connected in parallel by vias V21 and V22.
  • the two wires W11 and W21 are replaced with one of the wires W11 and W21 closest to the substrate surface F1, and the conductive structure The information D1 'is generated.
  • the data since one end of the via V22 is open, the data may be treated as not having the via V22. This simplifies the wiring structure of the substrate B, and facilitates subsequent processing.
  • the inspection instruction information generating unit 31 sets the vias V or the columns of the vias V connected in parallel to each other.
  • the conductive structure information D1 ' is changed so as to be replaced with one or one row of vias (step S2: (e) step).
  • the vias V24 and V33 are connected in series to form a row, and the vias V25 and V34 are connected in series to form a row.
  • the row of vias V24 and V33 and the row of vias V25 and V34 are connected in parallel by the wiring W12 and the planar conductor IP.
  • via V32 and via V33 are connected in parallel by wiring W22 and planar conductor IP.
  • the columns of the vias V24 and V33 and the columns of the vias V25 and V34 are changed to one of the columns, for example, the columns of the vias V24 and V33, for the conductive structure information D1 '.
  • the replacement is performed by replacing the via V32 and the via V33 with one via V, for example, the via V32.
  • the vias V41 and V42 are connected in parallel by the series wiring of the wirings W41, W42 and W43 and the planar conductor IP.
  • the vias V41 and V42 are replaced with one via V, for example, the via V41 on the conductive structure information D1.
  • vias V43, V44, V45 are connected in parallel by the wires W44, W45 and the planar conductor IP.
  • the vias V43, V44, and V45 are replaced with one via V, for example, the via V43 for the conductive structure information D1 '. This simplifies the wiring structure of the substrate B, and facilitates subsequent processing.
  • the inspection instruction information generation unit 31 does not necessarily need to execute steps S1 and S2, and sets the conductive structure information D1 in the data format representing the actual wiring structure of the substrate B shown in FIG. May be performed.
  • the inspection instruction information generating unit 31 converts the data structure of the conductive structure information D1 'into a tree structure (step S3: (m) step).
  • the conductive structure information D1 'converted into the tree structure is referred to as conductive structure information D1' '.
  • one wiring W is represented by one node N
  • the planar conductor IP is represented by a root node NR
  • the via V is formed between the conductive part P and the node.
  • Or a branch M connecting nodes are shown in the conductive structure information D1 ′′.
  • the inspection instruction information generation unit 31 does not necessarily need to execute step S3, and executes the subsequent processing using the conductive structure information D1 and the conductive structure information D1 ′ in a data format representing the wiring structure of the substrate B. Is also good.
  • the processing for the node N is equivalent to the processing for the wiring W corresponding to the node N
  • the processing for the root node NR is equivalent to the processing for the planar conductor IP
  • the processing for the branch M is The processing is the same as the processing for the wiring W corresponding to the node N.
  • the node N11 corresponds to the wiring W11 (W21)
  • the node N12 corresponds to the wiring W12
  • the node N21 corresponds to the wiring W22
  • the node N41 corresponds to the wiring W22.
  • the node N42 corresponds to the wirings W44, W45, corresponding to the wirings W41, W42, W43.
  • Branch M11 is via V11 (V21)
  • branch M12 is via V12 (V22)
  • branch M13 is via V14
  • branch M14 is via V15
  • branch M22 is via V24 (V25)
  • branch Mr1 is vias V21, V31, and branch.
  • Mr2 is via V32 (V33)
  • branch Mr3 is via V16
  • V26 is via V35
  • branch Mr4 is via V17
  • V27 is via V36
  • branch M41 is via V51
  • branch M42 is via V52
  • branch M43 is via V53
  • branch M44 is via.
  • V54 branch M45 corresponds to via V55
  • branch M46 corresponds to via V56
  • branch M47 corresponds to via V57
  • branch Mr5 corresponds to via V41 (V42)
  • branch Mr6 corresponds to via V43 (V44, V45).
  • the inspection instruction information generation unit 31 selects the wiring layer L1 closest to the substrate surface F1 as the first selection layer LL1 and the wiring layer L4 closest to the substrate surface F2 as the second selection layer LL2 (Step S4: ( f) Step).
  • the processing of steps S4 to S27 and S101 to S501 corresponds to an example of the inspection instruction information generation processing.
  • inspection instruction information generation unit 31 executes the first step (Step S5).
  • inspection instruction information generating section 31 performs, based on conductive structure information D1 ′′, conductive section P of substrate surface F1 that is electrically connected to each other via node N (wiring W) of first selection layer LL1. These are grouped together (step S101: step (a) of step (f)).
  • the first selection layer LL1 is the wiring layer L1
  • the conductive portions P1 and P2 which are conductive via the node N11 of the first selection layer LL1 are grouped.
  • the conductive portions P4 and P5 that conduct through the node N12 of the first selection layer LL1 are grouped.
  • the inspection instruction information generation unit 31 selects two conductive units from among the conductive units P included in each group as a pair of first selected conductive units, It is recorded in the inspection instruction information D2 in association with the first selection layer LL1 (step S102: step (b) of step (f)).
  • the first selection conductive part is information indicating conductive parts (inspection locations) that can be inspected in parallel.
  • the conductive parts P1 and P2 from the group of the conductive parts P1 and P2 corresponding to the wiring layer L1, and the conductive parts P4 and P5 from the group of the conductive parts P4 and P5 are selected.
  • a pair of the conductive part P1 and the conductive part P2 is described as a conductive part pair P1, P2.
  • the inspection instruction information generating unit 31 Two conductive portions P including the conductive portion P not selected as the first selected conductive portion are selected as a pair of second selected conductive portions, and are recorded in the inspection instruction information D2 in association with the first selected layer LL1 (step).
  • the second selected conductive part is information indicating a conductive part (inspection location) to be inspected non-parallel to the first selected conductive part.
  • Step S104 Step (a) of Step (f)).
  • the second selection layer LL2 is the wiring layer L4
  • the conductive portions P11, P12, and P13 that conduct through the node N41 of the second selection layer LL2 in the tree-structured conductive structure information D1 ′′ illustrated in FIG. , P14 are grouped, and the conductive portions P15, P16, P17 conducting through the node N42 of the second selection layer LL2 are grouped.
  • the inspection instruction information generation unit 31 selects two conductive parts from the conductive parts P included in each group as a pair of first selected conductive parts. Is recorded in the inspection instruction information D2 in association with the second selection layer LL2 (step S105: step (b) of step (f)).
  • any of the conductive parts P11, P12, P13, and P14 for example, any conductive part P11, P12, and any one of the conductive parts P15, P16, and P17, for example, any conductive part P15 , P16 are selected.
  • step S104 when there is a group having a conductive part P not selected as the first selected conductive part among the groups grouped in step S104, the inspection instruction information generating unit 31 Two conductive portions P including the conductive portion P not selected as the first selected conductive portion are selected as a pair of second selected conductive portions, and are recorded in the inspection instruction information D2 in association with the second selected layer LL2 (step S106: The (b) step of the (f) step), the first step is finished, and the processing shifts to the step S7 (FIG. 7).
  • the inspection instruction information generating unit 31 selects the conductive part pair P13, P14 and the conductive part pair P16, P17 as the second selected conductive part.
  • the inspection instruction information generation unit 31 checks the flag Fip1, which is a control flag for controlling the processing (step S7).
  • step S7 When the flag Fip1 is 1 (YES in step S7), the flag Fip1 is already set to 1 in step S12 to be described later, and each wiring layer L on the substrate surface F1 side of the conductor layer Lc and the substrate surface F1 side of the conductor layer Lc. Means that the generation of the inspection instruction information D2 corresponding to. Has already been completed. Therefore, the inspection instruction information generation unit 31 proceeds to step S17 (FIG. 9) without executing steps S11 to S16.
  • step S7 the inspection instruction information generation unit 31 proceeds to step S11 (FIG. 8), and the conductor layer Lc is located on the side of the first selection layer LL1 that is away from the substrate surface F1. It is checked whether or not they are adjacent (step S11).
  • step S11 If the conductor layer Lc is adjacent to the first selection layer LL1 on the side away from the substrate surface F1 (YES in step S11), the inspection instruction information generation unit 31 sets the flag Fip1 to 1 (step S12), The process proceeds to step S301 (FIG. 12) in order to select a conductive part P used for inspection of the via V connected to the substrate surface F1 side of the conductor IP.
  • the inspection instruction information generation unit 31 determines whether the first selection layer LL1 has the substrate surface F1. Is selected as a new first selection layer LL1 (step S13: step (g)). Thus, steps S14 to S16 are executed with the new first selection layer LL1 as a processing target.
  • the first selection layer LL1 is the wiring layer L1.
  • the conductor layer Lc is not adjacent to the wiring layer L1 on the side away from the substrate surface F1 (NO in step S11), and the wiring layer L2 adjacent to the wiring layer L1 on the side away from the substrate surface F1 is a new first layer.
  • One selection layer LL1 is obtained (step S13).
  • the inspection instruction information generation unit 31 is connected to the node N of the first selection layer LL1 on the side away from the root node NR of the one node N corresponding to each of the nodes N.
  • One of the branches M (via V) is electrically connected on the opposite side of the node N, that is, one conductive portion P of the substrate surface F1 that is conductive is selected.
  • the inspection instruction information generation unit 31 groups the selected conductive units P for each corresponding node N (step S14: (g1) step).
  • the node N21 is provided in the wiring layer L2 which is the first selection layer LL1.
  • Branch M21 and branch M22 are connected to node N21.
  • a conductive portion P3 as a conductive portion P on the substrate surface F1 that is directly or indirectly conductive to the side of the branch M21 opposite to the node N21. Therefore, the conductive part P3 corresponding to the branch M21 is selected.
  • Conductive portions P4 and P5 are provided as conductive portions P on the substrate surface F1 that are directly or indirectly conductive to the side of the branch M22 opposite to the node N21. Any one of the conductive portions P4 and P5, for example, the conductive portion P4 is selected as the conductive portion P corresponding to the branch M22. Thereby, conductive portions P3 and P4 are grouped corresponding to node N21.
  • the inspection instruction information generation unit 31 selects any two conductive parts from the conductive parts P included in each group as a pair of first selected conductive parts. Then, it is recorded in the inspection instruction information D2 in association with the first selection layer LL1 (Step S15: Step (b) of the step (g2)).
  • two conductive portions P3 and P4 are selected as a pair of first selected conductive portions from among the conductive portions P3 and P4 grouped in step S14.
  • conductive portions P1 and P2 as the conductive portions P on the substrate surface F1 that conducts directly or indirectly to the side opposite to N21. Any one of the conductive portions P1 and P2, for example, the conductive portion P1 is selected as the conductive portion P corresponding to the branch M23. Then, conductive portions P1, P3, and P4 obtained by adding conductive portion P1 to conductive portions P3 and P4 described above are grouped corresponding to node N21.
  • step S15 two conductive portions, for example, the conductive portions P1 and P3 are selected from the conductive portions P1, P3 and P4 as a pair of first selected conductive portions.
  • step S14 when there is a group having the conductive part P not selected as the first selected conductive part among the groups grouped in step S14, the inspection instruction information generating unit 31 Two conductive portions P including the conductive portion P not selected as one selected conductive portion are selected as a pair of second selected conductive portions, and are recorded in the inspection instruction information D2 in association with the first selected layer LL1 (step S16). : (G2) step (b) step), and then proceeding to step S17 (FIG. 9).
  • step S14 when there is no group having the conductive part P not selected as the first selected conductive part among the groups grouped in step S14, the inspection instruction information generating unit 31 proceeds to step S17.
  • the inspection instruction information generation unit 31 checks a flag Fip2 which is a control flag for controlling the processing (step S17).
  • step S17 If the flag Fip2 is 1 (YES in step S17), the flag Fip2 is already set to 1 in step S19 to be described later, and each wiring layer L on the substrate surface F2 side of the conductor layer Lc and the substrate surface F2 side of the conductor layer Lc. Means that the generation of the inspection instruction information D2 has already been completed. Therefore, the inspection instruction information generator 31 proceeds to step S26 (FIG. 10) without executing steps S18 to S24.
  • step S17 the inspection instruction information generation unit 31 proceeds to step S18, and determines whether the conductor layer Lc is adjacent to the second selection layer LL2 on the side away from the substrate surface F2. It is checked whether or not it is (step S18).
  • the inspection instruction information generation unit 31 sets the flag Fip2 to 1 (step S19), and The process proceeds to step S401 (FIG. 13) in order to select a conductive portion P used for inspection of the via V connected to the substrate surface F2 side of the conductor IP.
  • step S19 the routine goes to step S401 (FIG. 13).
  • step S401 the inspection instruction information generation unit 31 determines, for each branch M (via V) connected to the substrate surface F2 side of the root node NR (planar conductor IP), the root node NR Is electrically connected to the opposite side, that is, by selecting one conductive portion P to be conductive, the selected conductive portion P is grouped as a conductive portion corresponding to the substrate surface F2 side of the root node NR (step S401). : (H) step).
  • the branches Mr5 and Mr6 are connected to the substrate surface F2 of the root node NR.
  • the conductive portions P that conduct to the branch Mr5 include the conductive portions P11, P12, P13, and P14.
  • the conductive portions P that conduct to the branch Mr6 include conductive portions P15, P16, and P17. Therefore, in step S401, any one of the conductive parts P11, P12, P13, and P14, for example, the conductive part P11 is selected, and any one of the conductive parts P15, P16, and P17, for example, the conductive part P15 Is selected. Thereby, the conductive portions P11 and P15 are grouped.
  • the inspection instruction information generating unit 31 selects two conductive portions P from the conductive portions P grouped in step S401 as a pair of first selected conductive portions, and selects the root node NR on the substrate surface F2 side. It is recorded in the inspection instruction information D2 in association with each other (step S402: (h) step).
  • step S402 two conductive parts P are selected as a pair of first selected conductive parts from the conductive parts P11 and P15 grouped in step S401.
  • Step S401 when there is a group having a conductive part P not selected as the first selected conductive part among the groups grouped in step S401, the inspection instruction information generating unit 31 Two conductive parts P including the conductive part P not selected as one selected conductive part are selected as a pair of second selected conductive parts, and are recorded in the inspection instruction information D2 in association with the substrate surface F2 side of the root node NR. (Step S403), the process proceeds to step S26 (FIG. 10).
  • the inspection instruction information generating part 31 directly performs the processing in step S26 (FIG. Go to 10).
  • the inspection instruction information generation unit 31 selects a plurality of pairs of conductive parts P so as to include all the conductive parts P selected in step S401, and selects a plurality of pairs of first conductive parts P.
  • the selected conductive portion may be recorded in the inspection instruction information D2 in association with the substrate surface F2 side of the root node NR.
  • a plurality of pairs of conductive parts P are selected so as to include all the conductive parts P selected in step S401, and the plurality of pairs of first selected conductive parts are selected as the root node NR.
  • the inspection instruction information generating unit 31 determines whether the second selection layer LL2 has the substrate surface F2. Is selected as a new second selection layer LL2 (step S21: step (g)). Thus, steps S22 to S24 are executed with the new second selection layer LL2 as a processing target.
  • the inspection instruction information generating unit 31 is connected to the node N of the second selection layer LL2 on the side away from the root node NR of one of the nodes N.
  • One of the branches M (via V) is electrically connected on the side opposite to the node N, that is, one conductive portion P of the substrate surface F2 that is conductive is selected.
  • the inspection instruction information generating unit 31 groups the selected conductive units P for each corresponding node N (step S22: (g1) step).
  • the inspection instruction information generation unit 31 selects any two conductive parts from the conductive parts P included in each group as a pair of first selected conductive parts. Then, it is recorded in the inspection instruction information D2 in association with the second selection layer LL2 (Step S23: Step (b) of the step (g2)).
  • the inspection instruction information generating unit 31 Two conductive parts P including the conductive part P not selected as one selected conductive part are selected as a pair of second selected conductive parts, and are recorded in the inspection instruction information D2 in association with the second selected layer LL2 (Step S24). : (G2) step (b) step), and then proceeding to step S26 (FIG. 10).
  • step S22 when there is no group having the conductive part P not selected as the first selected conductive part among the groups grouped in step S22, the inspection instruction information generating unit 31 keeps step S23 to step S26 (FIG. Go to 10).
  • the inspection instruction information generation unit 31 shifts the processing from step S23 to step S26 (FIG. 10) without recording the inspection instruction information D2.
  • the inspection instruction information generator 31 checks whether or not inspection instruction information D2 corresponding to all the wiring layers L and the substrate surfaces F1 and F2 of the planar conductor IP has been generated (step S26).
  • step S26 When the inspection instruction information D2 corresponding to all the wiring layers L and the substrate surfaces F1 and F2 of the planar conductor IP has been generated (YES in step S26), the process proceeds to step S27. On the other hand, when the wiring layer L or the planar conductor IP on the substrate surfaces F1 and F2 side where the corresponding inspection instruction information D2 has not yet been generated remains (NO in step S26), the process proceeds to step S11 (FIG. 8). I do.
  • step S11 the inspection instruction information generating unit 31 checks whether or not the conductor layer Lc is adjacent to the first selection layer LL1 on the side away from the substrate surface F1 (step S11).
  • the first selection layer LL1 is now the wiring layer L2. Since the conductor layer Lc is adjacent to the wiring layer L2 on the side away from the substrate surface F1 (YES in step S11), the inspection instruction information generation unit 31 sets the flag Fip1 to 1 (step S12), and proceeds to step S301. The processing shifts to (FIG. 12).
  • step S301 the inspection instruction information generating unit 31 conducts the conduction on the opposite side to the root node NR for each branch M (via V) connected to the substrate surface F1 side of the root node NR (plane conductor IP).
  • the selected conductive part P is grouped as a conductive part corresponding to the substrate surface F1 side of the root node NR (step S301: (h) step).
  • the branches Mr1, Mr2, Mr3, and Mr4 are connected to the substrate surface F1 side of the root node NR.
  • the conductive portions P that conduct to the branch Mr1 include the conductive portions P1 and P2.
  • the conductive portions P that conduct to the branch Mr2 include the conductive portions P3, P4, and P5.
  • the conductive portion P that is electrically connected to the branch Mr4 includes a conductive portion P7.
  • any one of the conductive portions P1 and P2, for example, the conductive portion P1 is selected, and any one of the conductive portions P3, P4, and P5, for example, the conductive portion P3 is selected. Further, conductive portions P6 and P7 are selected. Thereby, the conductive portions P1, P3, P6, and P7 are grouped.
  • the inspection instruction information generating unit 31 selects any two conductive portions P from the conductive portions P grouped in step S301 as a pair of first selected conductive portions, and selects the substrate surface F1 of the root node NR. It is recorded in the inspection instruction information D2 in association with the side (step S302: (h) step).
  • any two conductive portions P for example, the conductive portions P1 and P3 are selected from the conductive portions P1, P3, P6, and P7 grouped in step S301 as a pair of first selected conductive portions. Selected.
  • Step S301 when there is a group having the conductive part P not selected as the first selected conductive part among the groups grouped in step S301, the inspection instruction information generating unit 31 Two conductive parts P including the conductive part P not selected as one selected conductive part are selected as a pair of second selected conductive parts, and recorded in the inspection instruction information D2 in association with the substrate surface F1 side of the root node NR. (Step S303), the process proceeds to Step S17 (FIG. 9).
  • step S302 among the conductive portions P1, P3, P6, and P7 grouped in step S301, the conductive portions P6 and P7 are not selected as the first selected conductive portions.
  • the conductive portions P6 and P7 are selected as a pair of second selected conductive portions (step S303).
  • step S303 for example, when the conductive parts included in the group are three conductive parts P1, P3, and P6, and only one conductive part P6 is not selected as the first selected conductive part, the conductive part P6 And one of the conductive portions P1 and P3 is selected as a pair of second selected conductive portions.
  • the inspection instruction information generating unit 31 includes a plurality of pairs of conductive units P so as to include all the conductive units P selected in step S301. May be selected and recorded in the inspection instruction information D2 in association with the substrate surface F1 side of the root node NR as a plurality of pairs of first selected conductive portions.
  • the inspection instruction information generating unit 31 pairs the conductive units P1, P3 and the conductive units P6, P7 from the conductive units P1, P3, P6, P7 grouped in step S301, and , P3 and the conductive portions P6, P7 may be recorded in the inspection instruction information D2 in association with the substrate surface F1 side of the root node NR as a plurality of pairs of first selected conductive portions.
  • step S17 since the flag Fip2 is now 1, the inspection instruction information generating unit 31 shifts the processing to step S26 (FIG. 10).
  • step S26 since the processes of steps S5 to S403 have been performed on all the wiring layers L and the substrate surfaces F1 and F2 of the planar conductor IP (YES in step S26), further leakage of the inspection location is prevented. In order to do so, a second step is executed (step S27).
  • inspection instruction information generation unit 31 searches for a wiring W that is not sandwiched between any pair of the first and second selected conductive units selected in steps S1 to S403 (step S501: (J) Step).
  • a pair of the second selected conductive portions a pair of conductive portions P6 and P7, a pair of conductive portions P13 and P14, and a pair of conductive portions. P16 and P17 are selected.
  • the conductive portions P1 to P7 are continuously selected as a first and a second selected conductive portion in a daisy chain, any one of the pair of the first and the second selected conductive portions is selected. There is no wiring W that is not sandwiched.
  • the conductive portion pair P11, P12 and the conductive portion pair P13, P14 are discontinuous.
  • FIG. 15 is an explanatory diagram for explaining the second step.
  • FIG. 15 is a partially enlarged view of the vicinity of the conductive portions P11 to P14 in FIG.
  • the pair of conductive portions P11 and P12 and the pair of conductive portions P13 and P14 are selected as the pair of the first and second selected conductive portions.
  • the set pair P12, P13 is not selected.
  • the wiring W42 illustrated in FIG. 15 is not sandwiched between any of the pair of the first and second selection conductive units.
  • the inspection instruction information generation unit 31 checks the presence or absence of the corresponding wiring W (step S503), and if there is the corresponding wiring W (YES in step S503), proceeds to step S504. On the other hand, if there is no corresponding wiring W (NO in step S503), the inspection instruction information generating unit 31 ends the processing. In the example shown in FIG. 6, the wiring W42 corresponds.
  • step S ⁇ b> 504 the inspection instruction information generation unit 31 connects the conductive part P to one end of the corresponding wiring W without passing through the wiring W and connects to the other end of the wiring W without passing through the wiring W.
  • the conductive part P to be inspected is recorded in the inspection instruction information D2 as a pair of third selected conductive parts to be inspected non-parallel to the first selected conductive part (step S504: (k) step).
  • a conductive portion P12 that conducts to one end T1 of the corresponding wiring W42 without passing through the wiring W42, and a conductive portion P13 that conducts to the other end T2 of the wiring W42 without passing through the wiring W42. are selected as a pair of third selection conductive parts (step S504).
  • the inspection instruction information generation unit 31 checks whether or not the substrate B includes a plurality of conductor layers Lc (step S505). If there is a plurality of conductor layers Lc (YES in step S505), the process proceeds to step S506. I do. On the other hand, if there is no plurality of conductor layers Lc (NO in step S505), the inspection instruction information generating unit 31 ends the processing.
  • step S506 the inspection instruction information generation unit 31 checks whether there is a via V connecting the planar conductors IP of the plurality of conductor layers Lc (step S506). If there is the via V (YES in step S506), the process proceeds to step S507. On the other hand, if the via V does not exist (NO in step S506), the inspection instruction information generating unit 31 ends the processing.
  • the substrate B shown in FIG. 17 includes two conductor layers Lc, and is provided with a via Vc for connecting the planar conductors IP of the two conductor layers Lc.
  • a via Vc for connecting the planar conductors IP of the two conductor layers Lc.
  • step S507 the inspection instruction information generation unit 31 inspects one of the conductive parts P on the substrate surface F1 and one of the conductive parts P on the substrate surface F2 non-parallel to the first selected conductive part. It is recorded in the inspection instruction information D2 as a pair of fourth selection conductive parts to be performed (step S507: (l) step), and the processing ends.
  • the board inspection apparatus 2 can inspect the via Vc by inspection based on the inspection instruction information D2.
  • the conductive portion P on the substrate surface F1 and the conductive portion P on the substrate surface F2 correspond to the inspection target. Only the fourth selected conductive portion for inspecting the via Vc is selected as the pair of conductive portions P, and it is minimized to select the pair of conductive portions P from both surfaces of the substrate B. .
  • the conductive portion P straddling between the two surfaces of the substrate B is the minimum fourth selection conductive portion necessary for inspecting the via Vc, and the other is the one surface of the substrate B Is a pair of the first, second, and third selected conductive portions, the effect of noise when an inspection based on the inspection instruction information D2 is performed is reduced.
  • the probe Pr of the measuring jig 4U When a via is inspected between both surfaces of the substrate B, the probe Pr of the measuring jig 4U is brought into contact with the conductive portion P of the substrate surface F1 of the substrate B, and the measuring jig is brought into contact with the conductive portion P of the substrate surface F2 of the substrate B. It is necessary to bring 4 L probe Pr into contact. At this time, if any one of the probe Pr of the measurement jig 4U and the probe Pr of the measurement jig 4L has a poor contact, it is not possible to specify which probe Pr caused the poor contact.
  • both probes Pr are once separated from the substrate B, and both probes Pr are brought into contact with the substrate B again, and the inspection is performed again. Such a re-inspection needs to be repeated a number of times until both probes Pr that come into contact with both surfaces of the substrate B both normally contact the conductive portion P.
  • the inspection time is extended and the conductive portion P is easily damaged.
  • steps S1 to S507 the inspection of the conductive portions P extending over both surfaces of the substrate B is minimized, and most of the inspections are performed between the conductive portions P provided on one surface of the substrate B. It is easy to reduce re-inspection due to failure and reduce the possibility that the conductive portion P is damaged.
  • the inspection instruction information generating device 3 can generate the inspection instruction information D2 by the processes of steps S1 to S507. Also, according to steps S1 to S507, the order recorded in the inspection instruction information D2 for each corresponding substrate surface corresponds to the order of the conductive portion pairs in which the substrate inspection apparatus 2 should execute the inspection. . Specifically, it is recorded in the inspection instruction information D2 in order from the one corresponding to the layer close to the substrate surfaces F1 and F2.
  • each conductive part pair to be inspected is The inspection instruction information D2 illustrated in FIG. 18 is generated in association with the surface, the layer, and the type of the first, second, third, and fourth selected conductive units.
  • layer means each layer of the wiring layer L and the conductor layer Lc.
  • FIG. 18 five pairs of conductive portions are associated with the substrate surface F1, and the order in which inspections are to be performed is shown from top to bottom. Similarly, six conductive portion pairs are associated with the substrate surface F2, and the order in which inspections are to be performed is shown in order from top to bottom.
  • the inspection instruction information D2 obtained in this manner is transmitted to the board inspection apparatus 2 by, for example, a communication circuit (not shown), or the inspection instruction information D2 is stored in a storage medium such as a USB memory. By reading the data into the device 2, the data can be stored in the storage unit 22.
  • the storage unit 22 stores the test instruction information D2 illustrated in FIG.
  • the inspection processing unit 21 selects, as the inspection layer LT1, the layer having the earliest order among the layers on the substrate surface F1 based on the inspection instruction information D2 (step S51).
  • the layer (the top layer) in the first order (the top layer) associated with the substrate surface F1 is the wiring layer L1, and thus the wiring layer L1 is set as the inspection layer LT1.
  • the inspection processing unit 21 selects the layer having the earliest order as the inspection layer LT2 among the layers on the substrate surface F2 side (Step S52).
  • the layer (the uppermost layer) in the earliest order associated with the substrate surface F2 is the wiring layer L4, and thus the wiring layer L4 is set as the inspection layer LT2.
  • the inspection processing unit 21 performs a first current supply process of flowing a measurement current in parallel between the paired conductive portions with respect to the conductive portion pair of the first selected conductive portion in the test layers LT1 and LT2.
  • the inspection processing unit 21 determines whether the conductive layer pair is the first selected conductive part of the wiring layers L1 and L4.
  • a measuring current is passed in parallel to P1, P2, conductive part pairs P4, P5, conductive part pairs P11, P12, and conductive part pairs P15, P16.
  • the inspection processing unit 21 detects a voltage between the pair of conductive portions of the first selected conductive portion in the inspection layers LT1 and LT2, and based on the voltage and the measurement current, determines a current path between the conductive portions.
  • the via V and the wiring W are inspected (step S54: (c1) step).
  • the inspection processing unit 21 causes a current to flow between each pair of the conductive part pairs P1 and P2, the conductive part pairs P4 and P5, the conductive part pairs P11 and P12, and the conductive part pairs P15 and P16, Detect the voltage between pairs. Then, the inspection processing unit 21 calculates the resistance value between each pair by, for example, dividing the voltage between each pair by the current flowing between each pair. The inspection processing unit 21 compares each of the calculated resistance values with, for example, a reference value stored in advance in the storage unit 22. If each of the resistance values is equal to or less than the reference value, the board B is determined to be good. Is larger than the reference value, the board B is determined to be defective.
  • step S54 the inspection processing unit 21 notifies the user of the determination result by, for example, displaying the information on a notifying unit such as a display device (not shown). Note that the inspection processing unit 21 does not necessarily need to notify the user of the determination result.
  • step S54 the current path between each pair of the conductive part pair P1, P2, the conductive part pair P4, P5, the conductive part pair P11, P12, and the conductive part pair P15, P16 selected as the first selected conductive part is determined.
  • the vias V corresponding to the branches M11, M12, M13, M14, M41, M42, M45, M46 and the wirings W corresponding to the nodes N11, N12, N41, N42 are inspected.
  • step S53 a parallel connection is made between each pair of the conductive portion pairs P1 and P2, the conductive portion pairs P4 and P5, the conductive portion pairs P11 and P12, and the conductive portion pairs P15 and P16 selected as the first selected conductive portion. Current, and the voltage between each pair can be measured, so that the inspection time of the substrate can be easily reduced.
  • the conductive portion pair P of the first selected conductive portion is selected for each layer so that current overlap does not occur even when a measurement current is passed in parallel. Therefore, in steps S51 to S54, the conductive part pair P through which the measuring current is caused to flow in parallel based on the inspection instruction information D2 is determined, thereby reducing the risk of lowering the inspection accuracy and shortening the substrate inspection time. It is possible to do.
  • step S54 when it is determined in step S54 that the substrate B is defective (YES in step S55), the inspection processing unit 21 ends the processing without executing the subsequent processing. On the other hand, when the substrate B is not determined to be defective in step S54 (NO in step S55), the inspection processing unit 21 shifts the processing to step S61 (FIG. 20).
  • step S61 the inspection processing unit 21 applies the current for measurement to the pair of conductive portions of the second selected conductive portion in the inspection layers LT1 and LT2 in a non-parallel to the first current supply process between the paired conductive portions. Is performed (step S61: (c2) step).
  • the inspection processing unit 21 detects a voltage between the conductive portion pair of the second selected conductive portions in the test layers LT1 and LT2, and based on the voltage and the measurement current, forms the paired second selected conductive portion.
  • the via V and the wiring W of the current path therebetween are inspected (step S62: (c2) step).
  • the inspection processing unit 21 performs the inspection and reports the determination result by the same method as in step S54.
  • steps S61 and S62 the inspection of the second selected conductive unit is performed in a non-parallel manner to the inspection of the first selected conductive unit, thereby preventing the measurement current from being duplicated.
  • the processes of steps S61 and S62 for the conductive portion pair of the second selected conductive portion in the test layer LT1 and the conductive portion pair of the second selected conductive portion in the test layer LT2 may be performed in parallel.
  • the inspection processing unit 21 performs steps S61 and S62 for the conductive part pairs P13 and P14, which are the second selected conductive parts of the wiring layers L1 and L4, and the conductive part pairs P16 and P17. Run in parallel.
  • the inspection processing unit 21 determines that the substrate B is defective in the inspection in step S62 (YES in step S63), the inspection processing unit 21 ends the processing without performing the subsequent processing. On the other hand, when the substrate B is not determined to be defective in the inspection in Step S62 (NO in Step S63), the inspection processing unit 21 proceeds to Step S64.
  • step S64 the inspection processing unit 21 checks whether or not both the inspection layers LT1 and LT2 are the conductor layers Lc and whether one of the inspection layers LT1 and LT2 is the conductor layer Lc and the other is absent. Step S64). When both the inspection layers LT1 and LT2 are the conductor layers Lc, and when one of the two does not correspond to the conductor layer Lc and the other is absent (NO in step S64), the inspection processing unit 21 proceeds to step S65.
  • step S64 when both of the inspection layers LT1 and LT2 are the conductor layers Lc, or when one of the inspection layers LT1 and LT2 is the conductor layer Lc and the other is without the inspection layer described later (YES in step S64), the inspection processing unit The process proceeds to step S71 (FIG. 21). Now, since neither of the inspection layers LT1 and LT2 is the conductor layer Lc (NO in step S64), the process proceeds to step S65.
  • step S65 if the inspection layer LT1 is not the conductor layer Lc, the inspection processing unit 21 sets the next layer of the layers on the substrate surface F1 side as the inspection layer LT1 based on the inspection instruction information D2 (step S65). S65). When the current inspection layer LT1 is the conductor layer Lc, the inspection processing unit 21 determines that there is no new inspection layer LT1. Next, if the inspection layer LT2 is not the conductor layer Lc, the inspection processing unit 21 sets the next layer of the layers on the substrate surface F2 side as the inspection layer LT2 based on the inspection instruction information D2 (Step S66). Then, the process proceeds to step S53 (FIG. 19). When the current inspection layer LT2 is the conductor layer Lc, the inspection processing unit 21 determines that there is no new inspection layer LT2.
  • the inspection processing unit 21 sets the new inspection layer LT1 as the wiring layer L2 and sets the new inspection layer LT2 as the conductor layer Lc in step S53. (FIG. 19).
  • step S53 the inspection processing unit 21 determines the pair of conductive portions P3 and P4, which are the first selected conductive portions of the wiring layer L2, and the pair of conductive portions P11, P15, which are the first selected conductive portions of the conductive layer Lc on the substrate surface F2. And a voltage between the conductive part pairs P3 and P4 and a voltage between the conductive part pairs P11 and P15 are detected in parallel with respect to, and based on the voltage and the measurement current, the conductive current is detected.
  • the via V and the wiring W of the current path between the sections are inspected (steps S53 and S54: (c1) step).
  • step S55 the inspection processing unit 21 proceeds to step S61.
  • steps S61 to S63 are not executed and the process proceeds to step S64. I do.
  • step S64 when both the inspection layers LT1 and LT2 are the conductor layers Lc, and when one of the inspection layers LT1 and LT2 is the conductor layer Lc and the other does not have the inspection layer, the process proceeds to step S65, and the inspection processing unit 21 Sets the conductor layer Lc, which is the layer in the order next to the wiring layer L2 on the substrate surface F1 side in the inspection instruction information D2, as the inspection layer LT1 (step S65). In step S66, since the inspection layer LT2 is the conductor layer Lc, the inspection processing unit 21 returns to step S53 without any new inspection layer LT2.
  • step S53 the inspection processing unit 21 supplies a measurement current to the conductive portion pairs P1 and P3, which are the first selected conductive portions of the conductive layer Lc on the substrate surface F1, and sets a voltage between the conductive portion pairs P1 and P3. Is detected, and the via V and the wiring W of the current path between the conductive parts are inspected based on the voltage and the measuring current (steps S53 and S54: (c1) step).
  • step S55 the inspection processing unit 21 proceeds to step S61.
  • the inspection processing unit 21 executes steps S61 and S62 on the conductive unit pairs P6 and P7.
  • step S63 the inspection processing unit 21 proceeds to step S64.
  • the inspection layer LT1 is set to the conductor layer Lc in the above-described step S65, and the inspection layer LT2 is set to be absent in the above-described step S66 (YES in step S64), and the process proceeds to step S71 (FIG. 21).
  • step S71 the inspection processing unit 21 performs a third current supply process for flowing a measurement current between the paired conductive portions with respect to the conductive portion pair of the third selected conductive portion.
  • the processing is executed in a non-parallel manner (step S71).
  • the inspection processing unit 21 detects a voltage between the conductive part pairs of the third selected conductive part, and based on the voltage and the measurement current, determines the via V of the current path between the conductive parts and the wiring W. Is inspected (step S72). The inspection processing unit 21 performs the inspection and reports the determination result by the same method as in step S54.
  • the inspection processing unit 21 performs the third current supply process for flowing the measurement current between the conductive portions of the conductive portion pair P12 and P13 in a manner not parallel to the first and second current supply processes (step S71). ), A voltage between the conductive parts of the conductive part pair P12, P13 is detected, and based on the voltage and the measuring current, the via V of the current path between the conductive parts and the wiring W are inspected (step S72). .
  • the wiring W42 of the current path between the conductive portion pair P12 and P13 shown in FIG. 15 is inspected.
  • the possibility that the inspection of the wiring W may be omitted can be reduced, and the inspection accuracy of the substrate B can be improved.
  • the inspection processing unit 21 performs a fourth current supply process of flowing a measurement current between the paired conductive portions with respect to the conductive portion pair of the fourth selected conductive portion, by performing the first to third current supply processes. Are executed in a non-parallel manner (step S73).
  • the inspection processing unit 21 detects a voltage between the pair of conductive portions of the fourth selected conductive portion, and, based on the voltage and the measurement current, determines the via V and the wiring W of the current path between the conductive portions. Is inspected (step S74), and the process ends.
  • the inspection processing unit 21 performs the inspection and reports the determination result by the same method as in step S54.
  • the inspection processing unit 21 ends the processing without executing steps S73 and S74.
  • the via Vc of the substrate B provided with two conductor layers Lc and provided with the vias Vc connecting the planar conductors IP of the two conductor layers Lc to each other is provided. Can be inspected.
  • the inspection instruction information D2 is ordered by the inspection instruction information generating device 3 for each substrate surface in order from the one corresponding to the layer closer to the substrate surfaces F1 and F2.
  • the board inspection apparatus 2 determines the inspection order in steps S51, S52, S65, and S66, so that the wiring layers L can be sequentially inspected in order from the one closer to the substrate surfaces F1 and F2.
  • the number of conductive portion pairs of the first selected conductive portion corresponding to one layer increases.
  • the number of conductive part pairs of the first selected conductive part is larger, the number of conductive part pairs that can be inspected in parallel in step S53 increases.
  • the number of parallel inspections at an early stage of the inspection can be increased by setting the wiring layers L as inspection targets in order from the one closer to the substrate surfaces F1 and F2. If the number of parallel inspections at the beginning of the inspection can be increased, a defect of the substrate B can be detected at an early stage of the inspection. Therefore, when the inspection is ended when a defect is detected as in steps S55 and S63, the wiring layers L are inspected in order from the one closer to the substrate surfaces F1 and F2. In addition, it is possible to shorten the time required to detect a defect and increase the possibility of shortening the inspection time.
  • the inspection instruction information generating device 3 and the substrate inspection device 2 are configured as separate devices, but the inspection instruction information generating device 3 and the substrate inspection device 2 are configured as a single device. May be.
  • the board inspection device 2 may include the inspection instruction information generation unit 31 and the storage unit 32, so that the substrate inspection device 2 may also function as the inspection instruction information generation device.
  • a board inspection system is constituted by one board inspection apparatus also serving as an inspection instruction information generating apparatus.
  • the inspection instruction information generating device 3 and the inspection instruction information generating method do not necessarily need to execute all the flows shown in FIGS. 7 to 14, and the inspection processing unit 21 does not necessarily have to execute the flow shown in FIGS. 19 to 21. It is not necessary to execute all the flows.
  • the inspection instruction information generating device 3 and the inspection instruction information generating method for example, even when only steps S101 and S102 are executed, the wiring W of the wiring layer L1 adjacent to the substrate surface F1, and the wiring adjacent to the substrate surface F1. Inspection instruction information D2 that can easily reduce the inspection time of the via V connecting the layer L1 and the conductive portion P can be generated.
  • the inspection processing unit 21 may execute steps S53 and S54.
  • the example in which the wiring layer L and the conductive portion P are provided on both surfaces of the conductor layer Lc has been described, but the wiring layer L and the conductive portion P may be provided only on one surface of the conductor layer Lc.
  • the substrate B may not include the substrates B4 and B5.
  • the processing related to the second selection layer LL2 does not need to be executed, and for example, steps S18 to S24, S104 to S106, S401 to S403, S52, S66, etc. are unnecessary.
  • the inspection processing unit 21 may be configured not to execute steps S55 and S63 and to continue the inspection even when a defect is detected during the inspection.
  • the inspection instruction information generating apparatus 3 and the inspection instruction information generating method always record the conductive part pairs in the inspection instruction information D2 in steps S4, S13, and S21 in order from the one corresponding to the layer closer to the substrate surfaces F1 and F2. It is not limited to the example to make it.
  • the conductive part pairs may be recorded in the inspection instruction information D2 in an arbitrary order.
  • the inspection instruction information generating apparatus includes a conductor layer that is a layer provided with a conductive planar conductor that spreads in a planar or mesh shape, and a substrate surface on which a plurality of conductive portions are provided.
  • a wiring layer that is a layer laminated between the conductor layer and the substrate surface, a via connecting the wiring of the wiring layer and the plurality of conductive portions, and a wiring of the wiring layer and the conductive layer.
  • a storage unit that stores conductive structure information indicating how the planar conductor, the conductive portion, the wiring, and the via in the substrate including the planar conductor and the via are connected.
  • the inspection instruction information generating method includes a conductor layer that is a layer provided with a conductive planar conductor that spreads in a planar or mesh shape, and a substrate surface provided with a plurality of conductive portions.
  • a wiring layer that is a layer laminated between the conductor layer and the substrate surface, a via connecting the wiring of the wiring layer and the plurality of conductive portions, and a wiring of the wiring layer and the conductive layer.
  • the wiring layer is formed based on conductive structure information indicating how the planar conductor, the conductive portion, the wiring, and the via are electrically connected to each other on a substrate including a planar conductor and a via connecting the via.
  • the information indicating the conductive part is Including inspection instruction information generation step of executing the test instruction information generating process of generating a.
  • the inspection instruction information generation program includes a conductor layer that is a layer provided with a conductive planar conductor that spreads in a planar or mesh shape, and a substrate surface provided with a plurality of conductive portions.
  • a wiring layer that is a layer laminated between the conductor layer and the substrate surface, a via connecting the wiring of the wiring layer and the plurality of conductive portions, and a wiring of the wiring layer and the conductive layer.
  • the wiring layer is formed based on conductive structure information indicating how the planar conductor, the conductive portion, the wiring, and the via are electrically connected to each other on a substrate including a planar conductor and a via connecting the via.
  • a pair of the conductive parts is selected as a first selected conductive part from each of the groups, and a first selection of the selected plurality of pairs is performed.
  • the inspection instruction information generating process of generating the information causes the computer to execute.
  • a pair of first selection conductive units is selected from one group, and thus a plurality of pairs of first selection conductive units belong to different groups. Then, even if currents are supplied in parallel to a plurality of pairs of the first selected conductive portions indicated by the inspection instruction information, currents do not overlap. Therefore, by using a plurality of pairs of the first selected conductive portions based on the inspection instruction information obtained as described above as inspection locations, inspections at a plurality of locations can be performed in parallel, resulting in a reduction in board inspection time. It becomes easy to do.
  • the inspection instruction information generation processing includes: (a) a step of grouping the conductive parts that are electrically connected to each other via the wiring of the wiring layer based on the conductive structure information; and (b) the grouping.
  • the inspection instruction information generation processing includes: (a) a step of grouping the conductive parts that are electrically connected to each other via the wiring of the wiring layer based on the conductive structure information; and (b) the grouping.
  • two conductive portions are selected as the pair of first selected conductive portions from among the conductive portions included in each group, and the selected plurality of pairs of the first selected conductive portions are arranged in parallel. Recording in the inspection instruction information as an inspection location that can be inspected by using the inspection instruction information.
  • conductive portions that are electrically connected to each other via the wiring of the wiring layer that is, conductive portions that may overlap with each other if a current flows through a plurality of conductive portion pairs.
  • the groups are grouped together.
  • two conductive portions are selected as a pair of first selected conductive portions from among the conductive portions included in each of the groups, and the selected plural pairs of first selected conductive portions are connected in parallel. It is recorded in the inspection instruction information as an inspection location that can be inspected.
  • a pair of first selection conductive units is selected from one group, and thus a plurality of pairs of first selection conductive units belong to different groups. Therefore, even if currents are supplied in parallel to a plurality of pairs of the first selected conductive portions indicated by the inspection instruction information, currents do not overlap. Therefore, by using a plurality of pairs of the first selected conductive portions based on the inspection instruction information obtained as described above as inspection locations, inspections at a plurality of locations can be performed in parallel, resulting in a reduction in board inspection time. It becomes easy to do.
  • the conductive part that is not selected as the first selected conductive part is added to the group. It is preferable to record the two conductive portions included in the inspection instruction information as a pair of second selected conductive portions to be tested non-parallel to the plurality of pairs of first selected conductive portions.
  • the substrate includes a plurality of the wiring layers, and further includes a plurality of vias connecting the plurality of wiring layers
  • the inspection instruction information generating unit includes: (d) wiring of the plurality of wiring layers in parallel. If connected, the conductive structure information is changed before the step (a) so that the plurality of wirings connected in parallel are replaced with one of the wirings closest to the substrate surface. It is preferable to further execute a step of performing the inspection instruction information generation processing based on the conductive structure information changed in the step (d).
  • the inspection instruction information generating process is executed based on the simplified conductive structure information. As a result, the execution of the inspection instruction information generation processing becomes easy.
  • the inspection instruction information generating unit may perform the connection in parallel before the step (a). Further performing the step of changing the conductive structure information changed in the step (d) so as to replace the via or the row of the vias with one or a row of vias, and changing the conductive structure information changed in the step (e). It is preferable to execute the inspection instruction information generation processing based on structure information.
  • the inspection instruction information generating process is executed based on the simplified conductive structure information. As a result, the execution of the inspection instruction information generation processing becomes easy.
  • the substrate includes a plurality of the wiring layers, and further includes a plurality of vias connecting the plurality of wiring layers
  • the inspection instruction information generating unit includes: (f) the most one of the plurality of wiring layers; Performing the steps (a) and (b) on a wiring layer near the substrate surface as a processing target; and (g) performing the other wiring layers on the other wiring layers except for the wiring layer closest to the substrate surface.
  • G1 For each of the wirings of the wiring layer to be processed, corresponding to one of the wirings, a single via connected to a side of the one wiring away from the conductor layer is set as a processing target.
  • the selected conductive portion is grouped for each corresponding wiring, and ( g2) Grouping in the step (g1)
  • the step (b) is performed on the group, and in the step (b), the first selection conductive portion of each pair is recorded in the inspection instruction information in association with the wiring layer to be processed. preferable.
  • the plurality of pairs of the first selected conductive portions are connected to the wiring layer in order from the one selected as a wiring layer close to the substrate surface as a processing target. It is preferable that the inspection instruction information is recorded in the order of each layer.
  • the number of pairs of the first selection conductive parts with respect to the wiring layer to be processed that is, the number of conductive parts that can flow a measuring current in parallel during the inspection is increased.
  • the inspection instruction information is obtained at the time of inspection.
  • the wiring layers to be inspected are selected in the order in which the wiring layers have been inspected, and the inspection can be performed by applying a measuring current to the first selected conductive portion pair corresponding to the wiring layer.
  • the inspection can be performed by applying a measuring current to the first selected conductive portion pair corresponding to the wiring layer.
  • one of the conductive parts electrically connected on the opposite side to the planar conductor is selected.
  • the conductive portions are grouped as conductive portions corresponding to one side of the planar conductor, and two conductive portions are selected as a pair of first selected conductive portions from the grouped conductive portions, and the selected conductive portions are selected. It is preferable to record a pair of first selected conductive portions in the inspection instruction information.
  • the via connected to the planar conductor can be inspected.
  • the inspection instruction information generating process includes: (j) searching for the wiring that is not sandwiched between the pair of the first selected conductive portions and that is not sandwiched between the pair of the second selected conductive portions; A conductive portion that conducts without passing through the wire to one end of the searched wire, and a conductive portion that conducts without passing through the wire to the other end of the wire, the plurality of pairs of first selected conductive portions,
  • the method further includes a step of recording in the inspection instruction information as a pair of third selected conductive portions to be inspected non-parallel.
  • the substrate surface and the wiring layer are provided on both sides of the conductor layer, respectively, and the inspection instruction information generating unit executes the inspection instruction information generation processing on both sides of the conductor layer.
  • the substrate includes a plurality of the conductor layers and vias connecting the planar conductors of the plurality of conductor layers
  • the inspection instruction information generation processing includes: One of the conductive portions on the substrate surface and one of the conductive portions on the other substrate surface, the plurality of pairs of the first selected conductive portions as a pair of fourth selected conductive portions to be inspected non-parallel, It is preferable that the method further includes a step of recording the inspection instruction information.
  • the inspection instruction information generating unit converts the conductive structure information into a tree-structured data structure by associating the via with a node, the wiring with a branch, and the planar conductor with a root node. Is preferably further executed, and the inspection instruction information generating process is executed based on the conductive structure information converted into the tree structure in the step (m).
  • the inspection instruction information generating process is executed based on the simplified conductive structure information. As a result, the execution of the inspection instruction information generation processing becomes easy.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first A step of detecting a voltage between the selected conductive parts and inspecting vias and wiring of a current path between the first selected conductive parts of each pair based on the current and the voltage.
  • the first current supply process is performed in parallel on a plurality of pairs of the first selected conductive units based on the test instruction information, so that the test at a plurality of locations can be performed while avoiding overlapping of the measured currents.
  • the inspection time of the substrate can be easily reduced.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first Detecting a voltage between the selected conductive portions, and testing vias and wiring of a current path between each pair of the first selected conductive portions based on the current and the voltage; (c2) the test instruction information Between the second selected conductive portions forming a pair, the first current supply process performs a second current supply process of flowing current in a non-parallel manner, and the voltage between the paired second selected conductive portions is And based on the detected current and voltage, Via the current path between the conductive portion and executes the step of examining the wiring.
  • a board inspection system includes the above-described inspection instruction information generation device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit (C1) a first current flowing between a pair of first selected conductive portions with respect to a plurality of pairs of first selected conductive portions indicated by the inspection instruction information for each of the wiring layers in the order indicated by the information; The supply process is performed in parallel, the voltage between the pair of first selected conductive units is detected, and based on the current and the voltage, the via of the current path between the pair of first selected conductive units and A step of inspecting the wiring is performed, and if the result of the inspection in the step (c1) is defective, the step (c1) is not performed on the wiring layer having the next or subsequent order.
  • a board inspection system includes the above-described inspection instruction information generating device, and an inspection processing unit that inspects the substrate based on the inspection instruction information, wherein the inspection processing unit comprises: (c1) For a plurality of pairs of first selected conductive portions indicated by the inspection instruction information, a first current supply process for flowing a current between the paired first selected conductive portions is performed in parallel, and the first Detecting a voltage between the selected conductive parts, and inspecting vias and wiring of a current path between the pair of first selected conductive parts based on the current and the voltage, and performing the step (c1).
  • the inspection instruction information generating apparatus, the inspection instruction information generating method, and the inspection instruction information generating program having such a configuration can generate the inspection instruction information indicating the inspection location where the inspection time of the board can be easily reduced. it can.
  • the board inspection system having such a configuration can easily reduce the board inspection time.

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  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Dans la présente invention, sur la base d'informations de structure de conduction D1 indiquant comment un conducteur plan IP, une pluralité de parties de conduction P, un câblage W, et un trou d'interconnexion V sont connectés de façon conductrice dans un substrat comprenant une couche de conducteur Lc, une surface de substrat F sur laquelle les parties de conduction P sont disposées, une couche de câblage L, et le trou d'interconnexion V, s'il existe une pluralité de groupes de parties de conduction P électriquement connectées les unes aux autres par l'intermédiaire du câblage W de la couche de câblage L, un traitement de génération d'informations d'instruction d'inspection est effectué dans lequel des parties de conduction P sont sélectionnées parmi les groupes une paire à la fois en tant que premières parties de conduction sélectionnées et des informations indiquant une pluralité des paires de premières parties de conduction sélectionnées qui ont été sélectionnées sont générées en tant qu'informations d'instruction d'inspection D2.
PCT/JP2019/028270 2018-09-14 2019-07-18 Dispositif de génération d'informations d'instruction d'inspection, système d'inspection de substrat, procédé de génération d'informations d'instruction d'inspection et programme de génération d'informations d'instruction d'inspection WO2020054214A1 (fr)

Priority Applications (3)

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JP2020546728A JP7352840B2 (ja) 2018-09-14 2019-07-18 検査指示情報生成装置、基板検査システム、検査指示情報生成方法、及び検査指示情報生成プログラム
KR1020217011041A KR102707838B1 (ko) 2018-09-14 2019-07-18 검사 지시 정보 생성 장치, 기판 검사 시스템, 검사 지시 정보 생성 방법 및 검사 지시 정보 생성 프로그램
CN201980060230.8A CN112689769B (zh) 2018-09-14 2019-07-18 检查指示信息产生装置与方法、基板检查系统及存储介质

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