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WO2020040090A1 - Electro-optical device, electronic apparatus, and driving method - Google Patents

Electro-optical device, electronic apparatus, and driving method Download PDF

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Publication number
WO2020040090A1
WO2020040090A1 PCT/JP2019/032287 JP2019032287W WO2020040090A1 WO 2020040090 A1 WO2020040090 A1 WO 2020040090A1 JP 2019032287 W JP2019032287 W JP 2019032287W WO 2020040090 A1 WO2020040090 A1 WO 2020040090A1
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Prior art keywords
transistor
driving
light emitting
line
gate electrode
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Ceased
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PCT/JP2019/032287
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French (fr)
Japanese (ja)
Inventor
直史 豊村
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to KR1020217003191A priority Critical patent/KR102632645B1/en
Priority to KR1020257019415A priority patent/KR20250092288A/en
Priority to KR1020247003342A priority patent/KR102821955B1/en
Priority to DE112019004175.4T priority patent/DE112019004175T5/en
Priority to CN201980053870.6A priority patent/CN112567448B/en
Priority to JP2020538377A priority patent/JP7389039B2/en
Priority to CN202410159561.XA priority patent/CN118015995A/en
Publication of WO2020040090A1 publication Critical patent/WO2020040090A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present technology relates to an electro-optical device, an electronic device, and a driving method.
  • An electro-optical device using an organic light emitting diode (hereinafter, referred to as an OLED (Organic Light Emitting Diode)) as a light emitting element is known.
  • OLED Organic Light Emitting Diode
  • a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel at an intersection of a scanning line and a data line.
  • the transistor supplies a current to the light emitting element according to the voltage between the gate and the source. Then, the light emitting element emits light with luminance according to the gradation level.
  • Vth threshold voltage of the transistor provided in each pixel
  • the current flowing through the light emitting element varies, and the image quality deteriorates.
  • Vth the threshold voltage of the transistor provided in each pixel
  • the drain and gate of a transistor are connected to a data signal supply line provided for each column, and the potential is set to a value corresponding to the threshold voltage of the transistor.
  • the parasitic capacitance is attached to the data signal supply line, the parasitic capacitance is charged or discharged when the compensation operation is performed.
  • the period of the compensation operation is lengthened by the time required for charging or discharging the parasitic capacitance. Further, if the period of the compensation operation is set without considering the time required for charging or discharging the parasitic capacitance, the compensation may be insufficient.
  • Patent Document 1 aims to speed up a compensation operation for compensating for variations in Vth.
  • the configuration described in Patent Literature 1 aims at high-speed driving as a circuit structure having a “relay line” that connects a plurality of pixels in the V direction and uses the “relay line” to hold charges when correcting Vth of each pixel.
  • Patent Document 1 requires six MOSFETs and two capacitors as elements for forming one pixel circuit. In this configuration, the number of elements is large and high-definition layout is difficult.
  • An object of the present technology is to provide an electro-optical device, an electronic apparatus, and a driving method that can realize high-speed compensation operation with a smaller number of elements to compensate for variations in threshold voltage of a transistor used for adjusting light emission intensity. Is to do.
  • This technology corresponds to a signal line, a relay line, a scanning line, a power supply line for supplying power for extinction, a transfer capacity connected between the signal line and the relay line, and a relay line and a scanning line.
  • Pixel circuit provided, and a driving circuit for driving the pixel circuit,
  • the pixel circuit includes a driving transistor including a gate electrode, a first current terminal, and a second current terminal; a light emitting element that emits light at a luminance corresponding to a magnitude of current supplied through the driving transistor; A first transistor connected between the gate electrode of the driving transistor, a first current terminal of the driving transistor, a second transistor for conducting the gate electrode of the driving transistor, and a first current terminal and a light emitting element.
  • the driving circuit turns on the first transistor, the second transistor, and the fourth transistor during a light emitting period of the light emitting element, shifts to a light extinction period, and includes the first transistor, the second transistor, and the third transistor.
  • This is an electro-optical device configured to be driven to a voltage reflecting a value voltage.
  • the present technology is an electronic apparatus including the above-described electro-optical device.
  • the present technology is configured to provide a signal line, a relay line, a scanning line, a power supply line for supplying extinction power, a first capacitor connected between the signal line and the relay line, a relay line and the scanning line.
  • the pixel circuit includes a driving transistor including a gate electrode, a first current terminal, and a second current terminal; a light emitting element that emits light at a luminance corresponding to a magnitude of current supplied through the driving transistor; A first transistor connected between the gate electrode of the driving transistor, a first current terminal of the driving transistor, a second transistor for conducting the gate electrode of the driving transistor, and a first current terminal and a light emitting element.
  • the driving circuit turns on the first transistor, the second transistor, and the fourth transistor during a light emitting period of the light emitting element, shifts to a light extinction period, and includes the first transistor, the second transistor, and the third transistor.
  • a pixel circuit capable of threshold value correction can be realized with a smaller number of elements.
  • the effects described here are not necessarily limited, and may be any of the effects described in the present technology or an effect different from them.
  • the contents of the present technology are not construed as being limited by the effects illustrated in the following description.
  • FIG. 1 is a connection diagram of an embodiment of a pixel circuit according to the present technology.
  • FIG. 2 is a timing chart for explaining the configuration of FIG.
  • FIG. 3 is a connection diagram of an example of a conventional pixel circuit.
  • FIG. 4 is a timing chart for explaining a conventional pixel circuit.
  • FIG. 3 shows a conventional pixel circuit
  • FIG. 4 is a timing chart showing its operation.
  • the electro-optical device includes a display panel and a control circuit for controlling the operation of the display panel.
  • the display panel includes a plurality of pixel circuits and a driving circuit for driving the pixel circuits.
  • a plurality of pixel circuits and a driver circuit included in the display panel are formed over a silicon substrate, and an OLED that is an example of a light-emitting element is used for the pixel circuit.
  • the control circuit is supplied in synchronization with the digital image data synchronization signal.
  • the image data is data that defines the gradation level of the pixel of the image to be displayed on the display panel by, for example, 8 bits.
  • the synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
  • the control circuit generates various control signals based on the synchronization signal, and supplies the control signals to the display panel. Further, the control circuit includes a voltage generation circuit. The voltage generation circuit supplies various potentials to the display panel. Further, the control circuit generates an analog image signal based on the image data.
  • the display panel includes a display unit and a driving circuit for driving the display unit.
  • pixel circuits corresponding to pixels of an image to be displayed are arranged in a matrix. That is, in the display unit, M rows of scanning lines are provided extending in the horizontal direction (X direction) in the figure, and (3N) columns of signal lines grouped every three columns are arranged in the vertical direction in the figure. (Y direction), and is provided so as to be insulated from each scanning line.
  • the pixel circuits are arranged in a matrix with M rows and 3N columns.
  • Each pixel circuit has the same configuration as each other.
  • the pixel circuit 11 will be described with reference to FIG.
  • One electrode of a transfer capacitance (first capacitance) Cs2 and one of a source and a drain of the fifth transistor AZ3 are connected to the signal line 12-1.
  • the other electrode of the transfer capacitor Cs2 and the other of the source and the drain of the fifth transistor AZ3 are connected to the relay line 12-2. That is, the transfer capacitor Cs2 and the fifth transistor AZ3 are connected in parallel between the signal line 12-1 and the relay line 12-2.
  • the pixel circuit 11 is connected to the relay line 12-2. That is, a gradation potential corresponding to the designated gradation is supplied to the pixel circuit 11 via the signal line 12-1 and the relay line 12-2.
  • the first transistor WS has a gate connected to the scanning line 16 and one of a source and a drain connected to the relay line 12-2.
  • the other of the source and the drain is connected to the gate of the driving transistor Drv and one electrode of the pixel capacitance Cs1, respectively. That is, the first transistor WS is connected between the gate of the driving transistor Drv and the second electrode of the transfer capacitor Cs2.
  • the first transistor WS functions as a transistor that controls the connection between the gate of the driving transistor Drv and the second electrode of the transfer capacitor Cs2 connected to the relay line 12-2.
  • the drive transistor Drv has its source (second current terminal) connected to the power supply line 15, and its drain (first current terminal) connected to one of the source or drain of the second transistor AZ2 and the source of the third transistor DS. It is connected to the.
  • the power supply line 15 is supplied with a potential VCCP which is a higher side of the power supply in the pixel circuit 11. A current flows according to the voltage between the gate and the source of the driving transistor Drv.
  • the second transistor AZ2 functions as a switching transistor that controls the connection between the gate and the drain of the drive transistor Drv.
  • the second transistor AZ2 is a transistor for conducting between the gate and the drain of the driving transistor Drv via the first transistor WS.
  • the third transistor DS functions as a switching transistor that controls the connection between the drain of the drive transistor Drv and the anode of the OLED.
  • the fourth transistor AZ1 has a gate connected to the control line and is supplied with a control signal.
  • the drain of the fourth transistor AZ1 is connected to a power supply line 13 as a power supply line for extinction, and is maintained at an extinction potential Vss.
  • the extinction potential Vss is a voltage for keeping the OLED in an extinction state.
  • the fourth transistor AZ1 functions as a switching transistor that controls connection between the power supply line 13 and the anode of the OLED.
  • a control signal is supplied to the gate of the fifth transistor AZ3.
  • One of a source and a drain of the fifth transistor AZ3 is connected to the relay line 12-2, and the other of the source and the drain of the second transistor AZ2 and the second electrode of the transfer capacitor Cs2 via the relay line 12-2. It is connected to the.
  • the other of the source and the drain is connected to the signal line 12-1.
  • the fifth transistor AZ3 mainly functions as a switching transistor that controls connection between the signal line 12-1 and the relay line 12-2.
  • the pixel capacitance Cs1 has one electrode connected to the gate of the drive transistor Drv and the other electrode connected to the power supply line 15 (potential VCCP).
  • the pixel capacitance Cs1 functions as a storage capacitor that holds a voltage between the gate and the source of the drive transistor Drv.
  • the pixel capacitance Cs1 may be a capacitance parasitic on the gate of the driving transistor Drv, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.
  • the anode of the OLED is a pixel electrode provided individually for each pixel circuit 11.
  • the cathode of the OLED is a common electrode provided in common to all the pixel circuits 11, and is maintained at the potential Vcath on the lower side of the power supply in the pixel circuits 11.
  • An OLED is an element in which a white organic EL layer is sandwiched between an anode and a light-transmissive cathode on a silicon substrate. A color filter corresponding to one of RGB is superimposed on the emission side (cathode side) of the OLED.
  • FIG. 4 shows the on / off state of the transistors constituting the pixel circuit 11. A high level indicates the off state of the transistor, and a low level indicates the on state of the transistor. Gate represents the gate potential of the driving transistor Drv.
  • the third transistor DS is turned on, and the transistors WS, AZ2, AZ1, and AZ3 are turned off.
  • the drive transistor Drv supplies the OLED with a drive current corresponding to the voltage held by the pixel capacitor Cs1, that is, the gate-source voltage.
  • a current corresponding to a gradation potential corresponding to a designated gradation of each pixel is supplied to the OLED by the driving transistor Drv, and the OLED emits light at a luminance corresponding to the current.
  • the transistor OFS is turned off, and the transmission gate 42 is turned off.
  • the transistor DS is turned off from the light emitting period, the transistor AZ1 is turned on, and the light emitting period is started. As a result, the path of the current supplied to the OLED is interrupted, so that the OLED is turned off.
  • the transistor OFS, the transistor WS, and the transistor AZ3 connected to the signal line 12-1 are turned on, and the Vth correction reference voltage Vofs ⁇ is written to the signal line 12-1 to perform an initialization operation.
  • the fifth transistor AZ3 since the fifth transistor AZ3 is on, the signal line 12-1 and the relay line 12-2 are connected, and the second electrode of the transfer capacitor Cs2 is also set to the initial potential. Thereby, the transfer capacity Cs2 is initialized.
  • the Vth correction period starts.
  • the transistors WS, AZ2, and AZ1 turn on, and the third transistors DS and AZ3 turn off.
  • the gate of the driving transistor Drv is connected to its own drain via the first transistor WS and the second transistor AZ2, and a drain current flows through the driving transistor Drv to charge the gate. That is, the drain and the gate of the driving transistor Drv are connected to the relay line 12-2, and when the threshold voltage of the driving transistor Drv is Vth, the potential Vg of the gate of the driving transistor Drv becomes (VCCP-Vth). The convergence is completed, and the Vth correction is completed.
  • the transistor OFS is turned on and the transmission gate 14 is turned off.
  • the length of the relay line 12-2 is short, the time required for charging or discharging the parasitic capacitance associated with the relay line 12-2 is reduced, and the Vth correction period itself is shortened.
  • the writing period starts.
  • the transistors WS and AZ1 are turned on, while the transistors AZ2, DS and AZ3 are turned off.
  • the transistor OFS turns off and the transmission gate 14 turns on. Therefore, the gradation potential is supplied to one electrode of the transfer capacitor Cs2. Then, a signal in which the gradation potential is level-shifted is supplied to the gate of the drive transistor Drv, and is written into the pixel capacitance Cs1.
  • the Vth correction operation is performed with the first transistor WS turned on. Therefore, the Vth correction voltage is written not only to the pixel capacitance Cs1 but also to the parasitic capacitance Cp of the relay line 12-2.
  • the relay line 12-2 is configured to be shared by a plurality of pixels, and the capacitance value changes according to the number of shared pixels. When the number of shared pixels is reduced, the capacitance value is reduced, the Vth correction speed can be increased, and an operation advantageous for high-speed driving is achieved.
  • FIG. 1 is a circuit diagram of an embodiment of the present technology.
  • One embodiment has a configuration in which the fifth transistor AZ3 in the circuit configuration of FIG. 3 is omitted. Further, a predetermined voltage rst is applied to the signal line 12-1 via the transistor RST. A control signal is supplied to the gate of the transistor RST.
  • FIG. 2 shows the drive timing according to an embodiment of the present technology.
  • the third transistor DS is turned on, and the transistors WS, AZ1, and AZ2 are turned off.
  • the drive transistor Drv supplies the OLED with a drive current corresponding to the voltage held by the pixel capacitor Cs1, that is, the voltage between the gate and the source.
  • a current corresponding to a gradation potential corresponding to a designated gradation of each pixel is supplied to the OLED by the driving transistor Drv, and the OLED emits light at a luminance corresponding to the current.
  • the transistor RST is turned off, and the transmission gate 42 is turned off.
  • the first transistor WS, the fourth transistor AZ1, the second transistor AZ2, and the transistor RST are turned on, and the state shifts to the extinction state.
  • the extinction potential Vss of the power supply line 13 is written via the transistor AZ2, the transistor DS, and the transistor AZ1 in preparation for Vth correction.
  • the extinction potential Vss is set such that the OLED is extinguished and the drive transistor Drv is turned on during Vth correction preparation.
  • the voltage for turning on the transistors AZ1, AZ2, and DS is represented as V_Low
  • the gate voltage Vg of the driving transistor Drv is expressed by the following equation.
  • + V_Low Vg
  • the third transistor DS is turned off to start the Vth correction period.
  • the drain of the drive transistor Drv is disconnected from the OLED.
  • the gate of the driving transistor Drv converges to (VCCP-Vth) and the Vth correction period is completed.
  • the operation shifts to the writing period.
  • the first transistor WS is turned on
  • the third transistor DS is turned off
  • the fourth transistor AZ1 is turned on
  • the third transistor AZ3 and the transistor RST are turned off.
  • the gate voltage of the driving transistor Drv becomes a voltage reflecting Vth, and Vth is canceled at the time of light emission.
  • the first transistor WS and the fourth transistor AZ1 are turned off, the third transistor DS is turned on, and the light emitting period is started.
  • the drive timing at which the Vth correction preparation voltage is written from Vss is used.
  • Vth correction operation can be performed. That is, the pixel circuit of the present technology uses a power supply connected to the anode of an OLED as a light emitting element via a switch transistor instead of writing a Vth correction preparation voltage from a signal line at the time of Vth correction preparation. Since the number of elements can be reduced in this way, a pixel circuit that is advantageous for a high-definition pixel layout can be realized.
  • the transistors are unified with the P-channel type, but may be unified with the N-channel type. Further, the P-channel type and the N-channel type may be appropriately combined.
  • the OLED which is a light emitting element is exemplified as the electro-optical element.
  • an electroluminescent element such as an inorganic light emitting diode or an LED (Light Emitting Diode) may be used as long as it emits light at a luminance according to current.
  • the electro-optical device is suitable for applications in which pixels have a small size and display with high definition. Therefore, the present invention can be applied to display devices such as head mounted displays, smart glasses, smart phones, and electronic viewfinders of digital cameras as electronic devices.
  • the present technology may also have the following configurations.
  • Electro-optical device (2) The electro-optical device according to (1), wherein the quenching power supply is set such that the driving transistor is turned on during the quenching period while the light emitting element is quenched. (3) One of the electrodes is connected to the gate electrode of the drive transistor, and the other electrode is connected to the voltage supply line, and has a pixel capacitance for holding a voltage between the gate and the source of the drive transistor. (1) or (2) An electro-optical device according to claim 1.
  • the pixel circuit includes: A driving transistor having a gate electrode, a first current terminal, and a second current terminal; A light-emitting element that emits light at a luminance corresponding to the magnitude of the current supplied through the drive transistor; A first transistor connected between the relay line and the gate electrode of the driving transistor; A second transistor for conducting the first current terminal of the drive transistor and the gate electrode of the drive transistor; A third transistor inserted between the first current terminal and one terminal of the light emitting element; A fourth transistor inserted between the power supply line and one terminal of the light emitting element,
  • the driving circuit includes: In a light emitting period of the light emitting element, the first transistor, the second transistor, and the fourth transistor are turned on
  • An electro-optical device that corrects a threshold voltage of the driving transistor by turning off the third transistor, and drives a voltage of a gate electrode of the driving transistor to a voltage reflecting the threshold voltage.
  • Drive method (6)
  • the pixel circuit has a pixel capacitance that has one electrode connected to the gate electrode of the drive transistor and the other electrode connected to a voltage supply line, and holds a voltage between the gate and the source of the drive transistor. Or the driving method of the electro-optical device according to (6).

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Abstract

The present invention realizes a pixel circuit that is advantageous to a high-precision pixel layout in which the number of elements is small. This electro-optical device comprises a pixel circuit (11) provided to correspond to a relaying line (12-2) and a scanning line (16), and a driving circuit that drives the pixel circuit, wherein the driving circuit is configured to perform driving to: turn on a first transistor (WS), a second transistor (AZ2), and a fourth transistor (AZ1) in a light emitting time period of a light emitting element (OLED); and, upon transition to a quenching time period, write a quenching power source (Vss) into a gate electrode of a driving transistor (Drv) through the first transistor, the second transistor, a third transistor (DS), and the fourth transistor, turn off the third transistor to correct a threshold voltage for the driving transistor, and adjust the voltage of the gate electrode of the driving transistor to a voltage reflecting the threshold voltage.

Description

電気光学装置、電子機器及び駆動方法Electro-optical device, electronic apparatus, and driving method

　本技術は、電気光学装置、電子機器及び駆動方法に関する。 The present technology relates to an electro-optical device, an electronic device, and a driving method.

　発光素子として有機発光ダイオード（以下、ＯＬＥＤ（Organic Light Emitting Diode）という）素子などを用いた電気光学装置が知られている。電気光学装置では、走査線とデータ線との交差箇所に対して、発光素子やトランジスタなどを含む画素回路が画素に対応して設けられる。画素回路に対して、画素の階調レベルに応じた電位のデータ信号が当該トランジスタのゲートに印加されると、当該トランジスタは、ゲート・ソース間の電圧に応じた電流を発光素子に対して供給し、発光素子が階調レベルに応じた輝度で発光する。 2. Related Art An electro-optical device using an organic light emitting diode (hereinafter, referred to as an OLED (Organic Light Emitting Diode)) as a light emitting element is known. In the electro-optical device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel at an intersection of a scanning line and a data line. When a data signal of a potential corresponding to the gradation level of the pixel is applied to the gate of the transistor to the pixel circuit, the transistor supplies a current to the light emitting element according to the voltage between the gate and the source. Then, the light emitting element emits light with luminance according to the gradation level.

　各画素に設けられたトランジスタのしきい値電圧（以下Ｖthと適宜称する）がばらつくと、発光素子に流れる電流がばらつき画質が低下する。画質の低下を防止するために、Ｖthのばらつきを補償する必要がある。補償を行う場合、トランジスタのドレイン及びゲートを、列ごとに設けられたデータ信号の供給線に接続し、その電位をトランジスタのしきい値電圧に応じた値に設定する方法が知られている。 (4) When the threshold voltage (hereinafter, appropriately referred to as Vth) of the transistor provided in each pixel varies, the current flowing through the light emitting element varies, and the image quality deteriorates. In order to prevent the image quality from deteriorating, it is necessary to compensate for variations in Vth. When performing compensation, a method is known in which the drain and gate of a transistor are connected to a data signal supply line provided for each column, and the potential is set to a value corresponding to the threshold voltage of the transistor.

　しかしながら、データ信号の供給線には寄生容量が付随しているので、補償動作を実行する際には寄生容量への充電又は放電も行われる。この寄生容量への充電又は放電に要する時間分だけ、補償動作の期間が長くなる。また、寄生容量への充電又は放電に要する時間を考慮しないで補償動作の期間を設定すると、補償が不充分になることが生じる。 However, since the parasitic capacitance is attached to the data signal supply line, the parasitic capacitance is charged or discharged when the compensation operation is performed. The period of the compensation operation is lengthened by the time required for charging or discharging the parasitic capacitance. Further, if the period of the compensation operation is set without considering the time required for charging or discharging the parasitic capacitance, the compensation may be insufficient.

　特許文献１は、Ｖthのばらつきを補償する補償動作の高速化を図るものである。特許文献１に記載の構成は、Ｖ方向に複数の画素を接続し各々の画素のＶthの補正時の電荷保持に用いる「中継線」を有する回路構造として、高速駆動化を図っている。 Patent Document 1 aims to speed up a compensation operation for compensating for variations in Vth. The configuration described in Patent Literature 1 aims at high-speed driving as a circuit structure having a “relay line” that connects a plurality of pixels in the V direction and uses the “relay line” to hold charges when correcting Vth of each pixel.

特開２０１６－０３８４２５公報JP 2016-03845A

　しかしながら、特許文献１の構成は、１個の画素回路を構成するための素子として、６個のＭＯＳＦＥＴと２個のコンデンサを必要とするものであった。素子数が多く高精細レイアウトが困難な構成であった。 However, the configuration of Patent Document 1 requires six MOSFETs and two capacitors as elements for forming one pixel circuit. In this configuration, the number of elements is large and high-definition layout is difficult.

　本技術の目的は、発光強度の調節に用いるトランジスタのしきい値電圧のばらつきを補償する補償動作の高速化をより少ない素子数で実現することができる電気光学装置、電子機器及び駆動方法を提供することにある。 An object of the present technology is to provide an electro-optical device, an electronic apparatus, and a driving method that can realize high-speed compensation operation with a smaller number of elements to compensate for variations in threshold voltage of a transistor used for adjusting light emission intensity. Is to do.

　本技術は、信号線と、中継線と、走査線と、消光用電源を供給する給電線と、信号線及び中継線の間に接続された転送容量と、中継線と走査線とに対応して設けられた画素回路と、画素回路を駆動する駆動回路とを有し、
　画素回路は、ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、中継線と、駆動トランジスタのゲート電極との間に接続された第１トランジスタと、駆動トランジスタの第１電流端と、駆動トランジスタのゲート電極とを導通させるための第２トランジスタと、第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、給電線と発光素子の一方の端子間に挿入された第４のトランジスタとを含み、
　駆動回路は、発光素子の発光期間において、第１のトランジスタ、第２のトランジスタ及び第４のトランジスタをオンとし、消光期間に移行すると共に、第１のトランジスタ、第２のトランジスタ、第３のトランジスタ及び第４のトランジスタを通じて、消光用電源を駆動トランジスタのゲート電極に書き込み、第３のトランジスタをオフすることで、駆動トランジスタのしきい値電圧を補正し、駆動トランジスタのゲート電極の電圧をしきい値電圧を反映した電圧とするように駆動するように構成された電気光学装置である。
　また、本技術は、上述した電気光学装置を備える電子機器である。
　さらに、本技術は、信号線と、中継線と、走査線と、消光用電源を供給する給電線と、信号線及び中継線の間に接続された第１容量と、中継線と走査線とに対応して設けられた画素回路と、画素回路を駆動する駆動回路とを有し、
　画素回路は、ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、中継線と、駆動トランジスタのゲート電極との間に接続された第１トランジスタと、駆動トランジスタの第１電流端と、駆動トランジスタのゲート電極とを導通させるための第２トランジスタと、第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、給電線と発光素子の一方の端子間に挿入された第４のトランジスタとを含み、
　駆動回路は、発光素子の発光期間において、第１のトランジスタ、第２のトランジスタ及び第４のトランジスタをオンとし、消光期間に移行すると共に、第１のトランジスタ、第２のトランジスタ、第３のトランジスタ及び第４のトランジスタを通じて、消光用電源を駆動トランジスタのゲート電極に書き込み、第３のトランジスタをオフすることで、駆動トランジスタのしきい値電圧を補正し、駆動トランジスタのゲート電極の電圧をしきい値電圧を反映した電圧とするように駆動する電気光学装置の駆動方法である。 This technology corresponds to a signal line, a relay line, a scanning line, a power supply line for supplying power for extinction, a transfer capacity connected between the signal line and the relay line, and a relay line and a scanning line. Pixel circuit provided, and a driving circuit for driving the pixel circuit,
The pixel circuit includes a driving transistor including a gate electrode, a first current terminal, and a second current terminal; a light emitting element that emits light at a luminance corresponding to a magnitude of current supplied through the driving transistor; A first transistor connected between the gate electrode of the driving transistor, a first current terminal of the driving transistor, a second transistor for conducting the gate electrode of the driving transistor, and a first current terminal and a light emitting element. A third transistor inserted between one terminal and a fourth transistor inserted between the power supply line and one terminal of the light emitting element;
The driving circuit turns on the first transistor, the second transistor, and the fourth transistor during a light emitting period of the light emitting element, shifts to a light extinction period, and includes the first transistor, the second transistor, and the third transistor. And writing the extinction power supply to the gate electrode of the driving transistor through the fourth transistor and turning off the third transistor to correct the threshold voltage of the driving transistor and to threshold the voltage of the gate electrode of the driving transistor. This is an electro-optical device configured to be driven to a voltage reflecting a value voltage.
Further, the present technology is an electronic apparatus including the above-described electro-optical device.
Further, the present technology is configured to provide a signal line, a relay line, a scanning line, a power supply line for supplying extinction power, a first capacitor connected between the signal line and the relay line, a relay line and the scanning line. Having a pixel circuit provided corresponding to the, a driving circuit for driving the pixel circuit,
The pixel circuit includes a driving transistor including a gate electrode, a first current terminal, and a second current terminal; a light emitting element that emits light at a luminance corresponding to a magnitude of current supplied through the driving transistor; A first transistor connected between the gate electrode of the driving transistor, a first current terminal of the driving transistor, a second transistor for conducting the gate electrode of the driving transistor, and a first current terminal and a light emitting element. A third transistor inserted between one terminal and a fourth transistor inserted between the power supply line and one terminal of the light emitting element;
The driving circuit turns on the first transistor, the second transistor, and the fourth transistor during a light emitting period of the light emitting element, shifts to a light extinction period, and includes the first transistor, the second transistor, and the third transistor. And writing the extinction power supply to the gate electrode of the driving transistor through the fourth transistor and turning off the third transistor to correct the threshold voltage of the driving transistor and to threshold the voltage of the gate electrode of the driving transistor. This is a method for driving an electro-optical device that drives to a voltage reflecting a value voltage.

　少なくとも一つの実施形態によれば、より少ない素子数でもって、しきい値補正が可能な画素回路を実現できる。なお、ここに記載された効果は必ずしも限定されるものではなく、本技術中に記載されたいずれかの効果又はそれらと異質な効果であっても良い。また、以下の説明における例示された効果により本技術の内容が限定して解釈されるものではない。 According to at least one embodiment, a pixel circuit capable of threshold value correction can be realized with a smaller number of elements. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present technology or an effect different from them. In addition, the contents of the present technology are not construed as being limited by the effects illustrated in the following description.

図１は本技術による画素回路の一実施形態の接続図である。FIG. 1 is a connection diagram of an embodiment of a pixel circuit according to the present technology. 図２は図１の構成の説明のためのタイミングチャートである。FIG. 2 is a timing chart for explaining the configuration of FIG. 図３は従来の画素回路の一例の接続図である。FIG. 3 is a connection diagram of an example of a conventional pixel circuit. 図４は従来の画素回路の説明のためのタイミングチャートである。FIG. 4 is a timing chart for explaining a conventional pixel circuit.

　以下に説明する実施形態は、本技術の好適な具体例であり、技術的に好ましい種々の限定が付されている。しかしながら、本技術の範囲は、以下の説明において、特に本技術を限定する旨の記載がない限り、これらの実施形態に限定されないものとする。
　なお、本技術の説明は、下記の順序にしたがってなされる。
＜１．従来の構成＞
＜２．本技術の一実施形態＞
＜３．変形例＞
＜４．応用例＞ The embodiments described below are preferable specific examples of the present technology, and various technically preferable limitations are added. However, the scope of the present technology is not limited to these embodiments unless otherwise specified in the following description.
The description of the present technology will be given in the following order.
<1. Conventional configuration>
<2. One embodiment of the present technology>
<3. Modification>
<4. Application>

＜１．従来の構成＞
　本技術の一実施形態の説明に先立って特許文献１に記載されている従来の構成について説明する。図３は、従来の画素回路を示し、図４は、その動作を示すタイミングチャートである。図示しないが、電気光学装置は、表示パネルと、表示パネルの動作を制御する制御回路を備える。表示パネルは、複数の画素回路と、当該画素回路を駆動する駆動回路とを備える。表示パネルが備える複数の画素回路及び駆動回路は、シリコン基板に形成され、画素回路には、発光素子の一例であるＯＬＥＤが用いられる。 <1. Conventional configuration>
Prior to the description of an embodiment of the present technology, a conventional configuration described in Patent Document 1 will be described. FIG. 3 shows a conventional pixel circuit, and FIG. 4 is a timing chart showing its operation. Although not shown, the electro-optical device includes a display panel and a control circuit for controlling the operation of the display panel. The display panel includes a plurality of pixel circuits and a driving circuit for driving the pixel circuits. A plurality of pixel circuits and a driver circuit included in the display panel are formed over a silicon substrate, and an OLED that is an example of a light-emitting element is used for the pixel circuit.

　制御回路には、デジタルの画像データ同期信号に同期して供給される。画像データは、表示パネルで表示すべき画像の画素の階調レベルを例えば８ビットで規定するデータである。また、同期信号とは、垂直同期信号、水平同期信号、及び、ドットクロック信号を含む信号である。制御回路は、同期信号に基づいて、各種制御信号を生成し、これを表示パネルに対して供給する。また、制御回路は電圧生成回路を含む。電圧生成回路は、表示パネルに対して、各種電位を供給する。さらに、制御回路は、画像データに基づいて、アナログの画像信号を生成する。 The control circuit is supplied in synchronization with the digital image data synchronization signal. The image data is data that defines the gradation level of the pixel of the image to be displayed on the display panel by, for example, 8 bits. The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. The control circuit generates various control signals based on the synchronization signal, and supplies the control signals to the display panel. Further, the control circuit includes a voltage generation circuit. The voltage generation circuit supplies various potentials to the display panel. Further, the control circuit generates an analog image signal based on the image data.

　表示パネルは、表示部と、これを駆動する駆動回路を備える。表示部には、表示すべき画像の画素に対応した画素回路がマトリクス状に配列されている。すなわち、表示部において、Ｍ行の走査線が図において横方向（Ｘ方向）に延在して設けられ、また、３列毎にグループ化された（３Ｎ）列の信号線が図において縦方向（Ｙ方向）に延在し、かつ、各走査線と互いに絶縁を保って設けられている。画素回路は、縦Ｍ行×横（３Ｎ）列でマトリクス状に配列されている。 The display panel includes a display unit and a driving circuit for driving the display unit. In the display unit, pixel circuits corresponding to pixels of an image to be displayed are arranged in a matrix. That is, in the display unit, M rows of scanning lines are provided extending in the horizontal direction (X direction) in the figure, and (3N) columns of signal lines grouped every three columns are arranged in the vertical direction in the figure. (Y direction), and is provided so as to be insulated from each scanning line. The pixel circuits are arranged in a matrix with M rows and 3N columns.

　各画素回路は、互いに同一構成を有する。図３を参照して画素回路１１について説明する。信号線１２－１には転送容量（第１容量）Ｃs2の一方の電極と、第５トランジスタＡＺ３のソース及びドレインの一方とが接続されている。また、転送容量Ｃs2の他方の電極と、第５トランジスタＡＺ３のソース及びドレインの他方とは、中継線１２－２に接続されている。つまり、信号線１２－１と中継線１２－２との間には、転送容量Ｃs2と第５トランジスタＡＺ３とが並列に接続される。 Each pixel circuit has the same configuration as each other. The pixel circuit 11 will be described with reference to FIG. One electrode of a transfer capacitance (first capacitance) Cs2 and one of a source and a drain of the fifth transistor AZ3 are connected to the signal line 12-1. The other electrode of the transfer capacitor Cs2 and the other of the source and the drain of the fifth transistor AZ3 are connected to the relay line 12-2. That is, the transfer capacitor Cs2 and the fifth transistor AZ3 are connected in parallel between the signal line 12-1 and the relay line 12-2.

　また、画素回路１１は、中継線１２－２に対して接続される。すなわち、画素回路１１には、信号線１２－１及び中継線１２－２を介して、指定階調に応じた階調電位が供給される。 {Circle around (2)} The pixel circuit 11 is connected to the relay line 12-2. That is, a gradation potential corresponding to the designated gradation is supplied to the pixel circuit 11 via the signal line 12-1 and the relay line 12-2.

　画素容量Ｃs1及び転送容量Ｃs2は、それぞれ２つの電極を有する。第１トランジスタＷＳは、ゲートが走査線１６に接続され、ソース及びドレインの一方が、中継線１２－２に接続されている。また、第１トランジスタＷＳは、ソースまたはドレインの他方が、駆動トランジスタＤrvのゲートと、画素容量Ｃs1の一方の電極に、それぞれ接続されている。すなわち、第１トランジスタＷＳは、駆動トランジスタＤrvのゲートと転送容量Ｃs2の第２電極との間に接続されている。そして、第１トランジスタＷＳは、駆動トランジスタＤrvのゲートと、中継線１２－２に接続された転送容量Ｃs2の第２電極との間の接続を制御するトランジスタとして機能する。 Each of the pixel capacitance Cs1 and the transfer capacitance Cs2 has two electrodes. The first transistor WS has a gate connected to the scanning line 16 and one of a source and a drain connected to the relay line 12-2. In the first transistor WS, the other of the source and the drain is connected to the gate of the driving transistor Drv and one electrode of the pixel capacitance Cs1, respectively. That is, the first transistor WS is connected between the gate of the driving transistor Drv and the second electrode of the transfer capacitor Cs2. The first transistor WS functions as a transistor that controls the connection between the gate of the driving transistor Drv and the second electrode of the transfer capacitor Cs2 connected to the relay line 12-2.

　駆動トランジスタＤrvは、そのソース（第２電流端）が給電線１５に接続され、そのドレイン（第１電流端）は、第２トランジスタＡＺ２のソースまたはドレインの一方と、第３トランジスタＤＳのソースとに接続されている。給電線１５には、画素回路１１において電源の高位側となる電位ＶＣＣＰが給電される。駆動トランジスタＤrvのゲート及びソース間の電圧に応じた電流が流れる。 The drive transistor Drv has its source (second current terminal) connected to the power supply line 15, and its drain (first current terminal) connected to one of the source or drain of the second transistor AZ2 and the source of the third transistor DS. It is connected to the. The power supply line 15 is supplied with a potential VCCP which is a higher side of the power supply in the pixel circuit 11. A current flows according to the voltage between the gate and the source of the driving transistor Drv.

　第２トランジスタＡＺ２は、駆動トランジスタＤrvのゲートとドレインとの間の接続を制御するスイッチングトランジスタとして機能する。第２トランジスタＡＺ２は、第１トランジスタＷＳを介して駆動トランジスタＤrvのゲート及びドレインの間を導通させるためのトランジスタである。 The second transistor AZ2 functions as a switching transistor that controls the connection between the gate and the drain of the drive transistor Drv. The second transistor AZ2 is a transistor for conducting between the gate and the drain of the driving transistor Drv via the first transistor WS.

　第３トランジスタＤＳは、駆動トランジスタＤrvのドレインと、ＯＬＥＤのアノードとの間の接続を制御する、スイッチングトランジスタとして機能する。第４トランジスタＡＺ１は、ゲートが制御線に接続され、制御信号が供給される。また、第４トランジスタＡＺ１のドレインは消光用電源供給線としての給電線１３に接続されて消光用電位Ｖssに保たれている。消光用電位Ｖssは、ＯＬＥＤを消光状態に保つための電圧である。この第４トランジスタＡＺ１は、給電線１３と、ＯＬＥＤのアノードとの間の接続を制御するスイッチングトランジスタとして機能する。 (3) The third transistor DS functions as a switching transistor that controls the connection between the drain of the drive transistor Drv and the anode of the OLED. The fourth transistor AZ1 has a gate connected to the control line and is supplied with a control signal. The drain of the fourth transistor AZ1 is connected to a power supply line 13 as a power supply line for extinction, and is maintained at an extinction potential Vss. The extinction potential Vss is a voltage for keeping the OLED in an extinction state. The fourth transistor AZ1 functions as a switching transistor that controls connection between the power supply line 13 and the anode of the OLED.

　第５トランジスタＡＺ３は、ゲートに制御信号が供給される。また、第５トランジスタＡＺ３は、ソース及びドレインの一方が、中継線１２－２と接続され、中継線１２－２を介して転送容量Ｃs2の第２電極及び第２トランジスタＡＺ２のソース及びドレインの他方に接続されている。また、第５トランジスタＡＺ３は、ソース及びドレインの他方が、信号線１２－１と接続されている。この第５トランジスタＡＺ３は、主として、信号線１２－１と中継線１２－２との間の接続を制御するスイッチングトランジスタとして機能する。 (5) A control signal is supplied to the gate of the fifth transistor AZ3. One of a source and a drain of the fifth transistor AZ3 is connected to the relay line 12-2, and the other of the source and the drain of the second transistor AZ2 and the second electrode of the transfer capacitor Cs2 via the relay line 12-2. It is connected to the. In the fifth transistor AZ3, the other of the source and the drain is connected to the signal line 12-1. The fifth transistor AZ3 mainly functions as a switching transistor that controls connection between the signal line 12-1 and the relay line 12-2.

　画素容量Ｃs1は、一方の電極が駆動トランジスタＤrvのゲートに接続され、他方の電極が給電線１５（電位ＶＣＣＰ）に接続される。画素容量Ｃs1は、駆動トランジスタＤrvのゲート・ソース間の電圧を保持する保持容量として機能する。なお、画素容量Ｃs1としては、駆動トランジスタＤrvのゲートに寄生する容量を用いても良いし、シリコン基板において互いに異なる導電層で絶縁層を挟持することによって形成される容量を用いても良い。 The pixel capacitance Cs1 has one electrode connected to the gate of the drive transistor Drv and the other electrode connected to the power supply line 15 (potential VCCP). The pixel capacitance Cs1 functions as a storage capacitor that holds a voltage between the gate and the source of the drive transistor Drv. Note that the pixel capacitance Cs1 may be a capacitance parasitic on the gate of the driving transistor Drv, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.

　ＯＬＥＤのアノードは、画素回路１１毎に個別に設けられる画素電極である。これに対して、ＯＬＥＤのカソードは、全ての画素回路１１に対して共通に設けられる共通電極であり、画素回路１１において電源の低位側となる電位Ｖcathに保たれている。ＯＬＥＤは、シリコン基板において、アノードと光透過性を有するカソードで白色有機ＥＬ層を挟持した素子である。そして、ＯＬＥＤの出射側（カソード側）にはＲＧＢのいずれかに対応したカラーフィルターが重ねられる。 The anode of the OLED is a pixel electrode provided individually for each pixel circuit 11. On the other hand, the cathode of the OLED is a common electrode provided in common to all the pixel circuits 11, and is maintained at the potential Vcath on the lower side of the power supply in the pixel circuits 11. An OLED is an element in which a white organic EL layer is sandwiched between an anode and a light-transmissive cathode on a silicon substrate. A color filter corresponding to one of RGB is superimposed on the emission side (cathode side) of the OLED.

　このようなＯＬＥＤにおいて、アノードからカソードに電流が流れると、アノードから注入された正孔とカソードから注入された電子とが有機ＥＬ層で再結合して励起子が生成され、白色光が発生する。このときに発生した白色光は、シリコン基板（アノード）とは反対側のカソードを透過し、カラーフィルターによる着色を経て、観察者側に視認される。 In such an OLED, when a current flows from the anode to the cathode, the holes injected from the anode and the electrons injected from the cathode are recombined in the organic EL layer to generate excitons, thereby generating white light. . The white light generated at this time passes through the cathode on the opposite side of the silicon substrate (anode), is colored by a color filter, and is visually recognized by the observer.

　図４の駆動タイミングチャートを参照して従来の画素回路の動作の概略を説明する。１水平走査期間は、発光期間と、消光期間と、初期化期間と、Ｖth補正期間と、信号書込期間とに分けられる。時間的には、発光期間→消光期間→初期化期間→Ｖth補正期間→書込期間→発光期間というサイクルの繰り返しとなる。図４は、画素回路１１を構成するトランジスタのオン／オフの状態を示している。ハイレベルがトランジスタのオフ状態を表し、ローレベルがトランジスタのオン状態を表している。また、Ｇａｔｅは、駆動トランジスタＤrvのゲート電位を表す。 (4) An outline of the operation of the conventional pixel circuit will be described with reference to the drive timing chart of FIG. One horizontal scanning period is divided into a light emission period, a light extinction period, an initialization period, a Vth correction period, and a signal writing period. In terms of time, a cycle of light emission period → extinction period → initialization period → Vth correction period → writing period → light emission period is repeated. FIG. 4 shows the on / off state of the transistors constituting the pixel circuit 11. A high level indicates the off state of the transistor, and a low level indicates the on state of the transistor. Gate represents the gate potential of the driving transistor Drv.

　発光期間では、第３トランジスタＤＳがオンし、トランジスタＷＳ、ＡＺ２，ＡＺ１，ＡＺ３がオフする。これにより、駆動トランジスタＤrvは、画素容量Ｃs1によって保持された電圧、すなわちゲート・ソース間の電圧に応じた駆動電流をＯＬＥＤに供給する。ＯＬＥＤに対して、駆動トランジスタＤrvによって各画素の指定階調に応じた階調電位に応じた電流が供給され、当該電流に応じた輝度でＯＬＥＤが発光する。ここで、発光期間において、トランジスタＯＦＳがオフし、トランスミッションゲート４２がオフする。 (4) In the light emitting period, the third transistor DS is turned on, and the transistors WS, AZ2, AZ1, and AZ3 are turned off. As a result, the drive transistor Drv supplies the OLED with a drive current corresponding to the voltage held by the pixel capacitor Cs1, that is, the gate-source voltage. A current corresponding to a gradation potential corresponding to a designated gradation of each pixel is supplied to the OLED by the driving transistor Drv, and the OLED emits light at a luminance corresponding to the current. Here, in the light emitting period, the transistor OFS is turned off, and the transmission gate 42 is turned off.

　発光期間からトランジスタＤＳがオフし、トランジスタＡＺ１がオンとなり、消光期間に移行する。これにより、ＯＬＥＤに供給される電流の経路が遮断されるので、ＯＬＥＤは、消光状態となる。 (4) The transistor DS is turned off from the light emitting period, the transistor AZ1 is turned on, and the light emitting period is started. As a result, the path of the current supplied to the OLED is interrupted, so that the OLED is turned off.

　その後の初期化期間では、信号線１２－１に接続されているトランジスタＯＦＳ、トランジスタＷＳ、トランジスタＡＺ３がオンとされ、信号線１２－１にＶth補正基準電圧Ｖofs を書きこみ初期化動作を行う。これと共に、第５トランジスタＡＺ３がオンしているため、信号線１２－１と中継線１２－２とが接続され、転送容量Ｃs2の第２電極も初期電位に設定される。これにより、転送容量Ｃs2が初期化される。 {In the subsequent initialization period, the transistor OFS, the transistor WS, and the transistor AZ3 connected to the signal line 12-1 are turned on, and the Vth correction reference voltage Vofs} is written to the signal line 12-1 to perform an initialization operation. At the same time, since the fifth transistor AZ3 is on, the signal line 12-1 and the relay line 12-2 are connected, and the second electrode of the transfer capacitor Cs2 is also set to the initial potential. Thereby, the transfer capacity Cs2 is initialized.

　上述した初期化期間が終わると、Ｖth補正期間となる。Ｖth補正期間では、トランジスタＷＳ、ＡＺ２、ＡＺ１がオンし、第３トランジスタＤＳ、ＡＺ３がオフする。このとき、駆動トランジスタＤrvのゲートは、第１トランジスタＷＳと第２トランジスタＡＺ２とを介して自身のドレインに接続され、駆動トランジスタＤrvにはドレイン電流が流れてゲートを充電する。すなわち、駆動トランジスタＤrvのドレインとゲートとは、中継線１２－２に接続され、駆動トランジスタＤrvのしきい値電圧をＶthとすると、駆動トランジスタＤrvのゲートの電位Ｖｇは、（ＶＣＣＰ－Ｖth）に収束し、Ｖth補正が完了する。 (4) When the above-described initialization period ends, the Vth correction period starts. In the Vth correction period, the transistors WS, AZ2, and AZ1 turn on, and the third transistors DS and AZ3 turn off. At this time, the gate of the driving transistor Drv is connected to its own drain via the first transistor WS and the second transistor AZ2, and a drain current flows through the driving transistor Drv to charge the gate. That is, the drain and the gate of the driving transistor Drv are connected to the relay line 12-2, and when the threshold voltage of the driving transistor Drv is Vth, the potential Vg of the gate of the driving transistor Drv becomes (VCCP-Vth). The convergence is completed, and the Vth correction is completed.

　ここで、Ｖth補正期間においては、トランジスタＯＦＳがオンし、トランスミッションゲート１４がオフする。このとき、中継線１２－２が短いため、中継線１２－２に付随する寄生容量への充電又は放電に要する時間が短縮され、Ｖth補正期間自体が短縮される。 Here, in the Vth correction period, the transistor OFS is turned on and the transmission gate 14 is turned off. At this time, since the length of the relay line 12-2 is short, the time required for charging or discharging the parasitic capacitance associated with the relay line 12-2 is reduced, and the Vth correction period itself is shortened.

　なお、第３トランジスタＤＳはオフしているため、駆動トランジスタＤrvのドレインはＯＬＥＤと電気的に非接続である。また、初期化期間と同様、第４トランジスタＡＺ１がオンすることによって、ＯＬＥＤのアノードと給電線１３とが接続され、アノードの電位が消光用電位Ｖssに設定される。 (4) Since the third transistor DS is off, the drain of the drive transistor Drv is not electrically connected to the OLED. Similarly to the initialization period, when the fourth transistor AZ1 is turned on, the anode of the OLED is connected to the power supply line 13, and the potential of the anode is set to the extinction potential Vss.

　上述したＶth補正期間を終えると、書込期間が開始する。書込期間では、画素回路１１においてはトランジスタＷＳ、ＡＺ１がオンする一方、トランジスタＡＺ２、ＤＳ、ＡＺ３がオフする。書込期間においては、トランジスタＯＦＳがオフし、トランスミッションゲート１４がオンする。このため、転送容量Ｃs2の一方の電極に対して階調電位が供給される。そして、階調電位がレベルシフトされた信号が、駆動トランジスタＤrvのゲートに供給され、画素容量Ｃs1に書き込まれる。 (4) When the above-described Vth correction period ends, the writing period starts. In the writing period, in the pixel circuit 11, the transistors WS and AZ1 are turned on, while the transistors AZ2, DS and AZ3 are turned off. In the writing period, the transistor OFS turns off and the transmission gate 14 turns on. Therefore, the gradation potential is supplied to one electrode of the transfer capacitor Cs2. Then, a signal in which the gradation potential is level-shifted is supplied to the gate of the drive transistor Drv, and is written into the pixel capacitance Cs1.

　なお、第３トランジスタＤＳはオフしているため、駆動トランジスタＤrvのドレインはＯＬＥＤと電気的に非接続である。また、初期化期間と同様、第４トランジスタＡＺ１がオンすることによって、ＯＬＥＤのアノードと給電線１３とが接続され、アノードの電位が消光用電位Ｖssに初期化される。そして、上述した発光期間に移行する。 (4) Since the third transistor DS is off, the drain of the drive transistor Drv is not electrically connected to the OLED. Similarly to the initialization period, when the fourth transistor AZ1 is turned on, the anode of the OLED is connected to the power supply line 13, and the potential of the anode is initialized to the extinction potential Vss. Then, the process proceeds to the above-described light emission period.

＜２．本技術の一実施形態＞
　上述した従来の画素回路１１は、第１トランジスタＷＳがオンの状態で、Ｖth補正動作が行われる。したがって、Ｖth補正の電圧は、画素容量Ｃs1のみならず、中継線１２－２の寄生容量Ｃｐに書き込まれる。この中継線１２－２は、複数画素で共有化された構成になっており、共有する画素数に応じて容量値が変化する。共有する画素数を少なくすると容量値が小さくなり、Ｖth補正スピードを速くすることができ、高速駆動に有利な動作となる。一方で、トランジスタ数と容量素子を合わせて８素子で構成する必要があり、素子数が多く、高精細レイアウトの妨げになるというデメリットがある。 <2. One embodiment of the present technology>
In the conventional pixel circuit 11 described above, the Vth correction operation is performed with the first transistor WS turned on. Therefore, the Vth correction voltage is written not only to the pixel capacitance Cs1 but also to the parasitic capacitance Cp of the relay line 12-2. The relay line 12-2 is configured to be shared by a plurality of pixels, and the capacitance value changes according to the number of shared pixels. When the number of shared pixels is reduced, the capacitance value is reduced, the Vth correction speed can be increased, and an operation advantageous for high-speed driving is achieved. On the other hand, it is necessary to configure the number of transistors and the capacitance element as eight elements in total, and there are disadvantages in that the number of elements is large and a high definition layout is hindered.

　本技術は、かかる画素回路の機能を保ちつつ、素子数を削減する画素回路を提供する。図１は、本技術の一実施形態の回路図である。一実施形態は、図３の回路構成における第５トランジスタＡＺ３を削除した構成を有する。また、信号線１２－１に対してトランジスタＲＳＴを介して所定電圧ｒｓｔを印加するようになされている。トランジスタＲＳＴのゲートに制御信号が供給される。 The present technology provides a pixel circuit that reduces the number of elements while maintaining the function of the pixel circuit. FIG. 1 is a circuit diagram of an embodiment of the present technology. One embodiment has a configuration in which the fifth transistor AZ3 in the circuit configuration of FIG. 3 is omitted. Further, a predetermined voltage rst is applied to the signal line 12-1 via the transistor RST. A control signal is supplied to the gate of the transistor RST.

　図２は、本技術の一実施形態の駆動タイミングを示す。発光期間では、第３トランジスタＤＳがオンし、トランジスタＷＳ、ＡＺ１，ＡＺ２がオフする。これにより、駆動トランジスタＤrvは、画素容量Ｃs1によって保持された電圧、すなわちゲート・ソース間の電圧に応じた駆動電流をＯＬＥＤに供給する。ＯＬＥＤに対して、駆動トランジスタＤrvによって各画素の指定階調に応じた階調電位に応じた電流が供給され、当該電流に応じた輝度でＯＬＥＤが発光する。ここで、発光期間において、トランジスタＲＳＴがオフし、トランスミッションゲート４２がオフする。 FIG. 2 shows the drive timing according to an embodiment of the present technology. In the light emitting period, the third transistor DS is turned on, and the transistors WS, AZ1, and AZ2 are turned off. As a result, the drive transistor Drv supplies the OLED with a drive current corresponding to the voltage held by the pixel capacitor Cs1, that is, the voltage between the gate and the source. A current corresponding to a gradation potential corresponding to a designated gradation of each pixel is supplied to the OLED by the driving transistor Drv, and the OLED emits light at a luminance corresponding to the current. Here, in the light emitting period, the transistor RST is turned off, and the transmission gate 42 is turned off.

　発光期間において、第１トランジスタＷＳ、第４トランジスタＡＺ１、第２トランジスタＡＺ２及びトランジスタＲＳＴをオンにし、消光状態に移行する。これと共に、Ｖth補正準備のために、トランジスタＡＺ２、トランジスタＤＳ及びトランジスタＡＺ１を介して給電線１３の消光用電位Ｖssを書き込む。 (4) In the light emitting period, the first transistor WS, the fourth transistor AZ1, the second transistor AZ2, and the transistor RST are turned on, and the state shifts to the extinction state. At the same time, the extinction potential Vss of the power supply line 13 is written via the transistor AZ2, the transistor DS, and the transistor AZ1 in preparation for Vth correction.

　ここで、消光用電位Ｖssは、ＯＬＥＤを消光しつつ、Ｖth補正準備時に駆動トランジスタＤrvがターンオンするような電圧設定となされている。 Here, the extinction potential Vss is set such that the OLED is extinguished and the drive transistor Drv is turned on during Vth correction preparation.

　ここで、トランジスタＡＺ１、ＡＺ２及びＤＳをオンとするための電圧をＶ_Lowと表し、トランジスタＡＺ１、ＡＺ２及びＤＳのしきい値電圧をＶth(AZ1) ＝Ｖth(AZ2) ＝Ｖth(DS)＝Ｖthとすると、駆動トランジスタＤrvのゲート電圧Ｖｇは、次の式で表される。 Here, the voltage for turning on the transistors AZ1, AZ2, and DS is represented as V_Low, and the threshold voltages of the transistors AZ1, AZ2, and DS are expressed as Vth (AZ1) = Vth (AZ2) = Vth (DS) = Vth. Then, the gate voltage Vg of the driving transistor Drv is expressed by the following equation.

　Ｖss＜｜Ｖth｜＋Ｖ_Lowの時、Ｖｇ＝｜Ｖth｜＋Ｖ_Low
　Ｖss≧｜Ｖth｜＋Ｖ_Lowの時、Ｖｇ＝Ｖss When Vss <| Vth | + V_Low, Vg = | Vth | + V_Low
When Vss ≧ | Vth | + V_Low, Vg = Vss

　その後、第３トランジスタＤＳをオフすることによって、Ｖth補正期間が開始する。第３トランジスタＤＳはオフすると、駆動トランジスタＤrvのドレインはＯＬＥＤと非接続となる。駆動トランジスタＤrvのゲートが（ＶＣＣＰ－Ｖth）に収束してＶth補正期間か完了する。 (4) Thereafter, the third transistor DS is turned off to start the Vth correction period. When the third transistor DS is turned off, the drain of the drive transistor Drv is disconnected from the OLED. The gate of the driving transistor Drv converges to (VCCP-Vth) and the Vth correction period is completed.

　Ｖth補正期間後に書込期間に移行する。書込期間では、第１トランジスタＷＳがオンし、第３トランジスタＤＳがオフし、第４トランジスタＡＺ１がオンし、第３トランジスタＡＺ３及びトランジスタＲＳＴがオフする。Ｖsig 電圧がＶＣＣＰから（ＶＣＣＰ－Ｖsig）に遷移すると、ゲート電圧は、次の式で表すものに遷移する。 After the Vth correction period, the operation shifts to the writing period. In the writing period, the first transistor WS is turned on, the third transistor DS is turned off, the fourth transistor AZ1 is turned on, and the third transistor AZ3 and the transistor RST are turned off. When the voltage Vsig transitions from VCCP to (VCCP-Vsig), the gate voltage transitions to one represented by the following equation.

　ＶＣＣＰ－Ｖth－Ｖdata×Ｃs2／（Ｃs1＋Ｃs2） VCCP-Vth-Vdata × Cs2 / (Cs1 + Cs2)

　このように、駆動トランジスタＤrvのゲート電圧がＶthを反映した電圧となり、発光時にＶthがキャンセルされる。その後、第１トランジスタＷＳ及び第４トランジスタＡＺ１がオフ、第３トランジスタＤＳがオンとなり、発光期間に移行する。 Thus, the gate voltage of the driving transistor Drv becomes a voltage reflecting Vth, and Vth is canceled at the time of light emission. After that, the first transistor WS and the fourth transistor AZ1 are turned off, the third transistor DS is turned on, and the light emitting period is started.

　上述したように、従来の６トランジスタ２コンデンサの構成からトランジスタＡＺ３を削除して５トランジスタ２コンデンサの構成としても、Ｖth補正準備電圧をＶssから書き込む駆動タイミングとすることによって、従来の構成と同様にＶth補正動作を行うことができる。すなわち、本技術の画素回路は、Ｖth補正準備時に、Ｖth補正準備電圧を信号線から書き込むのではなく、発光素子としてのＯＬＥＤのアノードにスイッチトランジスタを介して接続される電源を用いるものである。このように素子数を減少することができるので、高精細画素レイアウトに有利な画素回路を実現することができる。 As described above, even when the transistor AZ3 is deleted from the conventional six-transistor two-capacitor configuration and the five-transistor two-capacitor configuration is used, the drive timing at which the Vth correction preparation voltage is written from Vss is used. Vth correction operation can be performed. That is, the pixel circuit of the present technology uses a power supply connected to the anode of an OLED as a light emitting element via a switch transistor instead of writing a Vth correction preparation voltage from a signal line at the time of Vth correction preparation. Since the number of elements can be reduced in this way, a pixel circuit that is advantageous for a high-definition pixel layout can be realized.

＜３．変形例＞
　以上、本技術の実施形態について具体的に説明したが、上述の各実施形態に限定されるものではなく、本技術の技術的思想に基づく各種の変形が可能である。例えば次に述べるような各種の変形が可能である。また、次に述べる変形の態様は、任意に選択された一または複数を、適宜に組み合わせることもできる。また、上述の実施形態の構成、方法、工程、形状、材料および数値などは、本技術の主旨を逸脱しない限り、互いに組み合わせることが可能である。 <3. Modification>
Although the embodiments of the present technology have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present technology are possible. For example, various modifications as described below are possible. In addition, one or a plurality of arbitrarily selected aspects of the modifications described below can be appropriately combined. The configurations, methods, steps, shapes, materials, numerical values, and the like of the above-described embodiments can be combined with each other without departing from the gist of the present technology.

　上述した実施形態では、トランジスタをＰチャネル型で統一したが、Ｎチャネル型で統一しても良い。また、Ｐチャネル型及びＮチャネル型を適宜組み合わせても良い。
　上述した実施形態では、電気光学素子として発光素子であるＯＬＥＤを例示したが、例えば無機発光ダイオードやＬＥＤ（Light Emitting Diode）など、電流に応じた輝度で発光するものであれば良い。 In the above-described embodiment, the transistors are unified with the P-channel type, but may be unified with the N-channel type. Further, the P-channel type and the N-channel type may be appropriately combined.
In the above-described embodiment, the OLED which is a light emitting element is exemplified as the electro-optical element. However, an electroluminescent element such as an inorganic light emitting diode or an LED (Light Emitting Diode) may be used as long as it emits light at a luminance according to current.

＜４．応用例＞
　次に、実施形態等や応用例に係る電気光学装置を適用した電子機器について説明する。電気光学装置は、画素が小サイズで高精細な表示な用途に向いている。そこで、電子機器として、ヘッドマウント・ディスプレイ、スマートメガネ、スマートフォン、デジタルカメラの電子式ビューファインダー等の表示装置に適用することができる。 <4. Application>
Next, an electronic apparatus to which the electro-optical device according to the embodiment or the application example is applied will be described. The electro-optical device is suitable for applications in which pixels have a small size and display with high definition. Therefore, the present invention can be applied to display devices such as head mounted displays, smart glasses, smart phones, and electronic viewfinders of digital cameras as electronic devices.

　なお、本技術は、以下のような構成も取ることができる。
（１）
　信号線と、
　中継線と、
　走査線と、
　消光用電源を供給する給電線と、
　前記信号線及び前記中継線の間に接続された転送容量と、
　前記中継線と前記走査線とに対応して設けられた画素回路と、
　前記画素回路を駆動する駆動回路と、
　を有し、
　前記画素回路は、
　ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、
　前記駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、
　前記中継線と、前記駆動トランジスタの前記ゲート電極との間に接続された第１トランジスタと、
　前記駆動トランジスタの前記第１電流端と、前記駆動トランジスタの前記ゲート電極とを導通させるための第２トランジスタと、
　前記第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、
　前記給電線と前記発光素子の一方の端子間に挿入された第４のトランジスタと
　を含み、
　前記駆動回路は、
　前記発光素子の発光期間において、前記第１のトランジスタ、前記第２のトランジスタ及び前記第４のトランジスタをオンとし、消光期間に移行すると共に、前記第１のトランジスタ、前記第２のトランジスタ、前記第３のトランジスタ及び前記第４のトランジスタを通じて、前記消光用電源を前記駆動トランジスタのゲート電極に書き込み、
　前記第３のトランジスタをオフすることで、前記駆動トランジスタのしきい値電圧を補正し、前記駆動トランジスタのゲート電極の電圧を前記しきい値電圧を反映した電圧とするように駆動するように構成された
　電気光学装置。
（２）
　前記消光用電源は、前記発光素子を消光しつつ、前記消光期間に前記駆動トランジスタがターンオンするように設定された
　（１）に記載の電気光学装置。
（３）
　一方の電極が前記駆動トランジスタのゲート電極に接続され、他方の電極が電圧供給線に接続され、前記駆動トランジスタのゲート・ソース間の電圧を保持する画素容量を有する
　（１）又は（２）に記載の電気光学装置。
（４）
　（１）に記載の電気光学装置を備える、
　電子機器。
（５）
　信号線と、
　中継線と、
　走査線と、
　消光用電源を供給する給電線と、
　前記信号線及び前記中継線の間に接続された第１容量と、
　前記中継線と前記走査線とに対応して設けられた画素回路と、
　前記画素回路を駆動する駆動回路と、
　を有し、
　前記画素回路は、
　ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、
　前記駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、
　前記中継線と、前記駆動トランジスタの前記ゲート電極との間に接続された第１トランジスタと、
　前記駆動トランジスタの前記第１電流端と、前記駆動トランジスタの前記ゲート電極とを導通させるための第２トランジスタと、
　前記第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、
　前記給電線と前記発光素子の一方の端子間に挿入された第４のトランジスタと
　を含み、
　前記駆動回路は、
　前記発光素子の発光期間において、前記第１のトランジスタ、前記第２のトランジスタ及び前記第４のトランジスタをオンとし、消光期間に移行すると共に、前記第１のトランジスタ、前記第２のトランジスタ、前記第３のトランジスタ及び前記第４のトランジスタを通じて、前記消光用電源を前記駆動トランジスタのゲート電極に書き込み、
　前記第３のトランジスタをオフすることで、前記駆動トランジスタのしきい値電圧を補正し、前記駆動トランジスタのゲート電極の電圧を前記しきい値電圧を反映した電圧とするように駆動する
　電気光学装置の駆動方法。
（６）
　前記消光用電源は、前記発光素子を消光しつつ、前記消光期間に前記駆動トランジスタがターンオンするように設定される
　（５）に記載の電気光学装置の駆動方法。
（７）
　前記画素回路が、一方の電極が前記駆動トランジスタのゲート電極に接続され、他方の電極が電圧供給線に接続され、前記駆動トランジスタのゲート・ソース間の電圧を保持する画素容量を有する
　（５）又は（６）に記載の電気光学装置の駆動方法。 Note that the present technology may also have the following configurations.
(1)
Signal lines,
Trunk line,
Scanning lines,
A power supply line for supplying extinction power,
A transfer capacity connected between the signal line and the relay line;
A pixel circuit provided corresponding to the relay line and the scanning line;
A driving circuit for driving the pixel circuit;
Has,
The pixel circuit includes:
A driving transistor having a gate electrode, a first current terminal, and a second current terminal;
A light-emitting element that emits light at a luminance corresponding to the magnitude of the current supplied through the drive transistor;
A first transistor connected between the relay line and the gate electrode of the driving transistor;
A second transistor for conducting the first current terminal of the drive transistor and the gate electrode of the drive transistor;
A third transistor inserted between the first current terminal and one terminal of the light emitting element;
A fourth transistor inserted between the power supply line and one terminal of the light emitting element,
The driving circuit includes:
In a light emitting period of the light emitting element, the first transistor, the second transistor, and the fourth transistor are turned on, and a transition is made to an extinction period, and the first transistor, the second transistor, and the second transistor are turned off. Writing the quenching power supply to the gate electrode of the driving transistor through the third transistor and the fourth transistor;
By turning off the third transistor, the threshold voltage of the drive transistor is corrected, and driving is performed so that the voltage of the gate electrode of the drive transistor reflects the threshold voltage. Electro-optical device.
(2)
The electro-optical device according to (1), wherein the quenching power supply is set such that the driving transistor is turned on during the quenching period while the light emitting element is quenched.
(3)
One of the electrodes is connected to the gate electrode of the drive transistor, and the other electrode is connected to the voltage supply line, and has a pixel capacitance for holding a voltage between the gate and the source of the drive transistor. (1) or (2) An electro-optical device according to claim 1.
(4)
Comprising the electro-optical device according to (1),
Electronics.
(5)
Signal lines,
Trunk line,
Scanning lines,
A power supply line for supplying extinction power,
A first capacitor connected between the signal line and the relay line;
A pixel circuit provided corresponding to the relay line and the scanning line;
A driving circuit for driving the pixel circuit;
Has,
The pixel circuit includes:
A driving transistor having a gate electrode, a first current terminal, and a second current terminal;
A light-emitting element that emits light at a luminance corresponding to the magnitude of the current supplied through the drive transistor;
A first transistor connected between the relay line and the gate electrode of the driving transistor;
A second transistor for conducting the first current terminal of the drive transistor and the gate electrode of the drive transistor;
A third transistor inserted between the first current terminal and one terminal of the light emitting element;
A fourth transistor inserted between the power supply line and one terminal of the light emitting element,
The driving circuit includes:
In a light emitting period of the light emitting element, the first transistor, the second transistor, and the fourth transistor are turned on, and a transition is made to an extinction period, and the first transistor, the second transistor, and the second transistor are turned off. Writing the quenching power supply to the gate electrode of the driving transistor through the third transistor and the fourth transistor;
An electro-optical device that corrects a threshold voltage of the driving transistor by turning off the third transistor, and drives a voltage of a gate electrode of the driving transistor to a voltage reflecting the threshold voltage. Drive method.
(6)
The driving method of the electro-optical device according to (5), wherein the quenching power supply is set such that the driving transistor is turned on during the quenching period while the light emitting element is quenched.
(7)
The pixel circuit has a pixel capacitance that has one electrode connected to the gate electrode of the drive transistor and the other electrode connected to a voltage supply line, and holds a voltage between the gate and the source of the drive transistor. Or the driving method of the electro-optical device according to (6).

　１１・・・画素回路、１２－１・・・信号線、１２－２・・・中継線、１３，１５・・・給電線、１４・・・トランスミッションゲート、１６・・・走査線、ＶＣＣＰ・・・給電線、Ｄrv、ＷＳ，ＡＺ２，ＤＳ，ＡＺ１，ＡＺ３・・・トランジスタ、Ｃs1・・・画素容量、Ｃs2・・・転送容量、Ｖss・・・消光用電位 11 pixel circuit, 12-1 signal line, 12-2 relay line, 13, 15 power supply line, 14 transmission gate, 16 scanning line, VCCP ..Supply line, Drv, WS, AZ2, DS, AZ1, AZ3 ... transistor, Cs1 ... pixel capacitance, Cs2 ... transfer capacitance, Vss ... extinction potential

Claims (7)

　信号線と、
　中継線と、
　走査線と、
　消光用電源を供給する給電線と、
　前記信号線及び前記中継線の間に接続された転送容量と、
　前記中継線と前記走査線とに対応して設けられた画素回路と、
　前記画素回路を駆動する駆動回路と、
　を有し、
　前記画素回路は、
　ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、
　前記駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、
　前記中継線と、前記駆動トランジスタの前記ゲート電極との間に接続された第１トランジスタと、
　前記駆動トランジスタの前記第１電流端と、前記駆動トランジスタの前記ゲート電極とを導通させるための第２トランジスタと、
　前記第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、
　前記給電線と前記発光素子の一方の端子間に挿入された第４のトランジスタと
　を含み、
　前記駆動回路は、
　前記発光素子の発光期間において、前記第１のトランジスタ、前記第２のトランジスタ及び前記第４のトランジスタをオンとし、消光期間に移行すると共に、前記第１のトランジスタ、前記第２のトランジスタ、前記第３のトランジスタ及び前記第４のトランジスタを通じて、前記消光用電源を前記駆動トランジスタのゲート電極に書き込み、
　前記第３のトランジスタをオフすることで、前記駆動トランジスタのしきい値電圧を補正し、前記駆動トランジスタのゲート電極の電圧を前記しきい値電圧を反映した電圧とするように駆動するように構成された
　電気光学装置。 Signal lines,
Trunk line,
Scanning lines,
A power supply line for supplying extinction power,
A transfer capacity connected between the signal line and the relay line;
A pixel circuit provided corresponding to the relay line and the scanning line;
A driving circuit for driving the pixel circuit;
Has,
The pixel circuit includes:
A driving transistor having a gate electrode, a first current terminal, and a second current terminal;
A light-emitting element that emits light at a luminance corresponding to the magnitude of the current supplied through the drive transistor;
A first transistor connected between the relay line and the gate electrode of the driving transistor;
A second transistor for conducting the first current terminal of the drive transistor and the gate electrode of the drive transistor;
A third transistor inserted between the first current terminal and one terminal of the light emitting element;
A fourth transistor inserted between the power supply line and one terminal of the light emitting element,
The driving circuit includes:
In a light emitting period of the light emitting element, the first transistor, the second transistor, and the fourth transistor are turned on, and a transition is made to an extinction period, and the first transistor, the second transistor, and the second transistor are turned off. Writing the quenching power supply to the gate electrode of the driving transistor through the third transistor and the fourth transistor;
By turning off the third transistor, the threshold voltage of the drive transistor is corrected, and driving is performed so that the voltage of the gate electrode of the drive transistor reflects the threshold voltage. Electro-optical device. 　前記消光用電源は、前記発光素子を消光しつつ、前記消光期間に前記駆動トランジスタがターンオンするように設定された
　請求項１に記載の電気光学装置。 The electro-optical device according to claim 1, wherein the quenching power supply is set such that the driving transistor is turned on during the quenching period while quenching the light emitting element. 　一方の電極が前記駆動トランジスタのゲート電極に接続され、他方の電極が電圧供給線に接続され、前記駆動トランジスタのゲート・ソース間の電圧を保持する画素容量を有する
　請求項１に記載の電気光学装置。 2. The electro-optical device according to claim 1, wherein one electrode is connected to a gate electrode of the driving transistor, and the other electrode is connected to a voltage supply line, and has a pixel capacitance that holds a voltage between a gate and a source of the driving transistor. apparatus. 　請求項１に記載の電気光学装置を備える、
　電子機器。 An electro-optical device according to claim 1,
Electronics. 　信号線と、
　中継線と、
　走査線と、
　消光用電源を供給する給電線と、
　前記信号線及び前記中継線の間に接続された第１容量と、
　前記中継線と前記走査線とに対応して設けられた画素回路と、
　前記画素回路を駆動する駆動回路と、
　を有し、
　前記画素回路は、
　ゲート電極、第１電流端、及び第２電流端を備える駆動トランジスタと、
　前記駆動トランジスタを介して供給される電流の大きさに応じた輝度で発光する発光素子と、
　前記中継線と、前記駆動トランジスタの前記ゲート電極との間に接続された第１トランジスタと、
　前記駆動トランジスタの前記第１電流端と、前記駆動トランジスタの前記ゲート電極とを導通させるための第２トランジスタと、
　前記第１電流端及び発光素子の一方の端子間に挿入された第３のトランジスタと、
　前記給電線と前記発光素子の一方の端子間に挿入された第４のトランジスタと
　を含み、
　前記駆動回路は、
　前記発光素子の発光期間において、前記第１のトランジスタ、前記第２のトランジスタ及び前記第４のトランジスタをオンとし、消光期間に移行すると共に、前記第１のトランジスタ、前記第２のトランジスタ、前記第３のトランジスタ及び前記第４のトランジスタを通じて、前記消光用電源を前記駆動トランジスタのゲート電極に書き込み、
　前記第３のトランジスタをオフすることで、前記駆動トランジスタのしきい値電圧を補正し、前記駆動トランジスタのゲート電極の電圧を前記しきい値電圧を反映した電圧とするように駆動する
　電気光学装置の駆動方法。 Signal lines,
Trunk line,
Scanning lines,
A power supply line for supplying extinction power,
A first capacitor connected between the signal line and the relay line;
A pixel circuit provided corresponding to the relay line and the scanning line;
A driving circuit for driving the pixel circuit;
Has,
The pixel circuit includes:
A driving transistor having a gate electrode, a first current terminal, and a second current terminal;
A light-emitting element that emits light at a luminance corresponding to the magnitude of the current supplied through the drive transistor;
A first transistor connected between the relay line and the gate electrode of the driving transistor;
A second transistor for conducting the first current terminal of the drive transistor and the gate electrode of the drive transistor;
A third transistor inserted between the first current terminal and one terminal of the light emitting element;
A fourth transistor inserted between the power supply line and one terminal of the light emitting element,
The driving circuit includes:
In a light emitting period of the light emitting element, the first transistor, the second transistor, and the fourth transistor are turned on, and a transition is made to an extinction period, and the first transistor, the second transistor, and the second transistor are turned off. Writing the quenching power supply to the gate electrode of the driving transistor through the third transistor and the fourth transistor;
An electro-optical device that corrects a threshold voltage of the driving transistor by turning off the third transistor, and drives a voltage of a gate electrode of the driving transistor to a voltage reflecting the threshold voltage. Drive method. 　前記消光用電源は、前記発光素子を消光しつつ、前記消光期間に前記駆動トランジスタがターンオンするように設定される
　請求項５に記載の電気光学装置の駆動方法。 The driving method for an electro-optical device according to claim 5, wherein the quenching power supply is set such that the driving transistor is turned on during the quenching period while the light emitting element is quenched. 　前記画素回路が、一方の電極が前記駆動トランジスタのゲート電極に接続され、他方の電極が電圧供給線に接続され、前記駆動トランジスタのゲート・ソース間の電圧を保持する画素容量を有する
　請求項５に記載の電気光学装置の駆動方法。 6. The pixel circuit according to claim 5, wherein one electrode is connected to a gate electrode of the driving transistor, and the other electrode is connected to a voltage supply line, and has a pixel capacitance that holds a voltage between a gate and a source of the driving transistor. 3. The method for driving an electro-optical device according to claim 1.
PCT/JP2019/032287 2018-08-20 2019-08-19 Electro-optical device, electronic apparatus, and driving method Ceased WO2020040090A1 (en)

Priority Applications (7)

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KR1020217003191A KR102632645B1 (en) 2018-08-20 2019-08-19 Electro-optical devices, electronic devices and driving methods
KR1020257019415A KR20250092288A (en) 2018-08-20 2019-08-19 Electro-optical device, electronic apparatus, and driving method
KR1020247003342A KR102821955B1 (en) 2018-08-20 2019-08-19 Electro-optical device, electronic apparatus, and driving method
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