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WO2020019869A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2020019869A1
WO2020019869A1 PCT/CN2019/089554 CN2019089554W WO2020019869A1 WO 2020019869 A1 WO2020019869 A1 WO 2020019869A1 CN 2019089554 W CN2019089554 W CN 2019089554W WO 2020019869 A1 WO2020019869 A1 WO 2020019869A1
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WIPO (PCT)
Prior art keywords
layer
transistor
substrate
gate
light
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PCT/CN2019/089554
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English (en)
French (fr)
Inventor
欧忠星
杨姗姗
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to US16/628,574 priority Critical patent/US20200381456A1/en
Publication of WO2020019869A1 publication Critical patent/WO2020019869A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates generally to the field of display technology. More specifically, the present disclosure relates to an array substrate, a display device including the array substrate, and a method of manufacturing the array substrate.
  • double-grid technology as a technology that can significantly reduce product costs, has received widespread attention.
  • double gate technology by optimizing the arrangement of the gate line, the data line, and the source driving integrated circuit and the gate driving integrated circuit connected thereto, the cost of the display panel can be reduced as a whole.
  • the gate lines are routed in the same layer in parallel, it is difficult to set the width of the two parallel gate lines and the distance between the gate lines to avoid electrical shorts, high aperture ratios, and transmission. Rate requirements.
  • An aspect of the present disclosure provides an array substrate including a substrate, a plurality of gate line groups disposed on the substrate, and a plurality of pixel units arranged in an array, each gate of the plurality of gate line groups A line group is arranged between two adjacent rows of pixel units, wherein each of the gate line groups includes a first gate line and a second gate line which are insulated from each other.
  • the first gate line is connected to the control electrode of the first transistor.
  • the two gate lines are connected to the control electrode of the second transistor, and the control electrode of the first transistor and the control electrode of the second transistor are disposed in different layers.
  • the first gate line is disposed in the same layer as the gate electrode of the first transistor, and the second gate line is disposed in the same layer as the gate electrode of the second transistor.
  • control electrode of the second transistor is closer to the substrate than the control electrode of the first transistor.
  • the array substrate further includes a plurality of data lines crossing the plurality of gate line groups, wherein each data line is separate from a first pole of a first transistor and a first pole of a second transistor Connected, the first transistor and the second transistor are respectively located on two sides of each data line and adjacent to each data line.
  • the first transistor includes a first insulating layer, a semiconductor layer, a source-drain electrode layer, a second insulating layer, and a first gate layer sequentially disposed on the substrate
  • the second The transistor includes a second gate layer, the first insulating layer, the semiconductor layer, the source-drain electrode layer, and the second insulating layer which are sequentially disposed on the substrate.
  • the first transistor further includes a first light-shielding layer disposed between the substrate and the first insulating layer, and an orthographic projection of the first light-shielding layer on the substrate and The orthographic projection of the active region of the first transistor on the substrate at least partially overlaps.
  • the second transistor further includes a second light-shielding layer disposed between the substrate and the second gate layer, and the orthographic projection of the second light-shielding layer on the substrate An orthographic projection of the active region of the second transistor on the substrate at least partially overlaps.
  • the first light shielding layer and the second light shielding layer are disposed in the same layer.
  • the array substrate further includes a conductive material layer disposed between the first light shielding layer and the second light shielding layer and the substrate.
  • the array substrate further includes a first electrode layer, an insulating material layer, and a second electrode layer sequentially disposed on the substrate, wherein the first electrode layer and the conductive material layer are disposed on a same layer.
  • the insulating material layer and the first insulating layer are disposed in a same layer.
  • Another aspect of the present disclosure also provides a display device including the above array substrate.
  • Another aspect of the present disclosure also provides a method for manufacturing the array substrate, wherein the first transistor includes a first insulating layer, a semiconductor layer, and a source-drain electrode layer sequentially disposed on the substrate.
  • a second insulating layer, and a first gate layer, and the second transistor includes a second gate layer, the first insulating layer, the semiconductor layer, and the source-drain current that are sequentially disposed on the substrate.
  • An electrode layer and the second insulating layer, and the preparation method includes: sequentially forming a second gate layer, a first insulating layer, a semiconductor layer, a source-drain electrode layer, a second insulating layer, and a first layer on the substrate. Gate layer.
  • the preparation method further includes forming a first light-shielding layer and a second light-shielding layer between the substrate and the first insulating layer by using the same patterning process and the same layer and the same material, wherein
  • the orthographic projection of the first light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active region of the first transistor on the substrate, and makes the second light-shielding layer on the substrate.
  • the orthographic projection on the bottom at least partially overlaps the orthographic projection of the active region of the second transistor on the substrate.
  • the manufacturing method further includes forming a conductive material layer between the first light shielding layer and the second light shielding layer and the substrate; and forming a first electrode layer on the substrate.
  • the first electrode layer, the conductive material layer, the first light-shielding layer, and the second light-shielding layer are formed in a same patterning process by using a half-tone photolithographic mask.
  • the preparation method further includes sequentially forming an insulating material layer and a second electrode layer on the first electrode layer, wherein the half-tone photolithography mask is used to form the same in a patterning process.
  • a second electrode layer and the first gate layer are sequentially forming an insulating material layer and a second electrode layer on the first electrode layer, wherein the half-tone photolithography mask is used to form the same in a patterning process.
  • FIG. 1 schematically illustrates a partial top view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 schematically illustrates a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • the gate lines are routed in parallel at the same layer.
  • the width of the two parallel gate lines and the spacing between the gate lines occupy more area, which makes the metal shading area of the display device larger and the effective pixel area smaller, which in turn makes the display device's aperture ratio and transmittance reduce.
  • an electrical short circuit between the two parallel gate lines cannot be completely avoided.
  • FIG. 1 schematically illustrates a partial top view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 schematically illustrates a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a substrate 100, a plurality of gate line groups (Gm1, Gm2) disposed on the substrate 100, a plurality of data lines Dn, and a plurality of common electrode lines Ct, C (t + 1), and a plurality of pixel units arranged in an array.
  • Each gate line group is arranged between two adjacent rows of pixel units.
  • Each gate line group includes a first gate line Gm1 and a second gate line Gm2 that are insulated from each other.
  • the first gate line Gm1 is connected to the control electrode of the first transistor T1
  • the second gate line Gm2 is connected to the control electrode of the second transistor T2
  • the control electrode of the first transistor T1 and the control electrode of the second transistor T2 are disposed on different layers. in.
  • the extending direction of the data line Dn intersects the first gate line Gm1 and the second gate line Gm2, and the data line Dn is connected to the first poles of the first and second transistors T1 and T2 adjacent to and adjacent to the two sides, respectively.
  • the first gate line Gm1 is disposed in the same layer as the gate of the first transistor T1
  • the second gate line Gm2 is disposed in the same layer as the gate of the second transistor T2.
  • the controller of the first transistor T1 and the control electrode of the second transistor T2 in different layers, and correspondingly the first gate line in each gate line group Gm1 and the second gate line Gm2 are disposed in different layers, which can eliminate the gap between the first gate line Gm1 and the second gate line Gm2 in the case where the first gate line Gm1 and the second gate line Gm2 are disposed in the same layer Requirements, thereby reducing the metal light-shielding area of the display device including the array substrate, increasing the effective pixel area, and further increasing the aperture ratio and transmittance of the display device. Moreover, since the first gate line Gm1 and the second gate line Gm2 are provided in different layers, the problem of electrical short circuit between the two parallel gate lines can be fundamentally avoided.
  • the array substrate may include any number of gate line groups whose extension directions are parallel to each other and any number of data lines whose extension directions are parallel to each other, and the extension direction of the gate line groups and the data lines according to actual needs. Can be perpendicular to each other.
  • each data line may be connected only to the first pole of a transistor located on one side thereof.
  • the control electrode of the second transistor T2 is closer to the substrate than the control electrode of the first transistor T1.
  • the first transistor T1 may have a top-gate structure
  • the second transistor T2 may have a bottom-gate structure.
  • the transistor has a bottom-gate structure.
  • the transistor has a top-gate structure.
  • the first transistor T1 includes a first insulating layer 101, a semiconductor layer 102, a source-drain electrode layer 103, a second insulating layer 104, and a first gate, which are sequentially disposed on a substrate 100.
  • the second transistor T2 includes a second gate layer 106, the first insulating layer 101, the semiconductor layer 102, the source-drain electrode layer 103, and the second insulating layer 104, which are sequentially disposed on the substrate 100.
  • the first insulating layer 101 of the first transistor T1 and the second transistor T2 may be formed at the same time, and the semiconductor layer 102 of the first transistor T1 and the second transistor T2 may be formed at the same time.
  • the source-drain electrode layer 103 may be formed at the same time, and the second insulating layer 104 of the first transistor T1 and the second transistor T2 may be formed at the same time.
  • the first transistor T1 further includes a first light-shielding layer 107 a disposed between the substrate 100 and the first insulating layer 101.
  • the orthographic projection of the first light-shielding layer 107a on the substrate 100 and the orthographic projection of the active region of the first transistor T1 on the substrate 100 at least partially overlap.
  • a display device including a backlight such as a liquid crystal display
  • light emitted by the backlight provided under the substrate 100 may adversely affect an active area of a transistor Electrical performance.
  • first light-shielding layer 107a between the substrate 100 and the first insulating layer 101, and making the orthographic projection of the first light-shielding layer 107a on the substrate 100 and the active area of the first transistor T1 on the substrate 100
  • the orthographic projections at least partially overlap, which can eliminate the adverse effect of the light emitted by the backlight on the active area of the first transistor T1, thereby ensuring the performance of the first transistor T1.
  • the second transistor T2 further includes a second light shielding layer 107 b disposed between the substrate 100 and the second gate layer 106.
  • the orthographic projection of the second light-shielding layer 170b on the substrate 100 and the orthographic projection of the active region of the second transistor T2 on the substrate 100 at least partially overlap.
  • the second light shielding layer 107b is provided between the substrate 100 and the second gate layer 106, and the orthographic projection of the second light shielding layer 107b on the substrate 100 and the active region of the second transistor T2 are on the substrate 100.
  • the orthographic projections overlap at least partially, which can eliminate the adverse effect of the light emitted by the backlight on the active area of the second transistor T2, thereby ensuring the performance of the second transistor T2.
  • the first light shielding layer 107a and the second light shielding layer 107b are disposed in the same layer. That is, the first light shielding layer 107a and the second light shielding layer 107b can be formed at the same time in the same patterning process, thereby simplifying the manufacturing process of the array substrate and reducing the manufacturing cost.
  • the array substrate may further include a conductive material layer 108 disposed between the first light shielding layer 107 a and the second light shielding layer 107 b and the substrate 100.
  • the array substrate further includes a first electrode layer 108 ′, an insulating material layer 101 ′, and a second electrode layer 109 that are sequentially disposed on the substrate 100.
  • the first electrode layer 108 ' is disposed in the same layer as the conductive material layer 108
  • the insulating material layer 101' is disposed in the same layer as the first insulating layer 101. That is, in this exemplary embodiment, the first electrode layer 108 ′ may be formed simultaneously with the conductive material layer 108 in the same patterning process, and the insulating material layer 101 ′ may be patterned with the first insulating layer 101 Simultaneously formed in the process.
  • An embodiment of the present disclosure also provides a method for manufacturing any of the foregoing array substrates.
  • the manufacturing method includes: the first transistor includes a first insulating layer, a semiconductor layer, a source-drain electrode layer, a second insulating layer, and a first gate layer sequentially disposed on the substrate, and the second transistor The method includes a second gate layer, the first insulating layer, the semiconductor layer, the source-drain electrode layer, and the second insulating layer which are sequentially disposed on the substrate.
  • the preparation method includes: A second gate layer, a first insulating layer, a semiconductor layer, a source-drain electrode layer, a second insulating layer, and a first gate layer are sequentially formed on the substrate.
  • half-tone lithographic mask refers to lithographic masks with different amounts of light transmission at different positions on the lithographic mask, so that the photoresist irradiated through the lithographic mask is The exposure amount is different at different positions on the etchant, some parts of the photoresist are fully exposed, some parts are partially exposed, and other parts are not exposed, so that a non-uniform thickness photoresist is formed after development.
  • Agent pattern Taking a positive photoresist as an example, a fully exposed photoresist is completely removed after development, and a partially exposed photoresist is partially removed (that is, thinned) after development without being The exposed photoresist did not change after development.
  • the "partial exposure” generally refers to exposure with a light transmission amount of 30%, 40%, 50%, or 60%.
  • the gate electrode of the first transistor and the gate electrode of the second transistor are arranged in different layers, and the first gate line and the second gate line in each gate line group are correspondingly set.
  • the gate lines are arranged in different layers, which can eliminate the requirement for the spacing between the first gate line and the second gate line in the case where the first gate line and the second gate line are arranged in the same layer, thereby reducing the inclusion of the array.
  • the metal light-shielding area of the display device of the substrate increases the effective pixel area, thereby further improving the aperture ratio and transmittance of the display device.
  • the first gate line and the second gate line are provided in different layers, the problem of electrical short between the two parallel gate lines can be fundamentally avoided.
  • the above-mentioned preparation method further includes forming a first light-shielding layer and a second light-shielding layer between the substrate and the first insulating layer in the same layer and the same material through the same patterning process.
  • the orthographic projection of the first light-shielding layer on the substrate and the orthographic projection of the active region of the first transistor on the substrate at least partially overlap
  • the orthographic projection of the second light-shielding layer on the substrate and the second transistor have The orthographic projections of the source regions on the substrate at least partially overlap.
  • the above manufacturing method further includes: forming a conductive material layer between the first and second light-shielding layers and the substrate; and forming a first electrode layer on the substrate.
  • a half-tone photolithographic mask is used to form a first electrode layer, a conductive material layer, a first light-shielding layer, and a second light-shielding layer in the same patterning process.
  • the above preparation method further includes sequentially forming an insulating material layer and a second electrode layer on the first electrode layer.
  • a half-tone lithographic mask is used to form the second electrode layer and the first gate layer in the same patterning process.
  • a conductive material layer 308 and a light shielding material layer 307 are sequentially deposited on a substrate 300, and a photoresist 310 is coated on the light shielding material layer 307.
  • the photoresist 310 is exposed and developed using a half-tone lithographic mask to form photoresist patterns with different thicknesses.
  • the conductive material layer 308 and the light-shielding material layer 307 are etched with the photoresist pattern as a mask to remove the conductive material on the area that does not cover the photoresist pattern. And shading materials.
  • an ashing process is performed on the photoresist pattern to remove a thinner portion of the photoresist pattern, and thinner the thicker portion of the photoresist pattern.
  • the conductive material layer 308 and the light-shielding material layer 307 are further etched to remove the light-shielding on the area not covering the photoresist pattern. material.
  • the remaining photoresist is removed to form a first electrode layer 308 ', a conductive material layer 308, a first light-shielding layer 307a, and a second light-shielding layer 307b.
  • a bottom gate metal material is deposited on the structure as shown in FIG. 3 (f), and the bottom gate metal material is patterned to form the second gate electrode 106 of the second transistor T2.
  • a first insulating layer 101, a semiconductor layer 102, a source-drain electrode layer 103, and a second insulating layer 104 are sequentially formed over the second control electrode 106, and vias are formed in the second insulating layer 104 to electrically connect the source-drain electrodes.
  • Layer 103 is
  • the second electrode layer 109 and the control electrode of the first transistor T1 can be formed simultaneously using a half-tone lithographic mask through a process similar to that shown in FIGS. 3 (a) -3 (f). Made) in order to significantly reduce the manufacturing cost of the array substrate.
  • an embodiment of the present disclosure also provides a display device including any of the above-mentioned array substrates.
  • the first gate line and the first gate line in each gate line group are correspondingly set.
  • the arrangement of the two gate lines in different layers can eliminate the requirement for the space between the first gate line and the second gate line in the case where the first gate line and the second gate line are disposed on the same layer, thereby reducing the
  • the metal light-shielding area of the display device of the array substrate increases the effective pixel area, thereby further improving the aperture ratio and transmittance of the display device.
  • the first gate line and the second gate line are provided in different layers, the problem of electrical short between the two parallel gate lines can be fundamentally avoided.
  • the concept of the present disclosure can be widely applied to various electronic systems having a display function, such as a mobile phone, a notebook computer, an LCD television, and the like.

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Abstract

本公开的实施例提供了一种阵列基板，包括衬底、设置在衬底上的多个栅线组，以及阵列排布的多个像素单元，所述多个栅线组中的每个栅线组布置在相邻的两行像素单元之间，其中每个所述栅线组包括相互绝缘的第一栅线和第二栅线，第一栅线与第一晶体管的控制极连接，第二栅线与第二晶体管的控制极连接，并且所述第一晶体管的控制极和所述第二晶体管的控制极设置在不同层中。。还提供了一种阵列基板的制备方法和一种显示装置。

Description

阵列基板及其制备方法、显示装置
相关申请的交叉引用
本申请要求于2018年7月27日递交中国专利局的、申请号为201810844542.5的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本公开一般涉及显示技术领域。更具体地，本公开涉及一种阵列基板、包括该阵列基板的显示装置，以及该阵列基板的制备方法。
背景技术
随着显示技术的不断发展，双栅技术作为一种可以显著降低产品成本的技术，得到人们的广泛重视。在双栅技术中，通过对栅线、数据线、以及与之相连的源极驱动集成电路、栅极驱动集成电路进行优化布置，总体上可以实现显示面板的成本的降低。但是，在以同层并行布线的方式对栅线进行布线的双栅技术中，两条并行的栅线宽度以及栅线间的间距的设置难以同时满足避免电器短路以及较高开口率和透过率的要求。
公开内容
本公开的一方面提供了一种阵列基板，包括衬底、设置在衬底上的多个栅线组，以及阵列排布的多个像素单元，所述多个栅线组中的每个栅线组布置在相邻的两行像素单元之间，其中每个所述栅线组包括相互绝缘的第一栅线和第二栅线，第一栅线与第一晶体管的控制极连接，第二栅线与第二晶体管的控制极连接，并且所述第一晶体管的控制极和所述第二晶体管的控制极设置在不同 层中。
在一些实施例中，所述第一栅线与所述第一晶体管的控制极设置在同一层中，并且所述第二栅线与所述第二晶体管的控制极设置在同一层中。
在一些实施例中，相比于所述第一晶体管的控制极，所述第二晶体管的控制极更靠近于所述衬底。
在一些实施例中，所述阵列基板还包括与所述多个栅线组交叉的多条数据线，其中，每一条数据线与第一晶体管的第一极和第二晶体管的第一极分别连接，所述第一晶体管和第二晶体管分别位于所述每一条数据线两侧并且与每一条数据线相邻。
在一些实施例中，所述第一晶体管包括依次设置在所述衬底上的第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层，并且所述第二晶体管包括依次设置在所述衬底上的第二栅极层、所述第一绝缘层、所述半导体层、所述源漏电极层和所述第二绝缘层。
在一些实施例中，所述第一晶体管还包括设置在所述衬底与所述第一绝缘层之间的第一遮光层，所述第一遮光层在所述衬底上的正投影与所述第一晶体管的有源区在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第二晶体管还包括设置在所述衬底与所述第二栅极层之间的第二遮光层，所述第二遮光层在所述衬底上的正投影与所述第二晶体管的有源区在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一遮光层和所述第二遮光层设置在同一层中。
在一些实施例中，所述阵列基板还包括设置在所述第一遮光层和所述第二遮光层与所述衬底之间的导电材料层。
在一些实施例中，所述阵列基板还包括依次设置在衬底上的第一电极层、绝缘材料层和第二电极层，其中所述第一电极层与所述导电材料层设置在同一层中，所述绝缘材料层与所述第一绝缘层设置在同一层中。
本公开的另一方面还提供了一种显示装置，包括上述阵列基板。
本公开的另一方面还提供了一种用于根据上述阵列基板的制备方法，其中，所述第一晶体管包括依次设置在所述衬底上的第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层，并且所述第二晶体管包括依次设置在所述衬底上的第二栅极层、所述第一绝缘层、所述半导体层、所述源漏电极层和所述第二绝缘层，所述制备方法包括：在所述衬底上依次形成第二栅极层、第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层。
在一些实施例中，所述制备方法还包括在所述衬底与所述第一绝缘层之间通过同一图案化工艺同层同材料地形成第一遮光层和第二遮光层，其中，使得所述第一遮光层在所述衬底上的正投影与所述第一晶体管的有源区在所述衬底上的正投影至少部分重叠，并且使得所述第二遮光层在所述衬底上的正投影与所述第二晶体管的有源区在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述制备方法还包括在所述第一遮光层和所述第二遮光层与所述衬底之间形成导电材料层；以及在所述衬底上形成第一电极层，其中，采用半阶调光刻掩模板在同一图案化工艺中形成所述第一电极层、导电材料层、第一遮光层和第二遮光层。
在一些实施例中，所述制备方法还包括在所述第一电极层上依次形成绝缘材料层和第二电极层，其中，采用半阶调光刻掩模板在同一图案化工艺中形成所述第二电极层和所述第一栅极层。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例。
图1示意性地示出了根据本公开的实施例的阵列基板的局部顶视图。
图2示意性地示出了根据本公开的实施例的阵列基板的局部截面视图。
图3(a)-3(f)示意性地示出了根据本公开的实施例的阵列基板的遮光 层和第一电极层的制作方法的各个步骤。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本发明构思的范围，而是通过参考特定实施例为本领域普通技术人员说明本公开的概念。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施例的技术方案作进一步地详细描述。
在其中一种双栅技术中，栅线采用同层并行布线的方式。为了避免同层布置的两条并行栅线之间的电气短路，通常需要在两条并行栅线之间设置至少6.5μm的间距。然而，两条并行的栅线宽度与栅线间的间距会占用较多的面积，使得显示装置的金属遮光面积较大，而有效像素面积较小，进而使得显示装置的开口率和透过率降低。而且，即使在两条并行栅线之间设置了足够的间距，也不能完全避免这两条并行栅线之间的电气短路。
有鉴于此，本公开提供了一种改进的阵列基板。图1示意性地示出了根据本公开的实施例的阵列基板的局部顶视图，并且图2示意性地示出了根据本公开的实施例的阵列基板的局部截面视图。如图1和2所示，阵列基板包括衬底100、设置在衬底100上的多个栅线组(Gm1，Gm2)、多条数据线Dn、多条公共电极线Ct、C(t+1)，以及阵列排布的多个像素单元。每个栅线组布置在相邻的两行像素单元之间。每个栅线组包括相互绝缘的第一栅线Gm1和第二栅线Gm2。第一栅线Gm1与第一晶体管T1的控制极连接，第二栅线Gm2与第二晶体管T2的控制极连接，并且第一晶体管T1的控制极和第二晶体管T2的控制极设置在不同层中。数据线Dn的延伸方向与第一栅线Gm1和第二栅线Gm2交叉，并且数据线Dn与位于其两侧并且与其相邻的第一晶体管T1和第二晶体管T2的第一极分别连接。
根据示例性实施例，特别地，第一栅线Gm1与第一晶体管T1的控制极设 置在同一层中，并且第二栅线Gm2与第二晶体管T2的控制极设置在同一层中。
在根据本公开的实施例的阵列基板中，通过将第一晶体管T1的控制器和第二晶体管T2的控制极设置在不同层中，并且相应地将每一个栅线组中的第一栅线Gm1和第二栅线Gm2设置在不同层中，可以消除对于在第一栅线Gm1和第二栅线Gm2同层设置的情况下，第一栅线Gm1与第二栅线Gm2之间的间距的要求，从而减小包括该阵列基板的显示装置的金属遮光面积，增大有效像素面积，进而使得显示装置的开口率和透过率提高。而且，由于第一栅线Gm1和第二栅线Gm2设置在不同层中，因此能够从根本上避免这两条并行栅线之间的电气短路的问题。
应当指出的是，尽管在图1中仅示意性地示出了一个栅线组和一条数据线，但是这仅仅是本公开的实施例提供的阵列基板的一部分。本领域技术人员将意识到：该阵列基板可以根据实际需要而包括延伸方向彼此平行的任何数目的栅线组以及延伸方向彼此平行的任何数目的数据线，并且栅线组和数据线的延伸方向可以相互垂直。
还应当指出的是，尽管在图1所示的实施例中，数据线Dn与位于其两侧并且与其相邻的第一晶体管T1和第二晶体管T2的第一极分别连接，但是本公开的概念不限于此。在可替换的实施例中，每一条数据线可以仅与位于其一侧的晶体管的第一极连接。本领域技术人员将意识到：本公开的概念同样适用于其它具有双栅结构的阵列基板。
在示例实施例中，如图2所示，相比于第一晶体管T1的控制极，第二晶体管T2的控制极更靠近于衬底。例如，第一晶体管T1可以具有顶栅结构，而第二晶体管T2可以具有底栅结构。典型地，相对于晶体管的有源层，如果该晶体管的栅极更加靠近衬底，则该晶体管具有底栅结构。相反，相对于晶体管的有源层，如果该晶体管的栅极更加远离衬底，则该晶体管具有顶栅结构。
在示例实施例中，如图2所示，第一晶体管T1包括依次设置在衬底100上的第一绝缘层101、半导体层102、源漏电极层103、第二绝缘层104和第一 栅极层105。第二晶体管T2包括依次设置在衬底100上的第二栅极层106、上述第一绝缘层101、上述半导体层102、上述源漏电极层103和上述第二绝缘层104。也就是说，第一晶体管T1和第二晶体管T2的第一绝缘层101可以同时形成，第一晶体管T1和第二晶体管T2的半导体层102可以同时形成，第一晶体管T1和第二晶体管T2的源漏电极层103可以同时形成，并且第一晶体管T1和第二晶体管T2的第二绝缘层104可以同时形成。
可选地，第一晶体管T1还包括设置在衬底100与第一绝缘层101之间的第一遮光层107a。第一遮光层107a在衬底100上的正投影与第一晶体管T1的有源区在衬底100上的正投影至少部分重叠。当根据本公开的实施例的阵列基板用在诸如液晶显示器之类的包括背光源的显示装置中时，由设置在衬底100下方的背光源发射的光可能会不利地影响晶体管的有源区的电气性能。通过在衬底100与第一绝缘层101之间设置第一遮光层107a，并且使得第一遮光层107a在衬底100上的正投影与第一晶体管T1的有源区在衬底100上的正投影至少部分重叠，可以消除背光源所发射的光对第一晶体管T1的有源区的不利影响，从而保证第一晶体管T1的性能。
根据本公开的一些示例性实施例，第二晶体管T2还包括设置在衬底100与第二栅极层106之间的第二遮光层107b。第二遮光层170b在衬底100上的正投影与第二晶体管T2的有源区在衬底100上的正投影至少部分重叠。当根据本公开的实施例的阵列基板用在诸如液晶显示器之类的包括背光源的显示装置中时，由设置在衬底100下方的背光源发射的光可能会不利地影响晶体管的有源区的电气性能。通过在衬底100与第二栅极层106之间设置第二遮光层107b，并且使得第二遮光层107b在衬底100上的正投影与第二晶体管T2的有源区在衬底100上的正投影至少部分重叠，可以消除背光源所发射的光对第二晶体管T2的有源区的不利影响，从而保证第二晶体管T2的性能。
在示例实施例中，第一遮光层107a和第二遮光层107b设置在同一层中。也就是说，可以在同一图案化工艺中同时形成第一遮光层107a和第二遮光层 107b，从而简化阵列基板的制作工艺，降低制作成本。
进一步地，如图2所示，阵列基板还可以包括设置在第一遮光层107a和第二遮光层107b与衬底100之间的导电材料层108。
在示例性实施例中，阵列基板还包括依次设置在衬底100上的第一电极层108'、绝缘材料层101'和第二电极层109。第一电极层108'与导电材料层108设置在同一层中，并且绝缘材料层101'与第一绝缘层101设置在同一层中。也就是说，在该示例性实施例中，第一电极层108'可以与导电材料层108在同一图案化工艺中同时形成，并且绝缘材料层101'可以与第一绝缘层101在同一图案化工艺中同时形成。
本公开的实施例还提供了一种上述任一种阵列基板的制备方法。该制备方法包括：所述第一晶体管包括依次设置在所述衬底上的第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层，并且所述第二晶体管包括依次设置在所述衬底上的第二栅极层、所述第一绝缘层、所述半导体层、所述源漏电极层和所述第二绝缘层，所述制备方法包括：在所述衬底上依次形成第二栅极层、第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层。
如本文所使用的，“半阶调光刻掩模板”是指光刻掩模板上的不同位置处的光透过量不同的光刻掩模板，使得通过该光刻掩模板被照射的光致抗蚀剂上的不同位置处的曝光量不同，光致抗蚀剂的一些部分被完全曝光，一些部分被部分曝光，并且其它部分未被曝光，从而在显影后形成厚度不均匀的光致抗蚀剂图案。以正性光致抗蚀剂为例，完全曝光的光致抗蚀剂在显影后被完全去除，部分曝光的光致抗蚀剂在显影后被部分去除(即被减薄)，而未被曝光的光致抗蚀剂在显影后没有变化。这里，“部分曝光”一般是指光透过量为30％、40％、50％或60％的曝光。
在采用上述制备方法制备的阵列基板中，通过将第一晶体管的控制极和第二晶体管的控制极设置在不同层中，并且相应地将每一个栅线组中的第一栅线和第二栅线设置在不同层中，可以消除对于在第一栅线和第二栅线同层设置的 情况下，第一栅线与第二栅线之间的间距的要求，从而减小包括该阵列基板的显示装置的金属遮光面积，增大有效像素面积，进而使得显示装置的开口率和透过率提高。而且，由于第一栅线和第二栅线设置在不同层中，因此能够从根本上避免这两条并行栅线之间的电气短路的问题。
在示例性实施例中，上述制备方法还包括在衬底与第一绝缘层之间通过同一图案化工艺同层同材料地形成第一遮光层和第二遮光层。使得第一遮光层在衬底上的正投影与第一晶体管的有源区在衬底上的正投影至少部分重叠，并且使得第二遮光层在衬底上的正投影与第二晶体管的有源区在衬底上的正投影至少部分重叠。
在示例性实施例中，上述制备方法还包括：在第一遮光层和第二遮光层与衬底之间形成导电材料层；以及在衬底上形成第一电极层。特别地，采用半阶调光刻掩模板在同一图案化工艺中形成第一电极层、导电材料层、第一遮光层和第二遮光层。
在示例性实施例中，上述制备方法还包括在第一电极层上依次形成绝缘材料层和第二电极层。特别地，采用半阶调光刻掩模板在同一图案化工艺中形成第二电极层和第一栅极层。
以下结合图2和图3(a)-3(f)来具体地说明根据本公开的实施例的阵列基板的制备方法。
首先，如图3(a)所示，在衬底300上依次沉积导电材料层308和遮光材料层307，并且在遮光材料层307上涂敷光致抗蚀剂310。
接着，如图3(b)所示，采用半阶调光刻掩模板对光致抗蚀剂310进行曝光和显影，从而形成厚度不一的光致抗蚀剂图案。
然后，如图3(c)所示，以光致抗蚀剂图案为掩模对导电材料层308和遮光材料层307进行蚀刻，以去除没有覆盖光致抗蚀剂图案的区域上的导电材料和遮光材料。
然后，如图3(d)所示，对光致抗蚀剂图案进行灰化工艺，以除去较薄的 光致抗蚀剂图案部分，并且将较厚的光致抗蚀剂图案部分减薄。
接着，如图3(e)所示，以光致抗蚀剂图案为掩模对导电材料层308和遮光材料层307进行进一步蚀刻，以去除没有覆盖光致抗蚀剂图案的区域上的遮光材料。
然后，如图3(f)所示，去除剩余的光致抗蚀剂，以形成第一电极层308'、导电材料层308、第一遮光层307a和第二遮光层307b。
在如图3(a)-3(f)所示的工艺中，仅采用一张掩模板即可同时形成第一电极层308'、导电材料层308、第一遮光层307a和第二遮光层307b，因此可以显著降低阵列基板的制造成本。
此后，在如图3(f)所示的结构上沉积底栅金属材料，并且对底栅金属材料进行图案化以形成第二晶体管T2的第二控制极106。此后，在第二控制极106上方依次形成第一绝缘层101、半导体层102、源漏电极层103、第二绝缘层104，并且在第二绝缘层104中形成过孔以电气连接源漏电极层103。
最后，可以通过与图3(a)-3(f)类似的工艺，采用一张半阶调光刻掩模板同时形成第二电极层109和第一晶体管T1的控制极(由第一栅极层105制成)，以便显著降低阵列基板的制造成本。
另外，本公开的实施例还提供了一种显示装置，包括上述任一种阵列基板。
在根据本公开的实施例的显示装置中，通过将第一晶体管的控制极和第二晶体管的控制极设置在不同层中，并且相应地将每一个栅线组中的第一栅线和第二栅线设置在不同层中，可以消除对于在第一栅线和第二栅线同层设置的情况下，第一栅线与第二栅线之间的间距的要求，从而减小包括该阵列基板的显示装置的金属遮光面积，增大有效像素面积，进而使得显示装置的开口率和透过率提高。而且，由于第一栅线和第二栅线设置在不同层中，因此能够从根本上避免这两条并行栅线之间的电气短路的问题。
本公开的概念可以广泛地应用于具有显示功能的各种电子系统，例如移动电话、笔记本计算机、液晶电视等等。
除非另外定义，否则本公开使用的技术术语或者科学术语应当为本公开所属领域普通技术人员所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。需要注意的是，在不冲突的前提下，上述实施例中的特征可以任意组合使用。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何本领域普通技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括衬底、设置在衬底上的多个栅线组，以及阵列排布的多个像素单元，所述多个栅线组中的每个栅线组布置在相邻的两行像素单元之间，其中
    每个所述栅线组包括相互绝缘的第一栅线和第二栅线，
    第一栅线与第一晶体管的控制极连接，
    第二栅线与第二晶体管的控制极连接，并且
    所述第一晶体管的控制极和所述第二晶体管的控制极设置在不同层中。
  2. 根据权利要求1所述的阵列基板，其中，所述第一栅线与所述第一晶体管的控制极设置在同一层中，并且所述第二栅线与所述第二晶体管的控制极设置在同一层中。
  3. 根据权利要求1或2所述的阵列基板，其中，相比于所述第一晶体管的控制极，所述第二晶体管的控制极更靠近于所述衬底。
  4. 根据权利要求1-3中任一项所述的阵列基板，还包括与所述多个栅线组交叉的多条数据线，其中，每一条数据线与第一晶体管的第一极和第二晶体管的第一极分别连接，所述第一晶体管和第二晶体管分别位于所述每一条数据线两侧并且与每一条数据线相邻。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第一晶体管包括依次设置在所述衬底上的第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层，并且所述第二晶体管包括依次设置在所述衬底上的第二栅极层、所述第一绝缘层、所述半导体层、所述源漏电极层和所述第二绝缘层。
  6. 根据权利要求5所述的阵列基板，其中，所述第一晶体管还包括设置在所述衬底与所述第一绝缘层之间的第一遮光层，所述第一遮光层在所述衬底上的正投影与所述第一晶体管的有源区在所述衬底上的正投影至少部分重叠。
  7. 根据权利要求5或6所述的阵列基板，其中，所述第二晶体管还包括设置在所述衬底与所述第二栅极层之间的第二遮光层，所述第二遮光层在所述衬底上的正投影与所述第二晶体管的有源区在所述衬底上的正投影至少部分重叠。
  8. 根据权利要求7所述的阵列基板，其中，所述第一遮光层和所述第二遮光层设置在同一层中。
  9. 根据权利要求7所述的阵列基板，还包括设置在所述第一遮光层和所述第二遮光层与所述衬底之间的导电材料层。
  10. 根据权利要求9所述的阵列基板，还包括依次设置在衬底上的第一电极层、绝缘材料层和第二电极层，其中所述第一电极层与所述导电材料层设置在同一层中，所述绝缘材料层与所述第一绝缘层设置在同一层中。
  11. 一种显示装置，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种用于根据权利要求1-10中任一项所述的阵列基板的制备方法，其中，所述第一晶体管包括依次设置在所述衬底上的第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层，并且所述第二晶体管包括依次设置在所述衬底上的第二栅极层、所述第一绝缘层、所述半导体层、所述源漏电极层和所述第二绝缘层，
    所述制备方法包括：
    在所述衬底上依次形成第二栅极层、第一绝缘层、半导体层、源漏电极层、第二绝缘层和第一栅极层。
  13. 根据权利要求12所述的制备方法，还包括在所述衬底与所述第一绝缘层之间通过同一图案化工艺同层同材料地形成第一遮光层和第二遮光层，其中，使得所述第一遮光层在所述衬底上的正投影与所述第一晶体管的有源区在所述衬底上的正投影至少部分重叠，并且使得所述第二遮光层在所述衬底上的正投影与所述第二晶体管的有源区在所述衬底上的正投影至少部分重叠。
  14. 根据权利要求12或13所述的制备方法，还包括：
    在所述第一遮光层和所述第二遮光层与所述衬底之间形成导电材料层；以及
    在所述衬底上形成第一电极层，
    其中，采用半阶调光刻掩模板在同一图案化工艺中形成所述第一电极层、导电材料层、第一遮光层和第二遮光层。
  15. 根据权利要求12-14中任一项所述的制备方法，还包括在所述第一电极层上依次形成绝缘材料层和第二电极层，
    其中，采用半阶调光刻掩模板在同一图案化工艺中形成所述第二电极层和所述第一栅极层。
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