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WO2019029309A1 - 数据编码方法、装置、存储介质及处理器 - Google Patents

数据编码方法、装置、存储介质及处理器 Download PDF

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Publication number
WO2019029309A1
WO2019029309A1 PCT/CN2018/095037 CN2018095037W WO2019029309A1 WO 2019029309 A1 WO2019029309 A1 WO 2019029309A1 CN 2018095037 W CN2018095037 W CN 2018095037W WO 2019029309 A1 WO2019029309 A1 WO 2019029309A1
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interleaving
matrix
ldpc
bit
sequence
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PCT/CN2018/095037
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English (en)
French (fr)
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李立广
徐俊
许进
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中兴通讯股份有限公司
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Priority to KR1020207007200A priority Critical patent/KR102343780B1/ko
Priority to JP2020507602A priority patent/JP7361017B2/ja
Priority to AU2018314548A priority patent/AU2018314548C1/en
Priority to RU2020110023A priority patent/RU2742912C1/ru
Priority to EP18844354.3A priority patent/EP3667963A4/en
Publication of WO2019029309A1 publication Critical patent/WO2019029309A1/zh
Priority to US16/787,009 priority patent/US11239946B2/en
Priority to US17/588,056 priority patent/US11791933B2/en
Priority to JP2022091958A priority patent/JP7565976B2/ja

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1162—Array based LDPC codes, e.g. array codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/1874—Buffer management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy

Definitions

  • the present invention relates to the field of communications, and in particular to a data encoding method, apparatus, storage medium, and processor.
  • the Kmax design method in the block segmentation method is such that the number of code blocks in each code block group is equal to avoid the number of code blocks in some code block groups is large, resulting in poor overall performance; and, for high-order quasi-cyclic LDPC coding
  • the problem of poor performance under modulation or fading channels is improved by the codeword interleaving method to improve the performance of quasi-cyclic LDPC coding.
  • the embodiments of the present invention provide a data encoding method, apparatus, storage medium, and processor to solve at least the problem that the transmission data is quasi-cyclic LDPC encoded and unstable in the related art in the related art.
  • a data encoding method including: performing quasi-cyclic LDPC encoding on an information packet bit sequence to obtain an LDPC codeword sequence, and determining a one-dimensional finite-length circular buffer according to the LDPC codeword sequence.
  • the predefined parameter includes at least one of the following: a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system column number, and an information packet bit sequence length Starting from the starting position, sequentially reading data bits of a specific length to form a bit sequence to be transmitted, and transmitting the bit sequence to be transmitted.
  • a data encoding apparatus comprising: an obtaining module configured to acquire data to be transmitted; and an interleaving module configured to perform quasi-cyclic LDPC encoding on the to-be-sent data to obtain an LDPC code a sequence of words, interleaving the LDPC codeword sequence to obtain an LDPC codeword sequence after interleaving; and a selecting module configured to perform cyclic bit selection on the LDPC codeword sequence after the interleaving to obtain a rate-matched codeword sequence
  • the starting position is determined according to a predetermined parameter, wherein the predetermined parameter comprises at least one of: a redundancy version, a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system column The number, the length of the information packet bit sequence, and the sending module, configured to send the rate matched codeword sequence.
  • a storage medium comprising a stored program, wherein the program is executed to execute the above data encoding method.
  • a processor for running a program wherein the program is executed to execute the data encoding method of the above-described alternative embodiment.
  • the LDPC codeword sequence is obtained by performing quasi-cyclic LDPC coding on the to-be-transmitted data, and interleaving the LDPC codeword sequence to obtain an LDPC codeword sequence after interleaving;
  • the codeword sequence performs cyclic bit selection from the start position to obtain a rate matched codeword sequence, wherein the start position is determined according to a predetermined parameter; and the rate matched codeword sequence is transmitted.
  • FIG. 1 is a flow chart of a data encoding method according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of LDPC encoded data processing in accordance with a preferred embodiment of the present invention.
  • a mobile communication network including but not limited to a 5G mobile communication network
  • the network architecture of the network may include a network side device (for example, a base station) and a terminal.
  • a network side device for example, a base station
  • an information transmission method that can be run on the network architecture is provided. It should be noted that the operating environment of the foregoing information transmission method provided in the embodiment of the present application is not limited to the foregoing network architecture.
  • the transmitting end may perform channel coding on the information sequence to obtain an encoded codeword, interleave the encoded codeword, and map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information.
  • the receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data at this time is already distorted, and specific processing is required to restore the original information sequence.
  • the receiving end can perform corresponding processing on the received data to reliably restore the original information sequence.
  • the encoding processing method is based on forward error correction (FEC) encoding, wherein forward error correction coding adds some redundant information to the information sequence, and the receiving end can use the redundant information to Recover the original information sequence reliably.
  • FEC forward error correction
  • FEC codes include: convolutional codes, Turbo codes, and LDPC codes.
  • the information sequence of the bit number k is FEC-encoded to obtain an n-bit FEC encoded codeword (redundant bits are n-k), and the FEC encoding code rate is k/n.
  • LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph. It is the sparseness of its check matrix that can realize low complexity codec, which makes LDPC practical. . After various practices and theoretical proofs, the LDPC code is the most excellent channel coding under the Additive White Gaussian Noise (AWGN) channel, and the performance is very close to the Shannon limit.
  • AWGN Additive White Gaussian Noise
  • each row is a parity code. If the value of an element of an index position is equal to 1 in each row, the bit participates in the parity code, and if it is equal to 0, The location bit does not participate in the parity code.
  • Quasi-cyclic LDPC codes have become mainstream applications due to their structural features, such as IEEE802.11ac, IEEE802.11ad, IEEE802.11aj, IEEE802.16e, IEEE802.11n, microwave communication, and fiber-optic communication.
  • the 5th generation mobile communication was adopted as a data channel coding scheme.
  • the parity check matrix H of the quasi-cyclic LDPC code is a matrix of M ⁇ Z rows and N ⁇ Z columns, which is composed of M ⁇ N sub-matrices, each of which is a different power of a basic permutation matrix of size Z ⁇ Z.
  • the sub-matrix obtained by cyclically shifting several values of the size of the Z ⁇ Z unit array.
  • the parity check matrix of the quasi-cyclic LDPC code can be described as having the following mathematical formula form:
  • Z and power hb ij can uniquely identify each block matrix. If a block matrix is an all-zero matrix, it can be represented by "-1" or null representation or other form representation; The cyclic shift s of the unit array is obtained, which is equal to s. All hb ij can form a quasi-cyclic LDPC encoded base matrix Hb, and the basic matrix Hb of the LDPC code can be expressed as follows:
  • the basic matrix Hb contains two elements: 1. an element indicating an all-zero square matrix; 2. an element indicating a cyclic shift of a unit array, generally represented by an integer of 0 to (Z-1).
  • the basic matrix Hb may also be referred to as a basic parity check matrix or a shift value matrix or a permutation value matrix or a basic parity check matrix or a parity check matrix, if the base matrix Hb is to be represented as an all-zero matrix
  • a base graph matrix or a template matrix of the quasi-cyclic LDPC encoding can be obtained.
  • the basic graph matrix described therein may also be described in a tabular form, for example, using a row and column index pair to indicate the position of the "1" of the corresponding base graph matrix or the position of the base matrix cyclic shift size element in the base matrix. Therefore, the basis matrix of the quasi-cyclic LDPC encoding can be determined according to the template matrix of the quasi-cyclic LDPC code and a set of shift values (or coefficients). And, the dimension Z of the basic permutation matrix or the all-zero square matrix may be defined as a shift size or a lifting size or a spreading factor or a sub-matrix size.
  • the structured LDPC code can be uniquely determined by the basic check matrix Hb and the boost value Z.
  • the base matrix Hb (2 rows and 4 columns) is as follows and the corresponding boost value z is equal to 4.
  • the parity check matrix H is obtained according to the basic matrix Hb and the boost value Z:
  • padding bits are used to assist coding or decoding, but are not transmitted, but in the case of In the encoding and decoding process, if more padding bits appear, the encoder or decoder performs more useless operations, thereby reducing the encoding and decoding speed, and the power consumption is also higher. And if the length of the transport block is relatively large, the number of code blocks is relatively large at this time.
  • all LDPC code blocks need to be divided into multiple code block groups, and each code block group includes several LDPC code block, and at the receiving end, the feedback of the correctness of the reception and the data retransmission operation are performed in units of code block groups; if the design of the code block group is not considered in the code block division process, the code block division is performed.
  • the block group is formed, the number of code blocks in the code block group is not equal, which brings about some short board effects and affects data communication robustness.
  • LDPC codes may have some poor performance problems, and codeword bits need to be interleaved to randomize bursts. Noise to improve the performance of quasi-cyclic LDPC code words under burst noise.
  • FIG. 1 is a flowchart of a data encoding method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 performing quasi-cyclic LDPC encoding on the information packet bit sequence to obtain an LDPC codeword sequence, and determining a one-dimensional finite-length cyclic buffer size according to the LDPC codeword sequence.
  • Step S104 Select a redundancy version value from a plurality of predetermined redundancy version values, and determine to read in the one-dimensional finite-length cyclic buffer according to the selected redundancy version value and predefined parameters. a starting position of the bit sequence to be transmitted; wherein the predefined parameter includes at least one of the following: a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system column number, and an information packet bit sequence length.
  • Step S106 starting from the starting position, sequentially reading data bits of a specific length to form a bit sequence to be transmitted, and transmitting the bit sequence to be transmitted.
  • the LDPC codeword sequence is obtained by performing quasi-cyclic LDPC coding on the information packet bit sequence, and determining a one-dimensional finite-length cyclic buffer size according to the LDPC codeword sequence; selecting from a plurality of predetermined redundancy version values Determining a value of the to-be-transmitted bit sequence in the one-dimensional finite-length cyclic buffer according to the selected redundancy version value and the predefined parameter; wherein the pre-predetermined position
  • the definition parameter includes at least one of the following: a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system column number, and an information packet bit sequence length; starting from the starting position, sequentially reading a specific length
  • the data bits form a sequence of bits to be transmitted and transmit the sequence of bits to be transmitted.
  • the execution body of the foregoing steps may be a base station, a terminal, or the like, but is not limited thereto.
  • the interleaving the LDPC codeword sequence to obtain the interleaved LDPC codeword sequence includes: performing block interleaving on the LDPC codeword sequence, wherein determining the row of the interlacing matrix according to the quasi-cyclic LDPC encoding parameter And the quasi-cyclic LDPC coding parameter includes at least one of the following: a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, and a basic graph matrix system column number, wherein the interleaving matrix is listed in the interleaving.
  • the number of rows of the interleaving matrix is equal to a positive integer factor of the quasi-cyclic LDPC boost value, or a positive integer multiple of the boost value of the quasi-cyclic LDPC code.
  • the number of rows of the interleaving matrix is equal to a positive integer factor of the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding, or a positive integer multiple of the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding.
  • the interleaving method further comprises: respectively obtaining the obtained interleaved bit sequence in a predetermined column order.
  • the intra-column interleaving method is determined based on the modulation order.
  • the intra-column interleaving method is performed, where the M0 is an integer greater than 1.
  • the starting position is determined based on the redundancy version, the boost value, and the total number of columns of the base map matrix.
  • the starting position corresponding to the redundancy version RVi is calculated by the following formula:
  • the nb in the first formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the ⁇ is a positive integer
  • the G is a real number greater than 0
  • the ⁇ is a positive real number
  • the ⁇ is a non-negative real number
  • the ⁇ is an integer, wherein the funtion(x) represents rounding up the real number x or rounding down or rounding off;
  • nb in the second formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the ⁇ is a positive integer
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • the ⁇ is a positive real number
  • ⁇ is a non-negative integer
  • the ⁇ is an integer
  • the funtion(x) represents rounding up the real number x or rounding down or rounding off
  • nb in the third formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • the ⁇ is a positive integer
  • the ⁇ is a positive real number
  • ⁇ is a non-negative integer
  • ⁇ is an integer
  • the funtion(x) indicates that the real number x is rounded up or rounded down or rounded off.
  • the starting position is determined according to the redundancy version, the boost value, the total number of rows of the base graph matrix, and the length of the information packet bit sequence.
  • the starting position corresponding to the redundancy version RVi is calculated by one of the following formulas:
  • K in the above two formulas is the length of the information packet bit sequence
  • the Z is the boost value
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • the ⁇ is a positive integer
  • the ⁇ is a positive real number
  • the ⁇ is an integer
  • funtion(x) means rounding up the real number x, or rounding down, or rounding off.
  • the LDPC codeword sequence is interleaved to obtain an interleaved LDPC codeword sequence, including: interleaving all the bits from the S0th bit to the S1th bit in the LDPC codeword sequence, where the S0, S1 is a positive integer, and the S1 is greater than the S0.
  • all the bits from the S0th bit to the S1th bit in the LDPC codeword sequence are interleaved, including: all bits from the S0th bit to the S1th bit in the LDPC codeword sequence according to the interlace matrix.
  • the Z0 is equal to a positive integer factor of the LDPC encoding boost value.
  • the Z0 is equal to Z
  • the Z is an LDPC code boost value
  • the S0 is equal to 2 x Z
  • the S1 is equal to E x Z-1, where E is an integer greater than two.
  • the E is equal to kb, kb+1, kb+2, kb+3 or kb+4, wherein the kb is the number of basic graph matrix system columns of the LDPC encoding.
  • the Z0 is determined by the following parameters: S0, S1 and a modulation order, wherein the modulation order is the number of bits carried by each modulation symbol.
  • the Z0 is obtained according to the following formula: Where M is a modulation order and the M is a positive integer.
  • the value of the S1 is determined by at least one of the following parameters: the length of the information packet bit sequence obtained after the code block segmentation of the data to be transmitted; the length of the bit sequence to be transmitted.
  • the LDPC code rate R when the LDPC code rate R is less than or equal to R0, all bits of the S0th bit to the S1th bit in the LDPC codeword sequence are interleaved according to the interlace matrix, wherein the R0 is greater than or equal to 3/. 4 and a real number less than 1, the LDCP code rate R is equal to the quotient of the length of the information packet bit sequence and the length of the bit sequence to be transmitted.
  • a quasi-cyclic LDPC coded data processing method is provided, which can be used in a NR (New Radio Access Technology) communication system.
  • the method proposed in this alternative embodiment may be used in an LTE mobile communication system or a future fifth generation (5G) mobile communication system or other wireless wired communication system, and the data transmission direction is that the base station transmits data to the mobile user (downlink transmission service data). ), or the data transmission direction is that the mobile user sends data to the base station (uplink transmission service data).
  • Mobile users include: mobile devices, as access terminals, user terminals, subscriber stations, subscriber units, mobile stations, remote stations, remote terminals, user agents, user devices, user equipment, or some other terminology.
  • the base station includes an access point (AP), or may be called a node B, a radio network controller (RNC), an evolved Node B (eNB), and a base station controller.
  • AP access point
  • RNC radio network controller
  • eNB evolved Node B
  • BSC Base Station Controller
  • BTS Base Transceiver Station
  • BS Base Station
  • TF Transceiver Function
  • RBS Radio Base Station
  • a quasi-cyclic LDPC coded data processing method provided by this alternative embodiment may be applied to enhanced mobile in a new radio access technology (New Radio Access Technology, referred to as new RAT).
  • new RAT New Radio Access Technology
  • eMBB Enhanced Mobile Broadband
  • URLLC Ultra-Reliable and Low Latency Communications
  • MMTC Massive Machine Type Communications
  • FIG. 2 is a flowchart of processing LDPC encoded data according to a preferred embodiment of the present invention. As shown in FIG. 2, the method includes the following steps:
  • Step S201 Obtain length information of the source data packet to be transmitted; determine, according to the control information, a length of the source data packet to be transmitted that is currently to be sent, which is also called a transport block size (TBS), and the control information may be It is obtained by downlink control information or uplink control information or other system information.
  • TBS transport block size
  • Step S202 the code block is divided, and the source data packet to be transmitted is divided according to the longest information block length Kmax, wherein the number of information packet bit sequences obtained by the segmentation is
  • the length of the information packet bit sequence obtained after the code block is divided includes: with Where K is the length of the information packet bit sequence, K is a positive integer, Kmax is a positive integer, and L is the length of the CRC sequence added for each information packet bit sequence.
  • step S203 a CRC sequence is added. After the code block is divided, a CRC (Cyclic Redundancy Check) sequence in which L bits are added in each information bit block is obtained, and the L is an integer greater than 0.
  • CRC Cyclic Redundancy Check
  • Step S204 padding the bits; padding the information bits in the information bit block after adding the CRC sequence, wherein the sub-bit bits are only used for auxiliary coding, and no transmission is performed.
  • Step S205 quasi-cyclic LDPC encoding; determining a lifting value used by the LDPC encoding according to the length of each information packet bit sequence obtained after the code block is divided, and determining and calculating a parity check matrix of the LDPC encoding according to the obtained lifting value information, according to the The parity check matrix and the LDPC code enhancement value correspond to each information packet bit sequence for quasi-cyclic LDPC coding to obtain an LDPC codeword sequence.
  • the basic graph matrix of the quasi-cyclic LDPC encoding includes two types: base graph 1 and base graph 2.
  • the number of rows of the basic graph matrix base graph 1 is 46
  • the total number of columns is equal to 68 or the total graph matrix total row number is equal to 46 or the basic graph matrix system column number is equal to 22, then it can be determined that the corresponding basic graph matrix index is 1 (base graph 1); and according to the basic graph matrix If the total number of columns is equal to 52 or the total number of rows of the basic graph matrix is equal to 42 or the number of columns of the basic graph matrix system is equal to 10, then it can be determined that the corresponding base graph matrix index is 2 (base graph 2). As shown in Table 1, the corresponding row index in the base graph 1 and base graph 2 is the "1" position of i, that is, it can be replaced with the cyclic permutation unit array position.
  • Table 2 corresponds to the boost value supported by the base graph 1 base graph 1, including 8 boost value sets;
  • Table 4 corresponds to the boost value supported by the base graph matrix base graph 2, and also includes 8 boost value sets.
  • the boost value is determined according to the above information of the boost value set index number i LS, i LS value set index matrix acquired shift value substantially corresponding to FIG. 1 matrix base graph values for each set of lift from the lift table 3,
  • a base map matrix corresponding to the current boost value Z c can be obtained.
  • the base graph matrix base graph 2 is selected, otherwise the base graph matrix base graph 1 is selected.
  • the first column corresponds to the row index number i indicating the base graph matrix 1 and the base graph matrix base graph 2
  • the second column corresponds to the column index number j indicating the base graph matrix base graph 1
  • [ i, j] collectively determines the "1" position of the base graph matrix base graph 1
  • the third column corresponds to the column index number j indicating the base graph matrix base graph 2.
  • Table 3 and Table 4 respectively illustrate eight shift value matrices corresponding to the base graph matrix 1 and the base graph matrix base graph 2, where i is used to indicate the row index, j is used to indicate the column index, and i LS is used for Indicates the boost value set index number.
  • Table 2 shows the lifting value of the base graph 1 (base graph 1), as shown in Table 2 below.
  • Set index(i LS ) Set of lifting sizes 1 ⁇ 2,4,8,16,32,64,128,256 ⁇ 2 ⁇ 3,6,12,24,48,96,192,384 ⁇ 3 ⁇ 5,10,20,40,80,160,320 ⁇ 4 ⁇ 7,14,28,56,112,224 ⁇ 5 ⁇ 9,18,36,72,144,288 ⁇ 6 ⁇ 11,22,44,88,176,352 ⁇ 7 ⁇ 13,26,52,104,208 ⁇ 8 ⁇ 15,30,60,120,240 ⁇
  • Table 3 shows the shift value of the base graph 1 as shown in Table 3 below.
  • Table 4 shows the lifting value of base graph 2, as shown in Table 4 below.
  • Set index(i LS ) Set of lifting sizes 1 ⁇ 2,4,8,16,32,64,128,256 ⁇ 2 ⁇ 3,6,12,24,48,96,192 ⁇ 3 ⁇ 5,10,20,40,80,160 ⁇ 4 ⁇ 7,14,28,56,112,224 ⁇ 5 ⁇ 9,18,36,72,144 ⁇ 6 ⁇ 11,22,44,88,176 ⁇ 7 ⁇ 13,26,52,104,208 ⁇ 8 ⁇ 15,30,60,120,240 ⁇
  • Table 5 shows the shift value of the base graph 2, as shown in Table 5 below.
  • Step S206 interleaving; the interleaving is to interleave the LDPC codeword sequence to obtain an LDPC codeword sequence after interleaving.
  • the interleaving method includes: performing block interleaving on the LDPC codeword sequence, wherein determining a row number of the interlace matrix according to a quasi-cyclic LDPC encoding parameter, where the quasi-cyclic LDPC encoding parameter includes at least one of the following: Value, total number of columns in the base graph matrix, total number of rows in the base graph matrix, and number of base graph matrix system columns.
  • the number of rows of the interlace matrix is equal to a positive integer factor of the quasi-cyclic LDPC boost value, or a positive integer multiple of the boost value of the quasi-cyclic LDPC code.
  • the number of rows of the interleaving matrix is equal to a positive integer factor of the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding, or equal to the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding. Integer multiple.
  • the interleaving matrix is listed in a listed interlace.
  • the interleaved bit sequence is obtained in a predetermined column order.
  • intra-column interleaving is performed on columns in the interleaving matrix, where the intra-column interleaving method includes: cyclic shift interleaving and random sequence interleaving.
  • the intra-column interleaving method is determined according to a modulation order. Preferably, if the modulation order is greater than 2, the intra-column interleaving method is performed.
  • the interleaving method includes: mapping all bits of the S0th bit to the S1th bit in the LDPC codeword sequence to a S0th bit to an S1th bit of the interleaved codeword sequence according to a predetermined interleaving index sequence, S0 is a positive integer and S1 is an integer greater than S0.
  • the predetermined interleaving index sequence is obtained according to a block interleaving method, the number of columns of the block interleaving matrix is Z0, and the Z0 is a positive integer.
  • the Z0 is equal to a positive integer factor of the LDPC encoding boost value.
  • the Z0 is equal to Z
  • the Z is an LDPC coding boost value
  • the S0 is equal to 2 ⁇ Z
  • the S1 is equal to E ⁇ Z-1, where E is an integer greater than 2.
  • the E is equal to kb, kb+1, kb+2, kb+3 or kb+4, wherein the kb is the number of basic graph matrix system columns of the LDPC encoding.
  • the S0 is equal to kb ⁇ Z
  • the S1 is equal to E ⁇ Z ⁇ 1
  • the Z is an LDPC coding promotion value
  • the E is equal to kb+ ⁇ mb
  • the ⁇ mb is an integer greater than 0, the kb being the number of system columns of the LDPC coded base graph matrix.
  • the ⁇ mb is determined according to one of the following parameter combinations: combination 1, the number of system columns of the LDPC coded basic graph matrix and the code rate; combination 2, the length of the information packet bit sequence, the length of the bit sequence to be transmitted, and the LDPC coding
  • combination 1 the number of system columns of the LDPC coded basic graph matrix and the code rate
  • combination 2 the length of the information packet bit sequence, the length of the bit sequence to be transmitted, and the LDPC coding
  • the value of the LDPC code check bit and the LDPC code boost value are included in the bit sequence to be transmitted.
  • the Z0 is determined by the following parameters: S0, S1 and a modulation order, wherein the modulation order is the number of bits carried by each modulation symbol.
  • the Z0 is obtained according to the following calculation formula: Where M is the modulation order and M is a positive integer.
  • the specific value of the S1 is determined by the following parameters: the length of the information packet bit sequence and the length of the bit sequence to be transmitted.
  • the block interleaving as described above is performed, where the R0 is a real number greater than or equal to 3/4 and less than 1, and the code rate R is equal to the information.
  • the length of the packet bit sequence is divided by the value obtained by the length of the bit sequence to be transmitted.
  • the above-mentioned interleaving method has the beneficial effects that the LDPC codeword can be randomly randomized, and the LDPC code can obtain better performance advantages in high-order modulation (such as 64QAM and 256QAM); and can effectively improve the fading channel.
  • the performance of the LDPC code is not limited to 64QAM and 256QAM.
  • Step S207 rate matching; performing cyclic bit selection on the LDPC codeword sequence after the interleaving from the starting position to obtain a rate matched codeword sequence.
  • the method is characterized in that the starting position is determined according to a predetermined parameter, wherein the predetermined parameter includes at least one of the following: a redundancy version, a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system The number of columns, the length of the information packet bit sequence.
  • the starting position is determined according to the redundancy version, the boosting value, and the total number of columns of the basic graph matrix. Further, the starting position corresponding to the redundancy version RVi is obtained by the following formula:
  • nb in the formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the ⁇ is a positive integer
  • the G is a real number greater than 0
  • the ⁇ is a real real number
  • the ⁇ is a non-negative real number
  • the ⁇ is an integer
  • the funtion(x) indicates that the real number x is rounded up or rounded down or rounded off.
  • nb in the formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the ⁇ is a positive integer
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • ⁇ is a positive real number
  • the ⁇ is a non-negative integer
  • ⁇ is an integer
  • funtion(x) represents rounding up the real number x or rounding down or rounding off.
  • nb in the formula is the total number of columns of the basic graph matrix
  • the Z is the boost value
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • the ⁇ is a positive integer
  • ⁇ is a positive real number
  • the ⁇ is a non-negative integer
  • ⁇ is an integer
  • funtion(x) represents rounding up the real number x or rounding down or rounding off.
  • the starting position is determined according to the redundancy version, the boosting value, the total number of rows of the basic graph matrix, and the length of the information packet bit sequence. Further, the starting position corresponding to the redundancy version RVi is obtained by one of the following formulas:
  • K in the formula is the length of the information packet bit sequence
  • the Z is the boost value
  • the G is a real number greater than 0
  • the ⁇ is a positive integer
  • the ⁇ is a positive integer
  • the ⁇ is a positive real number
  • the ⁇ is a non-negative integer
  • ⁇ is an integer, where funtion(x) represents rounding up the real number x, or rounding down, or rounding off.
  • Step S208 constellation modulation; the bit sequence to be transmitted is divided into a plurality of bit packets, the plurality of bit packets are mapped onto a constellation modulation symbol, and the constellation modulation symbol is transmitted.
  • the bits in the bit packet are respectively interleaved before being mapped to the constellation modulation symbol, and then the each interleaved bit packet is mapped to the constellation modulation symbol.
  • the modulation order of the constellation modulation symbols is M, and the modulation order represents the number of bits carried by each constellation modulation symbol.
  • Constellation symbol modulation includes one of the following: BPSK, QPSK, 16QAM, 64QAM, and 256QAM, and the corresponding modulation orders are: 1, 2, 4, 6, and 8, respectively.
  • the intra-bit packet is interleaved according to a modulation order, and if the modulation order is greater than M1, the interleaving method is performed, where the M1 is equal to 2, 3, 4 , 5 or 6.
  • the intra-bit packet interleaving comprises: cyclic shift interleaving, random index sequence interleaving.
  • the interleaving method of any adjacent F constellation symbols in all the constellation modulation symbols is different, and F is a positive integer.
  • there is a G0 type bit intra-packet interleaving method the G0 kinds of methods are different from each other, and the bit inter-frame bit interleaving selects the G1 kinds of methods from the G0 kinds of interleaving methods in order.
  • the bits within the bit packet are interleaved.
  • there is a plurality of inter-packet method sets in a bit packet and the intra-bit packet interleaving method is determined from the plurality of inter-method method sets according to the modulation order.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
  • a data encoding device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term “module” may implement a combination of software and/or hardware of a predetermined function.
  • the devices described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • a data encoding apparatus including:
  • An interleaving module is connected to the acquiring module, configured to perform quasi-cyclic LDPC encoding on the to-be-transmitted data to obtain an LDPC codeword sequence, and interleave the LDPC codeword sequence to obtain an LDPC codeword sequence after interleaving;
  • a selection module connected to the interleaving module, configured to perform cyclic bit selection on the interleaved LDPC codeword sequence from a starting position to obtain a rate matched codeword sequence, wherein the starting position is determined according to a predetermined parameter,
  • the predetermined parameter includes at least one of the following: a redundancy version, a lifting value, a total number of basic graph matrix columns, a total number of basic graph matrix rows, a basic graph matrix system column number, and an information packet bit sequence length;
  • a sending module connected to the selecting module, configured to send the rate matched codeword sequence.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
  • the forms are located in different processors.
  • a processor for running a program wherein the program is executed while performing the method described in any of the above alternative embodiments.
  • a storage medium comprising a stored program, wherein the program is executed while performing the method described in any of the above alternative embodiments.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.

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Abstract

本发明提供了一种数据编码方法、装置、存储介质及处理器，其中，该方法包括：获取待发送数据；对该待发送数据进行准循环低密度奇偶校验码(LDPC)编码后获得LDPC码字序列，对该LDPC码字序列进行交织获得交织后LDPC码字序列；对该交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列，其中，根据预定参数确定该起始位置；发送该速率匹配后码字序列。采用上述方案，解决了相关技术中对传输数据进行准循环LDPC编码后传输不稳定的问题，实现了准循环LDPC编码后的稳定传输。

Description

数据编码方法、装置、存储介质及处理器
相关申请的交叉引用
本申请基于申请号为201710687764.6、申请日为2017年08月11日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及通信领域，具体而言，涉及一种数据编码方法、装置、存储介质及处理器。
背景技术
在相关技术中，针对准循环低密度奇偶校验码(Low Density Parity Check Code，LDPC)编码过程中一旦出现较多填充比特则会降低LDPC码的编码/译码效率的问题，提供一种TBS表格设计规则，使得在进行LDPC编码时填充比特尽量少或者没有；以及针对传输块中的码块组中可能存在各个码块组内的码块数目不等导致一些短板效应的问题，提供码块分割方法中的Kmax设计方法，使得每个码块组内的码块数目相等避免某些码块组内的码块数较多导致整体性能不好；以及，针对准循环LDPC编码在高阶调制或者衰落信道下出现的性能不好的问题，通过码字交织方法来提高准循环LDPC编码的性能。
在实际通信系统中，由于实际需要传输的传输块的比特数目不一定等于准循环LDPC编码基础矩阵所支持的系统比特长度，所以需要对传输块进行码块分割以及填充比特。但是，对传输块进行码块分割以及填充的比特会导致数据传输不稳定的问题，如：降低编码和译码速度，能耗高，影 响数据通信鲁棒性等。
针对相关技术中对传输数据进行准循环LDPC编码后传输不稳定的问题，目前还没有有效的解决方案。
发明内容
本发明实施例提供了一种数据编码方法、装置、存储介质及处理器，以至少解决相关技术中相关技术中对传输数据进行准循环LDPC编码后传输不稳定的问题。
根据本发明的一个实施例，提供了一种数据编码方法，包括：对信息分组比特序列进行准循环LDPC编码后获得LDPC码字序列，并根据所述LDPC码字序列确定一维有限长度循环缓存大小；从多个预定的冗余版本取值中选择一个冗余版本取值，并根据所述选择的冗余版本取值和预定义参数确定在所述一维有限长度循环缓存中读取待传输比特序列的起始位置；其中，所述的预定义参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；从所述起始位置开始，顺序读取特定长度的数据比特组成待传输比特序列，并发送所述待传输比特序列。
根据本发明的另一个实施例，还提供了一种数据编码装置，包括：获取模块，配置为获取待发送数据；交织模块，配置为对所述待发送数据进行准循环LDPC编码后获得LDPC码字序列，对所述LDPC码字序列进行交织获得交织后LDPC码字序列；选择模块，配置为对所述交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列，其中，根据预定参数确定所述起始位置，其中，所述预定参数包括以下至少之一：冗余版本、提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；发送模块，用于发送所述速率匹配后码字序列。
根据本发明的另一个实施例，还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述数据编码方法。
根据本发明的另一个实施例，还提供了一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述可选实施例上述数据编码方法。
通过本发明，获取待发送数据；对所述待发送数据进行准循环LDPC编码后获得LDPC码字序列，对所述LDPC码字序列进行交织获得交织后LDPC码字序列；对所述交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列，其中，根据预定参数确定所述起始位置；发送所述速率匹配后码字序列。采用上述方案，解决了相关技术中对传输数据进行准循环LDPC编码后传输不稳定的问题，实现了准循环LDPC编码后的稳定传输。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的数据编码方法的流程图；
图2是根据本发明优选实施例的一种LDPC编码数据处理流程图。
具体实施方式
本申请实施例中提供了一种移动通信网络(包括但不限于5G移动通信网络)，该网络的网络架构可以包括网络侧设备(例如基站)和终端。在本实施例中提供了一种可运行于上述网络架构上的信息传输方法，需要说明的是，本申请实施例中提供的上述信息传输方法的运行环境并不限于上述网络架构。
在对本发明实施例进行详细说明之前，先对数字通信系统中的编码方 法的相关技术进行简要说明。
在相关技术的数字通信系统中，一般包括三个部分：发送端、信道和接收端。发送端可对信息序列进行信道编码从而获取编码码字，对编码码字进行交织，并将交织后的比特映射成调制符号，然后可以根据通信信道信息来处理和发送调制符号。在信道中，由于多径、移动等因素导致特定的信道响应，这些都会使数据传输失真，同时由于噪声和干扰也会进一步恶化数据传输。接收端接收通过信道后的调制符号数据，此时的调制符号数据已经失真，需要进行特定处理才能恢复原始信息序列。
根据发送端对信息序列的编码方法，接收端可以对接收数据进行相应处理从而可靠地恢复原始信息序列。一般地，所述编码处理方法是基于前向纠错(Forward Error Correction，FEC)编码，其中，前向纠错编码在信息序列中添加一些冗余信息，而接收端可以利用该冗余信息来可靠地恢复原始信息序列。
一些常见的FEC编码包括：卷积码、Turbo码和LDPC码。FEC编码过程中，对比特数目为k的信息序列进行FEC编码获得n比特的FEC编码码字(冗余比特为n-k)，FEC编码码率为k/n。LDPC码是一种可以用非常稀疏的奇偶校验矩阵或者二分图定义的线性分组码，正是利用它的校验矩阵的稀疏性，才能实现低复杂度的编译码，从而使得LDPC走向实用化。经过各种实践和理论证明，LDPC码是在加性高斯白噪声(Additive White Gaussian Noise，AWGN)信道下性能最为优良的信道编码，性能非常靠近香农极限。LDPC码的奇偶校验矩阵中，每一行都是一个奇偶校验码，每一行中如果某一索引位置元素值等于1则说明该比特参与到该奇偶校验码中，如果等于0，则说明该位置比特不参与该奇偶校验码。
准循环LDPC码由于具有结构化特征，逐渐成为主流应用，如在IEEE802.11ac、IEEE802.11ad、IEEE802.11aj、IEEE802.16e、IEEE802.11n、 微波通信以及光纤通信等中获得大量应用，以及被第5代移动通信采纳为数据信道编码方案。准循环LDPC码的奇偶校验矩阵H为M×Z行和N×Z列的矩阵，它是由M×N个子矩阵构成，每个子矩阵都是大小为Z×Z的基本置换矩阵的不同幂次，也就是大小为Z×Z单位阵的循环移位若干值所获得的子矩阵。为了从数学上更容易描述单位阵的循环移位，准循环LDPC码的奇偶校验矩阵可以描述为有如下的数学公式形式：
Figure PCTCN2018095037-appb-000001
如果hb ij＝＝-1，则有
Figure PCTCN2018095037-appb-000002
是大小为Z×Z的全零矩阵；否则，
Figure PCTCN2018095037-appb-000003
是对标准置换矩阵P的非负整数次幂，所述的标准置换矩阵P如下所示：
Figure PCTCN2018095037-appb-000004
通过这样定义，Z和幂次hb ij可以唯一标识每一个分块矩阵，如果某一分块矩阵为全0矩阵，可以用“-1”来表示或者空值表示或者其他形式表示；而如果是单位阵的循环移位s获得，则等于s。所有hb ij可以构成一个准循环LDPC编码的基础矩阵Hb，进而LDPC码的基础矩阵Hb可以表示如下：
Figure PCTCN2018095037-appb-000005
所以，基础矩阵Hb中包含2种元素：1.指示全零方阵的元素；2.指示单位阵循环移位大小的元素，一般采用0～(Z-1)的整数表示。可以将所述基础矩阵Hb也称为基础校验矩阵或者移位值矩阵或者置换值矩阵或者基本奇偶校验矩阵或者奇偶校验矩阵，所述基础矩阵Hb中，如果将表示为全 零矩阵的元素替换为“0”元素，并且将其他元素替换为“1”元素，可以获得准循环LDPC编码的基本图矩阵(Base Graph)或者模板矩阵。其中所述的基本图矩阵也可以采用表格形式描述，例如采用行和列索引对来指示对应基本图矩阵的“1”的位置或者基础矩阵中的指示单位阵循环移位大小元素的位置。所以可以根据准循环LDPC码的模板矩阵和一组移位值(或系数)可以确定准循环LDPC编码的基础矩阵。以及，可以将所述基本置换矩阵或全零方阵的维数Z定义为提升值(shift size或者lifting size)或者扩展因子或者子矩阵大小。
所以，结构化LDPC码完全可以由基础校验矩阵Hb和提升值Z唯一确定。例如，基础矩阵Hb(2行4列)如下且对应的提升值z等于4。
Figure PCTCN2018095037-appb-000006
则对应的模板矩阵为：
Figure PCTCN2018095037-appb-000007
则根据基础矩阵Hb和提升值Z获得奇偶校验矩阵H为：
Figure PCTCN2018095037-appb-000008
在准循环LDPC编码过程中，可以直接根据由基础矩阵Hb和提升值Z确定的奇偶校验矩阵进行编码，根据LDPC码的定义，满足H×C＝0，而H包括[Hs Hp]，其中Hs是奇偶校验矩阵的系统列部分矩阵，Hp是奇偶校验矩阵的校验列部分矩阵，以及C可以包括[Cs Cp]，其中Cs是LDPC码的系统比特序列(信息比特，已知比特)，Cp是LDPC码的校验比特序列(未 知比特)，LDPC编码过程即是计算校验比特序列的过程；进而，Hs×Cs＝Hp×Cp；然后，可以计算获得校验比特序列为Cp＝inv(Hp)×Hs×Cs，其中，计算式inv(x)表示对矩阵x进行二进制求逆，所以奇偶校验矩阵的校验列部分矩阵必须是方阵而且是二进制可逆；进而可以获得准循环LDPC编码序列为[Cs Cp]。当然，也可以根据每个Z比特块的循环移位进行处理计算获得。
本申请人在实施数据传输的过程中发现，对传输块进行码块分割以及填充比特时，对于LDPC码来说，填充比特是用来辅助编码或译码的，实际是不传输的，但是在编码和译码过程中，如果出现较多的填充比特，会使得编码器或译码器执行较多无用操作，从而降低编码和译码速度，并且能耗也会比较高。并且如果传输块的长度比较大时，此时码块数目比较大，为了方便反馈和提高处理效率，需要对所有LDPC码块进行划分成多个码块组，每个码块组内包含若干个LDPC码块，并且在接收端以码块组为单位进行接收正确与否的反馈以及数据重传操作；如果在码块分割过程中，没有考虑到码块组的设计，那么在进行码块划分成码块组时会导致码块组内的码块数目不等，从而带来一些短板效应，影响数据通信鲁棒性。以及，由于准循环LDPC编码本身存在一定的结构化特性，在一些高阶调制中或者衰落信道中，LDPC码可能会存在一些性能不好的问题，需要将码字比特进行交织以随机化突发噪声，以提高准循环LDPC码字在突发噪声下的性能。
实施例一
在本实施例中提供了一种数据编码方法，图1是根据本发明实施例的数据编码方法的流程图，如图1所示，该流程包括如下步骤：
步骤S102，对信息分组比特序列进行准循环LDPC编码后获得LDPC码字序列，并根据所述LDPC码字序列确定一维有限长度循环缓存大小。
步骤S104，从多个预定的冗余版本取值中选择一个冗余版本取值，并根据所述选择的冗余版本取值和预定义参数确定在所述一维有限长度循环缓存中读取待传输比特序列的起始位置；其中，所述的预定义参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度。
步骤S106，从所述起始位置开始，顺序读取特定长度的数据比特组成待传输比特序列，并发送所述待传输比特序列。
通过上述步骤，对信息分组比特序列进行准循环LDPC编码后获得LDPC码字序列，并根据所述LDPC码字序列确定一维有限长度循环缓存大小；从多个预定的冗余版本取值中选择一个冗余版本取值，并根据所述选择的冗余版本取值和预定义参数确定在所述一维有限长度循环缓存中读取待传输比特序列的起始位置；其中，所述的预定义参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；从所述起始位置开始，顺序读取特定长度的数据比特组成待传输比特序列，并发送所述待传输比特序列。采用上述方案，解决了相关技术中对传输数据进行准循环LDPC编码后传输不稳定的问题，实现了准循环LDPC编码后的稳定传输。
在一实施例中，上述步骤的执行主体可以为基站、终端等，但不限于此。
在一实施例中，该对该LDPC码字序列进行交织获得交织后LDPC码字序列，包括：对该LDPC码字序列进行块交织，其中，根据该准循环LDPC编码参数确定该交织矩阵的行数，其中，该准循环LDPC编码参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数，该交织矩阵是列进列出交织。
在一实施例中，该交织矩阵的行数等于该准循环LDPC提升值的正整 数因子、或等于该准循环LDPC编码的提升值的正整数倍。
在一实施例中，该交织矩阵的行数等于该准循环LDPC编码的基本图矩阵总列数的正整数因子、或等于该准循环LDPC编码的基本图矩阵总列数的正整数倍。
在一实施例中，该交织方法还包括：按预定列顺序分别输出获得交织后比特序列。
在一实施例中，根据调制阶数确定该列内交织方法。
可选地，若该调制阶数大于M0，则执行该的列内交织方法，其中，该M0是大于1的整数。
在一实施例中，根据该冗余版本、该提升值和该基本图矩阵总列数确定该起始位置。
在一实施例中，对应于该冗余版本为RVi的该起始位置由以下公式计算获得：
第一公式：S i＝α×funtion(β×(nb/G)×RV i+χ)×Z+δ；
其中，该第一公式中的该nb是该基本图矩阵总列数，该Z是该提升值，该α是正整数，该G是大于0的实数，该β是正实数，该χ是非负实数，该δ是整数，其中，该funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整；
或者，第二公式：S i＝α×(β×funtion(λ×nb/G)×RV i+χ)×Z+δ；
其中，该第二公式中的nb是该基本图矩阵总列数，该Z是该提升值，该α是正整数，该G是大于0的实数，该是β正整数，该λ是正实数，该χ是非负整数，该δ是整数，其中，该funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整；
或者，第三公式：S i＝α×(β×funtion(λ×nb×Z/G)×RV i+χ)+δ；
其中，该第三公式中的nb是该基本图矩阵总列数，该Z是该提升值， 该G是大于0的实数，该α是正整数，该是β正整数，该λ是正实数，该χ是非负整数，该δ是整数，其中，该funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整。
在一实施例中，根据该冗余版本、该提升值、该基本图矩阵总行数和该信息分组比特序列长度确定该起始位置。
在一实施例中，对应于冗余版本为RVi的该起始位置由以下公式之一计算获得：
S i＝α×(β×funtion((K+mb×Z)/G)×RV i+χ)+δ；
S i＝α×(β×funtion((K+mb×Z)/G)+χ)×RV i+δ
其中，上述两个公式中的K是该信息分组比特序列长度，该Z是该提升值，该G是大于0的实数，该α是正整数，该是β正整数，该λ是正实数，该χ是非负整数，该δ是整数，其中funtion(x)表示对实数x进行向上取整，或者向下取整，或者四舍五入取整。
在一实施例中，对该LDPC码字序列进行交织获得交织后LDPC码字序列，包括：对该LDPC码字序列中的第S0比特到第S1比特的所有比特进行交织，其中，该S0，S1均是正整数，且该S1大于该S0。
在一实施例中，对该LDPC码字序列中的第S0比特到第S1比特的所有比特进行交织，包括：依据交织矩阵对该LDPC码字序列中的第S0比特到第S1比特的所有比特进行块交织，其中，该块交织矩阵的列数为Z0，该Z0是由准循环LDPC编码参数确定，其中，该准循环LDPC编码参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数。
在一实施例中，该Z0等于LDPC编码提升值的正整数因子。
在一实施例中，该Z0等于Z，该Z是LDPC编码提升值，该S0等于2×Z，该S1等于E×Z-1，其中E是大于2的整数。
在一实施例中，该E等于kb、kb+1、kb+2、kb+3或者kb+4，其中，该kb是LDPC编码的基本图矩阵系统列数。
在一实施例中，该Z0由以下参数确定：S0、S1和调制阶数，其中，该调制阶数是每个调制符号所携带的比特数目。
在一实施例中，该Z0根据以下计算公式获得：
Figure PCTCN2018095037-appb-000009
其中，该M是调制阶数，且该M是正整数。
在一实施例中，通过以下参数至少之一确定该S1的数值：对该待发送数据进行码块分割后获得的信息分组比特序列的长度；待传输比特序列的长度。
在一实施例中，当LDPC编码码率R小于等于R0时，依据交织矩阵对该LDPC码字序列中的第S0比特到第S1比特的所有比特进行交织，其中，该R0是大于等于3/4且小于1的实数，该LDCP编码码率R等于信息分组比特序列的长度与待传输比特序列的长度的商。
下面结合本发明优选实施例进行详细说明。
优选实施例1
在本实施例中提供了一种准循环LDPC编码数据处理方法，可以用于NR(New Radio Access Technology，新无线接入技术)通信系统。在本可选实施例中提出的方法可以用于LTE移动通信系统或者未来第五代(5G)移动通信系统或者其他无线有线通信系统，数据传输方向为基站向移动用户发送数据(下行传输业务数据)，或者数据传输方向为移动用户向基站发送数据(上行传输业务数据)。移动用户包括：移动设备、为接入终端、用户终端、用户站、用户单元、移动站、远程站、远程终端、用户代理、用户装置、用户设备、或一些其它术语。基站包括接入点(Access Point，AP)、或可以称为节点B(node B)、无线电网络控制器(Radio Network Controller，RNC)、演进型Node B(Evolved Node B，eNB)、基站控制器(Base Station  Controller，BSC)、基站收发台(Base Transceiver Station，BTS)、基站(Base Station，BS)、收发机功能体(Transceiver Function，TF)、无线电路由器、无线电收发机、基本服务单元、扩展服务单元、无线电基站(Radio Base Station，RBS)，或一些其它术语。
根据本可选实施例的一个方面，本可选实施例提供的一种准循环LDPC编码数据处理方法，可以应用于新无线接入技术(New Radio Access Technology，简称为new RAT)中的增强移动宽带(enhanced Mobile Broadband，简称为eMBB)场景、超可靠低时延通信(Ultra-Reliable and Low Latency Communications，简称为URLLC)场景或者大规模物联网(massive Machine Type Communications，简称为mMTC)场景中。
图2是根据本发明优选实施例的一种LDPC编码数据处理流程图，如图2所示，包括以下步骤：
步骤S201，获取待传输源数据包的长度信息；依据控制信息从TBS表格中确定当前需要发送的待传输源数据包的长度(也叫传输快大小Transport Block Size，TBS)，所述控制信息可以是下行控制信息或者是上行控制信息或者其他系统信息中获取。
步骤S202，码块分割；对所述待传输源数据包按最长信息块长度Kmax进行分割，其中，分割获得信息分组比特序列数目为
Figure PCTCN2018095037-appb-000010
码块分割后获得的信息分组比特序列长度包括：
Figure PCTCN2018095037-appb-000011
和
Figure PCTCN2018095037-appb-000012
其中K是所述信息分组比特序列的长度，K是正整数，Kmax是正整数，所述L是每个信息分组比特序列添加的CRC序列长度。
步骤S203，添加CRC序列；在码块分割后获得每个信息比特块中添加L比特的CRC(Cyclic Redundancy Check)序列，所述L是大于0的整数。
步骤S204，填充比特；在添加CRC序列后的信息比特块中填充亚元比特，其中亚元比特只是用于辅助编码，不进行传输。
步骤S205，准循环LDPC编码；依据码块分割后获得的各个信息分组比特序列长度确定LDPC编码所使用的提升值，根据所述获得的提升值信息确定并计算LDPC编码的校验矩阵，根据所述校验矩阵和LDPC编码提升值对应各个信息分组比特序列进行准循环LDPC编码获得LDPC码字序列。
其中，所述准循环LDPC编码的基本图矩阵包括两种：base graph 1和base graph 2。其中基本图矩阵base graph 1的行数为46，列数为68，即基本图矩阵总列数等于68，基本图矩阵总行数等于46，以及基本图矩阵系统列数等于68-46＝22；基本图矩阵base graph 2的行数为42，列数为52，即基本图矩阵总列数等于52，基本图矩阵总行数等于42，以及基本图矩阵系统列数等于52-42＝10。依据基本图矩阵总列数等于68或者基本图矩阵总行数等于46或者基本图矩阵系统列数等于22，则可以判断确定对应的基本图矩阵索引为1(base graph 1)；以及依据基本图矩阵总列数等于52或者基本图矩阵总行数等于42或者基本图矩阵系统列数等于10，则可以判断确定对应的基本图矩阵索引为2(base graph 2)。如表1所示为基本图矩阵base graph 1和base graph 2中的对应行索引为i的“1”位置，即其可以替换为循环置换单位阵位置。表2对应于基本图矩阵base graph 1所支持的提升值，包括8个提升值集合；表4对应于基本图矩阵base graph 2所支持的提升值，也包括8个提升值集合。根据以上所述的提升值信息确定提升值集合索引号i LS，根据所述提升值集合索引号i LS从表格3中获取基本图矩阵base graph 1对应每个提升值集合的移位值矩阵，以及也可以根据提升值集合索引号从表格5中获取基本图矩阵base graph 2对应每个提升值集合的移位值矩阵，然后根据公式P i,j＝mod(V i,j,Z c)就可以获得对应于当前提升值Z c的基本图矩阵。如果所述信息分组比特序列大小小于或等于2560并且码率小于或等于2/3，则选择基本图矩阵base graph 2，否则选择基本图矩阵base graph 1。说 明：表1中，第1列对应于指示基本图矩阵base graph 1和基本图矩阵base graph 2的行索引号i，第2列对应于指示基本图矩阵base graph 1的列索引号j，[i,j]共同确定基本图矩阵base graph 1的“1”位置；以及第3列为对应于指示基本图矩阵base graph 2的列索引号j。表3和表4分别说明对应基本图矩阵base graph 1和基本图矩阵base graph 2的8个移位值矩阵，其中，i用于指示行索引，j用于指示列索引，i LS是用于指示提升值集合索引号。
表1基本图矩阵base graph 1和基本图矩阵base graph 2，如下表1所示，
Figure PCTCN2018095037-appb-000013
表2基本图矩阵1(base graph 1)的提升值，如下表2所示，
Set index(i LS) Set of lifting sizes
1 {2,4,8,16,32,64,128,256}
2 {3,6,12,24,48,96,192,384}
3 {5,10,20,40,80,160,320}
4 {7,14,28,56,112,224}
5 {9,18,36,72,144,288}
6 {11,22,44,88,176,352}
7 {13,26,52,104,208}
8 {15,30,60,120,240}
表3基本图矩阵1(base graph 1)的移位值，如下表3所示，
Figure PCTCN2018095037-appb-000014
Figure PCTCN2018095037-appb-000015
表4基本图矩阵2(base graph 2)的提升值，如下表4所示，
Set index(i LS) Set of lifting sizes
1 {2,4,8,16,32,64,128,256}
2 {3,6,12,24,48,96,192}
3 {5,10,20,40,80,160}
4 {7,14,28,56,112,224}
5 {9,18,36,72,144}
6 {11,22,44,88,176}
7 {13,26,52,104,208}
8 {15,30,60,120,240}
表5基本图矩阵2(base graph 2)的移位值，如下表5所示，
Figure PCTCN2018095037-appb-000016
Figure PCTCN2018095037-appb-000017
步骤S206，交织；所述交织是对LDPC码字序列进行交织，获得交织后LDPC码字序列。所述交织方法包括：对所述LDPC码字序列进行块交织，其中，根据准循环LDPC编码参数确定所述交织矩阵的行数，其中，所述准循环LDPC编码参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数。
一种具体实施方式中，所述交织矩阵的行数等于所述准循环LDPC提升值的正整数因子、或等于所述准循环LDPC编码的提升值的正整数倍。
一种具体实施方式中，所述交织矩阵的行数等于所述准循环LDPC编码的基本图矩阵总列数的正整数因子、或等于所述准循环LDPC编码的基本图矩阵总列数的正整数倍。
一种具体实施方式中，所述交织矩阵是列进列出交织。
一种具体实施方式中，所述交织方法中，按预定列顺序输出获得交织后比特序列。
一种具体实施方式中，所述交织方法中，对所述交织矩阵中的列分别进行列内交织，其中，所述列内交织方法包括：循环移位交织、随机序列交织。优选地，根据调制阶数确定所述列内交织方法。优选地，若所述调制阶数大于2，则执行所述的列内交织方法。
所述交织方法包括：对所述LDPC码字序列中的第S0比特到第S1比特的所有比特按预定交织索引序列映射到所述交织后码字序列的第S0比特到第S1比特，所述S0是正整数，S1是大于S0整数。
所述预定交织索引序列根据块交织方法获得，所述块交织矩阵的列数为Z0，所述Z0是正整数。
更为具体的一种实施方式中，所述Z0等于LDPC编码提升值的正整数 因子。
更为具体的一种实施方式中，所述Z0等于Z，所述Z是LDPC编码提升值，所述S0等于2×Z，所述S1等于E×Z-1，其中E是大于2的整数。进一步地，所述E等于kb、kb+1、kb+2、kb+3或者kb+4，其中，所述kb是LDPC编码的基本图矩阵系统列数。
优选地，更为具体的一种实施方式中，所述S0等于kb×Z，所述S1等于E×Z-1，其中，所述Z是LDPC编码提升值，所述E等于kb+Δmb，以及所述Δmb是大于0的整数，所述kb是LDPC编码基本图矩阵的系统列数。进一步地，所述Δmb根据以下参数组合之一确定：组合1，LDPC编码基本图矩阵的系统列数和编码码率；组合2，信息分组比特序列的长度、待传输比特序列的长度和LDPC编码提升值；组合3，待传输比特序列中包含LDPC码校验比特的数目和LDPC编码提升值。
更为具体的一种实施方式中，所述Z0由以下参数确定：S0、S1和调制阶数，其中，所述调制阶数是每个调制符号所携带的比特数目。优选地，所述Z0根据以下计算公式获得：
Figure PCTCN2018095037-appb-000018
其中，M是调制阶数，并且M是正整数。
更为具体的一种实施方式中，所述S1的具体数值由以下参数确定：信息分组比特序列的长度和待传输比特序列的长度。
更为具体的一种实施方式中，当码率R小于等于R0时，进行如上所述的块交织，其中，所述R0是大于或等于3/4且小于1的实数，码率R等于信息分组比特序列的长度除以待传输比特序列的长度所获得的数值。
以上所述的交织方法的有益效果在于：可以非常有效地随机化LDPC码字，可以使得LDPC码在高阶调制(如64QAM和256QAM)中获得较好性能优势；以及可以有效提高在衰落信道中的LDPC码的性能。
步骤S207，速率匹配；对交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列。其中特征在于，根据预定参数确定所述起始位置，其中，所述预定参数至少包括以下之一：冗余版本、提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度。
一种具体实施方式中，根据所述冗余版本、所述提升值和所述基本图矩阵总列数确定所述起始位置。进一步地，对应于冗余版本为RVi的所述起始位置由以下公式计算获得：
S i＝α×funtion(β×(nb/G)×RV i+χ)×Z+δ
其中，所述公式中的nb是所述基本图矩阵总列数，所述Z是所述提升值，所述α是正整数，所述G是大于0的实数，所述是β正实数，所述χ是非负实数，所述δ是整数，其中funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整。
以及进一步地，对应于冗余版本为RVi的所述起始位置由以下公式计算获得：
S i＝α×(β×funtion(λ×nb/G)×RV i+χ)×Z+δ
其中，所述公式中的nb是所述基本图矩阵总列数，所述Z是所述提升值，所述α是正整数，所述G是大于0的实数，所述β是正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整。
以及进一步地，对应于冗余版本为RVi的所述起始位置由以下公式计算获得：
S i＝α×(β×funtion(λ×nb×Z/G)×RV i+χ)+δ
其中，所述公式中的nb是所述基本图矩阵总列数，所述Z是所述提升值，所述G是大于0的实数，所述α是正整数，所述是β正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整。
一种具体实施方式中，根据所述冗余版本、所述提升值、所述基本图矩阵总行数和所述信息分组比特序列长度确定所述起始位置。进一步地，对应于冗余版本为RVi的所述起始位置由以下公式之一计算获得：
S i＝α×(β×funtion((K+mb×Z)/G)×RV i+χ)+δ；
S i＝α×(β×funtion((K+mb×Z)/G)+χ)×RV i+δ
其中，所述公式中的K是所述信息分组比特序列长度，所述Z是所述提 升值，所述G是大于0的实数，所述α是正整数，所述是β正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中funtion(x)表示对实数x进行向上取整，或者向下取整，或者四舍五入取整。
对交织后码字序列进行循环比特选择，其中，将交织后的码字序列中的第2×Z比特到尾比特存放于一个循环缓存中，依据冗余版本从所述循环缓存中依次获取N比特，构成待传输比特序列。
步骤S208，星座调制；所述待传输比特序列分为多个比特分组，将所述的多个比特分组映射到星座调制符号上，并发送所述星座调制符号。其中，一种优选实施方式中，在在映射到星座调制符号之前，分别对所述比特分组内的比特进行交织，然后将所述各个交织后比特分组映射到星座调制符号。所述星座调制符号的调制阶数为M，所述调制阶数表示每个星座调制符号所携带的比特数目。星座符号调制包括以下之一：BPSK、QPSK、16QAM、64QAM和256QAM，以及所对应的调制阶数分别为：1、2、4、6和8。优选地，一种具体实施方式中，根据调制阶数确定所述比特分组内交织，如若所述调制阶数大于M1，则执行所述的交织方法，其中，所述M1等于2、3、4、5或者6。优选地，所述比特分组内交织包括：循环移位交织、随机索引序号交织。其中优选地，所述所有星座调制符号中任意相邻的F个星座符号的交织方法不同，F是正整数。另外一种实施方式中，存在G0种比特分组内交织方法，所述G0种方法之间不相同，所述比特分组内比特交织从所述G0种交织方法选择G1种方法按一定顺序依次对各个比特分组内比特进行交织。另外一种实施方式中，其特征在于，存在多个比特分组内交织方法集合，根据所述调制阶数从所述多个交织方法集合中确定比特分组内交织方法。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以 是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例所述的方法。
实施例二
在本实施例中还提供了一种数据编码装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
根据本发明的另一个实施例，还提供了一种数据编码装置，包括：
获取模块，配置为获取待发送数据；
交织模块，连接至所述获取模块，配置为对所述待发送数据进行准循环LDPC编码后获得LDPC码字序列，对所述LDPC码字序列进行交织获得交织后LDPC码字序列；
选择模块，连接至所述交织模块，配置为对所述交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列，其中，根据预定参数确定所述起始位置，其中，所述预定参数包括以下至少之一：冗余版本、提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；
发送模块，连接至所述选择模块，配置为发送所述速率匹配后码字序列。
需要补充的是，在实施例一中的方法步骤均可以由本实施例中的装置来执行。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
实施例三
根据本发明的另一个实施例，还提供了一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述可选实施例任一项中所述的方 法。
实施例四
根据本发明的另一个实施例，还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述可选实施例任一项中所述的方法。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (30)

  1. 一种低密度奇偶校验数据编码方法，包括：
    对信息分组比特序列进行准循环低密度奇偶校验码LDPC编码后获得LDPC码字序列；
    根据所述LDPC码字序列确定一维有限长度循环缓存大小；
    从多个预定的冗余版本取值中选择一个冗余版本取值，并根据所述选择的冗余版本取值和预定义参数确定在所述一维有限长度循环缓存中读取待传输比特序列的起始位置；其中，所述的预定义参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；
    从所述起始位置开始，顺序读取特定长度的数据比特，以组成待传输比特序列；
    发送所述待传输比特序列。
  2. 根据权利要求1所述的方法，其中，所述根据所述LDPC码字序列确定一维有限长度循环缓存大小，包括：
    对所述LDPC码字序列进行交织获得交织后LDPC码字序列，并获取一维有限长度循环缓存数据。
  3. 根据权利要求2所述的方法，其中，所述对所述LDPC码字序列进行交织获得交织后LDPC码字序列，包括：
    对所述LDPC码字序列进行块交织，其中，根据所述准循环LDPC编码参数确定交织矩阵的行数；所述准循环LDPC编码参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数。
  4. 根据权利要求3所述的方法，其中，所述交织矩阵的行数等于所述准循环LDPC提升值的正整数因子、或等于所述准循环LDPC编码的提升值的正整数倍。
  5. 根据权利要求3所述的方法，其中，所述交织矩阵的行数等于所述准循环LDPC编码的基本图矩阵总列数的正整数因子、或等于所述 准循环LDPC编码的基本图矩阵总列数的正整数倍。
  6. 根据权利要求3至5任一项所述的方法，其中，所述交织方法还包括：按预定列顺序分别输出获得所述交织后LDPC比特序列。
  7. 根据权利要求6所述的方法，其中，所述交织方法还包括：对每列分别进行交织。
  8. 根据权利要求1所述的方法，其中，根据所述冗余版本、所述提升值和所述基本图矩阵总列数确定所述起始位置。
  9. 根据权利要求8所述的方法，其中，对应于所述冗余版本为RVi的所述起始位置由以下公式计算获得：
    第一公式：S i＝α×funtion(β×(nb/G)×RV i+χ)×Z+δ；
    其中，所述第一公式中的所述nb是所述基本图矩阵总列数，所述Z是所述提升值，所述α是正整数，所述G是大于0的实数，所述β是正实数，所述χ是非负实数，所述δ是整数，其中，所述funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整；
    或者，第二公式：S i＝α×(β×funtion(λ×nb/G)×RV i+χ)×Z+δ；
    其中，所述第二公式中的nb是所述基本图矩阵总列数，所述Z是所述提升值，所述α是正整数，所述G是大于0的实数，所述是β正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中，所述funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整；
    或者，第三公式：S i＝α×(β×funtion(λ×nb×Z/G)×RV i+χ)+δ；
    其中，所述第三公式中的nb是所述基本图矩阵总列数，所述Z是所述提升值，所述G是大于0的实数，所述α是正整数，所述是β正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中，所述funtion(x)表示对实数x进行向上取整或者向下取整或者四舍五入取整。
  10. 根据权利要求1所述的方法，其中，根据所述冗余版本、所述提升值、所述基本图矩阵总行数和所述信息分组比特序列长度确定所述起始位置。
  11. 根据权利要求10所述的方法，其中，对应于冗余版本为RVi的所述起始位置由以下公式之一计算获得：
    S i＝α×(β×funtion((K+mb×Z)/G)×RV i+χ)+δ；
    S i＝α×(β×funtion((K+mb×Z)/G)+χ)×RV i+δ
    其中，上述两个公式中的K是所述信息分组比特序列长度，所述Z是所述提升值，mb是所述基本图矩阵总行数，所述G是大于0的实数，所述α是正整数，所述是β正整数，所述λ是正实数，所述χ是非负整数，所述δ是整数，其中funtion(x)表示对实数x进行向上取整，或者向下取整，或者四舍五入取整。
  12. 根据权利要求2所述的方法，其中，对所述LDPC码字序列进行交织获得交织后LDPC码字序列，包括：
    对所述LDPC码字序列中的第S0比特到第S1比特的所有比特进行交织，其中，所述S0，S1均是正整数，且所述S1大于所述S0。
  13. 根据权利要求12所述的方法，其中，对所述LDPC码字序列中的第S0比特到第S1比特的所有比特进行交织，包括：
    依据交织矩阵对所述LDPC码字序列中的第S0比特到第S1比特的所有比特进行块交织，其中，所述块交织矩阵的列数为Z0，所述Z0是由准循环LDPC编码参数确定，其中，所述准循环LDPC编码参数至少包括以下之一：提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度。
  14. 根据权利要求13所述的方法，其中，所述Z0等于所述提升值的正整数因子、或者所述提升值的正整数倍。
  15. 根据权利要求13所述的方法，其中，所述Z0等于所述基本图矩阵总列数的正整数因子、或者所述基本图矩阵总列数的正整数倍。
  16. 根据权利要求12所述的方法，其中，所述S1等于所述提升值的正整数倍。
  17. 根据权利要求15所述的方法，其中，所述S1等于提升值的kb-2、kb-1、kb、kb+1或者kb+2倍，其中，所述kb是所述基本图矩阵系统列数。
  18. 根据权利要求13所述的方法，其中，所述Z0由以下参数确定：S0、S1和调制阶数，其中，所述调制阶数是每个调制符号所携带的比特数目。
  19. 根据权利要求18所述的方法，其中，所述Z0根据以下计算 公式获得：Z0＝function(α×(S1-S1+1)/M+δ)，其中，所述M是正整数，所述α是正实数，所述δ是非负整数，funtion(x)表示对实数x进行向上取整，或者向下取整，或者四舍五入取整。
  20. 根据权利要求12所述的方法，其中，通过以下参数至少之一确定所述S1的数值：
    信息分组比特序列的长度；
    待传输比特序列的长度。
  21. 根据权利要求2至7、12至20任一项所述的方法，其中，根据调制阶数确定所述交织方法。
  22. 根据权利要求21所述的方法，其中，若所述调制阶数大于M0，则执行所述的交织方法，其中，所述M0是大于1的整数。
  23. 根据权利要求2至7、12至20任一项所述的方法，其中，根据码率确定所述交织方法，其中，所述码率等于所述信息分组比特序列长度与所述待传输比特序列的比值，所述码率是大于0小于1的实数。
  24. 根据权利要求23所述的方法，其中，若所述码率大于R0，则执行所述的交织方法，其中，所述R0是大于1/2且小于1的实数。
  25. 根据权利要求1所述的方法，其中，所述发送所述待传输比特序列，包括：所述待传输比特序列分为多个比特分组，分别对所述比特分组内的比特进行交织，然后将所述各个交织后比特分组映射到星座调制符号。
  26. 根据权利要求25所述的方法，其中，其特征在于，根据调制阶数确定所述比特分组内交织。
  27. 根据权利要求26所述的方法，其中，若所述调制阶数大于M1，则执行所述的交织方法，其中，所述M1等于2、3、4、5或者6。
  28. 一种数据编码装置，包括：
    获取模块，配置为获取待发送数据；
    交织模块，配置为对所述待发送数据进行准循环低密度奇偶校验码LDPC编码后获得LDPC码字序列，对所述LDPC码字序列进行交织获得交织后LDPC码字序列；
    选择模块，配置为对所述交织后LDPC码字序列从起始位置开始进行循环比特选择获得速率匹配后码字序列，其中，根据预定参数确定所述起始位置，其中，所述预定参数包括以下至少之一：冗余版本、提升值、基本图矩阵总列数、基本图矩阵总行数、基本图矩阵系统列数、信息分组比特序列长度；
    发送模块，配置为发送所述速率匹配后码字序列。
  29. 一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述权利要求1至27任一项中所述的方法。
  30. 一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述权利要求1至27任一项中所述的方法。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020231124A1 (en) * 2019-05-10 2020-11-19 Samsung Electronics Co., Ltd. Method and apparatus for data transmission in wireless communication system
US11233531B2 (en) 2017-09-11 2022-01-25 Zte Corporation Methods and apparatus for processing LDPC coded data
CN114760662A (zh) * 2022-04-25 2022-07-15 北京星河亮点技术股份有限公司 一种低时延速率匹配方法、装置、电子设备及存储介质

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2525496A1 (en) * 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
CN108809509B (zh) * 2017-05-05 2021-01-22 电信科学技术研究院 低密度奇偶校验码的基础图选择方法及装置
MA47865B1 (fr) * 2017-08-24 2020-09-30 Ericsson Telefon Ab L M Sélection de graphe de base pour une nouvelle radio 3gpp
WO2020167088A1 (en) * 2019-02-15 2020-08-20 Samsung Electronics Co., Ltd. Method and apparatus for transmission or reception of data in communication system
CN112367088B (zh) * 2020-10-27 2023-03-21 上海宇航系统工程研究所 一种基于索引矩阵的编码方法及装置
US11764911B2 (en) 2021-04-05 2023-09-19 Nokia Technologies Oy Method of shifting redundancy version for the transmission of a transport block over multiple slots
CN115913472A (zh) * 2021-09-30 2023-04-04 华为技术有限公司 重传方法及装置
WO2023090480A1 (ko) * 2021-11-18 2023-05-25 엘지전자 주식회사 무선 통신 시스템에서 무선 신호 송수신 방법 및 장치
CN118473590A (zh) * 2023-02-09 2024-08-09 中兴通讯股份有限公司 一种数据传输方法、通信装置及存储介质
CN118473592A (zh) * 2023-02-09 2024-08-09 中兴通讯股份有限公司 数据传输方法、通信装置及存储介质
CN116318552B (zh) * 2023-03-15 2023-09-22 归芯科技(深圳)有限公司 Turbo码的交织或解交织方法及其器件、通信芯片和装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188428A (zh) * 2007-12-10 2008-05-28 中兴通讯股份有限公司 一种ldpc码的有限长度循环缓存的速率匹配方法
CN102075196A (zh) * 2010-12-10 2011-05-25 清华大学 多码率多码长qc-ldpc码构建方法及编码调制系统
US20110161772A1 (en) * 2008-09-02 2011-06-30 Panasonic Corporation Wireless communication device and wireless communication method
CN105811996A (zh) * 2014-12-30 2016-07-27 华为技术有限公司 一种基于准循环ldpc的数据处理方法及系统
CN107026654A (zh) * 2016-02-02 2017-08-08 中国科学院声学研究所 一种准循环多进制低密度奇偶校验码的快速频域编码方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1252935C (zh) * 2002-12-13 2006-04-19 清华大学 基于低密度奇偶检验编码的信源信道联合编码方法
KR100744343B1 (ko) * 2003-12-19 2007-07-30 삼성전자주식회사 이동 통신 시스템에서 불균일 오류 확률을 갖는 부호화에따른 데이터 송수신 방법 및 장치
KR100860504B1 (ko) * 2005-06-09 2008-09-26 삼성전자주식회사 이동통신 시스템에서 송수신 장치 및 방법
CN101034953B (zh) * 2006-03-06 2010-06-23 诺基亚西门子通信系统技术（北京）有限公司 应用低密度奇偶校验码进行数据传输的方法
US8024633B2 (en) * 2007-05-10 2011-09-20 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for combined packet retransmission and soft decoding of combined packets in a wireless communication network
CN101325474B (zh) 2007-06-12 2012-05-09 中兴通讯股份有限公司 Ldpc码的混合自动请求重传的信道编码及调制映射方法
CN101227259B (zh) * 2008-01-11 2013-06-05 中兴通讯股份有限公司 一种有限长度循环缓存速率匹配的数据读取方法
US8612820B2 (en) * 2009-04-11 2013-12-17 Qualcomm Incorporated Apparatus and methods for interleaving in a forward link only system
CN102035617B (zh) * 2009-09-29 2015-04-01 中兴通讯股份有限公司 一种通信系统中信道编码的速率匹配方法和装置
WO2014200303A1 (en) 2013-06-14 2014-12-18 Samsung Electronics Co., Ltd. Apparatuses and methods for encoding and decoding of parity check codes
KR102146803B1 (ko) * 2013-06-14 2020-08-21 삼성전자주식회사 패리티 검사 부호의 부호화 장치, 그의 부호화 방법, 복호화 장치 및 그의 복호화 방법
EP3131219B1 (en) 2014-04-30 2023-11-15 Huawei Technologies Co., Ltd. Puncturing of ldpc codes
WO2017091018A1 (en) 2015-11-24 2017-06-01 Samsung Electronics Co., Ltd. Method and apparatus for channel encoding/decoding in a communication or broadcasting system
US10291356B2 (en) * 2016-05-11 2019-05-14 Futurewei Technologies, Inc. Decoding procedures in systems with codeblock segmentation
KR102131834B1 (ko) * 2016-09-30 2020-07-08 엘지전자 주식회사 Qc ldpc 코드의 레이트 매칭 방법 및 이를 위한 장치
US10447312B2 (en) * 2016-11-25 2019-10-15 Lg Electronics Inc. Method of performing interleaving using LDPC and communication apparatus therefor
US10348329B2 (en) * 2017-02-13 2019-07-09 Qualcomm Incorporated Low density parity check (LDPC) circular buffer rate matching
US10778366B2 (en) * 2017-03-31 2020-09-15 Qualcomm Incorporated Techniques for rate matching and interleaving in wireless communications
JP2019004245A (ja) * 2017-06-13 2019-01-10 シャープ株式会社 端末装置、基地局装置、および、通信方法
CN110266448B (zh) * 2017-06-19 2020-11-10 华为技术有限公司 信息处理的方法、通信装置和存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188428A (zh) * 2007-12-10 2008-05-28 中兴通讯股份有限公司 一种ldpc码的有限长度循环缓存的速率匹配方法
US20110161772A1 (en) * 2008-09-02 2011-06-30 Panasonic Corporation Wireless communication device and wireless communication method
CN102075196A (zh) * 2010-12-10 2011-05-25 清华大学 多码率多码长qc-ldpc码构建方法及编码调制系统
CN105811996A (zh) * 2014-12-30 2016-07-27 华为技术有限公司 一种基于准循环ldpc的数据处理方法及系统
CN107026654A (zh) * 2016-02-02 2017-08-08 中国科学院声学研究所 一种准循环多进制低密度奇偶校验码的快速频域编码方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LG ELECTRONICS: "On rate matching with LDPC code for eMBB", 3GPP DRAFT; R1-1710343_ON RATE MATCHING WITH LDPC CODE FOR EMBB_FINAL, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, 26 June 2017 (2017-06-26), France, XP051299558 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11233531B2 (en) 2017-09-11 2022-01-25 Zte Corporation Methods and apparatus for processing LDPC coded data
US11728830B2 (en) 2017-09-11 2023-08-15 Zte Corporation Methods and apparatus for processing LDPC coded data
WO2020231124A1 (en) * 2019-05-10 2020-11-19 Samsung Electronics Co., Ltd. Method and apparatus for data transmission in wireless communication system
CN114760662A (zh) * 2022-04-25 2022-07-15 北京星河亮点技术股份有限公司 一种低时延速率匹配方法、装置、电子设备及存储介质

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