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WO2017152581A1 - 阵列基板及其制作方法以及显示装置 - Google Patents

阵列基板及其制作方法以及显示装置 Download PDF

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Publication number
WO2017152581A1
WO2017152581A1 PCT/CN2016/095290 CN2016095290W WO2017152581A1 WO 2017152581 A1 WO2017152581 A1 WO 2017152581A1 CN 2016095290 W CN2016095290 W CN 2016095290W WO 2017152581 A1 WO2017152581 A1 WO 2017152581A1
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Prior art keywords
common electrode
thin film
gate line
pattern
adjacent
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PCT/CN2016/095290
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English (en)
French (fr)
Inventor
木素真
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/512,508 priority Critical patent/US20190088681A1/en
Publication of WO2017152581A1 publication Critical patent/WO2017152581A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • a dual gate structure design is proposed in the related art.
  • two gate lines are disposed between adjacent two rows of pixels, and the previous one of the two gate lines connects the upper row of pixels of the two rows of pixels, and the next gate line Connect the next row of pixels in the two rows of pixels.
  • a common electrode trace parallel to the gate line is formed in the non-opening region between adjacent two rows of pixels.
  • the material of the common electrode trace is generally a metal having a low resistivity, and the common electrode trace is connected to the common electrode through a plurality of via holes and supplies a common voltage to the common electrode, thereby ensuring uniformity of voltage on the common electrode.
  • One purpose of the present disclosure is to increase the aperture ratio of a pixel.
  • a first aspect of the present disclosure provides an array substrate including: a substrate and a substrate A common electrode layer, a thin film transistor array, a pixel electrode pattern, a data line pattern, a gate line pattern, a common electrode trace pattern, and a connection portion pattern disposed on the substrate.
  • each gate line group is disposed between each pair of adjacent two rows of pixels, each gate line group includes two gate lines, and two columns of pixels are disposed between adjacent two data lines; each data line Two thin film transistors are connected at a position overlapping each of the gate line groups, and each of the two thin film transistors is correspondingly connected to one of the gate line groups; the common electrode trace pattern And the data line pattern is disposed in the same layer, and includes a plurality of sets of row direction common electrode traces; each set of row direction common electrode traces is disposed between the adjacent two rows of pixels, and each set of rows Each row direction common electrode trace in the direction common electrode trace is located in an idle area between the adjacent two data lines, the idle area being in a column direction and the adjacent two rows of pixels The individual thin film transistors are aligned.
  • connection portion pattern includes a plurality of connection portions, each of the plurality of connection portions being disposed at the position where each of the data lines overlaps each of the gate line groups, and is common in each of the row directions a via hole is disposed in a layer structure between the end of the electrode trace and the connection portion adjacent in the row direction, and the connection portion connects the adjacent two row direction common electrode traces through the via hole; and each of the a layer structure between the row electrode common electrode trace and the common electrode layer is further provided with a via hole at a position of the common electrode trace in each row direction, and each of the row direction common electrode traces The common electrode layer is connected through the via.
  • the common electrode trace pattern further includes a plurality of column direction common electrode traces, and each of the plurality of column direction common electrode traces is disposed correspondingly to the adjacent two data in the common electrode trace Between two adjacent columns of pixels between the lines, each of the row-direction common electrode traces and one of the plurality of column-direction common electrode traces are connected to the common electrode trace.
  • the common electrode trace pattern further includes a plurality of sets of auxiliary common electrode traces in a row direction; and each set of auxiliary common electrode traces is located at a bend of one row of pixel electrodes in a column direction, each of the groups Each of the auxiliary common electrode traces is located between the adjacent two data lines and is connected to one of the plurality of column-direction common electrode traces in the column direction common electrode trace.
  • each of the thin film transistors is correspondingly connected to one of the gate line groups and is in a bit And a side of the connected one of the gate lines that is away from the other of the gate lines, and further connected to the one of the connected ones of the gate lines that are away from the other of the gate lines a pixel electrode in one of the pixel rows; in each of the plurality of pairs of thin film transistors connected at a position overlapping the same gate line group in each of the data lines, the first thin film transistor in each pair is located in the gate line group a first side, the second thin film crystal in each pair is located on the second side of the gate line group; the fourth connected to the same data line at a position overlapping the two gate line groups adjacent in the column direction One of the thin film transistors is located on the first side of the corresponding gate line group, the other first thin film transistor is on the second side of the corresponding gate line group, and one second
  • connection portion pattern is disposed in the same layer as the pixel electrode pattern.
  • the common electrode layer is disposed on the substrate, and the thin film transistor array, the data line pattern, the gate line pattern, the common electrode trace pattern, and the connection portion pattern are disposed on On the common electrode layer.
  • the first thin film transistor is a thin film transistor located on a left side of a corresponding one of the data lines
  • the second thin film transistor is located on a right side of a corresponding one of the data lines Thin film transistor.
  • the present disclosure provides a method of fabricating an array substrate, the method comprising: forming a common electrode layer, a thin film transistor array, a pixel electrode pattern, a data line pattern, a gate line pattern, a common electrode trace pattern, and a connection pattern in which one gate line group is disposed between each pair of adjacent two rows of pixels, each gate line group includes two gate lines, and two columns of pixels are disposed between adjacent two data lines .
  • Each of the data lines connects two thin film transistors at a position overlapping each of the gate line groups, and each of the two thin film transistors is correspondingly connected to one of the gate line groups.
  • the common electrode trace pattern is adapted to be formed in the same process as the data line pattern, and includes a plurality of sets of row direction common electrode traces, each of the plurality of sets of row direction common electrode traces walking in a row direction common electrode
  • the line is disposed between adjacent two rows of pixels, and each set of row direction common electrode traces
  • Each of the row direction common electrode traces is located in an idle area between the adjacent two columns of data lines, and the idle area is aligned in the column direction with each of the thin film transistors between the adjacent two rows of pixels.
  • connection portion pattern includes a plurality of connection portions, each of the plurality of connection portions being disposed at the position where each of the data lines overlaps each of the gate line groups, and is common in each of the row directions
  • a via structure is disposed in the layer structure between the end of the electrode trace and the connection portion adjacent in the row direction, and the connection portion connects the adjacent two row-direction common electrode traces through the via hole.
  • a layer structure between the common electrode traces of the row direction and the common electrode layer is further provided with a via hole at a position of the common electrode trace of each row direction, and each of the row direction common electrodes is taken A line is connected to the common electrode layer through the via.
  • the common electrode trace pattern is formed in the same process of forming the data line pattern.
  • connection portion pattern is formed in the same process of forming the pixel electrode pattern.
  • the present disclosure provides a display device comprising the array substrate of the above first aspect.
  • a common electrode trace pattern in the same layer as the data line pattern is disposed, and the common electrode traces in one row are divided into a plurality of common electrode traces, and each common electrode trace is disposed in a plurality of The adjacent two data lines in the strip data line are connected by a connection pattern at each data line position; and an idle area aligned with each thin film transistor between the adjacent two lines of pixels in the column direction is disposed.
  • the array substrate provided by the present disclosure can reduce the area of the non-opening region, thereby increasing the aperture ratio of the pixel.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure.
  • a first aspect of the present disclosure provides an array substrate 1 including: a substrate and a common electrode layer disposed on the substrate, a thin film transistor array, a pixel electrode pattern, a data line pattern, a gate line pattern, and a common An electrode trace pattern and a connection portion pattern; wherein a gate line group is disposed between each pair of adjacent two rows of pixels, each gate line group includes two gate lines, and between adjacent two data lines Set up with two columns of pixels.
  • Each of the data lines connects two thin film transistors at a position overlapping each of the gate line groups, and each of the thin film transistors is correspondingly connected to one of the one of the gate line groups.
  • the common electrode trace pattern is disposed in the same layer as the data line pattern, and includes a plurality of sets of row direction common electrode traces. Each set of row direction common electrode traces is disposed between adjacent two rows of pixels, and each row direction common electrode trace in each row direction common electrode trace is located between adjacent two data lines The idle area is aligned with the respective thin film transistors between the adjacent two rows of pixels in the column direction.
  • connection portion pattern includes a plurality of connection portions each disposed at the position at which each of the data lines overlaps each of the gate line groups.
  • a via hole is disposed in a layer structure between the end of the common electrode trace and the adjacent connection portion in each row direction, and the connection portion passes the two row-direction common electrode traces adjacent in the row direction through the via hole connection.
  • the layer structure between the common electrode traces and the common electrode layer in each row direction is also provided with via holes at positions of the common electrode traces in the respective row directions, and the common electrode traces and the common electrode layers pass through the respective row directions.
  • the holes are connected.
  • a common electrode trace pattern in the same layer as the data line pattern is disposed, and the common electrode traces in the same row are divided into a plurality of common electrode traces; each common electrode trace Set between two adjacent data lines in a plurality of data lines and at each data line position
  • the connection is bridged by a connection pattern, and an idle area aligned with each of the thin film transistors between adjacent two rows of pixels in the column direction is disposed.
  • the array substrate 1 will be described in detail below with reference to specific drawings.
  • the array substrate 1 includes a substrate, a common electrode layer disposed on the substrate, and a thin film transistor array, a pixel electrode pattern, a data line pattern, a gate line pattern, a common electrode trace pattern formed on the common electrode layer, and a connection portion graphic; wherein the data line pattern includes a plurality of data lines.
  • the data lines are sequentially represented from left to right in FIG. 1 as D1, D2, D3, and D4.
  • the gate line pattern includes a plurality of gate lines.
  • the gate lines are sequentially represented as G1, G2, G3, G4, and G5 from top to bottom.
  • the thin film transistor array includes a plurality of thin film transistors.
  • the thin film transistors located on the left side of the connected data lines are collectively represented as T1
  • the thin film transistors located on the right side of the connected data lines are collectively represented as T2.
  • the pixel electrode pattern includes a plurality of pixel electrodes, and each pixel electrode is represented as P for convenience of description.
  • the connection portion pattern is provided in the same layer as the pixel electrode pattern, and can be formed of the same material. Therefore, in FIG. 1, the connection portion pattern is represented by the same pattern as the pattern of the pixel electrode.
  • the connection portion pattern includes a plurality of connection portions, and each of the connection portions is denoted by L in FIG. Meanwhile, for convenience of description, the common electrode layer in FIG.
  • the common electrode trace pattern can be made of the same material as the common electrode layer, and therefore is also represented by the same pattern in FIG. Specifically, the common electrode trace pattern includes a plurality of row direction common electrode traces and a plurality of column direction common electrode traces.
  • the row-direction common electrode trace is denoted as CL1
  • the column-direction common electrode trace is denoted as CL2.
  • a gate line group is disposed between each pair of adjacent two rows of pixels, and each gate line group includes two gate lines, such as gate lines G3 and G4, which are formed between adjacent two rows of pixels.
  • gate lines G3 and G4 are formed between adjacent two rows of pixels.
  • One gate line group; and two columns of pixels are disposed between two adjacent data lines (for example, D1 and D2 shown in FIG. 1).
  • Each of the data lines connects two thin film transistors T1 and T2 at a position overlapping each of the gate line groups, and each of the two thin film transistors T1 and T2 is correspondingly connected to one of the gate line groups line.
  • the common electrode trace pattern is set in the same layer as the data line pattern, and the plurality of row direction common electrode traces CL1 included in the common electrode trace pattern are divided into a plurality of groups, and each group of row direction common electrode traces CL1 is disposed between each pair of adjacent two rows of pixels; each row direction common electrode trace CL1 of each group of row direction common electrode traces is located in an idle area between adjacent two data lines,
  • the idle area refers to an area in which the respective thin film transistors are aligned with the adjacent two rows of pixels in the column direction.
  • connection portions L is disposed at a position where each of the data lines overlaps with each of the gate line groups; a layer structure between the end portions of the common electrode traces CL1 and the connection portions L adjacent in the row direction in each of the row directions (Including an insulating layer such as a gate insulating layer or an etch barrier layer, and a specific structure can refer to the structure of the array substrate in the related art), and a via hole is provided in the via hole (the via holes in the figure are all indicated by black solid dots), and each connection is performed.
  • the portion L connects the two row-direction common electrode traces CL1 on both sides of the same data line through the via holes at the position.
  • the layer structure between the common electrode trace CL1 and the common electrode layer Vcom in each row direction is further provided with a via hole at the position of the common electrode trace CL1 in each row direction, and the common electrode trace CL1 and the common electrode in each row direction Layer Vcom is connected by vias at this location.
  • Each column direction common electrode trace CL2 is correspondingly disposed between adjacent two columns of pixels between adjacent two data lines, and the row direction common electrode trace CL1 and the column direction common electrode trace CL2 are connected via via holes. .
  • each of the thin film transistors is correspondingly connected to one of the gate line groups and located at the connected gate line One side away from the other gate line, and also connected to one of the adjacent two rows of pixels in the pixel row on the side of the connected gate line away from the other gate line .
  • the thin film transistor T1 on the left side is located at the connected On the side of the gate line G4 that is away from the gate line G3, the corresponding thin film transistor T2 on the right side is located on the side of the gate line G3 to which it is connected away from the gate line G4.
  • the first thin film transistors T1 are located on the same side of the gate line group, and the second thin film crystal T2 is located The other side of the grid line group.
  • the first thin film transistors T1 and T2 to which each of the data lines D1, D2, D3, and D4 is overlapped with the gate line group composed of the gate lines G1 and G2 the first thin film The transistor T1 is located above the gate line group, and the second film Transistors T2 are each located below the set of gate lines.
  • one first thin film transistor T1 is located above the corresponding gate line group, and the other is A thin film transistor T1 is located below the corresponding gate line group; and one second thin film transistor T2 is located below the corresponding gate line group, and the other second thin film transistor T2 is located above the corresponding gate line group.
  • the first thin film transistor T1 is located above the corresponding gate line group, and the second thin film transistor T2 is located below the corresponding gate line group; and the data line D3 is in line with the gate line group composed of the gate lines G3 and G4 (the gate line group is adjacent to the gate line group composed of the gate lines G1 and G2)
  • the first thin film transistor T1 is located below the corresponding gate line group, and the second thin film transistor T2 is located above the corresponding gate line group.
  • the shape of the common electrode trace CL1 in each row direction is a fold line shape, and the position of the left end in the column direction coincides with the first thin film transistor T1 to which the data line adjacent to the left side of the left end is connected, and the right end thereof is in the column direction.
  • the position coincides with the second thin film transistor T2 to which the data line adjacent to the right side of the right end is connected.
  • the left end thereof is close to the data line D2
  • the transistor T1 is coincident; the right end of the row direction common electrode trace CL1 is close to the data line D3, and the position of the right end in the column direction coincides with the thin film transistor T2 connected to the data line D3 and located on the right side of the data line D3.
  • the common electrode trace pattern is disposed in the same layer as the data line pattern, and the row direction common electrode trace CL1 is disposed in the column direction in an idle area aligned with the corresponding thin film transistor.
  • the area of the non-opening region can be reduced, thereby increasing the aperture ratio of the pixel.
  • the idle area referred to in the embodiment of the present disclosure is relative to the related art, and specifically refers to an area not used for disposing a thin film transistor, a gate line, a data line, and a pixel electrode. Specifically, in FIG. 1, it may mean an area corresponding to a common electrode trace in each row direction.
  • connection pattern here may be disposed in the same layer as the pixel electrode pattern, and may be formed in the same process of forming the pixel electrode pattern. Accordingly, the material of the connection portion pattern may also be a material for forming a pixel electrode pattern such as ITO.
  • the above connection The joint pattern can also be made of other conductive materials. Under the premise that the adjacent row-direction common electrode traces can be electrically connected, the specific pattern used to form the joint portion pattern is not limited in the present disclosure.
  • the row-direction common electrode traces CL1 are arranged in a zigzag shape, so that each row-direction common electrode trace CL1 avoids the thin film transistor as close as possible to the corresponding data line, so that The length of the common electrode trace CL1 in the row direction can be increased to lower the length of the connection portion L, which contributes to lowering the overall resistivity in the row direction (the resistivity of the connection portion L is generally higher than the resistivity of the common electrode trace CL1).
  • the basic purpose of the present disclosure can be achieved by setting each of the row-direction common electrode traces CL1 into a straight line, and the corresponding technical solutions should also fall within the protection scope of the present disclosure.
  • a common electrode layer may also be disposed over the other various layer structures described above.
  • a column direction common electrode trace CL2 is further disposed, and the column direction common electrode trace CL2 and the row direction common electrode trace are further disposed.
  • the CL1 is connected in a unitary structure, which can further reduce the resistance when the common voltage is transmitted on the common electrode transfer structure including the common electrode trace pattern and the connection pattern.
  • the column-direction common electrode trace CL2 is not necessarily provided, and it is not difficult to understand that the column-direction common electrode trace CL2 is not provided. Affects the settings of other layer structures.
  • another embodiment of the present disclosure provides an array substrate 1 different from the previous embodiment in that the common electrode trace pattern further includes a plurality of sets of row direction auxiliary common electrode traces.
  • Each set of row direction auxiliary common electrode traces is located at a bend of a row of pixel electrodes in the column direction.
  • Each row direction auxiliary common electrode trace CL3 of each set of row direction auxiliary common electrode traces is located between adjacent two data lines and is connected to the column direction common electrode trace CL2.
  • each of the auxiliary common electrode traces CL3 is disposed at the pixel electrode. The bend of P does not significantly affect the aperture ratio of the pixel electrode P.
  • a second aspect of the present disclosure provides a method of fabricating an array substrate, the method of fabricating the array substrate can be used to fabricate the array substrate according to the first aspect, the method can include the steps of: forming a common electrode on the substrate a layer, a thin film transistor array, a pixel electrode pattern, a data line pattern, a gate line pattern, a common electrode trace pattern, and a connection portion pattern; wherein each pair of adjacent two rows of pixels is provided with a gate line group, each gate The line group includes two gate lines, and two columns of pixels are disposed between two adjacent data lines; each of the data lines connects two thin film transistors at a position overlapping each of the gate line groups, and each thin film transistor is connected a gate line of the gate line group; the common electrode trace pattern is adapted to be formed by the same process as the data line pattern, and includes a plurality of sets of row direction common electrode traces; each group of row direction common electrodes goes The line is disposed between two adjacent rows of pixels, and each row direction common electrode trace in each
  • the step of forming the common electrode trace pattern can be performed in the same process as forming the data line pattern, by which the fabrication difficulty of the array substrate can be reduced.
  • the overall electrode trace pattern thus formed is disposed in the same layer as the data line pattern.
  • the step of fabricating the pattern of the connection portion can be performed in the same process as the pattern of forming the pixel electrode, by which the fabrication difficulty of the array substrate can be reduced.
  • the entire connection pattern thus formed is disposed in the same layer as the data line pattern.
  • the present disclosure also provides a display device comprising the array substrate of the first aspect.
  • the display device herein may refer to other products with touch and display functions such as a mobile phone, a tablet computer, and a navigator.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（1）及其制作方法、显示装置，该阵列基板（1）包括：基底以及设置在该基底上的公共电极走线图形和连接部图形；该公共电极走线图形与数据线图形同层设置，包含多组行方向公共电极走线CL1；每一组行方向公共电极走线CL1设置在相邻两行的像素之间并通过连接部图形中的连接部L相连；其中的每一条行方向公共电极走线CL1位于相邻两列数据线之间的闲置区域，该闲置区域在列方向上与各个薄膜晶体管对齐。还提供了该阵列基板（1）的制作方法以及包括该阵列基板（1）的显示装置。该阵列基板（1）能够减少非开口区域的面积，从而提高像素的开口率。

Description

阵列基板及其制作方法以及显示装置
相关申请的交叉引用
本申请主张在2016年3月7日在中国提交的中国专利申请号No.201610129930.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法以及显示装置。
背景技术
为了实现极性反转或者降低数据驱动电路的使用个数，相关技术中提出了一种双栅(Dual Gate)结构设计。在这种双栅结构的阵列基板中，在相邻两行像素之间设置两条栅线，两条栅线中的上一条栅线连接这两行像素中的上一行像素，下一条栅线连接这两行像素中的下一行像素。
另一方面，为了提高公共电极上的公共电压的均一性，相关技术中在相邻两行像素之间的非开口区域制作一条与栅线平行的公共电极走线。该公共电极走线的材料一般为电阻率较低的金属，并且该公共电极走线通过多个过孔与公共电极相连并为公共电极提供公共电压，从而保证公共电极上的电压的均一性。
在双栅(Dual Gate)结构设计的基础上，如果再设置一条公共电极走线，则需要在相邻两行像素之间制作三条相互独立的金属线。而且，为了避免作为公共电极走线的金属线影响栅线与薄膜晶体管的连接，一般需要将公共电极走线设置在两条作为栅线的金属线之间，这样势必会大幅降低像素的开口率。
发明内容
本公开的一个目的在于提高像素的开口率。
本公开的第一方面提供了一种阵列基板，该阵列基板包括：基底以及设 置在所述基底上的公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形。
其中，在每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，在相邻两条数据线之间设置有两列像素；每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，所述两个薄膜晶体管中的每一个薄膜晶体管对应地连接该栅线组中的一条栅线；所述公共电极走线图形与所述数据线图形同层设置，且包含多组行方向公共电极走线；每一组行方向公共电极走线设置在所述相邻的两行像素之间，并且所述每一组行方向公共电极走线中的每一条行方向公共电极走线位于所述相邻两条数据线之间的闲置区域，所述闲置区域在列方向上与所述相邻的两行像素之间的各个薄膜晶体管对齐。
所述连接部图形包含多个连接部，所述多个连接部中的每一个连接部设置在每一条数据线与每一个栅线组交叠的所述位置处，并且在每一条行方向公共电极走线的端部与行方向上相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将相邻的两条行方向公共电极走线连接；并且所述每一条行方向公共电极走线与所述公共电极层之间的层结构在所述每一条行方向公共电极走线的位置处还设置有过孔，所述每一条行方向公共电极走线与所述公共电极层通过该过孔相连。
进一步地，所述公共电极走线图形还包括多条列方向公共电极走线，所述多条列方向公共电极走线中的每一条列方向公共电极走线对应地设置在相邻两条数据线之间的相邻两列像素之间，每一条行方向公共电极走线和所述多条列方向公共电极走线中的一条列方向公共电极走线相连。
进一步地，所述公共电极走线图形还包括行方向的多组辅助公共电极走线；并且每一组辅助公共电极走线在列方向上位于一行像素电极的弯折处，所述每一组辅助公共电极走线中的每一条辅助公共电极走线位于相邻两条数据线之间并且与所述多条列方向公共电极走线中的一条列方向公共电极走线相连。
进一步地，在每一条数据线在与每一个栅线组交叠的位置处所连接的两个薄膜晶体管中，每一个薄膜晶体管对应连接该栅线组中的一条栅线并且位 于所连接的所述一条栅线的与该栅线组中的另一条栅线远离的一侧，且还连接位于所连接的所述一条栅线的与所述另一条栅线远离的所述一侧的像素行中的一个像素电极；在每一条数据线中在与同一栅线组交叠的位置处所连接的多对薄膜晶体管中，每对中的第一薄膜晶体管均位于该栅线组的第一侧，每对中的第二薄膜晶体均位于该栅线组的第二侧；在同一条数据线在与列方向上相邻的两个栅线组交叠的位置处所连接的四个薄膜晶体管中，一个第一薄膜晶体管位于对应栅线组的所述第一侧，另一个第一薄膜晶体管位于对应栅线组的所述第二侧，并且一个第二薄膜晶体管位于对应栅线组的所述第二侧，另一个第二薄膜晶体管位于对应栅线组的所述第一侧；并且每一条行方向公共电极走线的第一端在列方向上的位置与该第一端相邻的数据线所连接的所述第一薄膜晶体管相一致，第二端在列方向上的位置与该第二端相邻的数据线所连接的所述第二薄膜晶体管相一致。
进一步地，所述连接部图形与所述像素电极图形同层设置。
进一步地，所述公共电极层设置在所述基底上，所述薄膜晶体管阵列、所述数据线图形、所述栅线图形、所述公共电极走线图形和所述连接部图形设置在所述公共电极层上。
进一步地，所述第一薄膜晶体管为位于所述各条数据线中对应数据线的左侧的薄膜晶体管，所述第二薄膜晶体管为位于所述各条数据线中对应数据线的右侧的薄膜晶体管。
第二方面，本公开提供了一种阵列基板的制作方法，该方法包括：在基底上形成公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形，其中，在每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，并且在相邻两条数据线之间设置有两列像素。每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，所述两个薄膜晶体管中的每一个薄膜晶体管对应连接该栅线组中的一条栅线。
所述公共电极走线图形适于与所述数据线图形同一工艺形成，并且包含多组行方向公共电极走线，所述多组行方向公共电极走线中的每一组行方向公共电极走线设置在相邻的两行像素之间，所述每一组行方向公共电极走线 中的每一条行方向公共电极走线位于所述相邻两列数据线之间的闲置区域，所述闲置区域在列方向上与所述相邻的两行像素之间的各个薄膜晶体管对齐。
所述连接部图形包含多个连接部，所述多个连接部中的每一个连接部设置在每一条数据线与每一个栅线组交叠的所述位置处，并且在每一条行方向公共电极走线的端部与行方向上相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将相邻的两条行方向公共电极走线连接。
所述每一条行方向公共电极走线与所述公共电极层之间的层结构在所述每一条行方向公共电极走线的位置处还设置有过孔，所述每一条行方向公共电极走线与所述公共电极层通过该过孔相连。
进一步地，在形成所述数据线图形的同一工艺中形成所述公共电极走线图形。
进一步地，在形成所述像素电极图形的同一工艺中形成所述连接部图形。
第三方面，本公开提供了一种显示装置，包括上述第一方面所述的阵列基板。
在本公开提供的阵列基板中，设置与数据线图形同层的公共电极走线图形，并将一行中的公共电极走线分为多条公共电极走线，每条公共电极走线设置在多条数据线中相邻的两条数据线之间并且在每条数据线位置处通过连接图形跨接；且设置在列方向上与相邻两行像素之间的各个薄膜晶体管对齐的闲置区域。与相关技术中在两条栅线之间专门设置一条公共电极走线的方式相比，本公开提供的阵列基板能够减少非开口区域的面积，从而提高像素的开口率。
附图说明
通过参考附图会更加清楚地理解本公开的特征信息和优点。附图是示意性的而不应理解为对本公开的任何限制，在附图中：
图1为本公开的一些实施例提供的阵列基板的结构示意图；以及
图2为本公开的一些实施例提供的阵列基板的结构示意图。
具体实施方式
为了能够更清楚地理解本公开的上述目的、特征和优点，下面结合附图和具体实施例对本公开进行进一步的详细描述。需要说明的是，在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节，以便充分理解本公开。但是，本公开还可以采用其他与本文描述的方式不同的方式来实施。因此，本公开的保护范围不受下面公开的具体实施例限制。
本公开的第一方面提供了一种阵列基板1，该阵列基板1包括：基底以及设置在所述基底上的公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形；其中，在每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，并且在相邻两条数据线之间设置有两列像素。
每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，每个薄膜晶体管对应地连接这一个栅线组中的一条栅线。
所述公共电极走线图形与所述数据线图形同层设置，并且包含多组行方向公共电极走线。每一组行方向公共电极走线设置在相邻的两行像素之间，并且每一组行方向公共电极走线中的每一条行方向公共电极走线位于相邻的两条数据线之间的闲置区域，所述闲置区域在列方向上与所述相邻的两行像素之间的各个薄膜晶体管对齐。
所述连接部图形包含多个连接部，每个连接部设置在每一条数据线与每一个栅线组交叠的所述位置处。在每一条行方向公共电极走线的端部与相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将行方向上相邻的两条行方向公共电极走线连接。
各条行方向公共电极走线与公共电极层之间的层结构还在各条行方向公共电极走线的位置处设置有过孔，各条行方向公共电极走线与公共电极层通过该过孔相连。
在本公开提供的阵列基板1中，设置与数据线图形位于同层的公共电极走线图形，并将同一行中的公共电极走线分为多条公共电极走线；每条公共电极走线设置在多条数据线中相邻的两条数据线之间且在每条数据线位置处 通过连接图形跨接，并且设置在列方向上与相邻两行像素之间的各个薄膜晶体管对齐的闲置区域。
下面结合具体附图对该阵列基板1进行详细说明。
本公开的实施例提供的阵列基板1的结构俯视图可以参见图1。该阵列基板1包括：基底，设置在所述基底上的公共电极层，以及形成在该公共电极层上的薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形；其中，数据线图形包含多条数据线。为了方便描述，在图1中将数据线从左向右依次表示为D1、D2、D3和D4。栅线图形包含多条栅线，为了方便描述，将栅线从上向下依次表示为G1、G2、G3、G4和G5。薄膜晶体管阵列包含多个薄膜晶体管，为了描述方便，将位于所连接的数据线左侧的薄膜晶体管统一表示为T1，将位于所连接的数据线右侧的薄膜晶体管统一表示为T2。像素电极图形包含多个像素电极，为了方便表述，将各个像素电极均表示为P。连接部图形与像素电极图形同层地设置，并可以采用相同的材料制作，因此在图1中连接部图形采用与像素电极的图案相同的图案进行表示。具体来说，该连接部图形包含多个连接部，各个连接部在图1中均表示为L。同时为了方便描述，将图1中的公共电极层表示为Vcom。公共电极走线图形可以采用与公共电极层相同的材料制作，因此在图1中也采用相同的图案进行表示。具体来说，该公共电极走线图形包含多条行方向公共电极走线和多条列方向公共电极走线。为了方便描述，将行方向公共电极走线表示为CL1，将列方向公共电极走线表示为CL2。
参见图1，在每对相邻的两行像素之间设置有一个栅线组，每个栅线组包含两条栅线，如栅线G3和G4就构成位于相邻的两行像素之间的一个栅线组；并且在相邻的两条数据线(例如图1中示出的D1和D2)之间设置有两列像素。
每条数据线在与每个栅线组交叠的位置处连接两个薄膜晶体管T1和T2，这两个薄膜晶体管T1和T2中的每个薄膜晶体管对应地连接该栅线组中的一条栅线。
公共电极走线图形与数据线图形同层设置，在公共电极走线图形中包含的多条行方向公共电极走线CL1分为多个组，每一组行方向公共电极走线 CL1设置在每对相邻的两行像素之间；每一组行方向公共电极走线中的每条行方向公共电极走线CL1均位于相邻的两条数据线之间的闲置区域，该闲置区域是指在列方向上与该相邻的两行像素之间的各个薄膜晶体管对齐的区域。
每一个连接部L设置在每一条数据线与每一个栅线组交叠的位置处；在每一条行方向公共电极走线CL1的端部与行方向上相邻的连接部L之间的层结构(通常包括栅绝缘层、刻蚀阻挡层等绝缘层，具体结构可以参考相关技术中的阵列基板的结构)中设置有过孔(图中的过孔均用黑色实心点表示)，每个连接部L通过该位置处的过孔将同一数据线两侧的两条行方向公共电极走线CL1连接。
各条行方向公共电极走线CL1与公共电极层Vcom之间的层结构在各条行方向公共电极走线CL1的位置处还设置有过孔，各条行方向公共电极走线CL1与公共电极层Vcom通过该位置处的过孔相连。
每一条列方向公共电极走线CL2对应设置在相邻的两条数据线之间的相邻两列像素之间，并且行方向公共电极走线CL1和列方向公共电极走线CL2经由过孔相连。
在每一条数据线在与每一个栅线组交叠的位置处所连接的两个薄膜晶体管中，每一个薄膜晶体管对应地连接该栅线组中的一条栅线并且位于所连接的这一条栅线的、与另一条栅线远离的一侧，且还连接至相邻的两行像素中的位于所连接的这一条栅线的与另一条栅线远离的一侧的像素行中的一个像素电极。举例来说，在数据线D3在与由栅线G3和栅线G4构成的栅线组交叠的位置处所连接的两个薄膜晶体管T1和T2中，左侧的薄膜晶体管T1位于其所连接的栅线G4的与栅线G3远离的一侧，相应的右侧的薄膜晶体管T2位于其所连接的栅线G3的与栅线G4远离的一侧。
更具体地，在各条数据线在与同一栅线组交叠的位置处所连接的各个薄膜晶体管中，第一薄膜晶体管T1均位于该栅线组的同一侧，且第二薄膜晶体T2均位于该栅线组的另一侧。例如，在数据线D1、D2、D3和D4中的每一条数据线在与由栅线G1和G2构成的栅线组交叠的位置处所连接的两个薄膜晶体管T1和T2中，第一薄膜晶体管T1均位于该栅线组的上方，第二薄膜 晶体管T2均位于该栅线组的下方。
而且，在同一条数据线在与列方向上相邻的两个栅线组交叠的位置处所连接的四个薄膜晶体管中，一个第一薄膜晶体管T1位于对应栅线组的上方，另一个第一薄膜晶体管T1位于对应栅线组的下方；并且一个第二薄膜晶体管T2位于对应栅线组的下方，另一个第二薄膜晶体管T2位于对应栅线组的上方。例如，在数据线D3在与由栅线G1和G2所构成的栅线组交叠的位置处所连接的两个薄膜晶体管中，第一薄膜晶体管T1位于对应栅线组的上方，第二薄膜晶体管T2位于对应栅线组的下方；而在数据线D3在与由栅线G3和G4所构成的栅线组(该栅线组与由栅线G1和G2所构成的栅线组相邻)交叠的位置处所连接的两个薄膜晶体管中，第一薄膜晶体管T1位于对应栅线组的下方，第二薄膜晶体管T2位于对应栅线组的上方。
每一条行方向公共电极走线CL1的形状为折线状，其左端在列方向上的位置与该左端左侧相邻的数据线所连接的第一薄膜晶体管T1相一致，其右端在列方向上的位置与该右端右侧相邻的数据线所连接的第二薄膜晶体管T2相一致。例如，对于位于数据线D2和D3之间的行方向公共电极走线CL1，其左端靠近数据线D2，且左端在列方向上的位置与连接至数据线D2且位于数据线D2左侧的薄膜晶体管T1相一致；该行方向公共电极走线CL1的右端靠近数据线D3，且右端在列方向的位置与连接至数据线D3且位于数据线D3右侧的薄膜晶体管T2相一致。
在本公开实施例提供的阵列基板1中，将公共电极走线图形与数据线图形同层设置且在列方向上将行方向公共电极走线CL1设置在与相应的薄膜晶体管对齐的闲置区域，与相关技术中在两条栅线之间专门设置一条公共电极走线的方式相比，能够减少非开口区域的面积，从而提高像素的开口率。
不难理解的是，本公开的实施例中所指的闲置区域是相对于相关技术而言，具体是指不用于设置薄膜晶体管、栅线、数据线以及像素电极的区域。具体到图1中，可以是指对应于各条行方向公共电极走线的区域。
在具体实施时，这里的连接部图形可以与像素电极图形同层设置，并且可以在形成像素电极图形的同一工艺中形成。相应地，连接部图形的材料也可以为ITO等用于形成像素电极图形的材料。当然在具体实施时，上述的连 接部图形也可以采用其他导电材料制作，在能够将相邻的行方向公共电极走线导电地连接的前提下，具体采用何种材料制作连接部图形在本公开中不做限定。
同时，在本公开实施例中，将各条行方向公共电极走线CL1设置为折线状，能够使得每一条行方向公共电极走线CL1避开薄膜晶体管而尽可能地接近对应的数据线，这样能够增加行方向公共电极走线CL1的长度而降低连接部L的长度，有助于降低行方向整体的电阻率(连接部L的电阻率一般高于公共电极走线CL1的电阻率)。当然在具体实施时，将每一条行方向公共电极走线CL1设置为直线形也能达到本公开的基本目的，相应的技术方案也应该落入本公开的保护范围。
需要指出的是，虽然本公开的实施例是以薄膜晶体管阵列、数据线图形、栅线图形、公共电极走线图形和连接部图形设置在所述公共电极层的上方进行的说明，但是在具体实施时，公共电极层与其他各个层结构的位置关系并不会影响本公开的实施。在一些其他类型的阵列基板中，公共电极层也可以设置在上述其他各个层结构的上方。
在本公开的实施例中，在相邻两条数据线之间的两列像素之间，还设置有列方向公共电极走线CL2，且列方向公共电极走线CL2与行方向公共电极走线CL1连接为一整体结构，这样能够进一步降低当公共电压在公共电极传输结构(该公共电极传输结构包含公共电极走线图形和连接部图形)上传输时的电阻。当然在实际应用中，就为了达到本公开的基本目的而言，列方向公共电极走线CL2并不是必需设置的结构，且不难理解的是，不设置列方向公共电极走线CL2也不会影响其他层结构的设置。
参见图2，本公开的另一实施例提供的阵列基板1与前一实施例不同的是，公共电极走线图形还包括多组行方向辅助公共电极走线。
每一组行方向辅助公共电极走线在列方向上位于一行像素电极的弯折处。每一组行方向辅助公共电极走线中的每一条行方向辅助公共电极走线CL3位于相邻两条数据线之间，并与列方向公共电极走线CL2相连。
在该实施例中，由于还将辅助公共电极走线CL3连接到列方向公共电极走线CL2上，所以能够进一步降低公共电压在相应的公共电极传输结构中的 传输电阻。另外，在实际应用中，由于在像素电极P的弯折处的液晶取向比较混乱，一般不参与发光显示，所以在本公开实施例中，将每一条辅助公共电极走线CL3均设置在像素电极P的弯折处，不会对该像素电极P的开口率造成明显的影响。
本公开的第二个方面提供了一种阵列基板的制作方法，该阵列基板的制作方法可以用于制作根据第一方面所述的阵列基板，该方法可以包括如下步骤：在基底上形成公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形；其中，每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，相邻两条数据线之间设置有两列像素；每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，每一个薄膜晶体管对应连接该栅线组中的一条栅线；所述公共电极走线图形适于利用与所述数据线图形相同的工艺形成，并且包含多组行方向公共电极走线；每一组行方向公共电极走线设置在相邻的两行像素之间，每一组行方向公共电极走线中的每一条行方向公共电极走线位于相邻两条数据线之间的闲置区域，所述闲置区域在列方向上所述相邻的两行像素之间的各个薄膜晶体管对齐；所述连接部图形包含多个连接部，每一个连接部设置在每一条数据线与栅线组交叠的位置处；在每一条行方向公共电极走线的端部与行方向上相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将行方向上相邻的两条行方向公共电极走线连接；并且各条行方向公共电极走线与公共电极层之间的层结构在各条行方向公共电极走线的位置处还设置有过孔，每条行方向公共电极走线与公共电极层通过该过孔相连。
在阵列基板上形成公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形的步骤均可以参见相关技术，本公开在此不再详细说明。
形成公共电极走线图形的步骤可以在与形成数据线图形的同一工艺中完成，通过这种方式能够降低阵列基板的制作难度。这样形成的公共电极走线图形整体与数据线图形设置在同一层。
而制作连接部图形的步骤可以在与形成像素电极图形的同一工艺中完成，通过这种方式能够降低阵列基板的制作难度。这样形成的连接部图形整体与数据线图形设置在同一层。
第三方面，本公开还提供了一种显示装置，该显示装置包括第一方面所述的阵列基板。
这里的显示装置可以是指手机、平板电脑、导航仪等其他具有触控和显示功能的产品。
虽然结合附图描述了本公开的实施方式，但是本领域技术人员可以在不脱离本公开的精神和范围的情况下做出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (15)

  1. 一种阵列基板，包括：
    基底；以及
    设置在所述基底上的公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形；
    其中，在每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，在相邻两条数据线之间设置有两列像素；
    每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，所述两个薄膜晶体管中的每一个薄膜晶体管对应地连接该栅线组中的一条栅线；
    所述公共电极走线图形与所述数据线图形同层设置且包含多组行方向公共电极走线，每一组行方向公共电极走线设置在所述相邻的两行像素之间，并且所述每一组行方向公共电极走线中的每一条行方向公共电极走线位于所述相邻两条数据线之间的闲置区域，所述闲置区域在列方向上与所述相邻的两行像素之间的各个薄膜晶体管对齐；
    所述连接部图形包含多个连接部，所述多个连接部中的每一个连接部设置在每一条数据线与每一个栅线组交叠的所述位置处，并且在每一条行方向公共电极走线的端部与行方向上相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将相邻的两条行方向公共电极走线连接；并且
    所述每一条行方向公共电极走线与所述公共电极层之间的层结构在所述每一条行方向公共电极走线的位置处还设置有过孔，所述每一条行方向公共电极走线与所述公共电极层通过该过孔相连。
  2. 如权利要求1所述的阵列基板，其中，所述公共电极走线图形还包括多条列方向公共电极走线，所述多条列方向公共电极走线中的每一条列方向公共电极走线对应地设置在相邻两条数据线之间的相邻两列像素之间，每一条行方向公共电极走线和所述多条列方向公共电极走线中的一条列方向公共电极走线相连。
  3. 如权利要求1所述的阵列基板，其中，所述公共电极走线图形还包括 行方向的多组辅助公共电极走线；并且
    每一组辅助公共电极走线在列方向上位于一行的像素电极的弯折处，所述每一组辅助公共电极走线中的每一条辅助公共电极走线位于相邻两条数据线之间并且与所述多条列方向公共电极走线中的一条列方向公共电极走线相连。
  4. 如权利要求1所述的阵列基板，其中，
    在每一条数据线在与每一个栅线组交叠的位置处所连接的两个薄膜晶体管中，每一个薄膜晶体管对应连接该栅线组中的一条栅线并且位于所连接的所述一条栅线的与该栅线组中的另一条栅线远离的一侧，且还连接位于所连接的所述一条栅线的与所述另一条栅线远离的所述一侧的像素行中的一个像素电极；
    在每一条数据线在与同一栅线组交叠的位置处所连接的多对薄膜晶体管中，每对中的第一薄膜晶体管均位于该栅线组的第一侧，每对中的第二薄膜晶体均位于该栅线组的第二侧；
    在同一条数据线在与列方向上相邻的两个栅线组交叠的位置处所连接的四个薄膜晶体管中，一个第一薄膜晶体管位于对应栅线组的所述第一侧，另一个第一薄膜晶体管位于对应栅线组的所述第二侧，并且一个第二薄膜晶体管位于对应栅线组的所述第二侧，另一个第二薄膜晶体管位于对应栅线组的所述第一侧；并且
    每一条行方向公共电极走线的第一端在列方向上的位置与该第一端相邻的数据线所连接的所述第一薄膜晶体管相一致，第二端在列方向上的位置与该第二端相邻的数据线所连接的所述第二薄膜晶体管相一致。
  5. 如权利要求1的阵列基板，其中，所述连接部图形与所述像素电极图形同层设置。
  6. 如权利要求1所述的阵列基板，其中，所述公共电极层设置在所述基底上，所述薄膜晶体管阵列、所述数据线图形、所述栅线图形、所述公共电极走线图形和所述连接部图形设置在所述公共电极层上。
  7. 如权利要求4所述的阵列基板，其中，所述第一薄膜晶体管为位于各条数据线中对应数据线的左侧的薄膜晶体管，所述第二薄膜晶体管为位于所 述各条数据线中对应数据线的右侧的薄膜晶体管。
  8. 一种阵列基板的制作方法，包括：
    在基底上形成公共电极层、薄膜晶体管阵列、像素电极图形、数据线图形、栅线图形、公共电极走线图形和连接部图形，
    其中，在每对相邻的两行像素之间设置有一个栅线组，每一个栅线组包含两条栅线，并且在相邻两条数据线之间设置有两列像素；
    每一条数据线在与每一个栅线组交叠的位置处连接两个薄膜晶体管，所述两个薄膜晶体管中的每一个薄膜晶体管对应地连接该栅线组中的一条栅线；
    所述公共电极走线图形适于与所述数据线图形同一工艺形成并且包含多组行方向公共电极走线，所述多组行方向公共电极走线中的每一组行方向公共电极走线设置在相邻的两行像素之间，所述每一组行方向公共电极走线中的每一条行方向公共电极走线位于所述相邻两条数据线之间的闲置区域，所述闲置区域在列方向上与所述相邻的两行像素之间的各个薄膜晶体管对齐；
    所述连接部图形包含多个连接部，所述多个连接部中的每一个连接部设置在每一条数据线与每一个栅线组交叠的所述位置处，并且在每一条行方向公共电极走线的端部与行方向上相邻的连接部之间的层结构中设置有过孔，该连接部通过该过孔将相邻的两条行方向公共电极走线连接；并且
    所述每一条行方向公共电极走线与所述公共电极层之间的层结构在所述每一条行方向公共电极走线的位置处还设置有过孔，所述每一条行方向公共电极走线与所述公共电极层通过该过孔相连。
  9. 如权利要求8所述的方法，其中，在形成所述数据线图形的同一工艺中形成所述公共电极走线图形。
  10. 如权利要求8所述的方法，其中，在形成所述像素电极图形的同一工艺中形成所述连接部图形。
  11. 如权利要求8所述的方法，其中，所述公共电极走线图形还包括多条列方向公共电极走线，所述多条列方向公共电极走线中的每一条列方向公共电极走线对应地设置在相邻两条数据线之间的相邻两列像素之间，每一条行方向公共电极走线和所述多条列方向公共电极走线中的一条列方向公共电 极走线相连。
  12. 如权利要求8所述的方法，其中，所述公共电极走线图形还包括行方向的多组辅助公共电极走线；并且
    每一组辅助公共电极走线在列方向上位于一行像素电极的弯折处，所述每一组辅助公共电极走线中的每一条辅助公共电极走线位于相邻两条数据线之间并且与所述多条列方向公共电极走线中的一条列方向公共电极走线相连。
  13. 如权利要求8所述的方法，其中，在每一条数据线在与每一个栅线组交叠的位置处所连接的两个薄膜晶体管中，每一个薄膜晶体管对应连接该栅线组中的一条栅线并且位于所连接的所述一条栅线的与该栅线组中的另一条栅线远离的一侧，且还连接位于所连接的所述一条栅线的与所述另一条栅线远离的所述一侧的像素行中的一个像素电极；
    在每一条数据线在与同一栅线组交叠的位置处所连接的多对薄膜晶体管中，每对中的第一薄膜晶体管均位于该栅线组的第一侧，每对中的第二薄膜晶体均位于该栅线组的第二侧；
    在同一条数据线在与列方向上相邻两个栅线组交叠的位置处所连接的四个薄膜晶体管中，一个第一薄膜晶体管位于对应栅线组的所述第一侧，另一个第一薄膜晶体管位于对应栅线组的所述第二侧，并且一个第二薄膜晶体管位于对应栅线组的所述第二侧，另一个第二薄膜晶体管位于对应栅线组的所述第一侧；并且
    每一条行方向公共电极走线的第一端在列方向上的位置与该第一端相邻的数据线所连接的所述第一薄膜晶体管相一致，第二端在列方向上的位置与该第二端相邻的数据线所连接的所述第二薄膜晶体管相一致。
  14. 如权利要求13所述的方法，其中，所述第一薄膜晶体管为位于各条数据线中对应数据线的左侧的薄膜晶体管，所述第二薄膜晶体管为位于所述各条数据线中对应数据线的右侧的薄膜晶体管。
  15. 一种显示装置，包括如权利要求1-7任一项所述的阵列基板。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105589273B (zh) * 2016-03-07 2019-06-18 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN106444179A (zh) * 2016-12-01 2017-02-22 武汉华星光电技术有限公司 液晶面板、阵列基板及其制作方法
CN108628045B (zh) * 2017-03-21 2022-01-25 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
KR102372127B1 (ko) * 2017-09-13 2022-03-07 엘지디스플레이 주식회사 어레이기판 및 이를 포함하는 표시장치
CN109375431A (zh) * 2018-10-26 2019-02-22 深圳市华星光电技术有限公司 一种显示面板及显示装置
CN114137769B (zh) * 2020-09-04 2023-09-29 京东方科技集团股份有限公司 阵列基板、显示装置及阵列基板制作方法
CN112147825B (zh) * 2020-09-27 2021-11-30 惠科股份有限公司 像素结构、阵列基板及显示面板
CN115119521A (zh) * 2021-01-08 2022-09-27 京东方科技集团股份有限公司 阵列基板、其驱动方法及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103901684A (zh) * 2012-12-28 2014-07-02 上海中航光电子有限公司 一种ips模式的液晶显示器
CN103926765A (zh) * 2013-04-22 2014-07-16 上海中航光电子有限公司 一种双栅极扫描线驱动的像素结构及其制作方法
CN104714345A (zh) * 2015-04-08 2015-06-17 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、液晶显示面板及显示装置
CN104880871A (zh) * 2015-06-23 2015-09-02 合肥鑫晟光电科技有限公司 显示面板和显示装置
CN104916650A (zh) * 2015-06-18 2015-09-16 合肥鑫晟光电科技有限公司 一种双栅线阵列基板、显示面板及显示装置
CN105159001A (zh) * 2015-10-20 2015-12-16 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板以及显示装置
CN105589273A (zh) * 2016-03-07 2016-05-18 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4869789B2 (ja) * 2006-05-31 2012-02-08 株式会社 日立ディスプレイズ 表示装置
KR102105285B1 (ko) * 2013-09-03 2020-06-01 삼성디스플레이 주식회사 액정 표시 장치
KR102021106B1 (ko) * 2013-11-12 2019-09-11 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103901684A (zh) * 2012-12-28 2014-07-02 上海中航光电子有限公司 一种ips模式的液晶显示器
CN103926765A (zh) * 2013-04-22 2014-07-16 上海中航光电子有限公司 一种双栅极扫描线驱动的像素结构及其制作方法
CN104714345A (zh) * 2015-04-08 2015-06-17 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、液晶显示面板及显示装置
CN104916650A (zh) * 2015-06-18 2015-09-16 合肥鑫晟光电科技有限公司 一种双栅线阵列基板、显示面板及显示装置
CN104880871A (zh) * 2015-06-23 2015-09-02 合肥鑫晟光电科技有限公司 显示面板和显示装置
CN105159001A (zh) * 2015-10-20 2015-12-16 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板以及显示装置
CN105589273A (zh) * 2016-03-07 2016-05-18 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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