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WO2017118028A1 - 一种浪涌防护器件 - Google Patents

一种浪涌防护器件 Download PDF

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Publication number
WO2017118028A1
WO2017118028A1 PCT/CN2016/095630 CN2016095630W WO2017118028A1 WO 2017118028 A1 WO2017118028 A1 WO 2017118028A1 CN 2016095630 W CN2016095630 W CN 2016095630W WO 2017118028 A1 WO2017118028 A1 WO 2017118028A1
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Prior art keywords
well layer
surge
protection device
well
deep
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PCT/CN2016/095630
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English (en)
French (fr)
Inventor
骆生辉
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深圳市槟城电子有限公司
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Publication of WO2017118028A1 publication Critical patent/WO2017118028A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/80—PNPN diodes, e.g. Shockley diodes or break-over diodes

Definitions

  • the present invention relates to the field of overvoltage protection products, and more particularly to a surge protection device.
  • TSS transient suppression diode
  • TVS is a voltage clamp type protection device.
  • THYRISTOR SURGE SUPPRESSOR (TSS) is a voltage switching protection device.
  • the unidirectional TVS needs to be used in series with the TSS.
  • the unidirectional TVS clamps the surge voltage to the Protects the electronics from operating within the normal operating voltage range; when subjected to a reverse surge, the TSS releases the surge voltage close to a short circuit, preventing the protected electronic device from being damaged by excessive reverse voltage.
  • the object of the present invention is to provide a surge protection device capable of providing forward surge protection and reverse surge protection for a circuit, and having higher integration, simple structure and low cost.
  • an embodiment of the present invention provides a surge protection device, including:
  • the N-type substrate is provided with a back surface P well layer on the entire back surface, a front surface P well layer on the front surface of the N type substrate, and an N+ implantation region on one side of the front surface P well layer.
  • the front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on a side where the N+ implant region is provided.
  • a front deep N-well is disposed under the front shallow P-well layer.
  • the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed on a side where the N+ implant region is provided.
  • a back deep N-well is provided on the back shallow P well layer.
  • the back deep P well layer is provided with a plurality of separate deep P wells.
  • the N+ injection zone is provided in plurality.
  • a short circuit hole is disposed between the plurality of N+ implant regions, and the short circuit hole has a large impedance.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 1 is a schematic cross-sectional view of a surge protection device according to Embodiment 1 of the present invention.
  • FIG. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a surge protection device according to Embodiment 2 of the present invention.
  • FIG. 4 is a cross-sectional view showing a surge protection device according to Embodiment 3 of the present invention.
  • FIG. 5 is a cross-sectional view showing a surge protection device according to Embodiment 4 of the present invention.
  • FIG. 6 is a cross-sectional view of a surge protection device according to a fifth embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a surge protection device according to Embodiment 1 of the present invention.
  • the surge protection device 1 of the present embodiment includes: a metal layer 11 of an external conductor, an N-type substrate, and a back surface P well layer on the entire back surface of the N-type substrate, the N-type substrate
  • the front side is provided with a front P-well layer, and one side of the front P-well layer is provided with an N+ implanted region.
  • the N+ implant region is provided with a plurality of electrodes for adjusting the sustain current and the sustain voltage of the device.
  • a short circuit hole 12 is provided between the plurality of N+ implant regions, and the short circuit hole 12 has a large impedance. The shorting holes are used to improve the anti-interference ability of the device. Since the device area is too large, if there is no short-circuit hole, the device will concentrate current in one part, while the other part has no current, which will adversely affect the performance of the device.
  • FIG. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention. The working process of the surge protection device provided by the present invention will be described below with reference to FIG. 1 and FIG.
  • the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current.
  • the structure on the right side of the device is N+ implant-front P-type-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.
  • the reverse diode formed by the N+ implant-front P well has a high withstand voltage
  • the reverse diode formed by the N-type substrate-front P well has a low withstand voltage
  • the N-type liner Avalanche breakdown occurs in the bottom-front P-well, and a leakage current forms a voltage drop through the short-circuit hole after breakdown.
  • the voltage drop is greater than the forward voltage drop of the front P-well-N+ implant, the PNPN structure formed by the backside P-well-N-substrate-front P-well-N+ implant produces positive feedback.
  • the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.
  • the working circuit of the device is equivalent to the circuit in which TVS and TSS are connected in parallel in FIG.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 3 is a cross-sectional view of a surge protection device according to Embodiment 2 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate
  • the front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on the side where the N+ implant region is provided.
  • the first embodiment corresponding to FIG. 1 has the following differences: the front P-well layer is a front deep P well layer and a front shallow P well layer on both sides, and the front shallow P well layer is disposed on the N+ implant. The side of the district. The remaining components are the same as those in the first embodiment, and are not described herein again.
  • the advantages are:
  • the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current.
  • the front deep P-well-N-substrate-backside P-well structure has a small negative-resistance characteristic, which can effectively reduce the residual voltage and improve the surge discharge capability.
  • the structure on the right side of the device is N+ implant-front shallow P-well-N-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front deep P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.
  • the reverse diode formed by the N+ implant-front deep P-well has a high withstand voltage
  • the reverse diode formed by the N-type substrate-front shallow P-well has a low withstand voltage
  • N The substrate-formal shallow P-well undergoes avalanche breakdown, and a leakage current forms a voltage drop through the short-circuit hole after breakdown.
  • the PNPN structure formed by the backside P-N-substrate-front shallow P-N+ implant produces positive feedback.
  • the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 4 is a cross-sectional view of a surge protection device according to Embodiment 3 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate An N+ implant region is disposed on a right side of the front P well layer, and the back P well layer is a back deep P well layer and a back shallow P well layer respectively disposed on both sides, and the back deep P well layer is disposed There is the side of the N+ injection zone.
  • the embodiment 1 corresponding to FIG. 1 has the following difference: the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed in the The side of the N+ injection zone.
  • the remaining components are the same as those in the first embodiment, and are not described herein again.
  • the advantage is that when the device is affected In the case of a reverse surge, the deep P-well layer on the back side can increase the surge bleed capacity of the device and reduce residual voltage.
  • the back deep P well layer is provided with a plurality of separate deep P wells.
  • the advantage is that the junction area of the back deep P-well-N substrate is increased, and the reverse surge bleed capability of the device is further improved.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 6 is a cross-sectional view of a surge protection device according to Embodiment 5 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate, and the back surface of the N-type substrate is provided with a back deep P well layer and a back shallow P well layer respectively on both sides, a back deep P well layer is disposed on a side where the N+ implant region is disposed, and the front surface of the N type substrate is provided with a front deep P well layer and a front shallow P well layer respectively on both sides, and the front shallow P well layer An N+ implant region is disposed thereon, and a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer.
  • the third embodiment corresponding to FIG. 4 has the following difference: a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer.
  • the remaining components are the same as those in the third embodiment, and are not described here.
  • the advantage is that the breakdown voltage when the device is subjected to the reverse surge can be adjusted by adjusting the front deep N-well; the breakdown voltage when the device is subjected to the forward surge can be adjusted by adjusting the back deep N-well, At the same time, the forward surge capability of the device is further improved, and the residual voltage is reduced.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.

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  • Emergency Protection Circuit Devices (AREA)

Abstract

一种浪涌防护器件，包括：N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层的一侧设有N+注入区。由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，解决了应用中需要用一颗TVS和一颗TSS串联使用的问题，而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。

Description

一种浪涌防护器件
本申请要求于2016年1月5日提交中国专利局、申请号为201610009821.0、发明名称为“一种浪涌防护器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及过压保护产品领域，特别是涉及一种浪涌防护器件。
背景技术
目前，通常作为浪涌防护器件使用的半导体器件主要有以下两种：一是瞬态抑制二极管(英文译为TRANSIENT VOLTAGE SUPPRESSOR，简称TVS)，TVS是一种电压钳位型保护器件，当其两端的电压超过反向击穿电压时，TVS迅速的由高阻态变为低阻态，将电压稳定在钳位电压，从而保护了与其并联的其他电子器件；二是半导体放电管(英文译为THYRISTOR SURGE SUPPRESSOR，简称TSS)，TSS是一种电压开关型保护器件，当其两端的电压超过反向击穿电压时，TSS迅速的由高阻态变为低阻态，将电压下降到几乎为零，从而保护了与其并联的其他电子器件。
在具体的应用场景，需要根据被保护电子器件的工作性能，选择适当的浪涌防护器件。例如，在浪涌电压既可能为正向也可能为反向的情况下，需要将单向TVS与TSS串联起来使用，当经受正向浪涌时，单向TVS将浪涌电压钳位至被保护电子器件的正常工作电压范围内；当经受反向浪涌时，TSS将浪涌电压释放至接近于短路，使被保护电子器件不致于承受过大的反向电压而损坏。而同时，为了使电路更加简化和集成化，目前普遍的做法是：将需要串联起来的单向TVS与TSS的晶片手工叠起来进行封装，该封装件结构复杂，成本高。
发明内容
本发明的目的在于提供一种浪涌防护器件，既能够为电路提供正向浪涌防护和反向浪涌防护，且集成度更高，结构简单，成本低廉。
有鉴于此，本发明实施例提供了一种浪涌防护器件，包括：
N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层的一侧设有N+注入区。
进一步的，所述正面P阱层为分别位于两侧的正面深P阱层和正面浅P阱层，所述正面浅P阱层设置在设有N+注入区的那一侧。
进一步的，所述正面浅P阱层下方设有正面深N阱。
进一步的，所述背面P阱层为分别位于两侧的背面深P阱层和背面浅P阱层，所述背面深P阱层设置在设有N+注入区的那一侧。
进一步的，在所述背面浅P阱层上设有背面深N阱。
进一步的，所述背面深P阱层设有多个分开的深P阱。
进一步的，所述N+注入区设有多个。
进一步的，所述多个N+注入区之间设有短路孔，所述短路孔阻抗大。
本发明的浪涌防护器件由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，完全解决了应用中需要用一颗TVS和一颗TSS串联使用的问题。而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。
附图说明
为了使本发明的内容更容易被清楚的理解，下面根据本发明的具体实施例并结合附图，对本发明作进一步详细的说明，其中
图1是本发明实施例一提供的浪涌防护器件的剖面示意图；
图2是本发明实施例提供的浪涌防护器件的等效电路图；
图3是本发明实施例二提供的浪涌防护器件的剖面示意图；
图4是本发明实施例三提供的浪涌防护器件的剖面示意图；
图5是本发明实施例四提供的浪涌防护器件的剖面示意图；
图6是本发明实施例五提供的浪涌防护器件的剖面示意图。
具体实施方式
以下将结合附图，使用以下实施例对本发明进行进一步阐述。
请参阅图1，图1是本发明实施例一提供的浪涌防护器件的剖面示意图。如图1所示，本实施例的浪涌防护器件1包括：外接导线的金属层11，N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层的一侧设有N+注入区。
优选的，所述N+注入区设有多个，用来调节器件的维持电流和维持电压。 在另一优选实施例中，所述多个N+注入区之间设有短路孔12，所述短路孔12阻抗大。所述短路孔用来提高该器件的抗干扰能力。由于器件面积过大，如果没有短路孔，器件会出现电流集中在某一部分，而另一部分没有电流通过，对器件的性能也会产生不利影响。
请结合参阅图2，图2是本发明实施例提供的浪涌防护器件的等效电路图，以下将结合图1与图2来描述本发明提供的浪涌防护器件的工作过程：
1、当器件受到正向浪涌冲击时，N型衬底-背面P阱所形成的反向PN结发生雪崩击穿，从而泄放掉浪涌电流。同时，器件右边的结构为N+注入-正面P阱-N型衬底-背面P阱，由于耐压高，将不会开启。所以当正向浪涌来临时，浪涌通过器件左边的正面P阱-N型衬底-背面P阱区域泄放掉。此时，该器件表现出的是TVS性能。当浪涌结束后，器件马上关断，不会出现续流的问题。
2、当器件受到负向浪涌冲击时，由于N+注入-正面P阱形成的反向二极管耐压高，而N型衬底-正面P阱形成的反向二极管耐压低，所以N型衬底-正面P阱发生雪崩击穿，发生击穿后漏电流通过短路孔形成压降。当该压降大于正面P阱-N+注入的正向压降时，背面P阱-N型衬底-正面P阱-N+注入形成的PNPN结构发生正反馈。当浪涌通过后，由于背面P阱接在低电位，器件马上关断，也不会出现续流的问题。
通过上述描述可见，该器件的工作电路就等效于图2中TVS与TSS并联的电路。
本实施例具有以下优点：
本发明的浪涌防护器件由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，完全解决了应用中需要用一颗TVS和一颗TSS串联使用的问题。而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。
请参阅图3，图3是本发明实施例二提供的浪涌防护器件的剖面示意图。如图3所示，本实施例的浪涌防护器件包括：N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层为分别位于两侧的正面深P阱层和正面浅P阱层，所述正面浅P阱层设置在设有N+注入区的那一侧。
本实施例与图1对应的实施例一具有以下区别：正面P阱层为分别位于两侧的正面深P阱层和正面浅P阱层，所述正面浅P阱层设置在设有N+注入区的那一侧。其余部件均与实施例一相同，此处不再赘述。其优点在于：
1、当器件受到正向浪涌冲击时，N型衬底-背面P阱所形成的反向PN结发生雪崩击穿，从而泄放掉浪涌电流。正面深P阱-N型衬底-背面P阱形成的三极管结构有较小的负阻特性，可以有效的降低残压和提高浪涌泄放能力。同时，器件右边的结构为N+注入-正面浅P阱-N型衬底-背面P阱，由于耐压高，将不会开启。所以当正向浪涌来临时，浪涌通过器件左边的正面深P阱-N型衬底-背面P阱区域泄放掉。此时，该器件表现出的是TVS性能。当浪涌结束后，器件马上关断，不会出现续流的问题。
2、当器件受到负向浪涌冲击时，由于N+注入-正面深P阱形成的反向二极管耐压高，而N型衬底-正面浅P阱形成的反向二极管耐压低，所以N型衬底-正面浅P阱发生雪崩击穿，发生击穿后漏电流通过短路孔形成压降。当该压降大于正面浅P阱-N+注入的正向压降时，背面P阱-N型衬底-正面浅P阱-N+注入形成的PNPN结构发生正反馈。当浪涌通过后，由于背面P阱接在低电位，器件马上关断，也不会出现续流的问题。
本实施例具有以下优点：
本发明的浪涌防护器件由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，完全解决了应用中需要用一颗TVS和一颗TSS串联使用的问题。而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。
请参阅图4，图4是本发明实施例三提供的浪涌防护器件的剖面示意图。如图4所示，本实施例的浪涌防护器件包括：N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层的右侧设有N+注入区，所述背面P阱层为分别位于两侧的背面深P阱层和背面浅P阱层，所述背面深P阱层设置在设有N+注入区的那一侧。
本实施例与图1对应的实施例一具有以下区别：所述背面P阱层为分别位于两侧的背面深P阱层和背面浅P阱层，所述背面深P阱层设置在设有N+注入区的那一侧。其余部件均与实施例一相同，此处不再赘述。其优点在于，当器件受 到反向浪涌冲击时，背面深P阱层的设置可以提高器件的浪涌泄放能力，以及降低残压。
在另一优选实施例四中，请结合参考图5，所述背面深P阱层设有多个分开的深P阱。其优点在于：增加背面深P阱-N型衬底的结面积，进一步提高器件的反向浪涌泄放能力。
其工作过程与图1所述实施例相同，此处不再赘述。
本实施例具有以下优点：
本发明的浪涌防护器件由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，完全解决了应用中需要用一颗TVS和一颗TSS串联使用的问题。而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。
请参阅图6，图6是本发明实施例五提供的浪涌防护器件的剖面示意图。如图5所示，本实施例的浪涌防护器件包括：N型衬底，所述N型衬底整个背面设有分别位于两侧的背面深P阱层和背面浅P阱层，所述背面深P阱层设置在设有N+注入区的那一侧，所述N型衬底正面设有分别位于两侧的正面深P阱层和正面浅P阱层，所述正面浅P阱层上设有N+注入区，所述正面浅P阱层下方设有正面深N阱，所述背面浅P阱层上设有背面深N阱。
本实施例与图4对应的实施例三具有以下区别：所述正面浅P阱层下方设有正面深N阱，所述背面浅P阱层上设有背面深N阱。其余部件均与实施例三相同，此处不再赘述。其优点在于，可以通过调节所述正面深N阱，调节器件经受反向涌浪时的击穿电压；可以通过调节所述背面深N阱，调节器件经受正向涌浪时的击穿电压，同时进一步提高器件的正向浪涌泄放能力，以及降低残压。
其工作过程与图1所述实施例相同，此处不再赘述。
本实施例具有以下优点：
本发明的浪涌防护器件由于将TVS、TSS集成在了一起，其在经受正向浪涌时，表现为TVS特性；经受到负向浪涌时，表现为TSS特性，完全解决了应用中需要用一颗TVS和一颗TSS串联使用的问题。而且该浪涌防护器件集成度高、产品成本较低，方便连接外部电路、应用简便。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的 限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (8)

  1. 一种浪涌防护器件，其特征在于，包括：
    N型衬底，所述N型衬底整个背面设有背面P阱层，所述N型衬底的正面设有正面P阱层，所述正面P阱层的一侧设有N+注入区。
  2. 根据权利要求1所述的浪涌防护器件，其特征在于：
    所述正面P阱层为分别位于两侧的正面深P阱层和正面浅P阱层，所述正面浅P阱层设置在设有N+注入区的那一侧。
  3. 根据权利要求2所述的浪涌防护器件，其特征在于：
    所述正面浅P阱层下方设有正面深N阱。
  4. 根据权利要求1所述的浪涌防护器件，其特征在于：
    所述背面P阱层为分别位于两侧的背面深P阱层和背面浅P阱层，所述背面深P阱层设置在设有N+注入区的那一侧。
  5. 根据权利要求4所述的浪涌防护器件，其特征在于：
    在所述背面浅P阱层上设有背面深N阱。
  6. 根据权利要求4所述的浪涌防护器件，其特征在于：
    所述背面深P阱层设有多个分开的深P阱。
  7. 根据权利要求1所述的浪涌防护器件，其特征在于：
    所述N+注入区设有多个。
  8. 根据权利要求7所述的浪涌防护器件，其特征在于：
    所述多个N+注入区之间设有短路孔，所述短路孔阻抗大。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108922885A (zh) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 一种大功率单向tvs器件
CN110459593A (zh) * 2019-08-01 2019-11-15 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN112614782A (zh) * 2020-12-15 2021-04-06 扬州杰利半导体有限公司 一种单向负阻浪涌防护芯片的制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105552873B (zh) * 2016-01-05 2024-03-29 深圳市槟城电子股份有限公司 一种浪涌防护器件
CN106783949A (zh) * 2016-12-19 2017-05-31 东莞市阿甘半导体有限公司 单向tvs结构及其制造方法
CN108428697A (zh) * 2017-11-09 2018-08-21 上海长园维安微电子有限公司 一种低电容双向带负阻tvs器件
CN111223914B (zh) * 2019-07-01 2024-12-03 上海维安半导体有限公司 一种具有负阻特性的半导体放电管及其制造方法
CN117116936B (zh) * 2023-09-25 2024-04-26 深圳长晶微电子有限公司 单向浪涌防护装置及其制作方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2181754Y (zh) * 1994-01-19 1994-11-02 东南大学 平面型硅抗电涌器件
US5401984A (en) * 1991-06-11 1995-03-28 Texas Instruments Incorporated Semiconductor component for transient voltage limiting
WO2004004007A2 (en) * 2002-06-29 2004-01-08 Bourns Ltd Overvoltage protection
CN101552465A (zh) * 2008-04-04 2009-10-07 半导体元件工业有限责任公司 瞬变电压抑制器和方法
CN102496619A (zh) * 2011-12-26 2012-06-13 天津环联电子科技有限公司 一种发光二极管的保护器件芯片及生产工艺
CN104505341A (zh) * 2014-12-18 2015-04-08 常熟市聚芯半导体科技有限公司 一种半导体放电管的制造方法
CN105552873A (zh) * 2016-01-05 2016-05-04 深圳市槟城电子有限公司 一种浪涌防护器件
CN105609549A (zh) * 2016-01-15 2016-05-25 上海瞬雷电子科技有限公司 双向放电管芯片及其制造方法
CN205283121U (zh) * 2016-01-05 2016-06-01 深圳市槟城电子有限公司 一种浪涌防护器件
CN205385026U (zh) * 2016-01-15 2016-07-13 上海瞬雷电子科技有限公司 双向放电管芯片

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101640414B (zh) * 2009-08-26 2011-06-15 苏州晶讯科技股份有限公司 具有深阱结构的可编程半导体抗浪涌保护器件
CN103384063B (zh) * 2013-07-08 2016-01-20 电子科技大学 一种浪涌保护电路及其制造方法
CN104377673A (zh) * 2013-08-13 2015-02-25 中兴通讯股份有限公司 浪涌防护装置和方法
CN104953575A (zh) * 2014-03-27 2015-09-30 林争 高速公路卡口专用防雷器
CN203932997U (zh) * 2014-04-30 2014-11-05 湖南威普讯通信科技有限公司 带感应灯装置单元的电涌保护器装置
CN104269835A (zh) * 2014-09-19 2015-01-07 华为技术有限公司 保护装置、电子设备和电源

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401984A (en) * 1991-06-11 1995-03-28 Texas Instruments Incorporated Semiconductor component for transient voltage limiting
CN2181754Y (zh) * 1994-01-19 1994-11-02 东南大学 平面型硅抗电涌器件
WO2004004007A2 (en) * 2002-06-29 2004-01-08 Bourns Ltd Overvoltage protection
CN101552465A (zh) * 2008-04-04 2009-10-07 半导体元件工业有限责任公司 瞬变电压抑制器和方法
CN102496619A (zh) * 2011-12-26 2012-06-13 天津环联电子科技有限公司 一种发光二极管的保护器件芯片及生产工艺
CN104505341A (zh) * 2014-12-18 2015-04-08 常熟市聚芯半导体科技有限公司 一种半导体放电管的制造方法
CN105552873A (zh) * 2016-01-05 2016-05-04 深圳市槟城电子有限公司 一种浪涌防护器件
CN205283121U (zh) * 2016-01-05 2016-06-01 深圳市槟城电子有限公司 一种浪涌防护器件
CN105609549A (zh) * 2016-01-15 2016-05-25 上海瞬雷电子科技有限公司 双向放电管芯片及其制造方法
CN205385026U (zh) * 2016-01-15 2016-07-13 上海瞬雷电子科技有限公司 双向放电管芯片

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108922885A (zh) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 一种大功率单向tvs器件
CN110459593A (zh) * 2019-08-01 2019-11-15 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN110459593B (zh) * 2019-08-01 2024-05-28 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN112614782A (zh) * 2020-12-15 2021-04-06 扬州杰利半导体有限公司 一种单向负阻浪涌防护芯片的制造方法

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