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WO2017113984A1 - 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017113984A1
WO2017113984A1 PCT/CN2016/104590 CN2016104590W WO2017113984A1 WO 2017113984 A1 WO2017113984 A1 WO 2017113984A1 CN 2016104590 W CN2016104590 W CN 2016104590W WO 2017113984 A1 WO2017113984 A1 WO 2017113984A1
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WO
WIPO (PCT)
Prior art keywords
pull
clock signal
node
shift register
register unit
Prior art date
Application number
PCT/CN2016/104590
Other languages
English (en)
French (fr)
Inventor
郝学光
先建波
吴新银
Original Assignee
京东方科技集团股份有限公司
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Priority to US15/533,042 priority Critical patent/US10224112B2/en
Publication of WO2017113984A1 publication Critical patent/WO2017113984A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a gate driving circuit applied to a display device includes a multi-stage shift register unit.
  • the shift register unit includes a pull-up node control unit, a pull-down node control unit, and a gate drive signal output unit, and the pull-up node control unit is connected to the pull-up node for controlling a potential of the pull-up node;
  • the node control unit is connected to the pull-down node for controlling the potential of the pull-down node;
  • the gate driving signal output unit is configured to control the output gate driving signal according to the potential of the pull-up node and the potential of the pull-down node, the gate
  • the pole drive signal simultaneously acts as a carry signal for the adjacent shift register unit, so that the corresponding speed is relatively slow.
  • the main device in the shift register unit is a thin film transistor, and the thin film transistor has a large drift of the threshold voltage when it is driven by a direct current voltage or under a high temperature operating condition, thereby causing low reliability, and when the thin film transistor is polysilicon When the thin film transistor is turned off, it has a large leakage current, so that the serious power consumption of the leakage increases, and may even affect the normal operation of the shift register unit.
  • a main object of the present disclosure is to provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which solve the problem that a threshold voltage of a thin film transistor is largely drifted under a long-term or high-temperature operating condition, and a response speed is slow.
  • the present disclosure provides a shift register unit including a gate drive signal output terminal, a carry signal output terminal, a first clock signal input terminal, and a carry signal input terminal.
  • the shift register unit further includes:
  • a first pull-up node control unit connected to the pull-up node and the carry signal input end;
  • a second pull-up node control unit connected to the pull-up node and connected to the first clock signal input terminal for controlling a potential of the pull-up node under control of a first clock signal in a pull-down hold phase Is the first level;
  • a first pull-down node control unit connected to the pull-down node, and connected to the first clock signal input end, configured to control the potential of the pull-down node under the control of the first clock signal in a pull-down hold phase Two levels
  • a second pull-down node control unit connected to the pull-up node and the pull-down node, configured to control a potential of the pull-down node to be a first level when a potential of the pull-up node is at a second level;
  • a gate driving signal output unit connected to the pull-up node, the pull-down node, and the gate driving signal output end, respectively, for controlling the gate under control of the pull-up node and the pull-down node a gate driving signal output terminal output signal;
  • a carry signal output unit respectively connected to the pull-up node, the pull-down node, and the carry signal output end, for controlling the output of the carry signal output under the control of the pull-up node and the pull-down node Carry signal.
  • the first pull-up node control unit is configured to control a potential of the pull-up node to a second level under control of a carry signal in an input phase, and maintain a potential of the pull-up node in an output phase. Two levels.
  • the carry signal input end includes a first carry signal input end and a second carry signal input end
  • the first carry signal input end is connected to the carry signal output end of the adjacent upper stage shift register unit;
  • the second carry signal input terminal is connected to the carry signal output terminal of the adjacent lower stage shift register unit.
  • the first pull-up node control unit includes:
  • a first input module is connected to the pull-up node, and is connected to a carry signal output end of an adjacent upper-stage shift register unit through the first carry signal input end, and is used for when scanning in the forward direction
  • the input phase controls the potential of the pull-up node to be the second power under the control of the first carry signal Flat;
  • a second input module is connected to the pull-up node, and is connected to the carry signal output end of the adjacent next-stage shift register unit through the second carry signal input end, and is used for The input phase controls the potential of the pull-up node to a second level under the control of the second carry signal.
  • the first input module includes: a first transistor, wherein the gate and the first pole are connected to the carry signal output end of the adjacent upper shift register unit through the first carry signal input end, and second a pole connected to the pull-up node;
  • the second input module includes: a second transistor, wherein the gate and the second pole are connected to the carry signal output end of the adjacent next stage shift register unit through the second carry signal input end, the first pole and the Said pull up the node connection.
  • the first pull-up node control unit further includes:
  • the first end is connected to the pull-up node, and the second end is connected to the gate drive signal output end;
  • the first end is connected to the pull-up node, and the second end is connected to the carry signal output end.
  • the first clock signal is at a second level at a time beginning of the pull-down hold phase, and then the first clock signal is at a second level every predetermined time interval, during the predetermined time
  • the first clock signal is at a first level.
  • the shift register unit of the present disclosure further includes a second clock signal input terminal
  • the gate driving signal output unit is further connected to a first level and is connected to the second clock signal input terminal for controlling under the control of the pull-up node in an input phase, an output phase, and a pull-down phase.
  • the gate driving signal output end outputs a second clock signal, and the gate driving signal output end is controlled to output a first level under the control of the pull-down node in a pull-down holding phase;
  • the carry signal output unit is further connected to the first level and is connected to the second clock signal input end for controlling the input under the control of the pull-up node in an input phase, an output phase, and a pull-down phase
  • the carry signal output terminal outputs the second clock signal, and controls the carry signal output end to output a first level under the control of the pull-down node in a pull-down hold phase;
  • the second clock signal In the input phase and the pull-down phase, the second clock signal is at a first level; In the output stage, the second clock signal is at a second level.
  • the duty ratio of the first clock signal and the duty ratio of the second clock signal are both 0.25;
  • the duration of the input phase, the duration of the output phase, and the duration of the pulldown phase are all a time unit
  • the first clock signal is delayed by two time units than the second clock signal.
  • the predetermined time is three time units.
  • the first level is a low level
  • the second level is a high level
  • the first level is a high level and the second level is a low level.
  • the second pull-up node control unit is further connected to the pull-down node, and is further configured to control a potential of the pull-up node to be a first level when a potential of the pull-down node is at a second level.
  • the second pull-up node control unit includes:
  • a third transistor a gate connected to the first clock signal input end, a first pole connected to the pull-up node, and a second pole connected to the first level;
  • a fourth transistor the gate is connected to the pull-down node, the first pole is connected to the pull-up node, and the second pole is connected to the first level.
  • the first pull-down node control unit includes: a fifth transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole is connected to the pull-down node.
  • the second pull-down node control unit is further connected to the carry signal output end of the adjacent next-stage shift register unit, and is also used for the carry signal output end of the adjacent next-stage shift register unit.
  • the potential of the pull-down node is controlled to be the first level.
  • the second pull-down node control unit includes:
  • the gate is connected to the carry signal output end of the adjacent next stage shift register unit through the second carry signal input end, the first pole is connected to the pull-down node, and the second pole is connected to the first power Flat;
  • a seventh transistor the gate is connected to the pull-up node, the first pole is connected to the pull-down node, and the second pole is connected to the first level.
  • the gate driving signal output unit includes:
  • a first gate driving signal output transistor a gate connected to the pull-up node, and a first pole
  • the second clock signal input end is connected, and the second pole is connected to the gate drive signal output end;
  • a second gate driving signal output transistor a gate connected to the pull-down node, a first pole connected to the gate driving signal output end, and a second pole connected to the first level;
  • the carry signal output unit includes:
  • a first carry signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input terminal, and a second pole connected to the carry signal output end;
  • a second carry signal output transistor the gate is connected to the pull-down node, the first pole is connected to the carry signal output end, and the second pole is connected to the first level.
  • the present disclosure also provides a driving method of a shift register unit, including:
  • the second pull-down node control unit controls the potential of the pull-down node to be a first level under the control of the pull-up node, and the first pull-up node control unit controls the potential of the pull-up node to be a second level;
  • the first pull-up node control unit controls the potential of the pull-up node to maintain the second level
  • the second pull-down node control unit controls the potential of the pull-down node to be the control under the control of the pull-up node.
  • the potential of the pull-up node is maintained at a second level, and the second pull-down node control unit controls the potential of the pull-down node to be a first level under the control of the pull-up node;
  • the second pull-up node control unit controls the potential of the pull-up node to be the first level under the control of the first clock signal, and the first pull-down node control unit controls under the control of the first clock signal
  • the potential of the pull-down node is at a second level.
  • the step of controlling, by the first pull-up node control unit, the potential of the pull-up node to a second level comprises:
  • the first pull-up node control unit controls the potential of the pull-up node to be a second level under the control of the first carry signal, and the first carry signal is adjacent to the previous one. a carry signal output by the stage shift register unit;
  • the first pull-up node control unit controls the potential of the pull-up node to be a second level under the control of the second carry signal, and the second carry signal is adjacent next The carry signal output by the stage shift register unit.
  • the driving method of the shift register unit of the present disclosure further includes: pulling up Under the control of the node and the pull-down node, the gate drive signal output unit controls the gate drive signal output terminal to output a gate drive signal, and the carry signal output unit controls the carry signal output terminal to output a carry signal.
  • the gate driving signal output unit controls the gate driving signal output end to output a gate driving signal
  • the carry signal output unit controls the carry signal output end
  • the gate driving signal output unit controls the gate driving signal output terminal to output a second clock signal under the control of the pull-up node;
  • the carry signal output unit is in the The control carry signal output end outputs the second clock signal under the control of the pull-up node;
  • the gate driving signal output unit controls the gate driving signal output end to output a first level under the control of the pull-down node, and the carry signal output unit is under the control of the pull-down node Controlling the carry signal output end to output a first level;
  • the second clock signal In the input phase and the pull-down phase, the second clock signal is at a first level; in the output phase, the second clock signal is at a second level.
  • the duty ratio of the first clock signal and the duty ratio of the second clock signal are both 0.25;
  • the duration of the input phase, the duration of the output phase, and the duration of the pulldown phase are all a time unit
  • the first clock signal is delayed by two time units than the second clock signal.
  • the present disclosure also provides a gate driving circuit comprising a plurality of stages of the above shift register unit;
  • the odd row shift register unit is disposed on the left side of the display panel, and the even row shift register unit is disposed on the right side of the display panel;
  • the even row shift register unit is disposed on the left side of the display panel, and the odd row shift register unit is disposed on the right side of the display panel.
  • the present disclosure also provides a gate driving circuit including a multi-stage shift register unit
  • the second clock signal input end of the 8n-7th shift register unit is connected to the first left clock signal or the first right clock signal;
  • the second clock signal input end of the 8n-5th shift register unit is connected to the second left clock signal Or a second right clock signal;
  • the first clock signal input end of the 8n-7th shift register unit is connected to the third left clock signal or the third right clock signal;
  • the first clock signal input end of the 8n-5th stage shift register unit is connected to the fourth left clock signal or the fourth right clock signal;
  • the second clock signal input end of the 8th-6th stage shift register unit is connected to the first right clock signal or the first left clock signal;
  • the second clock signal input end of the 8th-4th stage shift register unit is connected to the second right clock signal or the second left clock signal;
  • the first clock signal input end of the 8th-6th stage shift register unit is connected to the third right clock signal or the third left clock signal;
  • the first clock signal input end of the 8th-4th stage shift register unit is connected to the fourth right clock signal or the fourth left clock signal;
  • the second clock signal input end of the 8th-3th stage shift register unit is connected to the third left clock signal or the third right clock signal;
  • the second clock signal input end of the 8n-1th stage shift register unit is connected to the fourth left clock signal or the fourth right clock signal;
  • the first clock signal input end of the 8th-3th stage shift register unit is connected to the first left clock signal or the first right clock signal;
  • the first clock signal input end of the 8n-1th stage shift register unit is connected to the second left clock signal or the second right clock signal;
  • the second clock signal input end of the 8n-2 stage shift register unit is connected to the third right clock signal or the third left clock signal;
  • the second clock signal input end of the 8nth stage shift register unit is connected to the fourth right clock signal or the fourth left clock signal;
  • the first clock signal input end of the 8n-2th stage shift register unit is connected to the first right clock signal or the first left clock signal;
  • the first clock signal input end of the 8nth stage shift register unit is connected to the second right clock signal or the second left clock signal;
  • n is a positive integer
  • the second left clock signal is delayed by one time unit from the first left clock signal
  • the third left clock signal is delayed by one time unit from the second left clock signal
  • the fourth left clock signal is delayed from the third left clock signal.
  • the second right clock signal is delayed by one time unit from the first right clock signal
  • the third right clock signal is delayed by one time unit from the second right clock signal
  • the fourth right clock signal is delayed from the third right clock signal a time unit
  • the first right clock signal is delayed by 0.5 time units than the first left clock signal
  • the duty ratio of all clock signals is 0.25, all clock signals continue to be the first level for three time units, and all clock signals continue to be the second level for one time unit;
  • the first carry signal input terminal of each row of shift register cells on the left side is connected to the carry signal output terminal of the shift register unit of the adjacent row on the left side;
  • the first carry signal input end of each row of the shift register unit on the right side is connected with the carry signal output end of the shift register unit of the adjacent row on the right side except for the shift register unit of the first row on the right side;
  • the second carry signal input terminal of each shift register unit on the left side is connected to the carry signal output end of the shift register unit adjacent to the left row of the left side;
  • the second carry signal input terminal of each shift register unit on the right side is connected to the carry signal output terminal of the shift register unit adjacent to the next row on the right side.
  • the present disclosure also provides a display device including a display panel and the above-described gate driving circuit.
  • the shift register unit and driving method thereof, the gate driving circuit and the display device of the present disclosure control the first pull-up node control unit, the second pull-up node control unit, the first pull-down node control unit, and the second pull-down
  • the node control unit operates under the AC voltage, suppresses the leakage current of the polysilicon thin film transistor, and avoids the problem that the threshold voltage of the thin film transistor shifts greatly under long-term or high-temperature operating conditions; and the shift described in the embodiment of the present disclosure Bit register unit using carry letter
  • the discrete output of the gate and the gate drive signal improves the response speed of the amorphous silicon thin film transistor.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • Figure 2 is a timing chart showing the operation of the shift register unit shown in Figure 1;
  • 3A is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • 3B is a timing chart showing the operation of the shift register unit according to the embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • Figure 5 is a waveform diagram of the first clock signal CKB and the second clock signal CK;
  • FIG. 6 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 8 is a circuit diagram of a specific embodiment of a shift register unit of the present disclosure.
  • Figure 9 is a timing chart showing the operation of a specific embodiment of the shift register unit shown in Figure 8 of the present disclosure.
  • FIG. 10 is a waveform diagram of eight clock signals accessed by a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 11 is a structural diagram of a specific embodiment of a gate driving circuit according to the present disclosure.
  • Figure 12 is a timing diagram showing the operation of this embodiment of the gate drive circuit of the present disclosure.
  • the shift register unit includes a gate driving signal output terminal OUT_N, a carry signal output terminal STV_N, a first clock signal input terminal inputting a first clock signal CKB, and a carry signal input terminal.
  • the shift register unit further includes:
  • a first pull-up node control unit 11 connected to the pull-up node PU and the carry signal input end;
  • a second pull-up node control unit 12 connected to the pull-up node PU, and the first time
  • the clock signal input terminal is connected to control the potential of the pull-up node PU to be a first level under the control of the first clock signal CKB in the pull-down holding phase;
  • a first pull-down node control unit 13 connected to the pull-down node PD and connected to the first clock signal input terminal for controlling the pull-down node PD under the control of the first clock signal CKB in a pull-down hold phase
  • the potential is the second level
  • a second pull-down node control unit 14 is connected to the pull-up node PU and the pull-down node PD, and is configured to control the potential of the pull-down node PD to be the first when the potential of the pull-up node PU is at a second level Level
  • a gate driving signal output unit 15 connected to the pull-up node PU, the pull-down node PD, and the gate driving signal output terminal OUT_N, respectively, for the pull-up node PU and the pull-down node PD Controlling the gate driving signal output terminal OUT_N to output a gate driving signal under control;
  • a carry signal output unit 16 respectively connected to the pull-up node PU, the pull-down node PD, and the carry signal output terminal STV_N, for controlling the control under the control of the pull-up node PU and the pull-down node PD
  • the carry signal output terminal STV_N outputs a carry signal.
  • a pull-down phase is further included between the output phase and the pull-down hold phase, and the potential of the pull-up node is maintained at the second level in the pull-down phase, and the shift register unit of the present disclosure is in the input phase, the output phase, The specific working process of the pull-down phase and the pull-down hold phase will be described in detail later.
  • the first level may be a low level, and the second level may be a high level; or the first level may be a high level, and the second level may be a low level
  • FIG. 2 is specifically drawn with the first level being the low level and the second level being the high level, but the operation timing of the shift register unit according to the embodiment of the present disclosure is not limited by FIG. 2 .
  • T1 indicates an input phase
  • T2 indicates an output phase
  • T3 indicates a pull-down phase
  • T4 indicates a pull-down hold phase.
  • the shift register unit controls the first pull-up node control unit, the second pull-up node control unit, the first pull-down node control unit, and the second pull-down node control unit to operate under AC voltage driving. , suppressing leakage current of the polysilicon thin film transistor, and avoiding a large drift of the threshold voltage of the thin film transistor under long-term or high-temperature reliable working conditions, thereby failing to protect The problem of holding a low level and a high level; and the shift register unit described in the embodiment of the present disclosure increases the response speed of the amorphous silicon thin film transistor by using a manner in which the carry signal and the gate drive signal are discretely output.
  • the first pull-up node control unit is configured to control the potential of the pull-up node to a second level under the control of a carry signal in an input phase, and maintain the potential of the pull-up node in an output phase. Is the second level.
  • the carry signal input end includes a first carry signal input end and a second carry signal input end; the first carry signal input end inputs a first carry signal, and the second carry signal input end inputs the first Binary signal
  • the first carry signal input terminal is connected to the carry signal output end of the adjacent upper stage shift register unit, and the first carry signal is a carry output of the adjacent upper stage shift register unit.
  • the first pull-up node control unit is configured to control the pull-up under the control of the first carry signal in an input phase when performing a forward scan on the shift register unit according to the embodiment of the present disclosure.
  • the potential of the node is the second level;
  • the second carry signal input terminal is connected to the carry signal output end of the adjacent next stage shift register unit, and the second carry signal is a carry output of the adjacent next stage shift register unit.
  • the first pull-up node control unit is specifically configured to control the pull-up under the control of the second carry signal during an input phase when performing a reverse scan on the shift register unit according to the embodiment of the present disclosure.
  • the potential of the node is at the second level.
  • the carry signal input end may include a first carry signal input end and a second carry signal input end;
  • the carry signal outputted by the carry signal output terminal STV_N-1 of the adjacent upper stage shift register unit is input from the first carry signal input terminal;
  • the first pull-up node control unit includes:
  • the first input module 111 is connected to the pull-up node PU, and is connected to the carry signal output terminal STV_N-1 of the adjacent upper-stage shift register unit through the first carry signal input terminal, and is used for Controlling the pull-up node under control of the first carry signal during the input phase during scanning
  • the potential of the PU is the second level;
  • the second input module 112 is connected to the pull-up node PU, and is connected to the carry signal output terminal STV_N+1 of the adjacent next-stage shift register unit through the second carry signal input terminal for Controlling the potential of the pull-up node PU to a second level under the control of the second carry signal during the input phase;
  • the first carry signal is a carry signal outputted by the carry signal output terminal STV_N-1 of the adjacent upper stage shift register unit.
  • the carry signal outputted in the input stage STV_N-1 is the second power. level;
  • the second carry signal is a carry signal outputted by the carry signal output terminal STV_N+1 of the adjacent next stage shift register unit.
  • the carry signal outputted in the input stage STV_N+1 is the second power. level.
  • the first carry signal output by STV_N-1 and the second carry signal output by STV_N+1 are as shown in FIG. 3B.
  • the first input module may include: a first transistor, wherein the gate and the first pole are connected to the carry signal output end of the adjacent upper shift register unit through the first carry signal input end, a diode connected to the pull-up node;
  • the second input module may include: a second transistor, wherein the gate and the second pole are connected to the carry signal output end of the adjacent next stage shift register unit through the second carry signal input end, the first pole and The pull-up nodes are connected.
  • the first pull-up node control unit may further include:
  • a first storage capacitor the first end is connected to the pull-up node, and the second end is connected to the gate drive signal output end OUT_N;
  • a second storage capacitor the first end is connected to the pull-up node, and the second end is connected to the carry signal output end STV_N;
  • the first storage capacitor and/or the second storage capacitor are used to bootstrap the potential of the pull-up node PU during the output phase.
  • the first pull-up node control unit further includes:
  • a first storage capacitor C1 the first end is connected to the pull-up node PU, and the second end is connected to the gate drive signal output end OUT_N;
  • a second storage capacitor C2 the first end is connected to the pull-up node PU, and the second end is connected to the carry signal output end STV_N;
  • the first storage capacitor C1 and the second storage capacitor C2 simultaneously lift the potential of the pull-up node PU at the output stage.
  • the first clock signal is at a second level for a period of time at the beginning of the pull-down holding phase, and then the first clock signal is at a second level every predetermined time interval, and the predetermined time is The first clock signal is at a first level.
  • the waveform of the first clock signal CKB is described as follows:
  • the first clock signal CKB is at a high level to control the second pull-up node control unit to cause the PD to be connected to a low level to pull down the potential of the PD, after which The first clock signal CKB is at a high level every predetermined time interval, and the first clock signal CKB is at a low level for the predetermined time, so that the second pull-up node control unit is driven by an alternating voltage.
  • the shift register unit of the embodiment of the present disclosure further includes a second clock signal input end that inputs the second clock signal CK;
  • the gate drive signal output unit 15 is further connected to the first level V1 and is connected to the second clock signal input terminal for the pull-up node PU in the input phase, the output phase, and the pull-down phase. Controlling the gate drive signal output terminal OUT_N to output a second clock signal CK, and controlling the gate drive signal output terminal OUT_N to output a first level V1 under the control of the pull-down node PD in a pull-down hold phase;
  • the carry signal output unit 16 is further connected to the first level V1 and is connected to the second clock signal input end for controlling under the control of the pull-up node PU in the input phase, the output phase and the pull-down phase. Controlling the carry signal output terminal STV_N to output the second clock signal CK, and controlling the carry signal output terminal STV_N to output a first level V1 under the control of the pull-down node PD in a pull-down hold phase;
  • the second clock signal CK is at a first level; in the output phase, the second clock signal CK is at a second level.
  • the duty ratio of the first clock signal CKB and the duty ratio of the second clock signal CK are both 0.25;
  • the duration of the input phase, the duration of the output phase, and the pulldown phase is a time unit
  • the first clock signal CKB is delayed by two time units from the second clock signal CK;
  • the one marked as T in Fig. 5 is one time unit, and the predetermined time mentioned above is three time units.
  • the first level is a low level and the second level is a high level.
  • the first level may also be a high level and the second level is also Can be low.
  • the second pull-up node control unit 12 is further connected to the pull-down node PD, and is further configured to control the upper terminal when the potential of the pull-down node PD is at a second level.
  • the potential of the pull node PU is at the first level.
  • the second pull-up node control unit includes:
  • a third transistor a gate connected to the first clock signal input end, a first pole connected to the pull-up node, and a second pole connected to the first level;
  • a fourth transistor the gate is connected to the pull-down node, the first pole is connected to the pull-up node, and the second pole is connected to the first level.
  • the first pull-down node control unit includes: a fifth transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole is connected to the pull-down node.
  • the second pull-down node control unit 14 is further connected to the carry signal output terminal STV_N+1 of the adjacent next-stage shift register unit, and is also used when the adjacent next When the carry signal output terminal STV_N+1 of the stage shift register unit outputs the second level, the potential of the pull-down node PD is controlled to be the first level.
  • the second pulldown node control unit includes:
  • the gate is connected to the carry signal output end of the adjacent lower stage shift register unit, the first pole is connected to the pull-down node, and the second pole is connected to the first level;
  • a seventh transistor the gate is connected to the pull-up node, the first pole is connected to the pull-down node, and the second pole is connected to the first level.
  • the gate driving signal output unit includes:
  • a first gate driving signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input end, and a second pole connected to the gate driving signal output end;
  • a second gate driving signal output transistor the gate is connected to the pull-down node, and the first pole
  • the gate drive signal output is connected, and the second pole is connected to the first level.
  • the carry signal output unit includes:
  • a first carry signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input terminal, and a second pole connected to the carry signal output end;
  • a second carry signal output transistor the gate is connected to the pull-down node, the first pole is connected to the carry signal output end, and the second pole is connected to the first level.
  • the first level when the shift register unit included in the shift register unit of the embodiment includes a transistor and a carry signal output unit includes a transistor of an n-type transistor, the first level may be low.
  • the second level may be a high level; and when the shift register unit included in the shift register unit of the embodiment includes a transistor and a carry signal output unit including a p-type transistor, The first level can be a high level and the second level can be a low level.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the two poles except the gate are referred to as a first pole and a second pole, wherein the first pole and the second pole may be interchanged as the current flow direction changes, that is, the first Extreme source, second extremely drain, or, first, very drain, second, very source.
  • the transistor of the specific embodiment of the shift register unit of the present disclosure includes an n-type transistor, but the transistor included in the shift register unit of the embodiment of the present disclosure may also be a p-type transistor.
  • a specific embodiment of the shift register unit of the present disclosure includes a gate driving signal output terminal OUT_N, a carry signal output terminal STV_N, a first clock signal input terminal inputting the first clock signal CKB, and a first A carry signal input terminal and a second carry signal input terminal.
  • the carry signal output from the carry signal output terminal STV_N-1 of the adjacent upper stage shift register unit is input from the first carry signal input terminal.
  • the carry signal outputted by the carry signal output terminal STV_N+1 of the adjacent next stage shift register unit is input from the second carry signal input terminal.
  • the specific embodiment of the shift register unit of the present disclosure further includes a first pull-up node control unit 11, a second pull-up node control unit 12, a first pull-down node control unit 13, and a second pull-down.
  • the first pull-up node control unit 11 includes:
  • the first transistor M1, the gate and the drain are connected to the carry signal output terminal STV_N-1 of the adjacent upper stage shift register unit through the first carry signal input end, and the second pole and the pull-up node PU connection;
  • the second transistor M2, the gate and the source are connected to the carry signal output terminal STV_N+1 of the adjacent next-stage shift register unit through the second carry signal input end, the first pole and the pull-up node PU connection;
  • a first storage capacitor C1 the first end is connected to the pull-up node PU, and the second end is connected to the gate drive signal output end OUT_N;
  • the second storage capacitor C2 has a first end connected to the pull-up node PU and a second end connected to the carry signal output end STV_N.
  • the second pull-up node control unit 12 includes:
  • a third transistor M3 a gate connected to the first clock signal input end of the input first clock signal CKB, a drain connected to the pull-up node PU, and a source connected to the low level VGL;
  • the fourth transistor M4 has a gate connected to the pull-down node PD, a drain connected to the pull-up node PU, and a source connected to the low level VGL.
  • the first pull-down node control unit 13 includes a fifth transistor M5, a gate and a drain are both connected to the first clock signal input terminal, and a source is connected to the pull-down node PD.
  • the second pulldown node control unit 14 includes:
  • the sixth transistor M6 the gate is connected to the carry signal output terminal STV_N+1 of the adjacent next stage shift register unit, the first pole is connected to the pulldown node PD, and the second pole is connected to the low level VGL;
  • a seventh transistor M7 a gate connected to the pull-up node PU, a drain connected to the pull-down node PD, and a source connected to a low level VGL;
  • the eighth transistor M8 has a gate connected to the pull-up node PU, a drain connected to the pull-down node PD, and a source connected to the low level VGL.
  • the gate driving signal output unit 15 includes:
  • a first gate driving signal outputting transistor M9 a gate connected to the pull-up node, a drain connected to a second clock signal input end of the input second clock signal CK, a source and the gate driving signal
  • the output terminal OUT_N is connected;
  • the second gate driving signal output transistor M10 has a gate connected to the pull-down node, a drain connected to the gate driving signal output terminal OUT_N, and a second pole connected to the low level VGL.
  • the carry signal output unit 16 includes:
  • a first carry signal output transistor M11 a gate connected to the pull-up node PU, a drain connected to the second clock signal input end, and a source connected to the carry signal output terminal STV_N;
  • the second carry signal output transistor M12 has a gate connected to the pull-down node PD, a drain connected to the carry signal output terminal STV_N, and a source connected to the low level VGL.
  • all of the transistors are n-type transistors, the first level is a low level, and the second level is a high level;
  • M7 and M8 are employed to increase the speed at which the potential of the PD is pulled low.
  • the specific embodiment of the shift register unit shown in FIG. 8 of the present disclosure is in operation, during each display period,
  • STV_N-1 In the input phase T1, STV_N-1 outputs a high level, CK is a low level, M1 is turned on, the potential of the PU rises, and M9 and M11 are turned on, so that OUT_N and STV_N both output a low level, M7 and M8 lead Pass, the potential of the PD is pulled low;
  • STV_N-1 outputs a low level
  • CK is a high level
  • M1 is turned off. Due to the bootstrap action of C1 and C2, the potential of the PU continues to rise, and M9 and M11 continue to be in an on state, both OUT_N and STV_N Output high level; M7 and M8 are turned on, and the potential of PD is continuously pulled low;
  • CK is low level
  • CKB is high level
  • M3, M4 and M5 are all turned on to pull up the potential of PD
  • PU potential is pulled low
  • M10 and M12 are both led.
  • Pass, OUT_N and STV_N both output low level
  • CKB is again high, once again pulling the potential of the PD high.
  • M10 and M12 are in the on state, the potential of the PU is in the low state, and OUT_N and STV_N both output the low level, effectively avoiding the introduction of non-operating state noise.
  • the first pull-up node control unit 11, the second pull-up node control unit 12, the first pull-down node control unit 13 and The second pull-down node control unit 14 is all driven by the AC voltage, which suppresses the leakage current of the polysilicon thin film transistor, and avoids the large drift of the threshold voltage of the thin film transistor under long-term or high-temperature reliable working conditions, thereby preventing the low voltage from being maintained.
  • a problem of leveling a high level; and this embodiment of the shift register unit of the present disclosure increases the response speed of the amorphous silicon thin film transistor by means of a discrete output of the carry signal and the gate drive signal.
  • the shift register unit of the embodiment of the present disclosure may also use the first storage capacitor C1 and the second storage capacitor C2, and rely on the bootstrap function of the coupling capacitors Cgs and M11 of M9 to drive the PU. The potential is pulled high.
  • the second pull-down node control unit controls the potential of the pull-down node to be a first level under the control of the pull-up node, and the first pull-up node control unit controls the potential of the pull-up node to be a second level.
  • the first pull-up node control unit controls the potential of the pull-up node to maintain the second level
  • the second pull-down node control unit controls the potential of the pull-down node to be the control under the control of the pull-up node.
  • the potential of the pull-up node is maintained at a second level, and the second pull-down node control unit controls the potential of the pull-down node to be a first level under the control of the pull-up node;
  • the second pull-up node control unit controls the potential of the pull-up node to be the first level under the control of the first clock signal, and the first pull-down node control unit controls under the control of the first clock signal
  • the potential of the pull-down node is at a second level.
  • the driving method of the shift register unit controls the first pull-up node control unit, the second pull-up node control unit, the first pull-down node control unit, and the second pull-down node control unit to operate in the communication Under voltage driving, the leakage current of the polysilicon thin film transistor is suppressed, and the problem that the threshold voltage of the thin film transistor largely drifts under long-term or high-temperature operating conditions is avoided.
  • the first pull-up node control unit controls the pull-up node
  • the step of the potential being the second level includes:
  • the first pull-up node control unit controls the potential of the pull-up node to be a second level under the control of the first carry signal, and the first carry signal is an adjacent upper level shift a carry signal output by the bit register unit;
  • the first pull-up node control unit controls the potential of the pull-up node to be a second level under the control of the second carry signal, and the second carry signal is adjacent to the next level shift The carry signal output by the bit register unit.
  • the driving method of the shift register unit further includes: under the control of the pull-up node and the pull-down node, the gate driving signal output unit controls the gate driving signal output end output gate The pole drive signal, the carry signal output unit controls the carry signal output terminal to output a carry signal.
  • the shift register unit increases the response speed of the amorphous silicon thin film transistor by adopting a manner in which the carry signal and the gate drive signal are discretely output.
  • the gate driving signal output unit controls the gate driving signal output end to output a gate driving signal
  • the carry signal output unit controls the carry signal output
  • the step of outputting the carry signal includes:
  • the gate driving signal output unit controls the gate driving signal output terminal to output a second clock signal under the control of the pull-up node;
  • the carry signal output unit is in the The control carry signal output end outputs the second clock signal under the control of the pull-up node;
  • the gate driving signal output unit controls the gate driving signal output end to output a low level under the control of the pull-down node, and the carry signal output unit is controlled under the control of the pull-down node
  • the carry signal output terminal outputs a low level
  • the second clock signal In the input phase and the pull-down phase, the second clock signal is a low level; in the output phase, the second clock signal is a high level.
  • the duty ratio of the first clock signal and the duty ratio of the second clock signal are both 0.25.
  • the duration of the input phase, the duration of the output phase, and the duration of the pulldown phase are all a unit of time.
  • the first clock signal is delayed by two time units than the second clock signal.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of stages of the above shift register unit;
  • the odd row shift register unit is disposed on the left side of the display panel, and the even row shift register unit is disposed on the right side of the display panel;
  • the even row shift register unit is disposed on the left side of the display panel, and the odd row shift register unit is disposed on the right side of the display panel.
  • the gate driving circuit of the embodiment of the present disclosure interleaves the shift register unit on the left and right sides of the display panel to further reduce the frame size of the display panel, which is more conducive to the high-resolution display product.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of stages of the above shift register unit;
  • the second clock signal input end of the 8n-7th shift register unit is connected to the first left clock signal CK1L or the first right clock signal CK1R;
  • the second clock signal input end of the 8n-5th stage shift register unit is connected to the second left clock signal CK2L or the second right clock signal CK2R;
  • the first clock signal input end of the 8n-7th shift register unit is connected to the third left clock signal CK3L or the third right clock signal CK3R;
  • the first clock signal input end of the 8n-5th stage shift register unit is connected to the fourth left clock signal CK4L or the fourth right clock signal CK4R;
  • the second clock signal input end of the 8th-6th stage shift register unit is connected to the first right clock signal CK1R or the first left clock signal CK1L;
  • the second clock signal input end of the 8th-4th stage shift register unit is connected to the second right clock signal CK2R or the second left clock signal CK2L;
  • the first clock signal input end of the 8th-6th stage shift register unit is connected to the third right clock signal CK3R or the third left clock signal CK3L;
  • the first clock signal input end of the 8th-4th stage shift register unit is connected to the fourth right clock signal CK4R or the fourth left clock signal CK4L;
  • the second clock signal input end of the 8n-3 stage shift register unit is connected to the third left clock signal CK3L or the third right clock signal CK3R;
  • the second clock signal input end of the 8n-1th shift register unit is connected to the fourth left clock signal CK4L or fourth right clock signal CK4R;
  • the first clock signal input end of the 8th-3th stage shift register unit is connected to the first left clock signal CK1L or the first right clock signal CK1R;
  • the first clock signal input end of the 8n-1th stage shift register unit is connected to the second left clock signal CK2L or the second right clock signal CK2R;
  • the second clock signal input end of the 8n-2 stage shift register unit is connected to the third right clock signal CK3R or the third left clock signal CK3L;
  • the second clock signal input end of the 8nth stage shift register unit is connected to the fourth right clock signal CK4R or the fourth left clock signal CK3R;
  • the first clock signal input end of the 8n-2 stage shift register unit is connected to the first right clock signal CK1R or the first left clock signal CK1L;
  • the first clock signal input end of the 8nth stage shift register unit is connected to the second right clock signal CK2R or the second left clock signal CK2L;
  • n is a positive integer
  • the second left clock signal CK2L is delayed by one time unit from the first left clock signal CK1L
  • the third left clock signal CK3L is delayed by one time unit from the second left clock signal CK2L
  • the fourth left side The clock signal CK4L is delayed by one time unit than the third left clock signal CK3L.
  • the second right clock signal CK2R is delayed by one time unit from the first right clock signal CK1R
  • the third right clock signal CK3R is delayed by one time unit from the second right clock signal CK2R
  • the fourth right clock signal CK4R is third.
  • the right clock signal CK3R is delayed by one time unit.
  • the first right clock signal CK1R is delayed by 0.5 time units from the first left clock signal CK1L.
  • All clock signals have a duty cycle of 0.25, and all clock signals continue to be high for one time unit.
  • the first carry signal input of each row of shift register cells on the left side is coupled to the carry signal output of the adjacent row of shift register cells on the left side.
  • the shift register unit of each row on the right side A carry signal input terminal is connected to the carry signal output terminal of the shift register unit adjacent to the right side of the right side.
  • the second carry signal input of each row of shift register cells on the left side is coupled to the carry signal output of the next row of shift register cells on the left side.
  • the second carry signal input terminal of each shift register unit on the right side is connected to the carry signal output terminal of the shift register unit adjacent to the next row on the right side.
  • the gate driving circuit of the embodiment of the present disclosure adopts an 8-phase clock driving method (that is, 8 clock signals are used), thereby controlling the upper-stage shift register unit to output a high-level gate driving signal.
  • the first stage shift register unit can be precharged, thereby reducing the power consumption of the entire gate drive circuit.
  • the gate drive circuit of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the gate driving circuit of the present disclosure includes a first stage shift register unit X1, a second stage shift register unit X2, a third stage shift register unit X3, and a fourth Stage shift register unit X4, fifth stage shift register unit X5, sixth stage shift register unit X6, seventh stage shift register unit X7, eighth stage shift register unit X8, and ninth stage shift register unit (Not shown in Figure 11).
  • X1, X3, X5 and X7 are arranged on the left side of the display panel; X2, X4, X6 and X8 are arranged on the right side of the display panel.
  • the second clock signal input terminal CK of X1 is connected to the first left clock signal CK1L, and the first clock signal input terminal CKB of X1 is connected to the third left clock signal CK3L.
  • the second clock signal input terminal CK of X2 is connected to the first right clock signal CK1R, and the first clock signal input terminal CKB of X2 is connected to the third right clock signal CK3R.
  • the second clock signal input terminal CK of X3 is connected to the second left clock signal CK2L; the first clock signal input terminal CKB of X3 is connected to the fourth left clock signal CK4L.
  • the second clock signal input terminal CK of X4 is connected to the second right clock signal CK2R; the first clock signal input terminal CKB of X4 is connected to the fourth right clock signal CK4R.
  • the second clock signal input terminal CK of X5 is connected to the third left clock signal CK3L, the first of X5
  • the clock signal input terminal CKB is connected to the first left clock signal CK1L.
  • the second clock signal input terminal CK of X6 is connected to the third right clock signal CK3R, and the first clock signal input terminal CKB of X6 is connected to the first right clock signal CK1R.
  • the second clock signal input terminal CK of X7 is connected to the fourth left clock signal CK4L; the first clock signal input terminal CKB of X7 is connected to the second left clock signal CK2L.
  • the second clock signal input terminal CK of X8 is connected to the fourth right clock signal CK4R; the first clock signal input terminal CKB of X8 is connected to the second right clock signal CK2R.
  • the first start signal input of X1 is connected to the start signal STV; the first start signal input of X2 is also connected to the start signal STV.
  • the second start signal input of X1 is coupled to the carry signal output STV_N+1 of X3.
  • the first start signal input of X3 is coupled to the carry signal output STV_N of X1.
  • the second start signal input of X3 is connected to the carry signal output STV_N+2 of X5.
  • the first start signal input of X5 is coupled to the carry signal output STV_N+1 of X3.
  • the second start signal input of X5 is coupled to the carry signal output STV_N+3 of X7.
  • the first start signal input of X7 is connected to the carry signal output STV_N+2 of X5.
  • the second start signal input terminal of X7 is connected to the carry signal output terminal STV_N+4 of the ninth stage shift register unit.
  • the second start signal input of X2 is coupled to the carry signal output STV_NN+1 of X4.
  • the first start signal input of X4 is coupled to the carry signal output STV_NN of X2.
  • the second start signal input of X4 is coupled to the carry signal output STV_NN+2 of X6.
  • the first start signal input of X6 is coupled to the carry signal output STV_NN+1 of X4.
  • the second start signal input of X6 is connected to the carry signal output STV_NN+3 of X8.
  • the first start signal input of X8 is connected to the carry signal output STV_NN+2 of X6.
  • the second start signal input terminal of X8 is connected to the carry signal output terminal STV_NN+4 of the ninth stage shift register unit.
  • the gate drive signal output of X1 is labeled as OUT_N; the gate drive signal output of X2 is labeled OUT_N+1; the output of the gate drive signal of X3 is labeled OUT_N+2; the output of the gate drive signal of X4 is marked as OUT_N+3; the output of the gate drive signal of X5 is labeled OUT_N+4; the output of the gate drive signal of X6 is labeled OUT_N+5; the output of the gate drive signal of X7 is marked For OUT_N+6; the gate drive signal output of X8 is labeled OUT_N+7.
  • the second left clock signal CK2L is delayed by one time unit from the first left clock signal CK1L
  • the third left clock signal CK3L is delayed by one time unit from the second left clock signal CK2L
  • the fourth left side The clock signal CK4L is delayed by one time unit than the third left clock signal CK3L.
  • the second right clock signal CK2R is delayed by one time unit from the first right clock signal CK1R
  • the third right clock signal CK3R is delayed by one time unit from the second right clock signal CK2R
  • the fourth right clock signal CK4R is third.
  • the right clock signal CK3R is delayed by one time unit.
  • the first right clock signal CK1R is delayed by 0.5 time units from the first left clock signal CK1L.
  • All clock signals have a duty cycle of 0.25, and all clock signals continue to be high for one time unit.
  • FIG. 12 is a waveform diagram of the output signal of the gate drive signal output end of X1-X8.
  • the gate drive signals outputted by the adjacent stage shift register unit are sequentially delayed by 0.5 time units, that is, When the first stage shift register unit also outputs a high level gate drive signal, the adjacent next stage shift register unit has begun to precharge and output a gate drive signal, thereby reducing the work of the entire gate drive circuit. Consumption.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of stages of the above shift register unit; the even-numbered shift register unit is disposed on the left side of the display panel, and the odd-numbered shift register unit is disposed on the right side of the display panel;
  • the second clock signal input end of the 8n-7th shift register unit is connected to the first right clock signal
  • the second clock signal input end of the 8n-5th stage shift register unit is connected to the second right clock signal
  • the first clock signal input end of the 8n-7th shift register unit is connected to the third right clock signal
  • the first clock signal input end of the 8n-5th stage shift register unit is connected to the fourth right clock signal;
  • the second clock signal input end of the 8th-6th stage shift register unit is connected to the first left clock signal
  • the second clock signal input end of the 8th-4th stage shift register unit is connected to the second left clock signal
  • the first clock signal input end of the 8th-6th stage shift register unit is connected to the third left clock signal
  • the first clock signal input end of the 8th-4th stage shift register unit is connected to the fourth left clock signal
  • the second clock signal input end of the 8th-3th stage shift register unit is connected to the third right clock signal
  • the second clock signal input end of the 8n-1th stage shift register unit is connected to the fourth right clock signal
  • the first clock signal input end of the 8th-3th stage shift register unit is connected to the first right clock signal
  • the first clock signal input end of the 8n-1th stage shift register unit is connected to the second right clock signal
  • the second clock signal input end of the 8n-2th stage shift register unit is connected to the third left clock signal
  • the second clock signal input end of the 8nth stage shift register unit is connected to the fourth left clock signal
  • the first clock signal input end of the 8n-2th stage shift register unit is connected to the first left clock signal
  • the first clock signal input end of the 8th-stage shift register unit is connected to the second left clock signal
  • n is a positive integer.
  • the second left clock signal is delayed by one time unit from the first left clock signal
  • the third left clock signal is delayed by one time unit from the second left clock signal
  • the fourth left clock signal is delayed from the third left clock signal. A unit of time.
  • the second right clock signal is delayed by one time unit from the first right clock signal
  • the third right clock signal is delayed by one time unit from the second right clock signal
  • the fourth right clock signal is delayed from the third right clock signal A unit of time.
  • the first left clock signal is delayed by 0.5 time units than the first right clock signal.
  • All clock signals have a duty cycle of 0.25, and all clock signals continue to be high for one time unit.
  • the first carry signal input of each row of shift register cells on the left side is coupled to the carry signal output of the adjacent row of shift register cells on the left side.
  • the first carry signal input of each row of shift register cells on the right side is coupled to the carry signal output of the adjacent row of shift register cells on the right side.
  • the second carry signal input of each row of shift register cells on the left side is coupled to the carry signal output of the next row of shift register cells on the left side.
  • the second carry signal input terminal of each shift register unit on the right side is connected to the carry signal output terminal of the shift register unit adjacent to the next row on the right side.
  • the difference between the gate driving circuit of this embodiment and the specific embodiment of the gate driving circuit shown in FIG. 11 is that the even-numbered shift register unit is disposed on the left side of the display panel, and the odd-numbered shift The bit register unit is disposed on the right side of the display panel; the operation process of the gate driving circuit in the embodiment of the present disclosure is the same as the specific embodiment of the gate driving circuit shown in FIG. 11 of the present disclosure, and is also the upper shift register.
  • the adjacent next stage shift register unit has begun to precharge and output a gate drive signal, thereby reducing the power consumption of the entire gate drive circuit.
  • a display device includes a display panel and the above-described gate driving circuit.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元包括：第一上拉节点控制单元（11）；第二上拉节点控制单元（12），在下拉保持阶段在第一时钟信号的控制下控制上拉节点的电位为第一电平；第一下拉节点控制单元（13），在下拉保持阶段在第一时钟信号的控制下控制所述下拉节点的电位为第二电平；第二下拉节点控制单元（14）；栅极驱动信号输出单元（15），在上拉节点和下拉节点的控制下控制栅极驱动信号输出端输出栅极驱动信号；以及，进位信号输出单元（16），在上拉节点和下拉节点的控制下控制进位信号输出端输出进位信号。

Description

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2015年12月31日在中国提交的中国专利申请号No.201511029520.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。
背景技术
应用于显示装置的栅极驱动电路包括多级移位寄存器单元。所述移位寄存器单元包括上拉节点控制单元、下拉节点控制单元和栅极驱动信号输出单元，所述上拉节点控制单元与上拉节点连接，用于控制上拉节点的电位；所述下拉节点控制单元与下拉节点连接，用于控制下拉节点的电位；所述栅极驱动信号输出单元用于根据所述上拉节点的电位和所述下拉节点的电位控制输出栅极驱动信号，该栅极驱动信号同时作为相邻移位寄存器单元的进位信号，从而相应速度比较慢。并且，移位寄存器单元中的主要器件是薄膜晶体管，薄膜晶体管在长期被直流电压驱动时或在高温工作条件下其阈值电压会发生较大漂移从而导致信赖性低，并且当该薄膜晶体管为多晶硅薄膜晶体管时，其停止工作后具有较大的漏电流，使得漏电严重功耗增加，甚至有可能影响移位寄存器单元的正常工作。
发明内容
本公开的主要目的在于提供一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置，解决薄膜晶体管在长时间或高温工作条件下阈值电压发生较大漂移以及响应速度慢的问题。
为了达到上述目的，本公开提供了一种移位寄存器单元，包括栅极驱动信号输出端、进位信号输出端、第一时钟信号输入端和进位信号输入端，所 述移位寄存器单元还包括：
第一上拉节点控制单元，与上拉节点和进位信号输入端连接；
第二上拉节点控制单元，与所述上拉节点连接，并与所述第一时钟信号输入端连接，用于在下拉保持阶段在第一时钟信号的控制下控制所述上拉节点的电位为第一电平；
第一下拉节点控制单元，与下拉节点连接，并与所述第一时钟信号输入端连接，用于在下拉保持阶段在所述第一时钟信号的控制下控制所述下拉节点的电位为第二电平；
第二下拉节点控制单元，与所述上拉节点和所述下拉节点连接，用于在所述上拉节点的电位为第二电平时控制所述下拉节点的电位为第一电平；
栅极驱动信号输出单元，分别与所述上拉节点、所述下拉节点和所述栅极驱动信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下控制所述栅极驱动信号输出端输出栅极驱动信号；以及，
进位信号输出单元，分别与所述上拉节点、所述下拉节点和所述进位信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下控制所述进位信号输出端输出进位信号。
实施时，所述第一上拉节点控制单元用于在输入阶段在进位信号的控制下控制所述上拉节点的电位为第二电平，在输出阶段维持所述上拉节点的电位为第二电平。
实施时，所述进位信号输入端包括第一进位信号输入端和第二进位信号输入端；
在正向扫描时，所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接；
在反向扫描时，所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接。
实施时，所述第一上拉节点控制单元包括：
第一输入模块，与所述上拉节点连接，并通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，用于当正向扫描时，在所述输入阶段在第一进位信号的控制下控制所述上拉节点的电位为第二电 平；以及，
第二输入模块，与所述上拉节点连接，并通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，用于当反向扫描时，在所述输入阶段在第二进位信号的控制下控制所述上拉节点的电位为第二电平。
实施时，所述第一输入模块包括：第一晶体管，栅极和第一极都通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，第二极与所述上拉节点连接；
所述第二输入模块包括：第二晶体管，栅极和第二极都通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述上拉节点连接。
实施时，所述第一上拉节点控制单元还包括：
第一存储电容，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；和/或
第二存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端连接。
实施时，在所述下拉保持阶段最开始的一段时间所述第一时钟信号为第二电平，之后每间隔预定时间所述第一时钟信号为第二电平，在该预定时间内所述第一时钟信号为第一电平。
实施时，本公开所述的移位寄存器单元还包括第二时钟信号输入端；
所述栅极驱动信号输出单元，还接入第一电平，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点的控制下控制所述栅极驱动信号输出端输出第二时钟信号，在下拉保持阶段在所述下拉节点的控制下控制所述栅极驱动信号输出端输出第一电平；
所述进位信号输出单元，还接入第一电平，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点的控制下控制所述进位信号输出端输出所述第二时钟信号，在下拉保持阶段在所述下拉节点的控制下控制所述进位信号输出端输出第一电平；
在所述输入阶段和所述下拉阶段，所述第二时钟信号为第一电平；在所 述输出阶段，所述第二时钟信号为第二电平。
实施时，所述第一时钟信号的占空比和所述第二时钟信号的占空比都为0.25；
所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持续的时间都为一个时间单元；
所述第一时钟信号比所述第二时钟信号延迟两个时间单元。
实施时，所述预定时间为三个时间单元。
实施时，所述第一电平为低电平，所述第二电平为高电平；或者，
所述第一电平为高电平，所述第二电平为低电平。
实施时，所述第二上拉节点控制单元还与所述下拉节点连接，还用于当所述下拉节点的电位为第二电平时控制所述上拉节点的电位为第一电平。
实施时，所述第二上拉节点控制单元包括：
第三晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接，第二极接入第一电平；以及，
第四晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极接入第一电平。
实施时，所述第一下拉节点控制单元包括：第五晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉节点连接。
实施时，所述第二下拉节点控制单元，还与相邻下一级移位寄存器单元的进位信号输出端连接，还用于当所述相邻下一级移位寄存器单元的进位信号输出端输出第二电平时，控制所述下拉节点的电位为第一电平。
实施时，所述第二下拉节点控制单元包括：
第六晶体管，栅极通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述下拉节点连接，第二极接入第一电平；以及，
第七晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极接入第一电平。
实施时，所述栅极驱动信号输出单元包括：
第一栅极驱动信号输出晶体管，栅极与所述上拉节点连接，第一极与所 述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动信号输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入第一电平；
所述进位信号输出单元包括：
第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述进位信号输出端连接；以及，
第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极接入第一电平。
本公开还提供了一种移位寄存器单元的驱动方法，包括：
在输入阶段，第二下拉节点控制单元在上拉节点的控制下控制所述下拉节点的电位为第一电平，第一上拉节点控制单元控制上拉节点的电位为第二电平；
在输出阶段，第一上拉节点控制单元控制所述上拉节点的电位维持为第二电平，第二下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
在下拉阶段，所述上拉节点的电位维持为第二电平，第二下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
在下拉保持阶段，第二上拉节点控制单元在第一时钟信号的控制下控制上拉节点的电位为第一电平，第一下拉节点控制单元在所述第一时钟信号的控制下控制所述下拉节点的电位为第二电平。
实施时，在输入阶段，所述第一上拉节点控制单元控制所述上拉节点的电位为第二电平步骤包括：
当正向扫描时，所述第一上拉节点控制单元在所述第一进位信号的控制下控制所述上拉节点的电位为第二电平，所述第一进位信号为相邻上一级移位寄存器单元输出的进位信号；
当反向扫描时，所述第一上拉节点控制单元在所述第二进位信号的控制下控制所述上拉节点的电位为第二电平，所述第二进位信号为相邻下一级移位寄存器单元输出的进位信号。
实施时，本公开所述的移位寄存器单元的驱动方法还包括：在所述上拉 节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号。
实施时，所述在所述上拉节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号步骤包括：
在输入阶段、输出阶段和下拉阶段，所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端输出第二时钟信号；所述进位信号输出单元在所述上拉节点的控制下控制进位信号输出端输出所述第二时钟信号；
在下拉保持阶段，所述栅极驱动信号输出单元在所述下拉节点的控制下控制所述栅极驱动信号输出端输出第一电平，所述进位信号输出单元在所述下拉节点的控制下控制所述进位信号输出端输出第一电平；
在所述输入阶段和所述下拉阶段，所述第二时钟信号为第一电平；在所述输出阶段，所述第二时钟信号为第二电平。
实施时，所述第一时钟信号的占空比和所述第二时钟信号的占空比都为0.25；
所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持续的时间都为一个时间单元；
所述第一时钟信号比所述第二时钟信号延迟两个时间单元。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元；
奇数行移位寄存器单元设置于显示面板左侧，偶数行移位寄存器单元设置于显示面板右侧；或者，
偶数行移位寄存器单元设置于显示面板左侧，奇数行移位寄存器单元设置于显示面板右侧。
本公开还提供了一种栅极驱动电路，包括多级移位寄存器单元；
第8n-7级移位寄存器单元的第二时钟信号输入端接入第一左侧时钟信号或第一右侧时钟信号；
第8n-5级移位寄存器单元的第二时钟信号输入端接入第二左侧时钟信号 或第二右侧时钟信号；
第8n-7级移位寄存器单元的第一时钟信号输入端接入第三左侧时钟信号或第三右侧时钟信号；
第8n-5级移位寄存器单元的第一时钟信号输入端接入第四左侧时钟信号或第四右侧时钟信号；
第8n-6级移位寄存器单元的第二时钟信号输入端接入第一右侧时钟信号或第一左侧时钟信号；
第8n-4级移位寄存器单元的第二时钟信号输入端接入第二右侧时钟信号或第二左侧时钟信号；
第8n-6级移位寄存器单元的第一时钟信号输入端接入第三右侧时钟信号或第三左侧时钟信号；
第8n-4级移位寄存器单元的第一时钟信号输入端接入第四右侧时钟信号或第四左侧时钟信号；
第8n-3级移位寄存器单元的第二时钟信号输入端接入第三左侧时钟信号或第三右侧时钟信号；
第8n-1级移位寄存器单元的第二时钟信号输入端接入第四左侧时钟信号或第四右侧时钟信号；
第8n-3级移位寄存器单元的第一时钟信号输入端接入第一左侧时钟信号或第一右侧时钟信号；
第8n-1级移位寄存器单元的第一时钟信号输入端接入第二左侧时钟信号或第二右侧时钟信号；
第8n-2级移位寄存器单元的第二时钟信号输入端接入第三右侧时钟信号或第三左侧时钟信号；
第8n级移位寄存器单元的第二时钟信号输入端接入第四右侧时钟信号或第四左侧时钟信号；
第8n-2级移位寄存器单元的第一时钟信号输入端接入第一右侧时钟信号或第一左侧时钟信号；
第8n级移位寄存器单元的第一时钟信号输入端接入第二右侧时钟信号或第二左侧时钟信号；
n为正整数；
第二左侧时钟信号比第一左侧时钟信号延迟一个时间单元，第三左侧时钟信号比第二左侧时钟信号延迟一个时间单元，第四左侧时钟信号比第三左侧时钟信号延迟一个时间单元；
第二右侧时钟信号比第一右侧时钟信号延迟一个时间单元，第三右侧时钟信号比第二右侧时钟信号延迟一个时间单元，第四右侧时钟信号比第三右侧时钟信号延迟一个时间单元；
第一右侧时钟信号比第一左侧时钟信号延迟0.5个时间单元；
所有的时钟信号的占空比都为0.25，所有的时钟信号持续为第一电平的时间为三个时间单元，所有的时钟信号持续为第二电平的时间为一个时间单元；
除了左侧第一行移位寄存器单元之外，左侧每一行移位寄存器单元的第一进位信号输入端都与左侧相邻上一行移位寄存器单元的进位信号输出端连接；
除了右侧第一行移位寄存器单元之外，右侧每一行移位寄存器单元的第一进位信号输入端都与右侧相邻上一行移位寄存器单元的进位信号输出端连接；
除了左侧最后一行移位寄存器单元之外，左侧每一行移位寄存器单元的第二进位信号输入端都与左侧相邻下一行移位寄存器单元的进位信号输出端连接；
除了右侧最后一行移位寄存器单元之外，右侧每一行移位寄存器单元的第二进位信号输入端都与右侧相邻下一行移位寄存器单元的进位信号输出端连接。
本公开还提供了一种显示装置，包括显示面板和上述的栅极驱动电路。
本公开所述的移位寄存器单元及其驱动方法、栅极驱动电路和显示装置通过控制第一上拉节点控制单元、第二上拉节点控制单元、第一下拉节点控制单元和第二下拉节点控制单元均工作在交流电压驱动下，抑制了多晶硅薄膜晶体管的漏电流，避免了薄膜晶体管在长时间或高温工作条件下阈值电压发生较大漂移的问题；并且本公开实施例所述的移位寄存器单元采用进位信 号与栅极驱动信号分立输出的方式，提高了非晶硅薄膜晶体管的响应速度。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是图1所示的移位寄存器单元的工作时序图；
图3A是本公开另一实施例所述的移位寄存器单元的结构图；
图3B是本公开该实施例所述的移位寄存器单元的工作时序图；
图4是本公开又一实施例所述的移位寄存器单元的结构图；
图5是第一时钟信号CKB和所述第二时钟信号CK的波形图；
图6是本公开另一实施例所述的移位寄存器单元的结构图；
图7是本公开又一实施例所述的移位寄存器单元的结构图；
图8是本公开所述的移位寄存器单元的一具体实施例的电路图；
图9是本公开如图8所示的移位寄存器单元的具体实施例的工作时序图；
图10是本公开实施例所述的栅极驱动电路接入的8个时钟信号的波形图；
图11是本公开所述的栅极驱动电路的一具体实施例的结构图；
图12是本公开所述的栅极驱动电路的该具体实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的移位寄存器单元包括栅极驱动信号输出端OUT_N、进位信号输出端STV_N、输入第一时钟信号CKB的第一时钟信号输入端和进位信号输入端SI。
所述移位寄存器单元还包括：
第一上拉节点控制单元11，与上拉节点PU和所述进位信号输入端连接；
第二上拉节点控制单元12，与所述上拉节点PU连接，并与所述第一时 钟信号输入端连接，用于在下拉保持阶段在第一时钟信号CKB的控制下控制所述上拉节点PU的电位为第一电平；
第一下拉节点控制单元13，与下拉节点PD连接，并与所述第一时钟信号输入端连接，用于在下拉保持阶段在所述第一时钟信号CKB的控制下控制所述下拉节点PD的电位为第二电平；
第二下拉节点控制单元14，与所述上拉节点PU和所述下拉节点PD连接，用于在所述上拉节点PU的电位为第二电平时控制所述下拉节点PD的电位为第一电平；
栅极驱动信号输出单元15，分别与所述上拉节点PU、所述下拉节点PD和所述栅极驱动信号输出端OUT_N连接，用于在所述上拉节点PU和所述下拉节点PD的控制下控制所述栅极驱动信号输出端OUT_N输出栅极驱动信号；以及，
进位信号输出单元16，分别与所述上拉节点PU、所述下拉节点PD和所述进位信号输出端STV_N连接，用于在所述上拉节点PU和所述下拉节点PD的控制下控制所述进位信号输出端STV_N输出进位信号。
在实际操作时，在输出阶段和下拉保持阶段之间还包括下拉阶段，在下拉阶段上拉节点的电位维持为第二电平，本公开所述的移位寄存器单元在输入阶段、输出阶段、下拉阶段和下拉保持阶段的具体工作过程会在后续详细记载。
具体的，所述第一电平可以为低电平，所述第二电平可以为高电平；或者，第一电平可以为高电平，第二电平可以为低电平，下面的图2是以第一电平为低电平而第二电平为高电平来具体绘制的，但并不以图2对本公开实施例所述的移位寄存器单元的工作时序进行限定。
图2是如图1所示的移位寄存器单元在工作时的时序图，在图2中，T1标示输入阶段，T2标示输出阶段，T3标示下拉阶段，T4标示下拉保持阶段。
本公开实施例所述的移位寄存器单元通过控制第一上拉节点控制单元、第二上拉节点控制单元、第一下拉节点控制单元和第二下拉节点控制单元均工作在交流电压驱动下，抑制了多晶硅薄膜晶体管的漏电流，避免了薄膜晶体管在长时间或高温信赖性工作条件下阈值电压发生较大漂移而导致无法保 持低电平和高电平的问题；并且本公开实施例所述的移位寄存器单元采用进位信号与栅极驱动信号分立输出的方式，提高了非晶硅薄膜晶体管的响应速度。
在实际操作时，所述第一上拉节点控制单元用于在输入阶段在进位信号的控制下控制所述上拉节点的电位为第二电平，在输出阶段维持所述上拉节点的电位为第二电平。
具体的，所述进位信号输入端包括第一进位信号输入端和第二进位信号输入端；由所述第一进位信号输入端输入第一进位信号，由所述第二进位信号输入端输入第二进位信号；
在正向扫描时，所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，所述第一进位信号为相邻上一级移位寄存器单元输出的进位信号，在对本公开实施例所述的移位寄存器单元进行正向扫描时，所述第一上拉节点控制单元具体用于在输入阶段在所述第一进位信号的控制下控制所述上拉节点的电位为第二电平；
在反向扫描时，所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，所述第二进位信号为相邻下一级移位寄存器单元输出的进位信号，在对本公开实施例所述的移位寄存器单元进行反向扫描时，所述第一上拉节点控制单元具体用于在输入阶段在所述第二进位信号的控制下控制所述上拉节点的电位为第二电平。
具体的，所述进位信号输入端可以包括第一进位信号输入端和第二进位信号输入端；
如图3A所示，由所述第一进位信号输入端输入相邻上一级移位寄存器单元的进位信号输出端STV_N-1输出的进位信号；
由所述第二进位信号输入端输入相邻下一级移位寄存器单元的进位信号输出端STV_N+1输出的进位信号；
所述第一上拉节点控制单元包括：
第一输入模块111，与所述上拉节点PU连接，并通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端STV_N-1连接，用于当正向扫描时在所述输入阶段在第一进位信号的控制下控制所述上拉节点 PU的电位为第二电平；以及，
第二输入模块112，与所述上拉节点PU连接，并通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端STV_N+1连接，用于当反向扫描时在所述输入阶段在第二进位信号的控制下控制所述上拉节点PU的电位为第二电平；
所述第一进位信号即为相邻上一级移位寄存器单元的进位信号输出端STV_N-1输出的进位信号，当正向扫描时，在输入阶段STV_N-1输出的进位信号为第二电平；
所述第二进位信号即为相邻下一级移位寄存器单元的进位信号输出端STV_N+1输出的进位信号，当反向扫描时，在输入阶段STV_N+1输出的进位信号为第二电平。
STV_N-1输出的第一进位信号和STV_N+1输出的第二进位信号如图3B所示。
具体的，所述第一输入模块可以包括：第一晶体管，栅极和第一极都通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，第二极与所述上拉节点连接；
所述第二输入模块可以包括：第二晶体管，栅极和第二极都通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述上拉节点连接。
在实际操作时，所述第一上拉节点控制单元还可以包括：
第一存储电容，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端OUT_N连接；和/或，
第二存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端STV_N连接；
所述第一存储电容和/或所述第二存储电容用于在输出阶段自举拉升所述上拉节点PU的电位。
可选的，如图3所示，所述第一上拉节点控制单元还包括：
第一存储电容C1，第一端与所述上拉节点PU连接，第二端与所述栅极驱动信号输出端OUT_N连接；以及，
第二存储电容C2，第一端与所述上拉节点PU连接，第二端与所述进位信号输出端STV_N连接；
所述第一存储电容C1和所述第二存储电容C2同时在输出阶段自举拉升所述上拉节点PU的电位。
具体的，在所述下拉保持阶段最开始的一段时间所述第一时钟信号为第二电平，之后每间隔预定时间所述第一时钟信号为第二电平，在该预定时间内所述第一时钟信号为第一电平。
具体的，如图2所示，第一时钟信号CKB的波形描述如下：
在所述下拉保持阶段T4最开始的一段时间，所述第一时钟信号CKB为高电平，以控制第二上拉节点控制单元使得PD接入低电平，以拉低PD的电位，之后每间隔预定时间所述第一时钟信号CKB为高电平，在该预定时间内所述第一时钟信号CKB为低电平，以使得所述第二上拉节点控制单元被交流电压驱动。
具体的，如图4所示，本公开实施例所述的移位寄存器单元还包括输入第二时钟信号CK的第二时钟信号输入端；
所述栅极驱动信号输出单元15，还接入第一电平V1，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点PU的控制下控制所述栅极驱动信号输出端OUT_N输出第二时钟信号CK，在下拉保持阶段在所述下拉节点PD的控制下控制所述栅极驱动信号输出端OUT_N输出第一电平V1；
所述进位信号输出单元16，还接入第一电平V1，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点PU的控制下控制所述进位信号输出端STV_N输出所述第二时钟信号CK，在下拉保持阶段在所述下拉节点PD的控制下控制所述进位信号输出端STV_N输出第一电平V1；
在所述输入阶段和所述下拉阶段，所述第二时钟信号CK为第一电平；在所述输出阶段，所述第二时钟信号CK为第二电平。如图5所示，所述第一时钟信号CKB的占空比和所述第二时钟信号CK的占空比都为0.25；
所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持 续的时间都为一个时间单元；
所述第一时钟信号CKB比所述第二时钟信号CK延迟两个时间单元；
在图5中标示为T的为一个时间单元，此时上面提到的预定时间为三个时间单元。
图5是以第一电平为低电平而第二电平为高电平为例绘制的，在实际操作时所述第一电平也可以为高电平而所述第二电平也可以为低电平。
在实际操作时，如图6所示，所述第二上拉节点控制单元12还与所述下拉节点PD连接，还用于当所述下拉节点PD的电位为第二电平时控制所述上拉节点PU的电位为第一电平。
具体的，所述第二上拉节点控制单元包括：
第三晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接，第二极接入第一电平；以及，
第四晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极接入第一电平。
具体的，所述第一下拉节点控制单元包括：第五晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉节点连接。
具体的，如图7所示，所述第二下拉节点控制单元14，还与相邻下一级移位寄存器单元的进位信号输出端STV_N+1连接，还用于当所述相邻下一级移位寄存器单元的进位信号输出端STV_N+1输出第二电平时，控制所述下拉节点PD的电位为第一电平。
具体的，所述第二下拉节点控制单元包括：
第六晶体管，栅极与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述下拉节点连接，第二极接入第一电平；以及，
第七晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极接入第一电平。
具体的，所述栅极驱动信号输出单元包括：
第一栅极驱动信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动信号输出晶体管，栅极与所述下拉节点连接，第一极与所 述栅极驱动信号输出端连接，第二极接入第一电平。
所述进位信号输出单元包括：
第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述进位信号输出端连接；以及，
第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极接入第一电平。
在实际操作时，当本公开实施例所述的移位寄存器单元包括的栅极驱动信号输出单元包括的晶体管和进位信号输出单元包括的晶体管为n型晶体管时，第一电平可以为低电平，第二电平可以为高电平；而当本公开实施例所述的移位寄存器单元包括的栅极驱动信号输出单元包括的晶体管和进位信号输出单元包括的晶体管为p型晶体管时，第一电平可以为高电平，第二电平可以为低电平。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，将晶体管除栅极之外的两极称为第一极和第二极，其中，第一极和第二极可以随着电流流向的改变而互换，也即第一极为源极，第二极为漏极，或者，第一极为漏极，第二极为源极。本公开所述的移位寄存器单元的具体实施例包括的晶体管是n型晶体管，但是在实际操作时本公开实施例所述的移位寄存器单元包括的晶体管也可以为p型晶体管。
下面通过一具体实施例来说明本公开所述的移位寄存器单元：
如图8所示，本公开所述的移位寄存器单元的一具体实施例包括栅极驱动信号输出端OUT_N、进位信号输出端STV_N、输入第一时钟信号CKB的第一时钟信号输入端、第一进位信号输入端和第二进位信号输入端。
由所述第一进位信号输入端输入相邻上一级移位寄存器单元的进位信号输出端STV_N-1输出的进位信号。
由所述第二进位信号输入端输入相邻下一级移位寄存器单元的进位信号输出端STV_N+1输出的进位信号。
本公开所述的移位寄存器单元的该具体实施例还包括第一上拉节点控制单元11、第二上拉节点控制单元12、第一下拉节点控制单元13、第二下拉 节点控制单元14、栅极驱动信号输出单元15和进位信号输出单元16。
所述第一上拉节点控制单元11包括：
第一晶体管M1，栅极和漏极都通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端STV_N-1连接，第二极与所述上拉节点PU连接；
第二晶体管M2，栅极和源极都通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端STV_N+1连接，第一极与所述上拉节点PU连接；
第一存储电容C1，第一端与所述上拉节点PU连接，第二端与所述栅极驱动信号输出端OUT_N连接；以及，
第二存储电容C2，第一端与所述上拉节点PU连接，第二端与所述进位信号输出端STV_N连接。
所述第二上拉节点控制单元12包括：
第三晶体管M3，栅极与输入第一时钟信号CKB的第一时钟信号输入端连接，漏极与所述上拉节点PU连接，源极接入低电平VGL；以及，
第四晶体管M4，栅极与所述下拉节点PD连接，漏极与所述上拉节点PU连接，源极接入低电平VGL。
所述第一下拉节点控制单元13包括：第五晶体管M5，栅极和漏极都与所述第一时钟信号输入端连接，源极与所述下拉节点PD连接。
所述第二下拉节点控制单元14包括：
第六晶体管M6，栅极与相邻下一级移位寄存器单元的进位信号输出端STV_N+1连接，第一极与所述下拉节点PD连接，第二极接入低电平VGL；
第七晶体管M7，栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极接入低电平VGL；以及，
第八晶体管M8，栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极接入低电平VGL。
所述栅极驱动信号输出单元15包括：
第一栅极驱动信号输出晶体管M9，栅极与所述上拉节点连接，漏极与输入第二时钟信号CK的第二时钟信号输入端连接，源极与所述栅极驱动信号 输出端OUT_N连接；以及，
第二栅极驱动信号输出晶体管M10，栅极与所述下拉节点连接，漏极与所述栅极驱动信号输出端OUT_N连接，第二极接入低电平VGL。
所述进位信号输出单元16包括：
第一进位信号输出晶体管M11，栅极与所述上拉节点PU连接，漏极与所述第二时钟信号输入端连接，源极与所述进位信号输出端STV_N连接；以及，
第二进位信号输出晶体管M12，栅极与所述下拉节点PD连接，漏极与所述进位信号输出端STV_N连接，源极接入低电平VGL。
在图8所示的具体实施例中，所有的晶体管都是n型晶体管，第一电平为低电平，第二电平为高电平；
并且在图8所示的具体实施例中，采用了M7和M8以提高拉低PD的电位的速度。
如图9所示，本公开如图8所示的移位寄存器单元的具体实施例在工作时，在每一显示周期，
在输入阶段T1，STV_N-1输出高电平，CK为低电平，M1导通，PU的电位升高，M9和M11导通，以使得OUT_N和STV_N都输出低电平，M7和M8导通，PD的电位被拉低；
在输出阶段T2，STV_N-1输出低电平，CK为高电平，M1关闭，由于C1和C2的自举作用，PU的电位继续上升，M9和M11继续处于导通状态，OUT_N和STV_N都输出高电平；M7和M8导通，PD的电位持续被拉低；
在下拉阶段T3，CK为低电平，OUT_N和STV_N都输出低电平，由于此时C1和C2的自举功能消失，因此PU点的电位虽然维持为高电平，但是降低到初始拉高状态；
在下拉保持阶段T4：
在T4的最开始的一个时间单元，CK为低电平，CKB为高电平，M3、M4和M5都导通，以拉高PD的电位，PU的电位被拉低，M10和M12都导通，OUT_N和STV_N都输出低电平；
再经过三个时间单元，CKB再次为高电平，再一次将PD的电位拉高， 使得M10和M12处于导通状态，PU的电位处于拉低状态，并OUT_N和STV_N都输出低电平，有效避免了非工作状态噪声的引入。
并由以上本公开图8所示的移位寄存器单元的具体实施例的工作过程可知，第一上拉节点控制单元11、第二上拉节点控制单元12、第一下拉节点控制单元13和第二下拉节点控制单元14均工作在交流电压驱动下，抑制了多晶硅薄膜晶体管的漏电流，避免了薄膜晶体管在长时间或高温信赖性工作条件下阈值电压发生较大漂移而导致无法保持低电平和高电平的问题；并且本公开所述的移位寄存器单元的该具体实施例采用进位信号与栅极驱动信号分立输出的方式，提高了非晶硅薄膜晶体管的响应速度。
在实际操作时，本公开实施例所述的移位寄存器单元也可以不采用第一存储电容C1和第二存储电容C2，而依靠M9的耦合电容Cgs和M11的耦合电容的自举作用将PU的电位拉高。
本公开实施例所述的移位寄存器单元的驱动方法包括：
在输入阶段，第二下拉节点控制单元在上拉节点的控制下控制所述下拉节点的电位为第一电平，第一上拉节点控制单元控制所述上拉节点的电位为第二电平；
在输出阶段，第一上拉节点控制单元控制所述上拉节点的电位维持为第二电平，第二下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
在下拉阶段，所述上拉节点的电位维持为第二电平，第二下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
在下拉保持阶段，第二上拉节点控制单元在第一时钟信号的控制下控制上拉节点的电位为第一电平，第一下拉节点控制单元在所述第一时钟信号的控制下控制所述下拉节点的电位为第二电平。
本公开实施例所述的移位寄存器单元的驱动方法通过控制第一上拉节点控制单元、第二上拉节点控制单元、第一下拉节点控制单元和第二下拉节点控制单元均工作在交流电压驱动下，抑制了多晶硅薄膜晶体管的漏电流，避免了薄膜晶体管在长时间或高温工作条件下阈值电压发生较大漂移的问题。
具体的，在输入阶段，所述第一上拉节点控制单元控制所述上拉节点的 电位为第二电平步骤包括：
当正向扫描时，所述第一上拉节点控制单元在第一进位信号的控制下控制所述上拉节点的电位为第二电平，所述第一进位信号为相邻上一级移位寄存器单元输出的进位信号；
当反向扫描时，所述第一上拉节点控制单元在第二进位信号的控制下控制所述上拉节点的电位为第二电平，所述第二进位信号为相邻下一级移位寄存器单元输出的进位信号。
具体的，本公开实施例所述的移位寄存器单元的驱动方法还包括：在所述上拉节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号。
本公开实施例所述的移位寄存器单元采用进位信号与栅极驱动信号分立输出的方式，提高了非晶硅薄膜晶体管的响应速度。
更具体的，所述在所述上拉节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号步骤包括：
在输入阶段、输出阶段和下拉阶段，所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端输出第二时钟信号；所述进位信号输出单元在所述上拉节点的控制下控制进位信号输出端输出所述第二时钟信号；
在下拉保持阶段，所述栅极驱动信号输出单元在所述下拉节点的控制下控制所述栅极驱动信号输出端输出低电平，所述进位信号输出单元在所述下拉节点的控制下控制所述进位信号输出端输出低电平；
在所述输入阶段和所述下拉阶段，所述第二时钟信号为低电平；在所述输出阶段，所述第二时钟信号为高电平。
具体的，所述第一时钟信号的占空比和所述第二时钟信号的占空比都为0.25。
所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持续的时间都为一个时间单元。
所述第一时钟信号比所述第二时钟信号延迟两个时间单元。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元；
奇数行移位寄存器单元设置于显示面板左侧，偶数行移位寄存器单元设置于显示面板右侧；或者，
偶数行移位寄存器单元设置于显示面板左侧，奇数行移位寄存器单元设置于显示面板右侧。
本公开实施例所述的栅极驱动电路在显示面板的左侧和右侧交错设置移位寄存器单元，以进一步减小显示面板的边框尺寸，更利于高分辨率显示产品的涉及。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元；
第8n-7级移位寄存器单元的第二时钟信号输入端接入第一左侧时钟信号CK1L或第一右侧时钟信号CK1R；
第8n-5级移位寄存器单元的第二时钟信号输入端接入第二左侧时钟信号CK2L或第二右侧时钟信号CK2R；
第8n-7级移位寄存器单元的第一时钟信号输入端接入第三左侧时钟信号CK3L或第三右侧时钟信号CK3R；
第8n-5级移位寄存器单元的第一时钟信号输入端接入第四左侧时钟信号CK4L或第四右侧时钟信号CK4R；
第8n-6级移位寄存器单元的第二时钟信号输入端接入第一右侧时钟信号CK1R或第一左侧时钟信号CK1L；
第8n-4级移位寄存器单元的第二时钟信号输入端接入第二右侧时钟信号CK2R或第二左侧时钟信号CK2L；
第8n-6级移位寄存器单元的第一时钟信号输入端接入第三右侧时钟信号CK3R或第三左侧时钟信号CK3L；
第8n-4级移位寄存器单元的第一时钟信号输入端接入第四右侧时钟信号CK4R或第四左侧时钟信号CK4L；
8n-3级移位寄存器单元的第二时钟信号输入端接入第三左侧时钟信号CK3L或第三右侧时钟信号CK3R；
第8n-1级移位寄存器单元的第二时钟信号输入端接入第四左侧时钟信号 CK4L或第四右侧时钟信号CK4R；
第8n-3级移位寄存器单元的第一时钟信号输入端接入第一左侧时钟信号CK1L或第一右侧时钟信号CK1R；
第8n-1级移位寄存器单元的第一时钟信号输入端接入第二左侧时钟信号CK2L或第二右侧时钟信号CK2R；
第8n-2级移位寄存器单元的第二时钟信号输入端接入第三右侧时钟信号CK3R或第三左侧时钟信号CK3L；
第8n级移位寄存器单元的第二时钟信号输入端接入第四右侧时钟信号CK4R或第四左侧时钟信号CK3R；
第8n-2级移位寄存器单元的第一时钟信号输入端接入第一右侧时钟信号CK1R或第一左侧时钟信号CK1L；
第8n级移位寄存器单元的第一时钟信号输入端接入第二右侧时钟信号CK2R或第二左侧时钟信号CK2L；
n为正整数；
如图10所示，第二左侧时钟信号CK2L比第一左侧时钟信号CK1L延迟一个时间单元，第三左侧时钟信号CK3L比第二左侧时钟信号CK2L延迟一个时间单元，第四左侧时钟信号CK4L比第三左侧时钟信号CK3L延迟一个时间单元。
第二右侧时钟信号CK2R比第一右侧时钟信号CK1R延迟一个时间单元，第三右侧时钟信号CK3R比第二右侧时钟信号CK2R延迟一个时间单元，第四右侧时钟信号CK4R比第三右侧时钟信号CK3R延迟一个时间单元。
第一右侧时钟信号CK1R比第一左侧时钟信号CK1L延迟0.5个时间单元。
所有的时钟信号的占空比都为0.25，所有的时钟信号持续为高电平的时间为一个时间单元。
除了左侧第一行移位寄存器单元之外，左侧每一行移位寄存器单元的第一进位信号输入端都与左侧相邻上一行移位寄存器单元的进位信号输出端连接。
除了右侧第一行移位寄存器单元之外，右侧每一行移位寄存器单元的第 一进位信号输入端都与右侧相邻上一行移位寄存器单元的进位信号输出端连接。
除了左侧最后一行移位寄存器单元之外，左侧每一行移位寄存器单元的第二进位信号输入端都与左侧相邻下一行移位寄存器单元的进位信号输出端连接。
除了右侧最后一行移位寄存器单元之外，右侧每一行移位寄存器单元的第二进位信号输入端都与右侧相邻下一行移位寄存器单元的进位信号输出端连接。
本公开实施例所述的栅极驱动电路采用了8相位的时钟驱动方式(即采用了8个时钟信号)，从而控制上一级移位寄存器单元还在输出高电平的栅极驱动信号时下一级移位寄存器单元就可以进行预充电，从而降低了整个栅极驱动电路的功耗。
下面通过一具体实施例来说明本公开所述的栅极驱动电路。
如图11所示，本公开所述的栅极驱动电路的一具体实施例包括第一级移位寄存器单元X1、第二级移位寄存器单元X2、第三级移位寄存器单元X3、第四级移位寄存器单元X4、第五级移位寄存器单元X5、第六级移位寄存器单元X6、第七级移位寄存器单元X7、第八级移位寄存器单元X8和第九级移位寄存器单元(图11中未示)。
其中，X1、X3、X5和X7设置于显示面板的左侧；X2、X4、X6和X8设置于显示面板的右侧。
X1的第二时钟信号输入端CK接入第一左侧时钟信号CK1L，X1的第一时钟信号输入端CKB接入第三左侧时钟信号CK3L。
X2的第二时钟信号输入端CK接入第一右侧时钟信号CK1R，X2的第一时钟信号输入端CKB接入第三右侧时钟信号CK3R。
X3的第二时钟信号输入端CK接入第二左侧时钟信号CK2L；X3的第一时钟信号输入端CKB接入第四左侧时钟信号CK4L。
X4的第二时钟信号输入端CK接入第二右侧时钟信号CK2R；X4的第一时钟信号输入端CKB接入第四右侧时钟信号CK4R。
X5的第二时钟信号输入端CK接入第三左侧时钟信号CK3L，X5的第一 时钟信号输入端CKB接入第一左侧时钟信号CK1L。
X6的第二时钟信号输入端CK接入第三右侧时钟信号CK3R，X6的第一时钟信号输入端CKB接入第一右侧时钟信号CK1R。
X7的第二时钟信号输入端CK接入第四左侧时钟信号CK4L；X7的第一时钟信号输入端CKB接入第二左侧时钟信号CK2L。
X8的第二时钟信号输入端CK接入第四右侧时钟信号CK4R；X8的第一时钟信号输入端CKB接入第二右侧时钟信号CK2R。
X1的第一起始信号输入端接入起始信号STV；X2的第一起始信号输入端也接入起始信号STV。
X1的第二起始信号输入端与X3的进位信号输出端STV_N+1连接。
X3的第一起始信号输入端与X1的进位信号输出端STV_N连接。
X3的第二起始信号输入端与X5的进位信号输出端STV_N+2连接。
X5的第一起始信号输入端与X3的进位信号输出端STV_N+1连接。
X5的第二起始信号输入端与X7的进位信号输出端STV_N+3连接。
X7的第一起始信号输入端与X5的进位信号输出端STV_N+2连接。
X7的第二起始信号输入端与第九级移位寄存器单元的进位信号输出端STV_N+4连接。
X2的第二起始信号输入端与X4的进位信号输出端STV_NN+1连接。
X4的第一起始信号输入端与X2的进位信号输出端STV_NN连接。
X4的第二起始信号输入端与X6的进位信号输出端STV_NN+2连接。
X6的第一起始信号输入端与X4的进位信号输出端STV_NN+1连接。
X6的第二起始信号输入端与X8的进位信号输出端STV_NN+3连接。
X8的第一起始信号输入端与X6的进位信号输出端STV_NN+2连接。
X8的第二起始信号输入端与第九级移位寄存器单元的进位信号输出端STV_NN+4连接。
X1的栅极驱动信号输出端标示为OUT_N；X2的栅极驱动信号输出端标示为OUT_N+1；X3的栅极驱动信号输出端标示为OUT_N+2；X4的栅极驱动信号输出端标示为OUT_N+3；X5的栅极驱动信号输出端标示为OUT_N+4；X6的栅极驱动信号输出端标示为OUT_N+5；X7的栅极驱动信号输出端标示 为OUT_N+6；X8的栅极驱动信号输出端标示为OUT_N+7。
如图12所示，第二左侧时钟信号CK2L比第一左侧时钟信号CK1L延迟一个时间单元，第三左侧时钟信号CK3L比第二左侧时钟信号CK2L延迟一个时间单元，第四左侧时钟信号CK4L比第三左侧时钟信号CK3L延迟一个时间单元。
第二右侧时钟信号CK2R比第一右侧时钟信号CK1R延迟一个时间单元，第三右侧时钟信号CK3R比第二右侧时钟信号CK2R延迟一个时间单元，第四右侧时钟信号CK4R比第三右侧时钟信号CK3R延迟一个时间单元。
第一右侧时钟信号CK1R比第一左侧时钟信号CK1L延迟0.5个时间单元。
所有的时钟信号的占空比都为0.25，所有的时钟信号持续为高电平的时间为一个时间单元。
图12中绘制出了X1-X8的栅极驱动信号输出端的输出信号波形图，由图12可知，相邻级移位寄存器单元输出的栅极驱动信号之间依次延迟0.5个时间单元，即上一级移位寄存器单元还在输出高电平的栅极驱动信号的时候相邻下一级移位寄存器单元就已经开始预充电并输出栅极驱动信号，从而降低了整个栅极驱动电路的功耗。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元；偶数级移位寄存器单元设置于显示面板左侧，奇数级移位寄存器单元设置于显示面板右侧；其中，
第8n-7级移位寄存器单元的第二时钟信号输入端接入第一右侧时钟信号；
第8n-5级移位寄存器单元的第二时钟信号输入端接入第二右侧时钟信号；
第8n-7级移位寄存器单元的第一时钟信号输入端接入第三右侧时钟信号；
第8n-5级移位寄存器单元的第一时钟信号输入端接入第四右侧时钟信号；
第8n-6级移位寄存器单元的第二时钟信号输入端接入第一左侧时钟信号；
第8n-4级移位寄存器单元的第二时钟信号输入端接入第二左侧时钟信号；
第8n-6级移位寄存器单元的第一时钟信号输入端接入第三左侧时钟信号；
第8n-4级移位寄存器单元的第一时钟信号输入端接入第四左侧时钟信号；
第8n-3级移位寄存器单元的第二时钟信号输入端接入第三右侧时钟信号；
第8n-1级移位寄存器单元的第二时钟信号输入端接入第四右侧时钟信号；
第8n-3级移位寄存器单元的第一时钟信号输入端接入第一右侧时钟信号；
第8n-1级移位寄存器单元的第一时钟信号输入端接入第二右侧时钟信号；
第8n-2级移位寄存器单元的第二时钟信号输入端接入第三左侧时钟信号；
第8n级移位寄存器单元的第二时钟信号输入端接入第四左侧时钟信号；
第8n-2级移位寄存器单元的第一时钟信号输入端接入第一左侧时钟信号；
第8n-级移位寄存器单元的第一时钟信号输入端接入第二左侧时钟信号；
n为正整数。
第二左侧时钟信号比第一左侧时钟信号延迟一个时间单元，第三左侧时钟信号比第二左侧时钟信号延迟一个时间单元，第四左侧时钟信号比第三左侧时钟信号延迟一个时间单元。
第二右侧时钟信号比第一右侧时钟信号延迟一个时间单元，第三右侧时钟信号比第二右侧时钟信号延迟一个时间单元，第四右侧时钟信号比第三右侧时钟信号延迟一个时间单元。
第一左侧时钟信号比第一右侧时钟信号延迟0.5个时间单元。
所有的时钟信号的占空比都为0.25，所有的时钟信号持续为高电平的时间为一个时间单元。
除了左侧第一行移位寄存器单元之外，左侧每一行移位寄存器单元的第一进位信号输入端都与左侧相邻上一行移位寄存器单元的进位信号输出端连接。
除了右侧第一行移位寄存器单元之外，右侧每一行移位寄存器单元的第一进位信号输入端都与右侧相邻上一行移位寄存器单元的进位信号输出端连接。
除了左侧最后一行移位寄存器单元之外，左侧每一行移位寄存器单元的第二进位信号输入端都与左侧相邻下一行移位寄存器单元的进位信号输出端连接。
除了右侧最后一行移位寄存器单元之外，右侧每一行移位寄存器单元的第二进位信号输入端都与右侧相邻下一行移位寄存器单元的进位信号输出端连接。
本公开该实施例所述的栅极驱动电路与本公开如图11所示的栅极驱动电路的具体实施例的区别在于：偶数级移位寄存器单元设置于显示面板的左侧，奇数级移位寄存器单元设置于显示面板的右侧；本公开该实施例所述栅极驱动电路工作过程与本公开如图11所示的栅极驱动电路的具体实施例相同，也是上一级移位寄存器单元还在输出高电平的栅极驱动信号的时候相邻下一级移位寄存器单元就已经开始预充电并输出栅极驱动信号，从而可以降低整个栅极驱动电路的功耗。
本公开实施例所述的显示装置包括显示面板和上述的栅极驱动电路。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种移位寄存器单元，包括栅极驱动信号输出端、进位信号输出端、第一时钟信号输入端和进位信号输入端，所述移位寄存器单元还包括：
    第一上拉节点控制单元，与上拉节点和所述进位信号输入端连接；
    第二上拉节点控制单元，与所述上拉节点连接，并与所述第一时钟信号输入端连接，用于在下拉保持阶段在第一时钟信号的控制下控制所述上拉节点的电位为第一电平；
    第一下拉节点控制单元，与下拉节点连接，并与所述第一时钟信号输入端连接，用于在下拉保持阶段在所述第一时钟信号的控制下控制所述下拉节点的电位为第二电平；
    第二下拉节点控制单元，与所述上拉节点和所述下拉节点连接，用于在所述上拉节点的电位为第二电平时控制所述下拉节点的电位为第一电平；
    栅极驱动信号输出单元，分别与所述上拉节点、所述下拉节点和所述栅极驱动信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下控制所述栅极驱动信号输出端输出栅极驱动信号；以及，
    进位信号输出单元，分别与所述上拉节点、所述下拉节点和所述进位信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下控制所述进位信号输出端输出进位信号。
  2. 如权利要求1所述的移位寄存器单元，其中，所述第一上拉节点控制单元用于在输入阶段在进位信号的控制下控制所述上拉节点的电位为第二电平，在输出阶段维持所述上拉节点的电位为第二电平。
  3. 如权利要求1所述的移位寄存器单元，其中，所述进位信号输入端包括第一进位信号输入端和第二进位信号输入端；
    在正向扫描时，所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接；
    在反向扫描时，所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接。
  4. 如权利要求3所述的移位寄存器单元，其中，所述第一上拉节点控制 单元包括：
    第一输入模块，与所述上拉节点连接，并通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，用于当正向扫描时，在所述输入阶段在第一进位信号的控制下控制所述上拉节点的电位为第二电平；以及，
    第二输入模块，与所述上拉节点连接，并通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，用于当反向扫描时，在所述输入阶段在第二进位信号的控制下控制所述上拉节点的电位为第二电平。
  5. 如权利要求4所述的移位寄存器单元，其中，所述第一输入模块包括：第一晶体管，栅极和第一极都通过所述第一进位信号输入端与相邻上一级移位寄存器单元的进位信号输出端连接，第二极与所述上拉节点连接；
    所述第二输入模块包括：第二晶体管，栅极和第二极都通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述上拉节点连接。
  6. 如权利要求4所述的移位寄存器单元，其中，所述第一上拉节点控制单元还包括：
    第一存储电容，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；和/或
    第二存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端连接。
  7. 如权利要求1所述的移位寄存器单元，其中，在所述下拉保持阶段最开始的一段时间所述第一时钟信号为第二电平，之后每间隔预定时间所述第一时钟信号为第二电平，在该预定时间内所述第一时钟信号为第一电平。
  8. 如权利要求7所述的移位寄存器单元，还包括第二时钟信号输入端；
    其中，所述栅极驱动信号输出单元，还接入第一电平，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点的控制下控制所述栅极驱动信号输出端输出第二时钟信号，在下拉保持阶段在所述下拉节点的控制下控制所述栅极驱动信号输出端输出第一电平；
    所述进位信号输出单元，还接入第一电平，并与所述第二时钟信号输入端连接，用于在输入阶段、输出阶段和下拉阶段在所述上拉节点的控制下控制所述进位信号输出端输出所述第二时钟信号，在下拉保持阶段在所述下拉节点的控制下控制所述进位信号输出端输出第一电平；
    在所述输入阶段和所述下拉阶段，所述第二时钟信号为第一电平；在所述输出阶段，所述第二时钟信号为第二电平。
  9. 如权利要求8所述的移位寄存器单元，其中，所述第一时钟信号的占空比和所述第二时钟信号的占空比都为0.25；
    所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持续的时间都为一个时间单元；
    所述第一时钟信号比所述第二时钟信号延迟两个时间单元。
  10. 如权利要求9所述的移位寄存器单元，其中，所述预定时间为三个时间单元。
  11. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第一电平为低电平，所述第二电平为高电平；或者，
    所述第一电平为高电平，所述第二电平为低电平。
  12. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第二上拉节点控制单元还与所述下拉节点连接，还用于当所述下拉节点的电位为第二电平时控制所述上拉节点的电位为第一电平。
  13. 如权利要求12所述的移位寄存器单元，其中，所述第二上拉节点控制单元包括：
    第三晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接，第二极接入第一电平；以及，
    第四晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极接入第一电平。
  14. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第一下拉节点控制单元包括：第五晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉节点连接。
  15. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中， 所述第二下拉节点控制单元，还与相邻下一级移位寄存器单元的进位信号输出端连接，还用于当所述相邻下一级移位寄存器单元的进位信号输出端输出第二电平时，控制所述下拉节点的电位为第一电平。
  16. 如权利要求15所述的移位寄存器单元，其中，所述第二下拉节点控制单元包括：
    第六晶体管，栅极通过所述第二进位信号输入端与相邻下一级移位寄存器单元的进位信号输出端连接，第一极与所述下拉节点连接，第二极接入第一电平；以及，
    第七晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极接入第一电平。
  17. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述栅极驱动信号输出单元包括：
    第一栅极驱动信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
    第二栅极驱动信号输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入第一电平；
    所述进位信号输出单元包括：
    第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述进位信号输出端连接；以及，
    第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极接入第一电平。
  18. 一种移位寄存器单元的驱动方法，包括：
    在输入阶段，第二下拉节点控制单元在上拉节点的控制下控制下拉节点的电位为第一电平，第一上拉节点控制单元控制所述上拉节点的电位为第二电平；
    在输出阶段，所述第一上拉节点控制单元控制所述上拉节点的电位维持为第二电平，所述第二下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
    在下拉阶段，所述上拉节点的电位维持为第二电平，所述第二下拉节点 控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平；
    在下拉保持阶段，所述第二上拉节点控制单元在第一时钟信号的控制下控制所述上拉节点的电位为第一电平，所述第一下拉节点控制单元在所述第一时钟信号的控制下控制所述下拉节点的电位为第二电平。
  19. 如权利要求18所述的移位寄存器单元的驱动方法，其中，在输入阶段，所述第一上拉节点控制单元控制所述上拉节点的电位为第二电平步骤包括：
    当正向扫描时，所述第一上拉节点控制单元在所述第一进位信号的控制下控制所述上拉节点的电位为第二电平，所述第一进位信号为相邻上一级移位寄存器单元输出的进位信号；
    当反向扫描时，所述第一上拉节点控制单元在所述第二进位信号的控制下控制所述上拉节点的电位为第二电平，所述第二进位信号为相邻下一级移位寄存器单元输出的进位信号。
  20. 如权利要求18或19所述的移位寄存器单元的驱动方法，还包括：在所述上拉节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号。
  21. 如权利要求20所述的移位寄存器单元的驱动方法，其中，所述在所述上拉节点和所述下拉节点的控制下，栅极驱动信号输出单元控制栅极驱动信号输出端输出栅极驱动信号，进位信号输出单元控制所述进位信号输出端输出进位信号步骤包括：
    在输入阶段、输出阶段和下拉阶段，所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端输出第二时钟信号；所述进位信号输出单元在所述上拉节点的控制下控制进位信号输出端输出所述第二时钟信号；
    在下拉保持阶段，所述栅极驱动信号输出单元在所述下拉节点的控制下控制所述栅极驱动信号输出端输出第一电平，所述进位信号输出单元在所述下拉节点的控制下控制所述进位信号输出端输出第一电平；
    在所述输入阶段和所述下拉阶段，所述第二时钟信号为第一电平；在所 述输出阶段，所述第二时钟信号为第二电平。
  22. 如权利要求21所述的移位寄存器单元的驱动方法，其中，所述第一时钟信号的占空比和所述第二时钟信号的占空比都为0.25；
    所述输入阶段持续的时间、所述输出阶段持续的时间和所述下拉阶段持续的时间都为一个时间单元；
    所述第一时钟信号比所述第二时钟信号延迟两个时间单元。
  23. 一种栅极驱动电路，包括多级如权利要求1至13中任一权利要求所述的移位寄存器单元；
    奇数行移位寄存器单元设置于显示面板左侧，偶数行移位寄存器单元设置于显示面板右侧；或者，
    偶数行移位寄存器单元设置于显示面板左侧，奇数行移位寄存器单元设置于显示面板右侧。
  24. 一种栅极驱动电路，包括多级移位寄存器单元；
    第8n-7级移位寄存器单元的第二时钟信号输入端接入第一左侧时钟信号或第一右侧时钟信号；
    第8n-5级移位寄存器单元的第二时钟信号输入端接入第二左侧时钟信号或第二右侧时钟信号；
    第8n-7级移位寄存器单元的第一时钟信号输入端接入第三左侧时钟信号或第三右侧时钟信号；
    第8n-5级移位寄存器单元的第一时钟信号输入端接入第四左侧时钟信号或第四右侧时钟信号；
    第8n-6级移位寄存器单元的第二时钟信号输入端接入第一右侧时钟信号或第一左侧时钟信号；
    第8n-4级移位寄存器单元的第二时钟信号输入端接入第二右侧时钟信号或第二左侧时钟信号；
    第8n-6级移位寄存器单元的第一时钟信号输入端接入第三右侧时钟信号或第三左侧时钟信号；
    第8n-4级移位寄存器单元的第一时钟信号输入端接入第四右侧时钟信号或第四左侧时钟信号；
    第8n-3级移位寄存器单元的第二时钟信号输入端接入第三左侧时钟信号或第三右侧时钟信号；
    第8n-1级移位寄存器单元的第二时钟信号输入端接入第四左侧时钟信号或第四右侧时钟信号；
    第8n-3级移位寄存器单元的第一时钟信号输入端接入第一左侧时钟信号或第一右侧时钟信号；
    第8n-1级移位寄存器单元的第一时钟信号输入端接入第二左侧时钟信号或第二右侧时钟信号；
    第8n-2级移位寄存器单元的第二时钟信号输入端接入第三右侧时钟信号或第三左侧时钟信号；
    第8n级移位寄存器单元的第二时钟信号输入端接入第四右侧时钟信号或第四左侧时钟信号；
    第8n-2级移位寄存器单元的第一时钟信号输入端接入第一右侧时钟信号或第一左侧时钟信号；
    第8n级移位寄存器单元的第一时钟信号输入端接入第二右侧时钟信号或第二左侧时钟信号；
    n为正整数；
    第二左侧时钟信号比第一左侧时钟信号延迟一个时间单元，第三左侧时钟信号比第二左侧时钟信号延迟一个时间单元，第四左侧时钟信号比第三左侧时钟信号延迟一个时间单元；
    第二右侧时钟信号比第一右侧时钟信号延迟一个时间单元，第三右侧时钟信号比第二右侧时钟信号延迟一个时间单元，第四右侧时钟信号比第三右侧时钟信号延迟一个时间单元；
    第一右侧时钟信号比第一左侧时钟信号延迟0.5个时间单元；
    所有的时钟信号的占空比都为0.25，所有的时钟信号持续为第一电平的时间为三个时间单元，所有的时钟信号持续为第二电平的时间为一个时间单元；
    除了左侧第一行移位寄存器单元之外，左侧每一行移位寄存器单元的第一进位信号输入端都与左侧相邻上一行移位寄存器单元的进位信号输出端连 接；
    除了右侧第一行移位寄存器单元之外，右侧每一行移位寄存器单元的第一进位信号输入端都与右侧相邻上一行移位寄存器单元的进位信号输出端连接；
    除了左侧最后一行移位寄存器单元之外，左侧每一行移位寄存器单元的第二进位信号输入端都与左侧相邻下一行移位寄存器单元的进位信号输出端连接；
    除了右侧最后一行移位寄存器单元之外，右侧每一行移位寄存器单元的第二进位信号输入端都与右侧相邻下一行移位寄存器单元的进位信号输出端连接。
  25. 一种显示装置，包括显示面板和如权利要求23或24所述的栅极驱动电路。
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