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WO2017008345A1 - 薄膜晶体管、薄膜晶体管的制造方法及显示装置 - Google Patents

薄膜晶体管、薄膜晶体管的制造方法及显示装置 Download PDF

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WO2017008345A1
WO2017008345A1 PCT/CN2015/085737 CN2015085737W WO2017008345A1 WO 2017008345 A1 WO2017008345 A1 WO 2017008345A1 CN 2015085737 W CN2015085737 W CN 2015085737W WO 2017008345 A1 WO2017008345 A1 WO 2017008345A1
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layer
oxide
film transistor
thin film
gate
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PCT/CN2015/085737
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English (en)
French (fr)
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李文辉
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深圳市华星光电技术有限公司
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Priority to US14/905,802 priority Critical patent/US20170170330A1/en
Publication of WO2017008345A1 publication Critical patent/WO2017008345A1/zh

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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H10D62/864—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO further characterised by the dopants
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Definitions

  • the present invention claims the priority of the prior application entitled “Thin-film transistor, method of manufacturing a thin film transistor and display device”, which is incorporated by reference in its entirety. In this article.
  • the present invention relates to the field of manufacturing thin film transistors, and in particular to a thin film transistor, a method of manufacturing a thin film transistor, and a display device.
  • Oxide thin film transistors use an oxide semiconductor as an active layer, which has the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity, and can be applied to applications requiring fast response and large current. Such as high frequency, high resolution, large size display and organic light emitting display.
  • the thin film transistor in the prior art includes a gate line and a gate, a semiconductor layer, a source and a drain, a passivation layer, a pixel electrode, and the like.
  • a thin film transistor structure in which a source/drain electrode layer composed of a conventional metal material having a low resistance value and an oxide semiconductor film are directly contacted in a manufacturing process it is easy to form a contact surface between the source/drain electrode layer and the oxide semiconductor film.
  • the phenomenon of the special base junction affects the conductivity of the thin film transistor.
  • the present invention provides a method of manufacturing a thin film transistor, which avoids the formation of a Schottky junction at the contact surface of the source/drain electrode layer and the oxide semiconductor film, and ensures the performance of the thin film transistor.
  • the invention also provides a thin film transistor and a display device
  • the present invention provides a method of fabricating a thin film transistor, the method of manufacturing the thin film transistor comprising:
  • oxide conductor layer orthographically projected on the gate electrode on the gate insulating layer; wherein the oxide conductor layer is formed by physical vapor deposition;
  • the insulating protective layer is patterned on the substrate and the patterned second metal layer.
  • the plasma surface treatment uses a mixture of argon and oxygen.
  • the material of the oxide conductor layer is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide (ZnSnO) having an oxygen content of between 0 and 20%.
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • InZnO indium zinc oxide
  • ZnSnO zinc tin oxide
  • the method of manufacturing the thin film transistor further comprises forming an orthographic projection on the gate insulating layer a step of the second oxide channel layer of the gate; wherein the second oxide channel layer is between the gate and the oxide conductor layer, and the second oxide channel layer is orthographically projected Oxide conductor layer.
  • the material of the second oxide channel layer is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide with an oxygen content of 4%-50%. (ZnSnO).
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • InZnO indium zinc oxide
  • ZnSnO zinc tin oxide with an oxygen content of 4%-50%.
  • the method for manufacturing a thin film transistor further includes the step of patterning the insulating protective layer by an insulating protective layer formed on the substrate and the patterned second metal layer.
  • the gate insulating layer and the insulating protective layer are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • oxide layer overlying the gate insulating layer and directly above the gate, the oxide layer including an oxide channel layer and oxide conductors on opposite sides of the oxide channel layer Floor; as well as
  • a source and a drain are disposed on the compound conductor layer on opposite sides of the gate insulating layer and the oxide channel layer, and the source and the drain are electrically insulated from each other.
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • oxide layer covering directly over the second oxide channel layer, the oxide layer including a first oxide channel layer and oxides on opposite sides of the first oxide channel layer Conductor layer;
  • a source and a drain are disposed on the oxide conductor layer on opposite sides of the gate insulating layer and the first oxide channel layer, and the source and the drain are electrically insulated from each other.
  • the present invention provides a display device including the thin film transistor described above.
  • an oxide conductor layer having a small oxygen content is formed on the gate insulating layer to be in contact with the source and the drain, thereby ensuring good electrical contact between the source and the drain and the oxide conductor layer.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 to FIG. 8 are schematic cross-sectional views showing a thin film transistor in each manufacturing process of a thin film transistor method according to a preferred embodiment of the present invention.
  • FIG. 9 is a flow chart showing a method of fabricating a thin film transistor according to another preferred embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view showing a thin film transistor formed by the method of manufacturing the thin film transistor of FIG. Figure.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor belongs to an oxide semiconductor structure transistor.
  • the patterning refers to a patterning process, which may include a photolithography process, or a photolithography process and an etching step, and may also include printing, Other processes for forming a predetermined pattern such as inkjet;
  • a photolithography process refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the manufacturing method of the manufacturing method of the thin film transistor includes the following steps.
  • a substrate 10 is provided.
  • the substrate 10 is a glass substrate. It can be understood that in other embodiments, the substrate 10 is not limited to a glass substrate.
  • a first metal layer (not shown) is formed on the substrate 10, and the first metal 12 layer is patterned by a patterning process to include a pattern including the gate electrode 12.
  • the first metal layer is formed on one surface of the substrate 10 to serve as the gate electrode 12 of the thin film transistor 10.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the gate electrode 12 is patterned by patterning the first metal layer by a prior art patterning process such as photoresisting, exposure, and development.
  • a gate insulating layer 13 is formed on the substrate 10 and the patterned first metal layer, and the gate insulating layer 13 covers the surface of the substrate 10 and the gate. Specifically, the gate insulating layer 130 is formed on a surface of the substrate 10 not covering the first metal layer and on the gate electrode 12.
  • the material of the gate insulating layer 13 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • step S4 an oxide conductor layer 14 orthographically projected on the gate electrode 12 is formed on the gate insulating layer 13; wherein the oxide conductor layer 14 is formed by physical vapor deposition.
  • the material of the oxide conductor layer 14 is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide with an oxygen content of 0 to 20%. (ZnSnO).
  • the oxide conductor layer 14 is made of indium gallium zinc oxide (IGZO) having an oxygen content of 0-%10.
  • step S5 a second metal layer (not shown) is formed on the substrate of the gate insulating layer 13, and the second metal layer is patterned to form the source 15 of the thin film transistor.
  • the second metal layer and the oxide conductor layer 14 and the gate insulating layer 13 are sequentially stacked.
  • the second metal layer is patterned by a prior art patterning process to form source 15 and drain 16 as shown.
  • the material of the second metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the oxide conductor layer 14 that is not covered between the source 15 and the drain 16 and located between the source 15 and the drain 16 is subjected to plasma surface treatment to make the uncovered source 15
  • a first oxide channel layer 17 is formed with the oxide conductor layer 14 of the drain 16.
  • the oxide conductor layer 14 after the plasma surface treatment is used to form a channel that is turned on or off between the source 15 and the drain 16 of the thin film transistor.
  • the plasma surface treatment uses a mixture of argon gas and oxygen gas for the purpose of oxygen-repairing the portion of the oxide conductor layer 14 between the uncovered source 15 and the drain 16 between the source 15 and the drain 16.
  • the first oxide channel layer 17 is used for a channel that is turned on or off between the source 15 and the drain 16.
  • the underlying oxide conductor layer 14 forms a good ohmic contact with the first oxide channel layer 17, with low blocking, enabling the source 15 to pass through the first oxide channel layer 17 to the drain 16 well. Power-on performance.
  • the material of the second metal layer is generally a metal material.
  • the present invention is not limited thereto.
  • the material of the second metal layer may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or A stacked layer of metallic material and other conductive materials.
  • step S7 the insulating protective layer 19 is patterned on the substrate 10 and the patterned second metal layer (source 15 and drain 16) to pattern the insulating protective layer 19. .
  • the gate insulating layer 13 and the insulating protective layer 19 are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy). Up to this step, the thin film transistor manufacturing method in this embodiment is completed.
  • the gate insulating layer 13 and the insulating protective layer 19 are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • an oxide conductor layer 14 having a small oxygen content is formed on the gate insulating layer 13 to be in contact with the source 15 and the drain electrode 16, and the source 15 and the drain 16 and the oxide conductor layer 14 are secured.
  • an oxide channel layer having a high oxygen content that is, an oxide, is formed in a portion where the uncovered oxide conductor layer 14 is located between the source 15 and the drain 16 by plasma surface treatment.
  • the semiconductor layer achieves good electrical conductivity of the transistor.
  • the present invention also relates to a thin film transistor, comprising: a gate electrode, a gate insulating layer covering the gate; an oxide layer overlying the gate insulating layer and located at the Directly above the gate, the oxide layer includes an oxide channel layer and a compound conductor layer on opposite sides of the oxide channel layer; and a source and a drain located in the gate insulating layer
  • the oxide channel layer is on opposite sides of the compound conductor layer, and the source and the drain are electrically insulated from each other.
  • the method for manufacturing the thin film transistor further includes the step S3A, the gate insulating layer 13 in step S3 and step S4. a step of forming a second oxide channel layer 18 that is projected onto the gate electrode 12; wherein the second oxide channel layer 18 is between the gate electrode 12 and the oxide conductor layer 14, and The second oxide channel layer 18 is projected onto the oxide conductor layer 14.
  • the source 15 and the drain 16 are in partial contact with the oxide conductor layer 14 on both sides of the first oxide channel layer 17, respectively, the first oxide channel layer 17 and the second oxide trench
  • the track layers 18 collectively form the channel of the transistor.
  • the material of the second oxide channel layer 18 is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc oxide with an oxygen content of 4%-50%. Tin (ZnSnO).
  • the material of the second oxide channel layer 170 is preferably made of indium gallium zinc oxide (IGZO) having an oxygen content of between 5% and 200%.
  • the present invention further provides a thin film transistor including a gate, a gate insulating layer covering the gate, and a second oxide channel layer. Covering the gate insulating layer and directly above the gate; an oxide layer covering the gate insulating layer and directly above the gate, the oxide layer including a first oxide a channel layer and a compound conductor layer on opposite sides of the first oxide channel layer; and a source and a drain on opposite sides of the gate insulating layer and the first oxide channel layer On the oxide conductor layer, and the source and the drain are electrically insulated from each other.
  • the present invention also includes the display device of the thin film transistor of the above two modes.
  • the display device formed by the method for manufacturing the thin film transistor of the embodiment of the present invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, or an electronic paper. , digital photo frames, mobile phones, etc.

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Abstract

一种薄膜晶体管的制造方法，其包括在基板（10）上形成第一金属层，通过构图工艺使第一金属层形成包括栅极（12）的图案；在上述基板（10）及第一金属层上形成栅极绝缘层（13），栅极绝缘层（13）覆盖所述基板（10）的表面及所述栅极（12）；在所述栅极绝缘层（13）上形成正投影于所述栅极（12）的氧化物导体层（14）；在形成栅极绝缘层（13）的基板（10）上形成第二金属层，图案化所述第二金属层，形成所述薄膜晶体管的源极（15）及漏极（16），其中，所述源极（15）和漏极（16）均覆盖部分所述氧化物导体层（14）；对未覆盖源极（15）与漏极（16）且位于源极（15）与漏极（16）之间的氧化物导体层（14）进行等离子表面处理，使所述未覆盖源极（15）与漏极（16）的氧化物导体层（14）形成第一氧化物沟道层（17）；在所述基板（10）及所述图案化的第二金属层上形成的绝缘保护层（19），对所述绝缘保护层（19）进行图案化。

Description

薄膜晶体管、薄膜晶体管的制造方法及显示装置
本发明要求2015年7月16日递交的发明名称为“薄膜晶体管、薄膜晶体管的制造方法及显示装置”的申请号201510420701.5的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种薄膜晶体管、薄膜晶体管的制造方法及显示装置。
背景技术
目前广泛应用的Oxide薄膜晶体管采用氧化物半导体作为有源层，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。现有技术中薄膜晶体管包括栅线及栅极，半导体层，源漏极，钝化层及像素电极等。当在制造过程中采用惯用的电阻值低的金属材料构成的源漏电极层和氧化物半导体膜来直接接触的薄膜晶体管结构时，容易在源漏电极层和氧化物半导体膜的接触面形成肖特基结的现象，影响薄膜晶体管的导电性能。
发明内容
本发明提供一种薄膜晶体管的制造方法，避免在源漏电极层和氧化物半导体膜的接触面形成肖特基结的现象，保证薄膜晶体管性能。
本发明还提供一种薄膜晶体管及显示装置
本发明提供一种薄膜晶体管的制造方法，所述薄膜晶体管的制造方法包括：
提供一基板；
在所述基板上形成第一金属层，通过构图工艺使第一金属层形成包括栅极的图案；
在上述基板及第一金属层上形成栅极绝缘层，栅极绝缘层覆盖所述基板的表面及所述栅极；
在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层；其中，所述氧化物导体层采用物理气相沉积方式形成；
在形成栅极绝缘层的基板上形成第二金属层，图案化所述第二金属层，形成所述薄膜晶体管的源极及漏极，其中，所述源极和漏极均覆盖部分所述氧化物导体层；
对未覆盖源极与漏极且位于源极与漏极之间的氧化物导体层进行等离子表面处理，使所述未覆盖源极与漏极的氧化物导体层形成第一氧化物沟道层；
在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化。
其中，所述等离子表面处理采用氩气与氧气混合体。
其中，所述氧化物导体层的材料为含氧量在0至20％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
其中，在步骤“在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层”之前，所述薄膜晶体管的制造方法还包括在所述栅极绝缘层上形成正投影于所述栅极的第二氧化物沟道层的步骤；其中，所述第二氧化物沟道层位于栅极与所述氧化物导体层之间，并且第二氧化物沟道层正投影于氧化物导体层。
其中，所述第二氧化物沟道层的材料为含氧量为4％-50％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
其中，所述的薄膜晶体管的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化的步骤。
其中，所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
本发明提供一种薄膜晶体管，所述薄膜晶体管包括：
一栅极；
一栅绝缘层，覆盖所述栅极；
一氧化物层，覆盖于所述栅绝缘层上且位于所述栅极正上方，所述氧化物层包括一氧化物沟道层以及位于所述氧化物沟道层相对两侧的氧化物导体层； 以及
一源极与一漏极，位于所述栅绝缘层与所述氧化物沟道层相对两侧的化物导体层上，且所述源极与所述漏极彼此电性绝缘。
本发明提供一种薄膜晶体管，所述薄膜晶体管包括：
一栅极；
一栅绝缘层，覆盖所述栅极；
一第二氧化物沟道层，覆盖于所述栅绝缘层上且位于所述栅极正上方；
一氧化物层，覆盖于所述第二氧化物沟道层正上方，所述氧化物层包括一第一氧化物沟道层以及位于所述第一氧化物沟道层相对两侧的氧化物导体层；以及
一源极与一漏极，位于所述栅绝缘层与所述第一氧化物沟道层相对两侧的氧化物导体层上，且所述源极与所述漏极彼此电性绝缘。
本发明提供一种显示装置，其包括以上所述的薄膜晶体管。
本发明本发明的薄膜晶体管的制造方法在栅极绝缘层上形成含氧量少的氧化物导体层与源极和漏极接触，保证源极和漏极与氧化物导体层良好电性接触，在通过等离子表面处理方式将未被覆盖的氧化物导体层位于所述源极和漏极之间的部分形成含氧量高的氧化物沟道层，即氧化物半导体层，实现晶体管的良好的导电性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。
图2至图8为本发明较佳实施方式的薄膜晶体管方法的各个制造流程中薄膜晶体管的截面示意图。
图9为本发明另一较佳实施方式的薄膜晶体管的制造方法的流程图。
图10为图9所述的薄膜晶体管的制造方法的形成的薄膜晶体管截面示意 图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，其为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。所述薄膜晶体管属于氧化物半导体结构晶体管。在阐述具体制备方法之前，应所述理解，在本发明中，所述图案化即是指构图工艺，可包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影，等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
所述薄膜晶体管的制造方法制造方法包括如下步骤。
步骤S1，提供一基板10。请一并参阅图2，在本实施方式中，所述基板10为一玻璃基板。可以理解地，在其他实施方式中，所述基板10并不仅限于为玻璃基板。
请一并参阅图3，步骤S2，在所述基板10上形成第一金属层(图未示)，通过构图工艺使第一金属12层形成包括栅极12的图案；具体的，在所述基板10的一表面上形成所述第一金属层，以作为所述薄膜晶体管10的栅极12。所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。本实施方式中通过现有技术的涂光阻、曝光、显影等构图工艺对所述第一金属层图案化形成栅极12。
请一并参阅图4，步骤S3，在上述基板10及图案化的第一金属层上形成栅极绝缘层13，栅极绝缘层13覆盖所述基板10的表面及所述栅极。具体的在所述基板10未覆盖所述第一金属层的表面及所述栅极12上形成所述栅极绝缘层130。所述栅极绝缘层13的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
请一并参阅图5，步骤S4，在所述栅极绝缘层13上形成正投影于所述栅极12的氧化物导体层14；其中，所述氧化物导体层14采用物理气相沉积方式形成。本实施例中，所述氧化物导体层14的材料为含氧量在0至20％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。优选的，所述所述氧化物导体层14采用含氧量0-％10的氧化铟镓锌(IGZO)。
请一并参阅图6，步骤S5，在成型栅极绝缘层13的基板上形成第二金属层(图未示)，图案化所述第二金属层，形成所述薄膜晶体管的源极15及漏极16，其中，所述源极15和漏极16均覆盖部分所述氧化物导体层14。
具体的，所述第二金属层与所述氧化物导体层14及所述栅极绝缘层13依次层叠设置。通过现有技术的构图工艺对所述第二金属层进行图案化形成如图所示的源极15和漏极16。所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
请一并参阅图7，步骤S6，对未覆盖源极15与漏极16且位于源极15与漏极16之间的氧化物导体层14进行等离子表面处理，使所述未覆盖源极15与漏极16的氧化物导体层14形成第一氧化物沟道层17。
其中，通过进行等离子表面处理后的所述氧化物导体层14用于形成所述薄膜晶体管的源极15和漏极16之间导通或者断开的通道。所述等离子表面处理是采用氩气与氧气混合体，目的是将位于源极15与漏极16之间的未覆盖源极15与漏极16的氧化物导体层14部分进行补氧修复，形成含氧量较高的氧化物半导体，即所述的第一氧化物沟道层17。本实施例中，所述第一氧化物沟道层17用于源极15和漏极16之间导通或者断开的通道。所述第一氧化物沟道层17两侧分别与所述源极15及漏极16接触的氧化物导体层14部分相当于欧姆接触层的作用，源极15和漏极16可分别通过位于其下的氧化物导体层14与第一氧化物沟道层17形成一良好的欧姆接触(ohmic contact)，具有低阻止，实现源极15通过第一氧化物沟道层17到漏极16良好的通电性能。
本实施例中，第二金属层的材料一般是金属材料。但，本发明不限于此，在其他实施例中，第二金属层的材料也可以使用其他导电材料，如合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或是金属材料与其它导材料的堆叠层。
请参阅图8，步骤S7，在所述基板10及所述图案化的第二金属层(源极15和漏极16)上形成的绝缘保护层19，对所述绝缘保护层19进行图案化。所述栅极绝缘层13与所述绝缘保护层19采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。到此步骤，本实施例中的薄膜晶体管制造方法完成。
进一步的，所述栅极绝缘层13与所述绝缘保护层19采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
本发明的薄膜晶体管的制造方法在栅极绝缘层13上形成含氧量少的氧化物导体层14与源极15和漏极16接触，保证源极15和漏极16与氧化物导体层14良好电性接触，在通过等离子表面处理方式将未被覆盖的氧化物导体层14位于所述源极15和漏极16之间的部分形成含氧量高的氧化物沟道层，即氧化物半导体层，实现晶体管的良好的导电性能。
针对上述薄膜晶体管制造方法，本发明还涉及一种薄膜晶体管，其包括一栅极，一栅绝缘层，覆盖所述栅极；一氧化物层，覆盖于所述栅绝缘层上且位于所述栅极正上方，所述氧化物层包括一氧化物沟道层以及位于所述氧化物沟道层相对两侧的化物导体层；以及一源极与一漏极，位于所述栅绝缘层与所述氧化物沟道层相对两侧的化物导体层上，且所述源极与所述漏极彼此电性绝缘。
请参阅图9，本发明的另一实施例中，与上述方法不同的在于，在步骤S3与步骤S4之间，所述薄膜晶体管的制造方法还包括在步骤S3A，所述栅极绝缘层13上形成正投影于所述栅极12的第二氧化物沟道层18的步骤；其中，所述第二氧化物沟道层18位于栅极12与所述氧化物导体层14之间，并且第二氧化物沟道层18正投影于氧化物导体层14。所述源极15及漏极16分别与所述第一氧化物沟道层17两侧的氧化物导体层14部分接触，所述所述第一氧化物沟道层17与第二氧化物沟道层18共同构成所述晶体管的沟道。
其中，所述第二氧化物沟道层18的材料为含氧量为4％-50％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。本实施例中，优选的所述第二氧化物沟道层170的材料为含氧量为5％-200％之间的氧化铟镓锌(IGZO)制成。
请参阅图10，针对本实施方式的薄膜晶体管的制造方法本发明还提供一种薄膜晶体管，其包括一栅极，一栅绝缘层，覆盖所述栅极；一第二氧化物沟道层，覆盖于所述栅绝缘层上且位于所述栅极正上方；一氧化物层，覆盖于所述栅绝缘层上且位于所述栅极正上方，所述氧化物层包括一第一氧化物沟道层以及位于所述第一氧化物沟道层相对两侧的化物导体层；以及一源极与一漏极，位于所述栅绝缘层与所述第一氧化物沟道层相对两侧的氧化物导体层上，且所述源极与所述漏极彼此电性绝缘。
本发明还包括以上两个方式的薄膜晶体管的显示装置，通过本发明实施例薄膜晶体管的制造方法形成的显示装置，可以为：液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、手机等。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管的制造方法，其中，所述薄膜晶体管的制造方法包括：
    提供一基板；
    在所述基板上形成第一金属层，通过构图工艺使第一金属层形成包括栅极的图案；
    在上述基板及第一金属层上形成栅极绝缘层，栅极绝缘层覆盖所述基板的表面及所述栅极；
    在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层；其中，所述氧化物导体层采用物理气相沉积方式形成；
    在形成栅极绝缘层的基板上形成第二金属层，图案化所述第二金属层，形成所述薄膜晶体管的源极及漏极，其中，所述源极和漏极均覆盖部分所述氧化物导体层；
    对未覆盖源极与漏极且位于源极与漏极之间的氧化物导体层进行等离子表面处理，使所述未覆盖源极与漏极的氧化物导体层形成第一氧化物沟道层；
    在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化。
  2. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述等离子表面处理采用氩气与氧气混合体。
  3. 如权利要求2所述的薄膜晶体管的制造方法，其中，所述氧化物导体层的材料为含氧量在0至20％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
  4. 如权利要求1所述的薄膜晶体管的制造方法，其中，在步骤“在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层”之前，所述薄膜晶体管的制造方法还包括在所述栅极绝缘层上形成正投影于所述栅极的第二氧化物沟道层的步骤；其中，所述第二氧化物沟道层位于栅极与所述氧化物导体层之间，并且第二氧化物沟道层正投影于氧化物导体层。
  5. 如权利要求4所述的薄膜晶体管的制造方法，其中，所述第二氧化物沟道层的材料为含氧量为4％-50％之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、 氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
  6. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述的薄膜晶体管的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化的步骤。
  7. 如权利要求6所述的薄膜晶体管的制造方法，其中，所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
  8. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    一栅极；
    一栅绝缘层，覆盖所述栅极；
    一氧化物层，覆盖于所述栅绝缘层上且位于所述栅极正上方，所述氧化物层包括一氧化物沟道层以及位于所述氧化物沟道层相对两侧的氧化物导体层；以及
    一源极与一漏极，位于所述栅绝缘层与所述氧化物沟道层相对两侧的化物导体层上，且所述源极与所述漏极彼此电性绝缘。
  9. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    一栅极；
    一栅绝缘层，覆盖所述栅极；
    一第二氧化物沟道层，覆盖于所述栅绝缘层上且位于所述栅极正上方；
    一氧化物层，覆盖于所述第二氧化物沟道层正上方，所述氧化物层包括一第一氧化物沟道层以及位于所述第一氧化物沟道层相对两侧的氧化物导体层；以及
    一源极与一漏极，位于所述栅绝缘层与所述第一氧化物沟道层相对两侧的氧化物导体层上，且所述源极与所述漏极彼此电性绝缘。
  10. 一种显示装置，其包括权利要求8或权利要求9所述的薄膜晶体管。
PCT/CN2015/085737 2015-07-16 2015-07-31 薄膜晶体管、薄膜晶体管的制造方法及显示装置 WO2017008345A1 (zh)

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