[go: up one dir, main page]

WO2016191993A1 - 一种模拟预失真apd校正系统及方法 - Google Patents

一种模拟预失真apd校正系统及方法 Download PDF

Info

Publication number
WO2016191993A1
WO2016191993A1 PCT/CN2015/080442 CN2015080442W WO2016191993A1 WO 2016191993 A1 WO2016191993 A1 WO 2016191993A1 CN 2015080442 W CN2015080442 W CN 2015080442W WO 2016191993 A1 WO2016191993 A1 WO 2016191993A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
coefficient
error
apd
delay
Prior art date
Application number
PCT/CN2015/080442
Other languages
English (en)
French (fr)
Inventor
叶四清
尤览
曹斌
朱尔霓
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201580000955.XA priority Critical patent/CN106664269B/zh
Priority to PCT/CN2015/080442 priority patent/WO2016191993A1/zh
Publication of WO2016191993A1 publication Critical patent/WO2016191993A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present invention relates to the field of communications, and in particular, to an analog predistortion correction system and method.
  • PA Power Amplifier
  • PA Power Amplifier
  • PA is an amplifier that amplifies signal power and is often used in the field of communications.
  • the power of the PA to be transmitted is often amplified by the PA.
  • the signal to be transmitted after being amplified by the PA is distorted, which affects the communication quality.
  • the DPD Digital Pre-Distortion
  • APD Analog Pre-Distortion
  • the prior art APD correction system includes a pass-through/delay module 101, a core module 102, a feedforward receiver 103, a feedback receiver 104, and a training module 105, wherein:
  • the through/delay module 101 receives the system input signal, directly outputs the system input signal, or delays the system input signal to obtain a delay signal output;
  • the core module 102 receives the system input signal and the APD coefficient output by the training module 105, and generates a predistortion signal output according to the system input signal and the APD coefficient; a mixed signal of the output signal of the through/delay module 101 and the output signal of the core module 102. That is, the input signal of the PA, and the PA performs power amplification on the mixed signal and outputs it;
  • the feedforward receiver 103 receives the system input signal, performs down-conversion, analog-to-digital conversion processing, and obtains a feedforward digital signal output to the training module 105;
  • the feedback receiver 104 receives the output signal of the PA, performs down-conversion, analog-to-digital conversion processing, and obtains a feedback digital signal output to the training module 105;
  • the training module 105 receives the feedforward digital signal output from the feedforward receiver 103 and the feedback receiver 104.
  • the output feedback digital signal determines the APD coefficient based on the feedforward digital signal and the feedback digital signal, and outputs to the core module 102.
  • Embodiments of the present invention provide an APD correction system and method, which are easier to implement.
  • an APD correction system including a core unit, a gain adjustment unit, an error generation unit, and a training unit, wherein:
  • the core unit is configured to receive a system input signal and an APD coefficient output by the training unit; delaying the input signal of the system to obtain N delay signals with different delays, wherein one delay signal is used as a feedforward a signal is output to the error generating unit, N is an integer not less than 1; and an input signal of the power amplifier PA is obtained according to the system input signal, the N-channel delayed delay signal, and the APD coefficient, A part of the output signal of the PA is coupled as a feedback signal;
  • the gain adjustment unit is configured to receive the feedback signal, adjust a gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit;
  • the error generating unit is configured to receive a feedforward signal output by the core unit and a feedback adjustment signal output by the gain adjustment unit, generate an error signal of the feedforward signal and the feedback adjustment signal, and output the An error signal to the training unit;
  • the training unit is configured to receive an error signal output by the error generating unit, determine the APD coefficient according to the error signal, and output the APD coefficient to the core unit.
  • the training unit includes a variable gain amplifier, a power detector, an analog-to-digital converter, and a coefficient training module, where:
  • variable gain amplifier is configured to adjust a gain of the error signal to obtain an error adjustment signal
  • the power detector is configured to detect an average power of the error adjustment signal, and obtain Error power signal
  • the analog-to-digital converter is configured to perform analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error power digital signal.
  • the training unit includes a receiver and a coefficient training module, where:
  • the receiver is configured to perform down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error digital signal.
  • the core unit includes N delays , a nonlinear module, M digital vector modulators, and an adder, the APD coefficients including a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N +1, wherein:
  • the N delay devices are connected in series for delaying the input signals of the system to obtain delay signals of N different delays;
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal, the N-channel delay signal with different delays, and the nonlinear coefficient;
  • the M digital vector modulators wherein one digital vector modulator is used as a post digital vector modulator, and the other M-1 digital vector modulators are used as front digital vector modulators; the system input signal and the N path are different.
  • the N+1 signals composed of the delayed signals one signal is used as the center delay signal, and the other N signals are used as the non-center delay signal;
  • the M linear coefficients one linear coefficient and the adder Corresponding to the output signal, the other M-1 linear coefficients and the M-1 non-central delay signals in the N non-central delay signals are in one-to-one correspondence; each pre-digital vector modulator performs the M-1 path non-center Multiplication of a non-central delay signal in the delayed signal with a corresponding linear coefficient;
  • the adder performs the nonlinear predistortion signal, the center delay signal, and M-1 Addition of the output signal of the former digital vector modulator;
  • the post digital vector modulator performs multiplication of the output signal of the adder with a corresponding linear coefficient to obtain an input signal of the PA.
  • the core unit includes N delays , a nonlinear module, M digital vector modulators, and an adder, the APD coefficients including a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N +1, wherein:
  • the N delay devices are connected in series for delaying the input signals of the system to obtain delay signals of N different delays;
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal, the N-channel delay signal with different delays, and the nonlinear coefficient;
  • the M digital vector modulators wherein one digital vector modulator acts as a central digital vector modulator, and the other M-1 digital vector modulators act as non-center digital vector modulators;
  • the system input signal is different from the N path Among the N+1 signals composed of the delayed delay signals, one signal is used as the center delay signal, and the other N signals are used as the non-center delay signal;
  • the central digital vector modulator performs the central delay signal and corresponding a multiplication operation of a linear coefficient, each non-central digital vector modulator performing a multiplication operation of a non-central delay signal of the M-1 way non-center delay signal and a corresponding linear coefficient;
  • the adder performs addition of the nonlinear predistortion signal and the output signals of the M digital vector modulators to obtain an input signal of the PA.
  • an APD correction method including:
  • N is an integer not less than 1;
  • a part of the output signal of the PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal; one of the N delay signals is used as a feedforward signal to generate the feedforward And an error signal of the feedback adjustment signal; determining the APD coefficient based on the error signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error power digital signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and an M Linear coefficients, 1 ⁇ M ⁇ N+1;
  • an input signal of the PA according to the input signal of the system, the delay signal of the N different delays, and the APD coefficient, specifically including:
  • one linear coefficient other than the M-1 linear coefficients corresponds to the output signal of the addition; the multiplication of the output signal of the addition and the corresponding linear coefficient is performed to obtain a PA Input signal.
  • the APD coefficient includes a nonlinear coefficient and an M Linear coefficients, 1 ⁇ M ⁇ N+1;
  • an input signal of the PA according to the input signal of the system, the delay signal of the N different delays, and the APD coefficient, specifically including:
  • the addition of the nonlinear predistortion signal and the M multiplication output signals is performed to obtain an input signal of the PA.
  • an APD correction system including a core unit, a gain adjustment unit, an error generation unit, and a training unit, wherein:
  • the core unit is configured to receive a system input signal and an APD coefficient output by the training unit, and obtain an input signal of the power amplifier PA according to the system input signal and the APD coefficient, and a part of the PA output signal is coupled as a Feedback signal;
  • the gain adjustment unit is configured to receive the feedback signal, adjust a gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit;
  • the error generating unit is configured to receive the system input signal and the gain adjusting unit Outputting a feedback adjustment signal, the system input signal as a feedforward signal, generating an error signal of the feedforward signal and the feedback adjustment signal, and outputting the error signal to the training unit;
  • the training unit is configured to receive an error signal output by the error generating unit, determine the APD coefficient according to the error signal, and output the APD coefficient to the core unit.
  • the training unit includes a variable gain amplifier, a power detector, an analog-to-digital converter, and a coefficient training module, where:
  • variable gain amplifier is configured to adjust a gain of the error signal to obtain an error adjustment signal
  • the power detector is configured to detect an average power of the error adjustment signal to obtain an error power signal
  • the analog-to-digital converter is configured to perform analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error power digital signal.
  • the training unit includes a receiver and a coefficient training module, where:
  • the receiver is configured to perform down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error digital signal.
  • the core unit includes a nonlinear module, A digital vector modulator and an adder, the APD coefficients comprising a nonlinear coefficient and a linear coefficient, wherein:
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal and the nonlinear coefficient;
  • the adder performs an addition operation of the nonlinear predistortion signal and the system input signal
  • the digital vector modulator performs multiplication of the output signal of the adder with the linear coefficient to obtain an input signal of the PA.
  • the core unit includes a nonlinear module, A digital vector modulator and an adder, the APD coefficients comprising a nonlinear coefficient and a linear coefficient, wherein:
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal and the nonlinear coefficient;
  • the digital vector modulator performing a multiplication operation of the system input signal and the linear coefficient
  • the adder performs addition of the nonlinear predistortion signal and an output signal of the digital vector modulator to obtain an input signal of the PA.
  • an APD correction method including:
  • a part of the output signal of the power amplifier PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal;
  • the system input signal is used as a feedforward signal to generate an error signal of the feedforward signal and the feedback adjustment signal;
  • An input signal of the PA is obtained based on the system input signal and the APD coefficient.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error power digital signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient
  • the output signal of the addition is multiplied by the linear coefficient to obtain an input signal of the PA.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient
  • the nonlinear predistortion signal and the addition of the multiplied output signal are performed to obtain an input signal of the PA.
  • the core unit receiving system input signal, and the APD coefficient output by the training unit Delaying the input signal of the system to obtain delay signals of N different delays, wherein one delay signal is output as a feedforward signal to the error generating unit, and according to the system input signal, N different delayed delay signals And the APD coefficient, the input signal of the PA is obtained, and a part of the output signal of the PA is coupled as a feedback signal;
  • the gain adjustment unit receives the feedback signal, adjusts the gain of the feedback signal, and obtains a feedback adjustment signal, and And outputting the feedback adjustment signal to the error generation unit;
  • the error generation unit receives the delay signal output by the core unit and the feedback adjustment signal output by the gain adjustment unit, generates an error signal of the feedforward signal and the feedback adjustment signal, and outputs the error signal to the training a unit;
  • the training unit receives an error signal output by
  • FIG. 1 is a schematic structural view of an APD correction system in the prior art
  • FIG. 2 is a schematic structural diagram of an APD correction system according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure
  • FIG. 4 is a second schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present invention.
  • FIG. 5 is a third schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 6 is a fourth schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 7 is a fifth schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a nonlinear module in a core unit of an APD correction system according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a digital vector modulator in a core unit of an APD correction system according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an APD correction system according to Embodiment 1 of the present invention.
  • FIG. 11 is a schematic structural diagram of an APD correction system according to Embodiment 2 of the present invention.
  • FIG. 12 is a schematic structural diagram of a quadrature demodulator in a training unit of an APD correction system according to Embodiment 2 of the present invention.
  • FIG. 13 is a schematic flowchart of an APD correction method according to an embodiment of the present disclosure.
  • FIG. 14 is a second schematic structural diagram of an APD correction system according to an embodiment of the present disclosure.
  • FIG. 15 is a sixth structural diagram of a core unit in an APD correction system according to an embodiment of the present invention.
  • FIG. 16 is a second schematic flowchart of an APD correction method according to an embodiment of the present invention.
  • an embodiment of the present invention provides an APD correction system and method.
  • the preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used. The invention is illustrated and described, and is not intended to limit the invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
  • An embodiment of the present invention provides an APD correction system, as shown in FIG. 2, which may include a core unit 201, a gain adjustment unit 202, an error generation unit 203, and a training unit 204, where:
  • the core unit 201 is configured to receive the system input signal and the APD coefficient output by the training unit 204; delay the system input signal to obtain N delay signals of different delays, wherein one of the delay signals is output as a feedforward signal to the error
  • the generating unit 203, N is an integer not less than 1; and according to the system input signal, the N-channel delay signal and the APD coefficient, the PA input signal is obtained, the PA amplifies the input signal, and the PA output signal is coupled. Part of it as a feedback signal;
  • the gain adjustment unit 202 is configured to receive a feedback signal, adjust the gain of the feedback signal, obtain a feedback adjustment signal, that is, the adjusted feedback signal, and output the feedback adjustment signal to the error generation unit 203;
  • the error generating unit 203 is configured to receive the feedforward signal output by the core unit 201 and the feedback adjustment signal output by the gain adjustment unit 202, and generate an error signal of the feedforward signal and the feedback adjustment signal. And outputting the error signal to the training unit 204;
  • the training unit 204 is configured to receive an error signal output by the error generating unit 203, determine an APD coefficient according to the error signal, and output the APD coefficient to the core unit 201.
  • the training unit 204 adjusts the linear characteristic and the nonlinear characteristic of the core unit 201 by adjusting the APD coefficient, so that the error signal is as close as possible to zero, that is, the feedback adjustment signal is consistent with the feedforward signal, that is, the PA output signal is made.
  • the PA phase predistortion is achieved by the amplitude and phase modulation information of the input signal of the system, that is, the amplitude and phase of the signal change with time.
  • the core unit 201 has multiple implementation manners, for example:
  • the core unit 201 includes N delays, nonlinear modules, M DVM (Digital Vector Modulator) and adder, and the APD coefficients include nonlinear coefficients and M linear coefficients, 1 ⁇ M ⁇ N+ 1, where:
  • N delay devices are connected in series for delaying the input signal of the system to obtain delayed signals of N different delays;
  • a nonlinear module for generating a nonlinear predistortion signal according to a system input signal, N delay signals of different delays, and nonlinear coefficients;
  • M DVMs one of which is the central DVM, and the other M-1 DVMs are used as non-central digital vector modulators; one of the N+1 signals consisting of the system input signal and the N delay signals with different delays The center delay signal, the other N signals are used as the non-center delay signal; among the M linear coefficients, one linear coefficient corresponds to the center delay signal, and the other M-1 linear coefficients and N of the N non-central delay signals -1 way non-center delay signal one-to-one correspondence; central DVM multiplies the center delay signal and corresponding linear coefficient, and each non-center DVM performs one non-center delay signal in the M-1 non-center delay signal Multiplication with corresponding linear coefficients;
  • the adder performs addition of the nonlinear predistortion signal and the output signals of the M DVMs to obtain an input signal of the PA.
  • the core unit 201 implemented by the mode 1 is as shown in FIG. 3, At this time, the delay signal with the largest delay relative to the input signal of the system can be selected as the feedforward signal.
  • the core unit 201 can also use two adders, a first adder and a second adder, the first adder performs the addition of the output signals of the M DVMs, and the second adder performs the nonlinear predistortion signal,
  • the addition of the output signal of the first adder, and the connection between the first adder and the second adder via the buffer amplifier Buf, can prevent the interference of the feedforward signal caused by the forward leakage of the output signal of the core unit 201.
  • the feedback adjustment signal is consistent with the feedforward signal by adjusting the APD coefficient. Therefore, the feedforward signal is substantially a learning template signal of the feedback adjustment signal, and the feedforward signal is deteriorated by the interference. System performance.
  • the core unit 201 shown in FIG. 3 is as shown in FIG.
  • the core unit 201 includes N delays, nonlinear modules, M DVMs, and adders.
  • the APD coefficients include nonlinear coefficients and M linear coefficients, 1 ⁇ M ⁇ N +1, where:
  • N delay devices are connected in series for delaying the input signal of the system to obtain delayed signals of N different delays;
  • a nonlinear module for generating a nonlinear predistortion signal according to a system input signal, N delay signals of different delays, and nonlinear coefficients;
  • M DVMs one of which is the latter DVM, the other M-1 DVMs are used as the front DVM; among the N+1 signals consisting of the system input signal and the N delay signals with different delays, one signal is used as the center delay signal.
  • the other N signals are used as non-center delay signals; among the M linear coefficients, one linear coefficient corresponds to the output signal of the adder, and the other M-1 linear coefficients and the M-1 road in the N non-central delay signals
  • the non-central delay signals are in one-to-one correspondence; each pre-DVM performs multiplication of a non-central delay signal in the M-1 way non-center delay signal with a corresponding linear coefficient;
  • An adder that performs addition of a nonlinear predistortion signal, a center delay signal, and an output signal of M-1 pre-DVMs;
  • the post DVM performs multiplication of the output signal of the adder with the corresponding linear coefficient to obtain an input signal of the PA.
  • the DVM at the output end can adjust the power level of the signal, so that the output signal of the core unit 201 is adapted to the power level requirements of the input signals of different PAs.
  • the selection of the center delay signal and the feedforward signal may follow the following principle: the sum of the delay length of the center delay signal relative to the system input signal and the delay length of the PA is approximately equal to the former The length of the delay of the feed signal relative to the system input signal.
  • the delay length of the center delay signal relative to the system input signal may be approximately half of the delay length of the delay signal with the largest delay relative to the system input signal; after selecting the center delay signal, The above principle determines which delay signal is selected as the feedforward signal.
  • the feedforward signal can be determined first and then the center delay signal is determined, which is not limited herein.
  • the core unit 201 implemented by the second method includes two delays, a nonlinear module, three DVMs, and an adder, as shown in FIG. 5;
  • the delay length of the device 1 is equal to the delay length of the delay device 2 equal to the delay length of the PA, and the two delay devices are connected in series to delay the input signal of the system to obtain two delay signals with different delays;
  • the delay signal outputted by the delay device 1 is used as the center delay signal, and the delay signal outputted by the delay device 2 is used as the feedforward signal and also as the non-central delay signal;
  • the nonlinear module is different according to the system input signal and the 2 way.
  • the delayed delay signal and the nonlinear coefficient generate a nonlinear predistortion signal; in 3 DVMs, DVM0 is used as the post DVM, DVM1 and DVM2 are used as the front DVM; DVM1 is used to multiply the system input signal and the linear coefficient 1, and DVM2 is extended.
  • the delay signal output by the timer 2 is multiplied by the linear coefficient 2; the adder performs the addition of the nonlinear predistortion signal, the delay signal outputted by the delayer 1, the output signal of the DVM1, and the output signal of the DVM2; DVM3 Perform the output signal of the adder with a linear coefficient of 3 Calculation method, the input signal to obtain the PA.
  • the core unit 201 can also use two adders, a first adder and a second adder, the first adder performs the addition of the center delay signal and the output signals of the N pre-DVMs, and the second adder performs the second adder.
  • the nonlinear predistortion signal, the addition of the output signal of the first adder, and the first adder and the second adder are connected by the buffer amplifier Buf, which can prevent the output signal of the core unit 201 from leaking forward. The interference of the feedforward signal.
  • the core unit 201 shown in FIG. 5 is as shown in FIG. 6.
  • the core unit 201 implemented by the second method is as shown in FIG. 7, and includes one delay device, a nonlinear module, two DVMs, and an adder;
  • the delay signal output by the timer is used as the feedforward signal, and the system input signal is used as the center delay signal, and the delay signal output by the delay device is used as the non-center delay signal.
  • the specific structure and modified structure are not described in detail herein.
  • the number N of delay devices may be an odd number or an even number; the delay lengths of the N delay devices may be different or the same.
  • the number of specific delays and the length of the delay can be set based on actual needs, which is not limited herein.
  • N delay devices may also be connected in other manners, as long as N delay signals with different delays can be obtained, N delay devices Any connection method can be used. For example, multiple delays can be used in series to obtain multiple delay signals with different delays. One of the delay signals is used as the center delay signal, and a special delay device is used to delay the input signal of the system to generate feedforward. The signal, or a dedicated delayer, delays one of the multiple delayed signals of different delays to generate a feedforward signal.
  • the non-linear module may specifically include the envelope submodule 801 and the action matrix submodule 802, as shown in FIG.
  • the envelope sub-module 801 is configured to receive the input signal of the system, perform envelope detection on the input signal of the system, obtain an input envelope signal of different delays of the L channel, and output the input envelope signal of the L delay with different delays to the function.
  • the matrix sub-module 802; L is an integer not less than 1, and may be equal to N or may be equal to N;
  • the action matrix sub-module 802 is configured to receive N delay signals of different delays, input envelope signals of different delays of L channels, and nonlinear coefficients, according to different delayed delay signals of the N channels, and different delays of the L paths
  • the input envelope signal and the nonlinear coefficient form a nonlinear predistortion signal.
  • envelope sub-module 801 and the action matrix sub-module 802 are prior art and will not be described in detail herein.
  • the DVM may be implemented by using the structure shown in FIG. 9, including a QPS (Quadrature Phase Splitter), a subtractor, and
  • QPS Quadrature Phase Splitter
  • each of the above linear coefficients is a complex coefficient
  • the real part of the complex coefficient is the in-phase coefficient shown in FIG. 9
  • the imaginary part of the complex coefficient is the orthogonal coefficient shown in FIG. 9, specifically:
  • One multiplier of the two multipliers performs multiplication of the in-phase signal and the in-phase coefficient of the QPS output; the other multiplier performs multiplication of the orthogonal signal of the QPS output and the orthogonal coefficient;
  • the subtracter performs a subtraction of the output signals of the two multipliers; the output signal of the subtractor is the output signal of the DVM.
  • the gain adjustment unit 202 can be implemented by a VGA (Variable Gain Amplifier), and the gain of the VGA is related to the gain of the output signal of the system input signal to the PA, so the actual implementation
  • the gain of the VGA can be configured according to the gain requirement of the system input signal to the output signal of the PA.
  • the error generating unit 203 may be implemented by a subtractor that performs a subtraction operation of the feedforward signal and the feedback adjustment signal, that is, an error signal of the feedforward signal and the feedback adjustment signal.
  • the training unit 204 also has various implementation manners, which will be described in detail below with reference to the accompanying drawings.
  • the core unit 201 may be implemented in the foregoing manner, or may be implemented in the foregoing manner; the gain adjustment unit 202 may be implemented by using a VGA; and the error generation unit 203 may be implemented.
  • the subtraction unit is implemented; the training unit 204 determines the APD coefficient according to the power of the error signal output by the error generating unit 203.
  • the training unit 204 may include a VGA, a PDET (Power Detector), and an ADC (Analog to Digital). Converter, analog to digital converter) and coefficient training module, where:
  • VGA for receiving an error signal, adjusting the gain of the error signal to obtain an error adjustment signal, and outputting the error adjustment signal to the PDET;
  • the PDET is configured to receive an error adjustment signal of the VGA output, detect an average power of the error adjustment signal, obtain an error power signal, and output the error power signal to the ADC;
  • the ADC is configured to receive an error power signal output by the PDET, perform analog-to-digital conversion on the error power signal, obtain an error power digital signal, and output the error power digital signal to the coefficient training module;
  • the coefficient training module is configured to receive an error power digital signal output by the ADC, and determine an APD coefficient according to the error power digital signal, so that the error power digital signal approaches 0.
  • the coefficient training module can perform AGC (Automatic Gain Control) on the VGA to control the gain of the VGA, thereby controlling the adjustment range of the gain of the error signal, so that the error power signal input by the ADC is always close to the ADC.
  • AGC Automatic Gain Control
  • the size of the signal is good for coefficient training.
  • the APD correction system provided by Embodiment 1 of the present invention does not require a receiver; the ADC in the training unit 204 performs analog-to-digital conversion on the error power signal, and since the error power signal is a signal that changes slowly with time, the ADC is Low performance requirements are not only easy to implement, but also greatly reduce system cost.
  • the core unit 201 may be implemented in the foregoing manner, or may be implemented in the foregoing manner; the gain adjustment unit 202 may be implemented by using a VGA; and the error generation unit 203 may be implemented.
  • a subtractor implementation; training unit 204 which can include a receiver and a coefficient training module, wherein:
  • the receiver is configured to receive an error signal, perform down-conversion and analog-to-digital conversion processing on the error signal, obtain an error digital signal, and output the error digital signal to the coefficient training module;
  • the coefficient training module is configured to receive an error digital signal output by the receiver, and determine an APD coefficient according to the error digital signal, so that the error digital signal approaches 0.
  • the above receiver may specifically be in the form shown in FIG. 11, including a VGA, a QDM (Quadrature Demodulator), and two ADCs, and the coefficient training module performs AGC on the VGA in the receiver; wherein:
  • VGA adjusts the gain of the input signal of the receiver
  • QDM performs down-conversion processing on the output signal of the VGA
  • the two ADCs respectively perform analog-to-digital conversion processing on the two output signals of the QDM; the output signals of the two ADCs are the output signals of the receiver.
  • the QDM structure in Figure 11 is shown in Figure 12, including a -90° phase shifter, two multipliers, and two LPFs (Low-Pass Filters), where:
  • the -90° phase shifter performs a -90° phase shift on the local oscillator signal to obtain a local oscillator signal after phase shifting;
  • One of the two multipliers performs multiplication of the QDM input signal and the local oscillator signal; the other multiplier performs multiplication of the QDM input signal and the phase-shifted local oscillator signal;
  • the two LPFs respectively filter the output signals of the two multipliers; the output signals of the two LPFs are the output signals of the QDM.
  • receivers may also be other types of receivers in the prior art, which are not limited by the present invention.
  • Embodiment 2 of the present invention With the APD correction system provided by Embodiment 2 of the present invention, only one receiver is needed, which is easier to implement and lowers the system cost than the prior art.
  • the APD correction system according to the above embodiment of the present invention, correspondingly, the embodiment of the present invention further provides an APD correction method, which is shown in FIG.
  • Step 1301 delaying the input signal of the system to obtain a delay signal of N different delays, where N is an integer not less than 1;
  • Step 1302 Obtain an input signal of the power amplifier PA according to the input signal of the system, the delayed signal of the N different delays, and the APD coefficient; wherein the APD coefficient is determined as follows:
  • a part of the output signal of the PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal; a delay signal in the N-way delay signal is used as a feedforward signal to generate a feedforward signal and a feedback adjustment signal.
  • the error signal based on the error signal, the APD coefficient is determined.
  • generating an error signal of the feedforward signal and the feedback adjustment signal that is, performing a feedforward signal And the feedback adjustment signal is subtracted, and the obtained signal is the error signal of the feedforward signal and the feedback adjustment signal.
  • determining the APD coefficient according to the error signal may specifically include:
  • the APD coefficient is determined based on the power of the error signal.
  • determining the APD coefficient according to the power of the error signal may specifically include:
  • Adjusting the gain of the error signal to obtain an error adjustment signal ; detecting an average power of the error adjustment signal to obtain an error power signal; performing analog-to-digital conversion on the error power signal to obtain an error power digital signal; A digital signal that determines the APD coefficient.
  • determining the APD coefficient according to the error signal may specifically include:
  • the error signal is subjected to down-conversion and analog-to-digital conversion processing to obtain an error digital signal; and the APD coefficient is determined according to the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N+1; and step 1302 is based on the system input signal, the N-channel delayed delay signal, and the APD.
  • the coefficient obtains the input signal of the PA, and specifically includes:
  • a nonlinear predistortion signal according to the input signal of the system, the delay signal of the N different delays, and the nonlinear coefficient; the N+1 path formed by the input signal of the system and the delay signal of the N different delays In the signal, one signal is used as the center delay signal, and the other N signals are used as the non-central delay signal; among the M linear coefficients, M-1 linear coefficients and M-1 non-center delay signals
  • the central delay signals are in one-to-one correspondence; performing multiplication of each non-central delay signal in the M-1 way non-center delay signal with a corresponding linear coefficient; performing the nonlinear predistortion signal, the center delay signal, Addition of output signals of M-1 multiplication operations; among the M linear coefficients, a linear coefficient other than the M-1 linear coefficients corresponds to an output signal of the addition; an output signal of the addition operation is performed Corresponding to the multiplication of the linear coefficients, the input signal of the PA is obtained.
  • the APD coefficient includes a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N+1; and step 1302 is based on the input signal of the system and the delay of the N different delays.
  • the time signal and the APD coefficient are used to obtain an input signal of the PA, which may specifically include:
  • N ⁇ 2 the sum of the delay length of the center delay signal relative to the system input signal and the delay length of the PA is substantially equal to the delay length of the feedforward signal relative to the system input signal.
  • processing steps in the above process may correspond to the functions of the corresponding units shown in FIG. 2 to FIG. 12, and details are not described herein again.
  • an embodiment of the present invention further provides an APD correction system, as shown in FIG. 14, which may include a core unit 1401, a gain adjustment unit 1402, an error generation unit 1403, and a training unit 1404, where:
  • the core unit 1401 is configured to receive a system input signal and an APD coefficient output by the training unit 1404, and obtain an input signal of the power amplifier PA according to the system input signal and the APD coefficient, and a part of the PA output signal is coupled as a feedback signal;
  • the gain adjustment unit 1402 is configured to receive a feedback signal, adjust the gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit 1403;
  • the error generating unit 1403 is configured to receive the system input signal and the feedback adjustment signal output by the gain adjustment unit 1402, and the system input signal is used as a feedforward signal to generate an error signal of the feedforward signal and the feedback adjustment signal, and output the error signal to the training unit 1404. ;
  • the training unit 1404 is configured to receive an error signal output by the error generating unit 1403, determine an APD coefficient according to the error signal, and output the APD coefficient to the core unit 1401.
  • the training unit 1404 which can be seen in FIG. 10, includes Variable gain amplifier, power detector, analog to digital converter and coefficient training module, wherein:
  • variable gain amplifier for adjusting the gain of the error signal to obtain an error adjustment signal
  • a power detector for detecting an average power of the error adjustment signal to obtain an error power signal
  • An analog-to-digital converter for performing analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • a coefficient training module for determining an APD coefficient based on the error power digital signal.
  • the training unit 1404 includes a receiver and a coefficient training module, wherein:
  • a receiver for performing down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • a coefficient training module for determining an APD coefficient based on the error digital signal.
  • the core unit 1401 has various implementation manners, for example:
  • the core unit 1401 includes a nonlinear module, a digital vector modulator, and an adder, and the APD coefficients include a nonlinear coefficient and a linear coefficient, wherein:
  • a nonlinear module for generating a nonlinear predistortion signal based on a system input signal and a nonlinear coefficient
  • An adder for performing addition of a nonlinear predistortion signal and a system input signal
  • the digital vector modulator performs multiplication of the output signal of the adder and the linear coefficient to obtain an input signal of the PA.
  • the core unit 1401 includes a nonlinear module, a digital vector modulator and an adder, and the APD coefficients include a nonlinear coefficient and a linear coefficient, wherein:
  • a nonlinear module for generating a nonlinear predistortion signal based on a system input signal and a nonlinear coefficient
  • the adder performs addition of the nonlinear predistortion signal and the output signal of the digital vector modulator to obtain an input signal of the PA.
  • the gain adjustment unit 1402 can be implemented by a VGA.
  • the error generating unit 1403 may be implemented by a subtractor that performs a subtraction operation of the feedforward signal and the feedback adjustment signal, that is, obtains an error of the feedforward signal and the feedback adjustment signal. signal.
  • the embodiment of the present invention further provides an APD correction method, which is shown in FIG.
  • Step 1601 A part of the output signal of the power amplifier PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal.
  • Step 1602 The system input signal is used as a feedforward signal, and the error signal of the feedforward signal and the feedback adjustment signal is generated.
  • Step 1603 determining the APD coefficient according to the error signal
  • Step 1604 Obtain an input signal of the PA according to the system input signal and the APD coefficient.
  • Step 1602 generates an error signal of the feedforward signal and the feedback adjustment signal, that is, performs subtraction of the feedforward signal and the feedback adjustment signal, and the obtained signal is an error signal of the feedforward signal and the feedback adjustment signal.
  • the step 1603 determines the APD coefficient according to the error signal, which may specifically include:
  • Adjusting the gain of the error signal to obtain an error adjustment signal adjusting the signal for the error
  • the average power is detected to obtain an error power signal; the error power signal is subjected to analog-to-digital conversion to obtain an error power digital signal; and the APD coefficient is determined according to the error power digital signal.
  • the step 1603 determines the APD coefficient according to the error signal, which may specifically include:
  • the error signal is subjected to down-conversion and analog-to-digital conversion processing to obtain an error digital signal; and the APD coefficient is determined according to the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient; and the step 1604 obtains an input signal of the PA according to the input signal of the system and the APD coefficient, which may specifically include:
  • the APD coefficient includes a non-linear coefficient and a linear coefficient.
  • the input signal of the PA is obtained according to the input signal of the system and the APD coefficient, which may specifically include:
  • processing steps in the above process may correspond to the functions of the corresponding units shown in FIG. 14 to FIG. 15, and details are not described herein again.
  • the APD correction scheme provided by the embodiment of the present invention is easier to implement and has lower cost.
  • the coefficient training module of the training unit can be implemented by a digital circuit (including an optional AGC part), and other parts are implemented by using an analog circuit.
  • the APD correction scheme provided in any of the above embodiments may be applied to a system that requires APD, such as a mobile communication system, a wireless transmission system, or a radar system.
  • APD correction The scheme can be, but is not limited to, applied to a base station in a mobile communication system.
  • the embodiment of the invention further provides a base station, including any one of the above APD correction systems.
  • the signal to be transmitted that needs to be power amplified is used as the system input signal of the APD correction system, and the APD correction system generates the input signal of the PA. Since the distortion generated by the PA is corrected by the APD correction system, the output signal of the PA is relatively The input signal of the system has no distortion, that is, the signal to be transmitted after power amplification has no distortion, and the communication quality is ensured.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in a block or blocks of a flow or a flow and/or a block diagram of a flowchart Step.

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

一种APD校正系统及方法，易于实现。该系统包括核心单元、增益调整单元、误差生成单元和训练单元，其中：核心单元，对系统输入信号进行延时，得到N路不同延时的延时信号，其中一路延时信号作为前馈信号输出至误差生成单元，N为不小于1的整数；以及根据系统输入信号、N路不同延时的延时信号和APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；增益调整单元，对反馈信号的增益进行调整，得到反馈调整信号，并输出反馈调整信号至误差生成单元；误差生成单元，生成前馈信号和反馈调整信号的误差信号，并输出误差信号至训练单元；训练单元，根据误差信号，确定APD系数，并输出APD系数至核心单元。

Description

一种模拟预失真APD校正系统及方法 技术领域
本发明涉及通信领域，特别涉及一种模拟预失真校正系统及方法。
背景技术
PA(Power Amplifier，功率放大器)是一种对信号功率进行放大的放大器，常常应用在通信领域中。例如，在移动通信系统的基站中，常常使用PA对待发射信号的功率进行放大，但是，由于PA存在放大失真的问题，使得经过PA放大后的待发射信号存在失真，影响了通信质量。
为了保证通信质量，目前通常都采用DPD(Digital Pre-Distortion，数字预失真)系统对PA产生的失真进行校正，以消除经过PA放大后的信号存在的失真。但是有些场景，更加适合采用APD(Analog Pre-Distortion，模拟预失真)系统对PA产生的失真进行校正，以消除经过PA放大后的信号存在的失真。
现有技术中的APD校正系统如图1所示，包括直通/延时模块101、核心模块102、前馈接收机103、反馈接收机104和训练模块105，其中：
直通/延时模块101，接收系统输入信号，直接输出系统输入信号，或者对系统输入信号进行延时，得到一路延时信号输出；
核心模块102，接收系统输入信号以及训练模块105输出的APD系数，根据系统输入信号以及APD系数，生成预失真信号输出；直通/延时模块101的输出信号和核心模块102的输出信号的混合信号即为PA的输入信号，PA对该混合信号进行功率放大后输出；
前馈接收机103，接收系统输入信号，进行下变频、模数转换处理，得到前馈数字信号输出至训练模块105；
反馈接收机104，接收PA的输出信号，进行下变频、模数转换处理，得到反馈数字信号输出至训练模块105；
训练模块105，接收前馈接收机103输出的前馈数字信号和反馈接收机104 输出的反馈数字信号，根据该前馈数字信号和反馈数字信号确定APD系数，输出至核心模块102。
然而，现有技术中的APD校正系统需要两个接收机，不但成本较高，实现起来也较为复杂。
发明内容
本发明实施例提供一种APD校正系统及方法，更易于实现。
第一方面，提供一种APD校正系统，包括核心单元、增益调整单元、误差生成单元和训练单元，其中：
所述核心单元，用于接收系统输入信号以及所述训练单元输出的APD系数；对所述系统输入信号进行延时，得到N路不同延时的延时信号，其中一路延时信号作为前馈信号输出至所述误差生成单元，N为不小于1的整数；以及根据所述系统输入信号、所述N路不同延时的延时信号和所述APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；
所述增益调整单元，用于接收所述反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号，并输出所述反馈调整信号至所述误差生成单元；
所述误差生成单元，用于接收所述核心单元输出的前馈信号以及所述增益调整单元输出的反馈调整信号，生成所述前馈信号和所述反馈调整信号的误差信号，并输出所述误差信号至所述训练单元；
所述训练单元，用于接收所述误差生成单元输出的误差信号，根据所述误差信号，确定所述APD系数，并输出所述APD系数至所述核心单元。
结合第一方面，在第一种可能的实现方式中，所述训练单元，包括可变增益放大器、功率检测器、模数转换器和系数训练模块，其中：
所述可变增益放大器，用于对所述误差信号的增益进行调整，得到误差调整信号；
所述功率检测器，用于对所述误差调整信号的平均功率进行检测，得到 误差功率信号；
所述模数转换器，用于对所述误差功率信号进行模数转换，得到误差功率数字信号；
所述系数训练模块，用于根据所述误差功率数字信号，确定所述APD系数。
结合第一方面，在第二种可能的实现方式中，所述训练单元，包括接收机和系数训练模块，其中：
所述接收机，用于对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
所述系数训练模块，用于根据所述误差数字信号，确定所述APD系数。
结合第一方面，第一方面的第一种可能的实现方式，或者第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述核心单元，包括N个延时器、非线性模块、M个数字矢量调制器和加法器，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
所述N个延时器串联，用于对所述系统输入信号进行延时，得到N路不同延时的延时信号；
所述非线性模块，用于根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
所述M个数字矢量调制器，其中一个数字矢量调制器作为后数字矢量调制器，其它M-1个数字矢量调制器作为前数字矢量调制器；所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述加法器的输出信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；每个前数字矢量调制器进行所述M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
所述加法器，进行所述非线性预失真信号、所述中心延时信号、M-1个 前数字矢量调制器的输出信号的加法运算；
所述后数字矢量调制器进行所述加法器的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
结合第一方面，第一方面的第一种可能的实现方式，或者第一方面的第二种可能的实现方式，在第四种可能的实现方式中，所述核心单元，包括N个延时器、非线性模块、M个数字矢量调制器和加法器，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
所述N个延时器串联，用于对所述系统输入信号进行延时，得到N路不同延时的延时信号；
所述非线性模块，用于根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
所述M个数字矢量调制器，其中一个数字矢量调制器作为中心数字矢量调制器，其它M-1个数字矢量调制器作为非中心数字矢量调制器；所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；所述中心数字矢量调制器进行所述中心延时信号与对应线性系数的乘法运算，每个非中心数字矢量调制器进行所述M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
所述加法器，进行所述非线性预失真信号、所述M个数字矢量调制器的输出信号的加法运算，得到PA的输入信号。
第二方面，提供一种APD校正方法，包括：
对系统输入信号进行延时，得到N路不同延时的延时信号，N为不小于1的整数；
根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到功率放大器PA的输入信号；其中，所述APD系数采用如下方式确定：
PA的输出信号中耦合出一部分作为反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号；所述N路延时信号中的一路延时信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号；根据所述误差信号，确定所述APD系数。
结合第二方面，在第一种可能的实现方式中，根据所述误差信号，确定所述APD系数，具体包括：
对所述误差信号的增益进行调整，得到误差调整信号；
对所述误差调整信号的平均功率进行检测，得到误差功率信号；
对所述误差功率信号进行模数转换，得到误差功率数字信号；
根据所述误差功率数字信号，确定所述APD系数。
结合第二方面，在第二种可能的实现方式中，根据所述误差信号，确定所述APD系数，具体包括：
对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
根据所述误差数字信号，确定所述APD系数。
结合第二方面，第二方面的第一种可能的实现方式，或者第二方面的第二种可能的实现方式，在第三种可能的实现方式中，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1；
根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到PA的输入信号，具体包括：
根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行所述M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；
进行所述非线性预失真信号、所述中心延时信号、M-1个乘法运算的输 出信号的加法运算；
所述M个线性系数中，除所述M-1个线性系数以外的一个线性系数和所述加法运算的输出信号对应；进行所述加法运算的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
结合第二方面，第二方面的第一种可能的实现方式，或者第二方面的第二种可能的实现方式，在第四种可能的实现方式中，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1；
根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到PA的输入信号，具体包括：
根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行所述中心延时信号与对应线性系数的乘法运算，以及所述M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；
进行所述非线性预失真信号、M个乘法运算的输出信号的加法运算，得到PA的输入信号。
第三方面，提供一种APD校正系统，包括核心单元、增益调整单元、误差生成单元和训练单元，其中：
所述核心单元，用于接收系统输入信号以及所述训练单元输出的APD系数，根据所述系统输入信号和所述APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；
所述增益调整单元，用于接收所述反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号，并输出所述反馈调整信号至所述误差生成单元；
所述误差生成单元，用于接收所述系统输入信号以及所述增益调整单元 输出的反馈调整信号，所述系统输入信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号，并输出所述误差信号至所述训练单元；
所述训练单元，用于接收所述误差生成单元输出的误差信号，根据所述误差信号，确定所述APD系数，并输出所述APD系数至所述核心单元。
结合第三方面，在第一种可能的实现方式中，所述训练单元，包括可变增益放大器、功率检测器、模数转换器和系数训练模块，其中：
所述可变增益放大器，用于对所述误差信号的增益进行调整，得到误差调整信号；
所述功率检测器，用于对所述误差调整信号的平均功率进行检测，得到误差功率信号；
所述模数转换器，用于对所述误差功率信号进行模数转换，得到误差功率数字信号；
所述系数训练模块，用于根据所述误差功率数字信号，确定所述APD系数。
结合第三方面，在第二种可能的实现方式中，所述训练单元，包括接收机和系数训练模块，其中：
所述接收机，用于对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
所述系数训练模块，用于根据所述误差数字信号，确定所述APD系数。
结合第三方面，第三方面的第一种可能的实现方式，或者第三方面的第二种可能的实现方式，在第三种可能的实现方式中，所述核心单元，包括非线性模块、数字矢量调制器和加法器，所述APD系数包括非线性系数和线性系数，其中：
所述非线性模块，用于根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
所述加法器，进行所述非线性预失真信号、所述系统输入信号的加法运算；
所述数字矢量调制器进行所述加法器的输出信号与所述线性系数的乘法运算，得到PA的输入信号。
结合第三方面，第三方面的第一种可能的实现方式，或者第三方面的第二种可能的实现方式，在第四种可能的实现方式中，所述核心单元，包括非线性模块、数字矢量调制器和加法器，所述APD系数包括非线性系数和线性系数，其中：
所述非线性模块，用于根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
所述数字矢量调制器，进行所述系统输入信号与所述线性系数的乘法运算；
所述加法器，进行所述非线性预失真信号、所述数字矢量调制器的输出信号的加法运算，得到PA的输入信号。
第四方面，提供一种APD校正方法，包括：
功率放大器PA的输出信号中耦合出一部分作为反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号；
系统输入信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号；
根据所述误差信号，确定所述APD系数；
根据所述系统输入信号和所述APD系数，得到PA的输入信号。
结合第四方面，在第一种可能的实现方式中，根据所述误差信号，确定所述APD系数，具体包括：
对所述误差信号的增益进行调整，得到误差调整信号；
对所述误差调整信号的平均功率进行检测，得到误差功率信号；
对所述误差功率信号进行模数转换，得到误差功率数字信号；
根据所述误差功率数字信号，确定所述APD系数。
结合第四方面，在第二种可能的实现方式中，根据所述误差信号，确定所述APD系数，具体包括：
对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
根据所述误差数字信号，确定所述APD系数。
结合第四方面，第四方面的第一种可能的实现方式，或者第四方面的第二种可能的实现方式，在第三种可能的实现方式中，所述APD系数包括非线性系数和线性系数；
根据所述系统输入信号和所述APD系数，得到PA的输入信号，具体包括：
根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
进行所述非线性预失真信号、所述系统输入信号的加法运算；
进行所述加法运算的输出信号与所述线性系数的乘法运算，得到PA的输入信号。
结合第四方面，第四方面的第一种可能的实现方式，或者第四方面的第二种可能的实现方式，在第四种可能的实现方式中，所述APD系数包括非线性系数和线性系数；
根据所述系统输入信号和所述APD系数，得到PA的输入信号，具体包括：
根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
进行所述系统输入信号与所述线性系数的乘法运算；
进行所述非线性预失真信号、所述乘法运算的输出信号的加法运算，得到PA的输入信号。
根据第一方面提供的APD校正系统，第二方面提供的APD校正方法，第三方面提供的APD校正系统，第四方面提供的APD校正方法，核心单元接收系统输入信号以及训练单元输出的APD系数，对系统输入信号进行延时，得到N路不同延时的延时信号，其中一路延时信号作为前馈信号输出至误差生成单元，以及根据系统输入信号、N路不同延时的延时信号和APD系数，得到PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；增益调整单元接收反馈信号，对反馈信号的增益进行调整，得到反馈调整信号，并 输出该反馈调整信号至误差生成单元；误差生成单元接收核心单元输出的延时信号以及增益调整单元输出的反馈调整信号，生成前馈信号和反馈调整信号的误差信号，并输出该误差信号至训练单元；训练单元接收误差生成单元输出的误差信号，根据该误差信号，确定APD系数，并输出该APD系数至核心单元。显然，采用本发明实施例提供的方案，无需两个接收机便可以实现对PA的校正，不但成本较低，实现起来也更为容易。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中：
图1为现有技术中APD校正系统的结构示意图；
图2为本发明实施例提供的APD校正系统的结构示意图之一；
图3为本发明实施例提供的APD校正系统中核心单元的结构示意图之一；
图4为本发明实施例提供的APD校正系统中核心单元的结构示意图之二；
图5为本发明实施例提供的APD校正系统中核心单元的结构示意图之三；
图6为本发明实施例提供的APD校正系统中核心单元的结构示意图之四；
图7为本发明实施例提供的APD校正系统中核心单元的结构示意图之五；
图8为本发明实施例提供的APD校正系统的核心单元中非线性模块的结构示意图；
图9为本发明实施例提供的APD校正系统的核心单元中数字矢量调制器的结构示意图；
图10为本发明实施例1提供的APD校正系统的结构示意图；
图11为本发明实施例2提供的APD校正系统的结构示意图；
图12为本发明实施例2提供的APD校正系统的训练单元中正交解调器的结构示意图；
图13为本发明实施例提供的APD校正方法的流程示意图之一；
图14为本发明实施例提供的APD校正系统的结构示意图之二；
图15为本发明实施例提供的APD校正系统中核心单元的结构示意图之六；
图16为本发明实施例提供的APD校正方法的流程示意图之二。
具体实施方式
为了给出易于实现的APD校正方案，本发明实施例提供了一种APD校正系统及方法，以下结合说明书附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明实施例提供一种APD校正系统，如图2所示，可以包括核心单元201、增益调整单元202、误差生成单元203和训练单元204，其中：
核心单元201，用于接收系统输入信号以及训练单元204输出的APD系数；对系统输入信号进行延时，得到N路不同延时的延时信号，其中一路延时信号作为前馈信号输出至误差生成单元203，N为不小于1的整数；以及根据系统输入信号、N路不同延时的延时信号和APD系数，得到PA的输入信号，PA对输入信号进行放大，PA的输出信号中耦合出一部分作为反馈信号；
增益调整单元202，用于接收反馈信号，对该反馈信号的增益进行调整，得到反馈调整信号即经过调整的反馈信号，并输出该反馈调整信号至误差生成单元203；
误差生成单元203，用于接收核心单元201输出的前馈信号以及增益调整单元202输出的反馈调整信号，生成前馈信号和反馈调整信号的误差信号， 并输出该误差信号至训练单元204；
训练单元204，用于接收误差生成单元203输出的误差信号，根据该误差信号，确定APD系数，并输出该APD系数至核心单元201。
训练单元204通过调整APD系数，来实现核心单元201的线性特性与非线性特性的调整，使误差信号尽量趋近于0，即，使反馈调整信号与前馈信号一致，也就是使PA输出信号与系统输入信号的幅相调制信息即信号的幅度与相位随时间的变化特性一致，从而达成PA预失真。
本发明实施例提供的APD校正系统中，核心单元201具有多种实现方式，例如：
方式一：
核心单元201，包括N个延时器、非线性模块、M个DVM(Digital Vector Modulator，数字矢量调制器)和加法器，APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
N个延时器串联，用于对系统输入信号进行延时，得到N路不同延时的延时信号；
非线性模块，用于根据系统输入信号、N路不同延时的延时信号和非线性系数，生成非线性预失真信号；
M个DVM，其中一个DVM作为中心DVM，其它M-1个DVM作为非中心数字矢量调制器；系统输入信号和N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；M个线性系数中，一个线性系数和中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；中心DVM进行中心延时信号与对应线性系数的乘法运算，每个非中心DVM进行M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
加法器，进行非线性预失真信号、M个DVM的输出信号的加法运算，得到PA的输入信号。
例如，当N＝2、M＝N+1时，采用方式一实现的核心单元201如图3所示， 此时，可以但不限于选择相对于系统输入信号延时最大的延时信号作为前馈信号。
较佳的，核心单元201也可以采用第一加法器和第二加法器两个加法器，第一加法器进行M个DVM的输出信号的加法运算，第二加法器进行非线性预失真信号、第一加法器的输出信号的加法运算，并且，第一加法器和第二加法器之间通过缓冲放大器Buf相连，可以防止核心单元201的输出信号向前泄露造成的对前馈信号的干扰。在本发明实施例提供的APD校正系统中，要通过调整APD系数来使反馈调整信号与前馈信号一致，因此该前馈信号实质为反馈调整信号的学习范本信号，前馈信号受到干扰将恶化系统性能。
此时，图3所示的核心单元201如图4所示。
方式二：
核心单元201，包括N个延时器、非线性模块、M个DVM和加法器，APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
N个延时器串联，用于对系统输入信号进行延时，得到N路不同延时的延时信号；
非线性模块，用于根据系统输入信号、N路不同延时的延时信号和非线性系数，生成非线性预失真信号；
M个DVM，其中一个DVM作为后DVM，其它M-1个DVM作为前DVM；系统输入信号和N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；M个线性系数中，一个线性系数和加法器的输出信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；每个前DVM进行M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
加法器，进行非线性预失真信号、中心延时信号、M-1个前DVM的输出信号的加法运算；
后DVM进行加法器的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
采用方式二实现的核心单元201，输出端的DVM即后DVM可以对信号的功率电平进行调节，使核心单元201的输出信号适应不同的PA的输入信号的功率电平要求。
较佳的，当N≥2时，中心延时信号及前馈信号的选择可以遵循下述原则：中心延时信号相对于系统输入信号的延时长度与PA的延时长度之和大致等于前馈信号相对于系统输入信号的延时长度。具体实施时，中心延时信号相对于系统输入信号的延时长度可以大致为相对于系统输入信号延时最大的延时信号的延时长度的一半；在选择出中心延时信号后，再根据上述原则确定选择哪一路延时信号作为前馈信号，当然也可以先确定前馈信号再确定中心延时信号，在此不予限定。
例如，当N＝2、M＝N+1时，采用方式二实现的核心单元201如图5所示，包括2个延时器、非线性模块、3个DVM和加法器；其中：延时器1的延时长度等于延时器2的延时长度等于PA的延时长度，2个延时器串联，对系统输入信号进行延时，得到2路不同延时的延时信号；此时，延时器1输出的延时信号作为中心延时信号，延时器2输出的延时信号作为前馈信号,也为非中心延时信号；非线性模块，根据系统输入信号、2路不同延时的延时信号和非线性系数，生成非线性预失真信号；3个DVM中DVM0作为后DVM，DVM1和DVM2作为前DVM；DVM1进行系统输入信号与线性系数1的乘法运算，DVM2进行延时器2输出的延时信号与线性系数2的乘法运算；加法器，进行非线性预失真信号、延时器1输出的延时信号、DVM1的输出信号和DVM2的输出信号的加法运算；DVM3进行加法器的输出信号与线性系数3的乘法运算，得到PA的输入信号。
较佳的，核心单元201也可以采用第一加法器和第二加法器两个加法器，第一加法器进行中心延时信号、N个前DVM的输出信号的加法运算，第二加法器进行非线性预失真信号、第一加法器的输出信号的加法运算，并且，第一加法器和第二加法器之间通过缓冲放大器Buf相连，可以防止核心单元201的输出信号向前泄露造成的对前馈信号的干扰。
此时，图5所示的核心单元201如图6所示。
当N＝1、M＝N+1时，采用方式二实现的核心单元201如图7所示，包括1个延时器、非线性模块、2个DVM和加法器；此时，可以将延时器输出的延时信号作为前馈信号，将系统输入信号作为中心延时信号，延时器输出的延时信号作为非中心延时信号，其具体结构及变型结构在此不再详述。
进一步的，上述方式一和方式二的核心单元201中，延时器的数量N可以为奇数，也可以为偶数；N个延时器的延时长度可以不同，也可以相同。具体延时器的数量及延时长度可以基于实际需要进行设定，在此不予限定。
需要说明的是，在本发明的其它实现方式中，当N≥2时，N个延时器也可以采用其它方式连接，只要能得到N路不同延时的延时信号，N个延时器的任意连接方式均可。例如，可以采用多个延时器串联得到多路不同延时的延时信号，其中一路延时信号作为中心延时信号，采用专门的一个延时器对系统输入信号进行延时以产生前馈信号，或者，采用专门的一个延时器对多路不同延时的延时信号中的某一路延时信号进行再次延时，以产生前馈信号。
进一步的，上述方式一和方式二的核心单元201中，非线性模块具体可以如图8所示，包括包络子模块801和作用矩阵子模块802，其中：
包络子模块801，用于接收系统输入信号，对系统输入信号进行包络检测，得到L路不同延时的输入包络信号，并将该L路不同延时的输入包络信号输出至作用矩阵子模块802；L为不小于1的整数，可以和N相等，也可以和N不相等；
作用矩阵子模块802，用于接收N路不同延时的延时信号、L路不同延时的输入包络信号和非线性系数，根据该N路不同延时的延时信号、L路不同延时的输入包络信号和非线性系数，生成非线性预失真信号。
包络子模块801和作用矩阵子模块802的具体实现为现有技术，在此不再详述。
可选的，上述方式一和方式二的核心单元201中，DVM均可以采用图9所示结构实现，包括QPS(Quadrature Phase Splitter，正交分相器)、减法器和 两个乘法器，上述各线性系数均为复系数，复系数的实部即为图9中所示的同相系数，复系数的虚部即为图9中所示的正交系数，具体的：
QPS对DVM的输入信号进行正交分路；
两个乘法器中一个乘法器进行QPS输出的同相信号与同相系数的乘法运算；另一个乘法器进行QPS输出的正交信号与正交系数的乘法运算；
减法器进行该两个乘法器的输出信号的减法运算；该减法器的输出信号即为DVM的输出信号。
本发明实施例提供的APD校正系统中，增益调整单元202可以由VGA(Variable Gain Amplifier，可变增益放大器)实现，VGA的增益与系统输入信号到PA的输出信号的增益相关，因此，实际实施时，可以根据系统输入信号到PA的输出信号的增益需求，来配置VGA的增益。
本发明实施例提供的APD校正系统中，误差生成单元203可以由减法器实现，该减法器进行前馈信号和反馈调整信号的减法运算，即得到前馈信号和反馈调整信号的误差信号。
本发明实施例提供的APD校正系统中，训练单元204也具有多种实现方式，下面结合附图，用具体实施例来进行详细描述。
实施例1：
本发明实施例1提供的APD校正系统，如图10所示，核心单元201可以采用前述方式一实现，也可以采用前述方式二实现；增益调整单元202可以采用VGA实现；误差生成单元203可以采用减法器实现；训练单元204，根据误差生成单元203输出的误差信号的功率，确定APD系数，具体的，训练单元204，可以包括VGA、PDET(Power Detector，功率检测器)、ADC(Analog to Digital Converter，模数转换器)和系数训练模块，其中：
VGA，用于接收误差信号，对该误差信号的增益进行调整，得到误差调整信号，输出该误差调整信号至PDET；
PDET，用于接收VGA输出的误差调整信号，对该误差调整信号的平均功率进行检测，得到误差功率信号，输出该误差功率信号至ADC；
ADC，用于接收PDET输出的误差功率信号，对该误差功率信号进行模数转换，得到误差功率数字信号，输出该误差功率数字信号至系数训练模块；
系数训练模块，用于接收ADC输出的误差功率数字信号，根据该误差功率数字信号，确定APD系数，使该误差功率数字信号趋近于0。
具体实施时，可以由系数训练模块对VGA进行AGC(Automatic Gain Control，自动增益控制)，控制VGA的增益，进而控制对误差信号的增益的调整幅度，使ADC输入的误差功率信号始终保持接近ADC满刻度，而又不让ADC饱和，这样可以使ADC得到最充分的利用，使ADC输出信号的SNR(Signal to Noise Ratio，信噪比)最大，从而可以让系数训练模块最准确地看到误差信号的大小，有利于系数训练。
采用本发明实施例1提供的APD校正系统，不需要接收机；训练单元204中的ADC是对误差功率信号进行模数转换，由于误差功率信号是一个随时间缓慢变化的信号，因此对ADC的性能要求较低，不但易于实现，更大大降低了系统成本。
实施例2：
本发明实施例2提供的APD校正系统，如图11所示，核心单元201可以采用前述方式一实现，也可以采用前述方式二实现；增益调整单元202可以采用VGA实现；误差生成单元203可以采用减法器实现；训练单元204，可以包括接收机和系数训练模块，其中：
接收机，用于接收误差信号，对该误差信号进行下变频、模数转换处理，得到误差数字信号，并输出该误差数字信号至系数训练模块；
系数训练模块，用于接收接收机输出的误差数字信号，根据该误差数字信号，确定APD系数，使该误差数字信号趋近于0。
上述接收机具体可以为图11中所示的形式，包括VGA、QDM(Quadrature Demodulator，正交解调器)和两个ADC，由系数训练模块对接收机中的VGA进行AGC；其中：
VGA对接收机的输入信号的增益进行调整；
QDM对VGA的输出信号进行下变频处理；
两个ADC分别对QDM的两路输出信号进行模数转换处理；该两个ADC的输出信号即为接收机的输出信号。
图11中QDM结构如图12所示，包括-90°移相器、两个乘法器和两个LPF(Low-Pass Filter，低通滤波器)，其中：
-90°移相器对本振信号进行-90°移相，得到移相后本振信号；
两个乘法器中的一个乘法器进行QDM的输入信号与本振信号的乘法运算；另一个乘法器进行QDM的输入信号与移相后本振信号的乘法运算；
两个LPF分别对两个乘法器的输出信号进行滤波；该两个LPF的输出信号即为QDM的输出信号。
当然，上述接收机也可以为现有技术中的其它形式的接收机，本发明对此不做限定。
采用本发明实施例2提供的APD校正系统，仅需要一个接收机，相比于现有技术，更易于实现，降低了系统成本。
基于同一发明构思，根据本发明上述实施例提供的APD校正系统，相应地，本发明实施例还提供一种APD校正方法，其流程示意图如图13所示，具体包括：
步骤1301、对系统输入信号进行延时，得到N路不同延时的延时信号，N为不小于1的整数；
步骤1302、根据该系统输入信号、该N路不同延时的延时信号和APD系数，得到功率放大器PA的输入信号；其中，该APD系数采用如下方式确定：
PA的输出信号中耦合出一部分作为反馈信号，对该反馈信号的增益进行调整，得到反馈调整信号；N路延时信号中的一路延时信号作为前馈信号，生成前馈信号和反馈调整信号的误差信号；根据该误差信号，确定该APD系数。
可选的，生成前馈信号和反馈调整信号的误差信号，即，进行前馈信号 和反馈调整信号的减法运算，得到的信号即为前馈信号和反馈调整信号的误差信号。
在本发明的一个具体实施例中，根据该误差信号，确定该APD系数，具体可以包括：
根据该误差信号的功率，确定该APD系数。
可选的，根据该误差信号的功率，确定该APD系数，具体可以包括：
对该误差信号的增益进行调整，得到误差调整信号；对该误差调整信号的平均功率进行检测，得到误差功率信号；对该误差功率信号进行模数转换，得到误差功率数字信号；根据该误差功率数字信号，确定该APD系数。
在本发明的另一个具体实施例中，根据该误差信号，确定该APD系数，具体可以包括：
对该误差信号进行下变频、模数转换处理，得到误差数字信号；根据该误差数字信号，确定该APD系数。
在本发明的一个具体实施例中，APD系数包括非线性系数和M个线性系数，1≤M≤N+1；步骤1302根据该系统输入信号、该N路不同延时的延时信号和APD系数，得到PA的输入信号，具体可以包括：
根据该系统输入信号、该N路不同延时的延时信号和该非线性系数，生成非线性预失真信号；该系统输入信号和该N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；该M个线性系数中，M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行该M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；进行该非线性预失真信号、该中心延时信号、M-1个乘法运算的输出信号的加法运算；该M个线性系数中，除该M-1个线性系数以外的一个线性系数和该加法运算的输出信号对应；进行该加法运算的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
在本发明的另一个具体实施例中，该APD系数包括非线性系数和M个线性系数，1≤M≤N+1；步骤1302根据该系统输入信号、该N路不同延时的延 时信号和APD系数，得到PA的输入信号，具体可以包括：
根据该系统输入信号、该N路不同延时的延时信号和该非线性系数，生成非线性预失真信号；该系统输入信号和该N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；该M个线性系数中，一个线性系数和该中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行该中心延时信号与对应线性系数的乘法运算，以及该M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；进行该非线性预失真信号、M个乘法运算的输出信号的加法运算，得到PA的输入信号。
较佳的，N≥2，中心延时信号相对于系统输入信号的延时长度与PA的延时长度之和大致等于前馈信号相对于系统输入信号的延时长度。
上述流程中的各处理步骤可对应于图2-图12所示相应单元的功能，在此不再赘述。
基于同一发明构思，本发明实施例还提供一种APD校正系统，如图14所示，可以包括核心单元1401、增益调整单元1402、误差生成单元1403和训练单元1404，其中：
核心单元1401，用于接收系统输入信号以及训练单元1404输出的APD系数，根据系统输入信号和APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；
增益调整单元1402，用于接收反馈信号，对该反馈信号的增益进行调整，得到反馈调整信号，并输出该反馈调整信号至误差生成单元1403；
误差生成单元1403，用于接收系统输入信号以及增益调整单元1402输出的反馈调整信号，系统输入信号作为前馈信号，生成前馈信号和反馈调整信号的误差信号，并输出误差信号至训练单元1404；
训练单元1404，用于接收误差生成单元1403输出的误差信号，根据该误差信号，确定APD系数，并输出该APD系数至核心单元1401。
在本发明的一个具体实施例中，训练单元1404，可以参见图10，包括可 变增益放大器、功率检测器、模数转换器和系数训练模块，其中：
可变增益放大器，用于对误差信号的增益进行调整，得到误差调整信号；
功率检测器，用于对误差调整信号的平均功率进行检测，得到误差功率信号；
模数转换器，用于对误差功率信号进行模数转换，得到误差功率数字信号；
系数训练模块，用于根据误差功率数字信号，确定APD系数。
详见上述实施例1，在此不再详述。
在本发明的另一个具体实施例中，训练单元1404，可以参见图11，包括接收机和系数训练模块，其中：
接收机，用于对误差信号进行下变频、模数转换处理，得到误差数字信号；
系数训练模块，用于根据误差数字信号，确定APD系数。
详见上述实施例2，在此不再详述。
进一步的，图14所示的APD校正系统中，核心单元1401具有多种实现方式，例如：
方式一：
核心单元1401，如图15所示，包括非线性模块、数字矢量调制器和加法器，APD系数包括非线性系数和线性系数，其中：
非线性模块，用于根据系统输入信号和非线性系数，生成非线性预失真信号；
加法器，进行非线性预失真信号、系统输入信号的加法运算；
数字矢量调制器进行加法器的输出信号与线性系数的乘法运算，得到PA的输入信号。
方式二：
核心单元1401，包括非线性模块、数字矢量调制器和加法器，APD系数包括非线性系数和线性系数，其中：
非线性模块，用于根据系统输入信号和非线性系数，生成非线性预失真信号；
数字矢量调制器，进行系统输入信号与线性系数的乘法运算；
加法器，进行非线性预失真信号、数字矢量调制器的输出信号的加法运算，得到PA的输入信号。
上述方式一和方式二的核心单元1401的具体实现可以参见前文，在此不再详述。
可选的，图14所示的APD校正系统中，增益调整单元1402可以由VGA实现。
可选的，图14所示的APD校正系统中，误差生成单元1403可以由减法器实现，该减法器进行前馈信号和反馈调整信号的减法运算，即得到前馈信号和反馈调整信号的误差信号。
基于同一发明构思，根据本发明上述实施例提供的APD校正系统，相应地，本发明实施例还提供一种APD校正方法，其流程示意图如图16所示，具体包括：
步骤1601、功率放大器PA的输出信号中耦合出一部分作为反馈信号，对该反馈信号的增益进行调整，得到反馈调整信号；
步骤1602、系统输入信号作为前馈信号，生成该前馈信号和该反馈调整信号的误差信号；
步骤1603、根据该误差信号，确定该APD系数；
步骤1604、根据该系统输入信号和该APD系数，得到PA的输入信号。
其中，步骤1602生成前馈信号和反馈调整信号的误差信号，即，进行前馈信号和反馈调整信号的减法运算，得到的信号即为前馈信号和反馈调整信号的误差信号。
在本发明的一个具体实施例中，步骤1603根据该误差信号，确定该APD系数，具体可以包括：
对该误差信号的增益进行调整，得到误差调整信号；对该误差调整信号 的平均功率进行检测，得到误差功率信号；对该误差功率信号进行模数转换，得到误差功率数字信号；根据该误差功率数字信号，确定该APD系数。
在本发明的另一个具体实施例中，步骤1603根据该误差信号，确定该APD系数，具体可以包括：
对该误差信号进行下变频、模数转换处理，得到误差数字信号；根据该误差数字信号，确定该APD系数。
在本发明的一个具体实施例中，APD系数包括非线性系数和线性系数；步骤1604根据该系统输入信号和该APD系数，得到PA的输入信号，具体可以包括：
根据该系统输入信号和该非线性系数，生成非线性预失真信号；进行该非线性预失真信号、该系统输入信号的加法运算；进行该加法运算的输出信号与该线性系数的乘法运算，得到PA的输入信号。
在本发明的另一个具体实施例中，APD系数包括非线性系数和线性系数；步骤1604，根据该系统输入信号和该APD系数，得到PA的输入信号，具体可以包括：
根据该系统输入信号和该非线性系数，生成非线性预失真信号；进行该系统输入信号与该线性系数的乘法运算；进行该非线性预失真信号、该乘法运算的输出信号的加法运算，得到PA的输入信号。
上述流程中的各处理步骤可对应于图14-图15所示相应单元的功能，在此不再赘述。
综上所述，采用本发明实施例提供的APD校正方案，更易于实现，成本更低。
可以理解的是，作为一种可选的实施方式，以上系统中，训练单元的系数训练模块可以采用数字电路实现(包括可选的AGC部分)，而其他部分采用模拟电路实现。
以上任意一个实施例中提供的APD校正方案，可以应用于移动通信系统、无线传输系统，或是雷达系统等需要进行APD的系统中。具体的，APD校正 方案可以但不限于应用于移动通信系统中的基站中。
本发明实施例还提供一种基站，包括以上任意一种APD校正系统。
在基站中，将需要进行功率放大的待发射信号作为APD校正系统的系统输入信号，APD校正系统生成PA的输入信号，由于APD校正系统对PA产生的失真进行了校正，使得PA的输出信号相对于系统输入信号无失真，即功率放大后的待发射信号无失真，保证了通信质量。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步 骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (20)

  1. 一种模拟预失真APD校正系统，其特征在于，包括核心单元、增益调整单元、误差生成单元和训练单元，其中：
    所述核心单元，用于接收系统输入信号以及所述训练单元输出的APD系数；对所述系统输入信号进行延时，得到N路不同延时的延时信号，其中一路延时信号作为前馈信号输出至所述误差生成单元，N为不小于1的整数；以及根据所述系统输入信号、所述N路不同延时的延时信号和所述APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；
    所述增益调整单元，用于接收所述反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号，并输出所述反馈调整信号至所述误差生成单元；
    所述误差生成单元，用于接收所述核心单元输出的前馈信号以及所述增益调整单元输出的反馈调整信号，生成所述前馈信号和所述反馈调整信号的误差信号，并输出所述误差信号至所述训练单元；
    所述训练单元，用于接收所述误差生成单元输出的误差信号，根据所述误差信号，确定所述APD系数，并输出所述APD系数至所述核心单元。
  2. 如权利要求1所述的系统，其特征在于，所述训练单元，包括可变增益放大器、功率检测器、模数转换器和系数训练模块，其中：
    所述可变增益放大器，用于对所述误差信号的增益进行调整，得到误差调整信号；
    所述功率检测器，用于对所述误差调整信号的平均功率进行检测，得到误差功率信号；
    所述模数转换器，用于对所述误差功率信号进行模数转换，得到误差功率数字信号；
    所述系数训练模块，用于根据所述误差功率数字信号，确定所述APD系数。
  3. 如权利要求1所述的系统，其特征在于，所述训练单元，包括接收机和系数训练模块，其中：
    所述接收机，用于对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
    所述系数训练模块，用于根据所述误差数字信号，确定所述APD系数。
  4. 如权利要求1-3任一所述的系统，其特征在于，所述核心单元，包括N个延时器、非线性模块、M个数字矢量调制器和加法器，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
    所述N个延时器串联，用于对所述系统输入信号进行延时，得到N路不同延时的延时信号；
    所述非线性模块，用于根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
    所述M个数字矢量调制器，其中一个数字矢量调制器作为后数字矢量调制器，其它M-1个数字矢量调制器作为前数字矢量调制器；所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述加法器的输出信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；每个前数字矢量调制器进行所述M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
    所述加法器，进行所述非线性预失真信号、所述中心延时信号、M-1个前数字矢量调制器的输出信号的加法运算；
    所述后数字矢量调制器进行所述加法器的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
  5. 如权利要求1-3任一所述的系统，其特征在于，所述核心单元，包括N个延时器、非线性模块、M个数字矢量调制器和加法器，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1，其中：
    所述N个延时器串联，用于对所述系统输入信号进行延时，得到N路不同延时的延时信号；
    所述非线性模块，用于根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
    所述M个数字矢量调制器，其中一个数字矢量调制器作为中心数字矢量调制器，其它M-1个数字矢量调制器作为非中心数字矢量调制器；所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；所述中心数字矢量调制器进行所述中心延时信号与对应线性系数的乘法运算，每个非中心数字矢量调制器进行所述M-1路非中心延时信号中的一路非中心延时信号与对应线性系数的乘法运算；
    所述加法器，进行所述非线性预失真信号、所述M个数字矢量调制器的输出信号的加法运算，得到PA的输入信号。
  6. 一种模拟预失真APD校正方法，其特征在于，包括：
    对系统输入信号进行延时，得到N路不同延时的延时信号，N为不小于1的整数；
    根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到功率放大器PA的输入信号；其中，所述APD系数采用如下方式确定：
    PA的输出信号中耦合出一部分作为反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号；所述N路延时信号中的一路延时信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号；根据所述误差信号，确定所述APD系数。
  7. 如权利要求6所述的方法，其特征在于，根据所述误差信号，确定所述APD系数，具体包括：
    对所述误差信号的增益进行调整，得到误差调整信号；
    对所述误差调整信号的平均功率进行检测，得到误差功率信号；
    对所述误差功率信号进行模数转换，得到误差功率数字信号；
    根据所述误差功率数字信号，确定所述APD系数。
  8. 如权利要求6所述的方法，其特征在于，根据所述误差信号，确定所述APD系数，具体包括：
    对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
    根据所述误差数字信号，确定所述APD系数。
  9. 如权利要求6-8任一所述的方法，其特征在于，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1；
    根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到PA的输入信号，具体包括：
    根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
    所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行所述M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；
    进行所述非线性预失真信号、所述中心延时信号、M-1个乘法运算的输出信号的加法运算；
    所述M个线性系数中，除所述M-1个线性系数以外的一个线性系数和所述加法运算的输出信号对应；进行所述加法运算的输出信号与对应线性系数的乘法运算，得到PA的输入信号。
  10. 如权利要求6-8任一所述的方法，其特征在于，所述APD系数包括非线性系数和M个线性系数，1≤M≤N+1；
    根据所述系统输入信号、所述N路不同延时的延时信号和APD系数，得到PA的输入信号，具体包括：
    根据所述系统输入信号、所述N路不同延时的延时信号和所述非线性系数，生成非线性预失真信号；
    所述系统输入信号和所述N路不同延时的延时信号组成的N+1路信号中，一路信号作为中心延时信号，其它N路信号作为非中心延时信号；所述M个线性系数中，一个线性系数和所述中心延时信号对应，其它M-1个线性系数和N路非中心延时信号中的M-1路非中心延时信号一一对应；进行所述中心延时信号与对应线性系数的乘法运算，以及所述M-1路非中心延时信号中的每路非中心延时信号与对应线性系数的乘法运算；
    进行所述非线性预失真信号、M个乘法运算的输出信号的加法运算，得到PA的输入信号。
  11. 一种模拟预失真APD校正系统，其特征在于，包括核心单元、增益调整单元、误差生成单元和训练单元，其中：
    所述核心单元，用于接收系统输入信号以及所述训练单元输出的APD系数，根据所述系统输入信号和所述APD系数，得到功率放大器PA的输入信号，PA的输出信号中耦合出一部分作为反馈信号；
    所述增益调整单元，用于接收所述反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号，并输出所述反馈调整信号至所述误差生成单元；
    所述误差生成单元，用于接收所述系统输入信号以及所述增益调整单元输出的反馈调整信号，所述系统输入信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号，并输出所述误差信号至所述训练单元；
    所述训练单元，用于接收所述误差生成单元输出的误差信号，根据所述误差信号，确定所述APD系数，并输出所述APD系数至所述核心单元。
  12. 如权利要求11所述的系统，其特征在于，所述训练单元，包括可变增益放大器、功率检测器、模数转换器和系数训练模块，其中：
    所述可变增益放大器，用于对所述误差信号的增益进行调整，得到误差调整信号；
    所述功率检测器，用于对所述误差调整信号的平均功率进行检测，得到 误差功率信号；
    所述模数转换器，用于对所述误差功率信号进行模数转换，得到误差功率数字信号；
    所述系数训练模块，用于根据所述误差功率数字信号，确定所述APD系数。
  13. 如权利要求11所述的系统，其特征在于，所述训练单元，包括接收机和系数训练模块，其中：
    所述接收机，用于对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
    所述系数训练模块，用于根据所述误差数字信号，确定所述APD系数。
  14. 如权利要求11-13任一所述的系统，其特征在于，所述核心单元，包括非线性模块、数字矢量调制器和加法器，所述APD系数包括非线性系数和线性系数，其中：
    所述非线性模块，用于根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
    所述加法器，进行所述非线性预失真信号、所述系统输入信号的加法运算；
    所述数字矢量调制器进行所述加法器的输出信号与所述线性系数的乘法运算，得到PA的输入信号。
  15. 如权利要求11-13任一所述的系统，其特征在于，所述核心单元，包括非线性模块、数字矢量调制器和加法器，所述APD系数包括非线性系数和线性系数，其中：
    所述非线性模块，用于根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
    所述数字矢量调制器，进行所述系统输入信号与所述线性系数的乘法运算；
    所述加法器，进行所述非线性预失真信号、所述数字矢量调制器的输出 信号的加法运算，得到PA的输入信号。
  16. 一种模拟预失真APD校正方法，其特征在于，包括：
    功率放大器PA的输出信号中耦合出一部分作为反馈信号，对所述反馈信号的增益进行调整，得到反馈调整信号；
    系统输入信号作为前馈信号，生成所述前馈信号和所述反馈调整信号的误差信号；
    根据所述误差信号，确定所述APD系数；
    根据所述系统输入信号和所述APD系数，得到PA的输入信号。
  17. 如权利要求16所述的方法，其特征在于，根据所述误差信号，确定所述APD系数，具体包括：
    对所述误差信号的增益进行调整，得到误差调整信号；
    对所述误差调整信号的平均功率进行检测，得到误差功率信号；
    对所述误差功率信号进行模数转换，得到误差功率数字信号；
    根据所述误差功率数字信号，确定所述APD系数。
  18. 如权利要求16所述的方法，其特征在于，根据所述误差信号，确定所述APD系数，具体包括：
    对所述误差信号进行下变频、模数转换处理，得到误差数字信号；
    根据所述误差数字信号，确定所述APD系数。
  19. 如权利要求16-18任一所述的方法，其特征在于，所述APD系数包括非线性系数和线性系数；
    根据所述系统输入信号和所述APD系数，得到PA的输入信号，具体包括：
    根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
    进行所述非线性预失真信号、所述系统输入信号的加法运算；
    进行所述加法运算的输出信号与所述线性系数的乘法运算，得到PA的输入信号。
  20. 如权利要求16-18任一所述的方法，其特征在于，所述APD系数包 括非线性系数和线性系数；
    根据所述系统输入信号和所述APD系数，得到PA的输入信号，具体包括：
    根据所述系统输入信号和所述非线性系数，生成非线性预失真信号；
    进行所述系统输入信号与所述线性系数的乘法运算；
    进行所述非线性预失真信号、所述乘法运算的输出信号的加法运算，得到PA的输入信号。
PCT/CN2015/080442 2015-05-30 2015-05-30 一种模拟预失真apd校正系统及方法 WO2016191993A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201580000955.XA CN106664269B (zh) 2015-05-30 2015-05-30 一种模拟预失真apd校正系统及方法
PCT/CN2015/080442 WO2016191993A1 (zh) 2015-05-30 2015-05-30 一种模拟预失真apd校正系统及方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/080442 WO2016191993A1 (zh) 2015-05-30 2015-05-30 一种模拟预失真apd校正系统及方法

Publications (1)

Publication Number Publication Date
WO2016191993A1 true WO2016191993A1 (zh) 2016-12-08

Family

ID=57440146

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/080442 WO2016191993A1 (zh) 2015-05-30 2015-05-30 一种模拟预失真apd校正系统及方法

Country Status (2)

Country Link
CN (1) CN106664269B (zh)
WO (1) WO2016191993A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3633941B1 (en) 2017-06-26 2023-11-29 Huawei Technologies Co., Ltd. Correction device and correction method
CN110971197B (zh) * 2019-11-01 2023-03-24 深圳华臻信息技术有限公司 数字预失真装置及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060098680A (ko) * 2005-03-03 2006-09-19 삼성전자주식회사 무선 통신 시스템에서 전력 증폭기의 기억 효과를 보상하는아날로그 전치 왜곡 장치 및 방법
CN101807886A (zh) * 2010-03-26 2010-08-18 深圳市云海通讯股份有限公司 一种射频功率放大装置及其模拟预失真校正方法
CN103858397A (zh) * 2013-12-26 2014-06-11 华为技术有限公司 一种预失真反馈方法、装置及系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1166053C (zh) * 2001-05-08 2004-09-08 华为技术有限公司 自适应射频数字预失真线性化方法及其电路
CN1177449C (zh) * 2002-04-23 2004-11-24 华为技术有限公司 基于基带数字预失真技术的提高射频功率放大器效率的方法
US8706062B1 (en) * 2008-12-19 2014-04-22 Scintera Networks, Inc. Self-adaptive power amplification
CN102195912B (zh) * 2010-03-16 2015-03-04 富士通株式会社 数字预失真处理设备和方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060098680A (ko) * 2005-03-03 2006-09-19 삼성전자주식회사 무선 통신 시스템에서 전력 증폭기의 기억 효과를 보상하는아날로그 전치 왜곡 장치 및 방법
CN101807886A (zh) * 2010-03-26 2010-08-18 深圳市云海通讯股份有限公司 一种射频功率放大装置及其模拟预失真校正方法
CN103858397A (zh) * 2013-12-26 2014-06-11 华为技术有限公司 一种预失真反馈方法、装置及系统

Also Published As

Publication number Publication date
CN106664269B (zh) 2019-11-29
CN106664269A (zh) 2017-05-10

Similar Documents

Publication Publication Date Title
US7430250B2 (en) Distortion compensating apparatus
JP5811929B2 (ja) 無線装置、歪補償方法、及び歪補償プログラム
JP3707549B2 (ja) 送信装置
JP4327848B2 (ja) 送信機により生成された無線通信信号などの振幅および位相特性の調整
US7486744B2 (en) Distortion compensation apparatus
JP2008535388A (ja) 送信基底帯域におけるｄｃオフセット補正のためのシステム及び方法
US20100311360A1 (en) Transmitter, method for lowering signal distortion, and method for generating predistortion parameters utilized to lower signal distortion
JP2007318537A (ja) 歪補償装置及び歪補償方法
JP2010103869A (ja) Ｉｑミスマッチ補正回路
JP2012129661A (ja) 歪補償装置、歪補償方法、及び無線装置
US8792583B2 (en) Linearization in the presence of phase variations
JP5303809B2 (ja) 歪補償装置
EP3145080B1 (en) Radio frequency power amplification system, radio frequency power amplification method, transmitter, and base station
JP2004254175A (ja) 非線形歪補償回路および非線形歪補償方法ならびに送信回路
WO2016191993A1 (zh) 一种模拟预失真apd校正系统及方法
CN104124928A (zh) 自动增益调整装置与其方法
WO2014103174A1 (ja) 歪み補償装置及び歪み補償方法
CN104601121B (zh) 为功率放大器决定前置补偿数据的装置及方法
JP6094071B2 (ja) 歪補償装置及び歪補償方法
JP5673475B2 (ja) 歪補償装置および歪補償方法
US8417193B2 (en) Transmitting device and method for determining target predistortion setting value
JP6064714B2 (ja) 歪補償装置及び歪補償方法
JP2011176686A (ja) 前置歪み補償回路及び電力増幅器のメモリ効果歪み補償方法
KR100939882B1 (ko) 왜곡 보상 장치
JP2001268144A (ja) 非線形歪み補償回路および非線形歪み補償方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15893656

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15893656

Country of ref document: EP

Kind code of ref document: A1