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WO2015180352A1 - 像素电路及其驱动方法、有机发光显示面板及显示装置 - Google Patents

像素电路及其驱动方法、有机发光显示面板及显示装置 Download PDF

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Publication number
WO2015180352A1
WO2015180352A1 PCT/CN2014/087920 CN2014087920W WO2015180352A1 WO 2015180352 A1 WO2015180352 A1 WO 2015180352A1 CN 2014087920 W CN2014087920 W CN 2014087920W WO 2015180352 A1 WO2015180352 A1 WO 2015180352A1
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Prior art keywords
thin film
film transistor
signal input
level signal
unit
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PCT/CN2014/087920
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English (en)
French (fr)
Inventor
杨盛际
董学
王海生
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/758,746 priority Critical patent/US9805654B2/en
Publication of WO2015180352A1 publication Critical patent/WO2015180352A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, an organic light emitting display panel, and a display device.
  • Organic light-emitting display is one of the hotspots in the research field of flat panel displays. Compared with liquid crystal displays, organic light-emitting diodes (OLEDs) have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response. In the display fields of mobile phones, PDAs, digital cameras, etc., OLEDs have begun to replace traditional LCD displays. Pixel driver circuit design is the core technology content of AMOLED display, which has important research significance.
  • the circuit consists of only one driving thin film transistor (TFT), one switching thin film transistor TFT and one storage capacitor Cs, when the scan line selects a certain row.
  • TFT driving thin film transistor
  • T1 switching thin film transistor
  • storage capacitor Cs storage capacitor Cs
  • Vth threshold voltage of the driving thin film transistor at each pixel will drift, which causes the current flowing through each pixel point OLED to change due to the change of the threshold voltage, so that the display brightness is not Both, which affect the display of the entire image.
  • the present disclosure provides a pixel circuit and a driving method thereof, an organic light emitting display panel, and a display device, which can eliminate the influence of the threshold voltage of the driving thin film transistor on the light emitting driving current, thereby improving the uniformity of brightness of the organic light emitting display panel, and improving the display device.
  • the image is displayed.
  • An embodiment of the present disclosure provides a pixel circuit including a storage capacitor, a driving thin film transistor, and a light emitting unit, wherein a source of the driving thin film transistor is connected to the first level signal input end, and a gate of the driving thin film transistor is connected to the storage capacitor. The two ends of the driving thin film transistor are connected to the light emitting unit;
  • the pixel circuit further includes:
  • the potential of the first end of the storage capacitor is controlled to be the potential of the input signal of the second level signal input end, and the potential of the second end of the storage capacitor is controlled to be the potential and driving of the input signal of the first level signal input end.
  • the potential of the first end of the storage capacitor is controlled to be a data voltage, and the voltage of the second end of the storage capacitor is jumped to a data voltage and the input of the first level signal The sum of the difference between the potential of the input signal and the threshold voltage of the driving thin film transistor, so that the light-emitting unit performs a light-emitting compensating hopping unit with the data voltage after the illuminating phase after the compensating hopping phase.
  • the charging unit is respectively connected to the second level signal input end, the first scan signal input end, the drain of the driving thin film transistor, the first end and the second end of the storage capacitor.
  • the charging unit includes:
  • a source of the first thin film transistor is connected to the second level signal input end, a gate of the first thin film transistor is connected to the first scan signal input end, and a drain of the first thin film transistor is connected to the first end of the storage capacitor ;
  • the source of the second thin film transistor is connected to the drain of the driving thin film transistor, the gate of the second thin film transistor is connected to the first scan signal input end, and the drain of the second thin film transistor is connected to the second end of the storage capacitor.
  • the compensation hopping unit is respectively connected to the data line, the second scan signal input end, and the first end of the storage capacitor.
  • the compensation hopping unit includes:
  • the source of the third thin film transistor is connected to the data line, the gate of the third thin film transistor is connected to the second scan signal input end, and the drain of the third thin film transistor is connected to the first end of the storage capacitor.
  • the pixel circuit further includes:
  • a resetting unit for controlling a potential of the second end of the storage capacitor to be a potential of the input signal of the second level signal input end during a reset phase before the charging phase;
  • the reset unit is respectively connected to the second level signal input end, the third scan signal input end, and the second end of the storage capacitor.
  • the reset unit includes:
  • the source of the fourth thin film transistor is connected to the second level signal input terminal, the gate of the fourth thin film transistor is connected to the third scan signal input end, and the drain of the fourth thin film transistor is connected to the second end of the storage capacitor.
  • the pixel circuit further includes:
  • the control unit is respectively connected to the first level signal input terminal, the control signal input terminal and the driving thin film transistor.
  • control unit includes:
  • the source of the fifth thin film transistor is connected to the first level signal input terminal, the gate of the fifth thin film transistor is connected to the control signal input terminal, and the drain of the fifth thin film transistor is connected to the source of the driving thin film transistor.
  • the light emitting unit includes:
  • a source of the sixth thin film transistor is connected to a drain of the driving thin film transistor, a gate of the sixth thin film transistor is connected to a second scan signal input end, and a drain of the sixth thin film transistor is connected to an anode of the organic light emitting diode;
  • the cathode of the organic light emitting diode is connected to the second level signal input terminal.
  • the thin film transistor is a P-type thin film transistor
  • the signal input by the first level signal input terminal is a high level signal
  • the signal input to the second level signal input terminal is a low level signal.
  • the embodiment of the present disclosure further provides a pixel driving method for driving the pixel current provided by the embodiment of the present disclosure.
  • the method includes:
  • the potential of the first end of the storage capacitor is controlled to be the potential of the input signal of the second level signal input terminal, and the potential of the second end of the storage capacitor is controlled to be the potential of the input signal of the first level signal input terminal and the driving thin film transistor The difference between the threshold voltages;
  • the potential of the first end of the storage capacitor is controlled to be a data voltage, and the second terminal voltage of the storage capacitor is jumped to a data voltage and an input signal of the first level signal input end.
  • the sum of the difference between the potential and the threshold voltage of the driving thin film transistor is such that the light emitting unit emits light using the data voltage during the light emitting phase after the compensating transition phase.
  • the method further includes:
  • the potential of the second terminal of the storage capacitor is controlled to be the potential of the input signal of the second level signal input.
  • the charging phase further includes:
  • the illuminating phase further includes:
  • the signal input from the first level signal input terminal is transmitted to the driving thin film transistor to transmit the signal to the light emitting unit through the driving thin film transistor.
  • the third scan signal input terminal inputs a low level signal
  • the reset unit In the on state, the first and second scan signal input ends and the control signal input end input a high level signal, and the charging unit, the compensation hopping unit, the illuminating unit and the control unit are in an off state;
  • control signal input terminal and the first scan signal input end input a low level signal
  • control unit and the charging unit are in an on state
  • second and third scan signal input terminals input a high level signal, resetting the unit, and compensating
  • the hopping unit and the illuminating unit are in an off state
  • the second scan signal input end inputs a low level signal
  • the compensation jump unit and the light emitting unit are in an on state
  • the first and third scan signal input ends and the control signal input end input a high level signal
  • the weight is heavy.
  • the unit, the charging unit and the control unit are in an off state;
  • the second scan signal input end and the control signal input end input a low level signal
  • the control unit, the compensation jump unit and the light emitting unit are in an on state
  • the first and third scan signal input ends input a high level signal.
  • the reset unit and the charging unit are in an off state.
  • the potential of the data line transmission signal is a negative voltage
  • the potential of the data line transmission signal is a positive voltage
  • An embodiment of the present disclosure further provides an organic light emitting display panel, including the pixel circuit provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, including the organic light emitting display panel provided by the embodiment of the present disclosure.
  • the organic light emitting display panel and the display device are configured to control the potential of the first end of the storage capacitor to be the second power during the charging phase.
  • a potential of the input signal of the flat signal input terminal a charging unit that controls a potential of the second end of the storage capacitor to be a difference between a potential of the input signal of the first level signal input terminal and a threshold voltage of the driving thin film transistor;
  • the potential of the first end of the storage capacitor is controlled to be a data voltage, and the voltage of the second terminal of the storage capacitor is jumped to the potential of the data voltage and the input signal of the first level signal input end.
  • the sum of the difference values between the threshold voltages of the driving thin film transistors is such that the light emitting unit performs the light-emitting compensation hopping unit with the data voltages in the light-emitting phase after the compensation hopping phase.
  • the influence of the threshold voltage of the driving thin film transistor on the light-emission driving current can be eliminated, thereby improving the uniformity of the brightness of the organic light-emitting display panel and improving the image display effect of the display device.
  • Figure 1 is a schematic diagram of the prior art.
  • FIG. 2 is a schematic diagram 1 of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a second schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram 3 of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram 4 of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram 5 of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram 6 of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram 7 of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a pixel driving method according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of signal timing provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram 1 of a state of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a second schematic diagram of a state of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a third schematic diagram of a state of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a fourth schematic diagram of a state of a pixel circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 2, including a storage capacitor Cs, a driving thin film transistor DTFT, and a light emitting unit 1, wherein a source of the driving thin film transistor DTFT is connected to the first level signal input terminal, The gate of the driving thin film transistor DTFT is connected to the second end of the storage capacitor Cs, and the drain of the driving thin film transistor DTFT is connected to the light emitting unit 1;
  • the pixel circuit further includes:
  • the potential of the first end of the storage capacitor Cs is controlled to be the potential of the input signal of the second level signal input terminal, and the potential of the second end of the storage capacitor Cs is controlled to be the potential of the input signal of the first level signal input end.
  • a charging unit 2 that drives a difference between a threshold voltage Vth of the thin film transistor DTFT;
  • the potential of the first end of the storage capacitor Cs is controlled to be the data voltage V data , and the second terminal voltage of the storage capacitor Cs is jumped to the data voltage V data and the first level signal.
  • the pixel circuit provided by the embodiment of the present disclosure can make the driving current I OLED of the organic light emitting diode (OLED) not affected by the threshold voltage V th of the driving thin film transistor, thereby making the OLED in different pixel units in the organic light emitting display panel
  • the driving current is uniform, which can improve the uniformity of the brightness of the organic light emitting display panel and improve the image display effect of the display device.
  • the first electrical signal level of the signal input terminal involved, specifically, a high level signal, such as V dd and the like.
  • the signal input by the second level signal input end may be a low level signal, or the second level signal input end may be directly grounded, so that the second level signal input end is input to zero. Potential signal.
  • the potential of the second end of the storage capacitor Cs in the charging phase may be V dd -V th
  • the potential in the compensation jump phase is V dd -V th +V data .
  • the charging unit 2 may specifically be respectively connected to the second level signal input end, the first scan signal input end (scan 1), the drain of the driving thin film transistor DTFT, and the storage capacitor Cs.
  • the first end (node A) and the second end (node B) are connected.
  • the charging unit 2 may specifically include:
  • the source of the first thin film transistor T1 is connected to the second level signal input end, and the gate of the first thin film transistor T1 is connected to the first scan signal input end (scan 1), and the drain and storage capacitor of the first thin film transistor T1 are connected.
  • the first end of the Cs is connected;
  • the source of the second thin film transistor T2 is connected to the drain of the driving thin film transistor DTFT, the gate of the second thin film transistor T2 is connected to the first scan signal input end (scan 1), and the drain and storage capacitor of the second thin film transistor T2 The second end of the Cs is connected.
  • the first thin film transistor T1 and the second thin film transistor T2 are in an on state under the control of the first scan signal V scan1 input from the first scan signal input terminal, and the first thin film transistor T1 will be the second level signal.
  • the input signal of the input terminal is transmitted to the first end of the storage capacitor Cs, that is, the node A, so that the potential of the node A is the potential of the input signal of the second level signal input terminal, for example, zero, and the second thin film transistor T2 sets the first level signal.
  • the input signal at the input for example, V dd is transmitted to the second end of the storage capacitor Cs, that is, the node B (in the charging phase, the driving thin film transistor DTFT is in an on state), thereby charging the node B until the potential of the node B is V dd - V th .
  • the potential of the node A can be specifically zero, the voltage difference between the nodes A and B at both ends of the storage capacitor Cs is (V dd - V th ).
  • the compensation hopping unit 3 is respectively connected to the data line, the second scan signal input end (scan 2), and the first end of the storage capacitor Cs.
  • the compensation hopping unit 3 may specifically include:
  • the source of the third thin film transistor T3 is connected to the data line
  • the gate of the third thin film transistor T3 is connected to the second scan signal input end (scan 2)
  • the drain of the third thin film transistor T3 and the first end of the storage capacitor Cs connection is connected to the second scan signal input end (scan 2)
  • the third thin film transistor T3 is in an on state under the control of the second scan signal V scan2 input from the second scan signal input terminal, thereby transmitting the signal transmitted by the data line to the first end of the storage capacitor Cs.
  • the potential of the first end of the storage capacitor Cs is the potential of the input signal of the second level signal input terminal, such as zero, so that the potential of the first end of the storage capacitor Cs is changed from 0 to V data .
  • the second end of the storage capacitor Cs that is, the node B
  • the original voltage difference (V dd - V th ) of the nodes A and B at both ends of the storage capacitor Cs is maintained.
  • the potential of the node B will undergo an isobaric jump, that is, the potential of the node B jumps to V dd --V th +V data , and the potential is maintained unchanged, so as to follow the illumination. Prepare for the stage.
  • the potential of the second end of the storage capacitor Cs (ie, the node B) is the potential of the input signal V dd of the first level signal input terminal during the charging phase and the threshold voltage of the driving thin film transistor DTFT
  • the difference between Vth can be discharged to the second end of the storage capacitor Cs during the reset phase before the charging phase.
  • the pixel circuit provided by the embodiment of the present disclosure may specifically include:
  • the resetting unit 4 that controls the potential of the second terminal of the storage capacitor Cs to be the potential of the input signal of the second level signal input terminal.
  • the reset unit 4 is respectively connected to the second level signal input terminal, the third scan signal input terminal (scan 3), and the second end of the storage capacitor Cs.
  • the reset unit 4 may specifically include:
  • the source of the fourth thin film transistor T4 is connected to the input end of the second level signal, the gate of the fourth thin film transistor T4 is connected to the third scan signal input terminal Scan3, and the drain of the fourth thin film transistor T4 and the storage capacitor Cs The second end is connected.
  • the potential of the input signal of the second level signal input terminal can be specifically zero, the potential of the second end of the storage capacitor Cs can be reset to zero in the reset phase.
  • the potential of the second terminal of the storage capacitor Cs is reset to zero, and the driving thin film transistor DTFT can be turned on until the charging phase, so that the signal input to the first level signal input terminal during the charging phase (for example, V dd ) can be transmitted to the charging unit 2 (specifically, the source of the second thin film transistor T2 ) through the driving thin film transistor DTFT, so that the charging unit 2 utilizes a signal (for example, V dd ) input by the first level signal input terminal during the charging phase,
  • the second end of the storage capacitor Cs is charged to V dd -V th .
  • the pixel circuit may further include:
  • the input signal is transmitted to the driving thin film transistor DTFT so that the signal is transmitted to the control unit 5 of the light emitting unit 1 via the driving thin film transistor DTFT.
  • control unit 5 can be respectively connected to the first level signal input terminal, the control signal input terminal EM and the driving thin film transistor DTFT.
  • control unit 5 may specifically include:
  • the source of the fifth thin film transistor T5 is connected to the first level signal input terminal, the gate of the fifth thin film transistor T5 is connected to the control signal input terminal EM, the drain of the fifth thin film transistor T5 and the source of the driving thin film transistor DTFT connection.
  • control unit 5 may be an optional device.
  • the input timing of the second level signal may be controlled to implement and replace the control unit 5 . effect.
  • the lighting unit 1 may specifically include:
  • the source of the sixth thin film transistor T6 is connected to the drain of the driving thin film transistor DTFT, the gate of the sixth thin film transistor T6 is connected to the second scan signal input end (scan 2), and the drain and organic light of the sixth thin film transistor T6 are connected.
  • the cathode of the organic light emitting diode OLED is connected to the second level signal input terminal.
  • the thin film transistor and a sixth control means are in a conductive state, and therefore, the signal level of the first signal input terminal may be transmitted, such as V dd to the source electrode of the driving thin film transistor DTFT, so that the driving thin film transistor
  • V GS V dd -(V dd -V th +V data ).
  • the saturation current formula of the driving thin film transistor DTFT can be obtained:
  • I OLED K(V GS -V th ) 2
  • V GS is a gate-source voltage of the driving thin film transistor DTFT
  • K is a constant related to a production process and a driving design of the driving thin film transistor DTFT.
  • the pixel circuit provided by the embodiment of the present disclosure can make the driving current of the organic light emitting diode OLED independent of the threshold voltage V th of the driving thin film transistor DTFT, and only depends on the data voltage V data .
  • the pixel circuit provided by the embodiment of the present disclosure can eliminate the influence of the threshold voltage of the driving thin film transistor on the light emitting driving current, thereby improving the uniformity of the brightness of the organic light emitting display panel and improving the image display effect of the display device.
  • the thin film transistor according to the embodiment of the present disclosure includes a first thin film transistor T1 to a sixth thin film transistor T6, and a driving thin film transistor DTFT, and specifically may be a P-type transistor, and the above The source and drain in the transistor are interchangeable.
  • the data voltage Vdata involved in the embodiment of the present disclosure may specifically be a negative voltage, thereby calculating the value of the formula V dd -V th +V data
  • a negative value causes the P-type driving thin film transistor DTFT to be in an on state during the light emitting phase, so that the driving current I OLED of the organic light emitting diode (OLED) is transmitted to the organic light emitting diode OLED through the driving thin film transistor DTFT to make the organic light emitting diode OLED Glowing.
  • the embodiment of the present disclosure further provides a pixel driving method for driving the pixel circuit provided by the embodiment of the present disclosure. As shown in FIG. 9, the method may specifically include:
  • the potential of the first end of the storage capacitor Cs is controlled to be the potential of the input signal of the second level signal input terminal, and the potential of the second end of the storage capacitor Cs is controlled to be the potential of the input signal of the first level signal input terminal and the driving thin film transistor
  • the potential of the control terminal of the first storage capacitor Cs to the data voltage V data, the second terminal of the storage capacitor Cs voltage jump into the data voltage V data and the first level signal
  • the sum of the difference between the potential of the input signal at the input terminal and the threshold voltage Vth of the driving thin film transistor DTFT is such that the light-emitting unit 1 emits light using the data voltage Vdata during the light-emitting phase after the compensating transition phase.
  • the driving current I OLED of the organic light emitting diode (OLED) can be prevented from being affected by the threshold voltage V th of the driving thin film transistor, so that the OLED driving current in different pixel units in the organic light emitting display panel Consistently, the uniformity of brightness of the organic light-emitting display panel can be improved, and the image display effect of the display device can be improved.
  • the signal input by the first level signal input terminal may be a high level signal, such as V dd or the like.
  • the signal input by the second level signal input end may be a low level signal, or the second level signal input end may be directly grounded, so that the second level signal input end is input to zero. Potential signal.
  • the potential of the second end of the storage capacitor Cs in the charging phase may be V dd -V th
  • the potential in the compensation jump phase is V dd -V th +V data .
  • the method may further include:
  • the potential of the second terminal of the storage capacitor Cs is controlled to be the potential of the input signal of the second level signal input terminal.
  • the charging phase may further include:
  • the illuminating phase may further include:
  • the signal input from the first level signal input terminal is transmitted to the driving thin film transistor DTFT so that the signal is transmitted to the light emitting unit 1 through the driving thin film transistor DTFT.
  • the pixel driving method provided by the embodiment of the present disclosure is specifically applicable to the pixel circuit as shown in FIG. 8, and all the thin film transistors are P-type thin film transistors, and the first level signal is used in the circuit.
  • the input signal is V dd and the second level signal input is grounded.
  • the signal input timing diagram involved in this embodiment can be as shown in FIG.
  • the third scan signal input terminal (scan 3) inputs a low level signal
  • the reset unit 4 is in an on state, that is, the fourth thin film transistor T4 is in an on state, a scan signal input terminal (scan 1), a second scan signal input terminal (scan 2), and a control signal
  • the input terminal EM inputs a high level signal
  • the light emitting unit 1, the charging unit 2, the compensation hopping unit 3, and the control unit 5 are in an off state, that is, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3,
  • the five thin film transistors T5 and the sixth thin film transistor T6 are in an off state, and the state of the pixel circuit in this stage can be as shown in FIG.
  • the fourth thin film transistor T4 is turned on during the reset phase, the second terminal of the storage capacitor Cs, that is, the node B, is reset to ground, and the potential of the node B is 0V, thereby resetting the voltage signal before the node B. .
  • the control signal input terminal EM and the first scan signal input terminal (scan 1) input a low level signal
  • the control unit 5 and the charging unit 2 are in an on state, that is, the first film.
  • the transistor T1, the second thin film transistor T2 and the fifth thin film transistor T5 are in an on state
  • the second scan signal input end (scan 2), the third scan signal input end (scan 3) input a high level signal
  • the reset unit 4 The compensating hopping unit 3 and the illuminating unit 1 are in an off state, that is, the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6 are in an off state, and the state of the pixel circuit in this stage can be as shown in FIG. Show.
  • the driving thin film transistor DTFT Since the potential of the node B is already grounded during the reset phase, in the charging phase, the driving thin film transistor DTFT is in an on state, then the V dd signal passes through the fifth thin film transistor T5 ⁇ the driving thin film transistor DTFT ⁇ the second thin film transistor T2, Start charging node B, and always charge node B to V dd - V th (satisfying the voltage difference between the gate and source of the driving thin film transistor DTFT is V th ).
  • the potential of node A is always It is zero, so after the end of the charging phase, the potential of node B will remain at V dd -V th .
  • the sixth thin film transistor T6 since the sixth thin film transistor T6 is always in the off state during the charging phase, the current does not pass through the organic light emitting diode OLED, thereby reducing the lifetime loss of the organic light emitting diode OLED and prolonging the service life of the organic light emitting diode OLED.
  • the second scan signal input terminal (scan 2) inputs a low level signal
  • the compensation jump unit 3 and the light emitting unit 1 are in an on state, that is, the third thin film transistor T3.
  • the sixth thin film transistor T6 is in an on state, the first scan signal input end (scan 1), the third scan signal input end (scan 3), and the control signal input end EM input a high level signal, the reset unit 4, and the charging
  • the unit 2 and the control unit 5 are in an off state, that is, the first thin film transistor T1.
  • the second thin film transistor T2, the fourth thin film transistor T4, and the fifth thin film transistor T5 are in an off state, and the state of the pixel circuit in this stage can be as shown in FIG.
  • the jump compensation thin film transistor T3 of the third stage in the ON state therefore, the potential of the node A transitions from zero to V data, and since the node B is in a floating state, so to maintain the two ends of the storage capacitor Cs, node A B, the original differential pressure (V dd -V th ), then in the case of the potential V data of the node A, the potential of the node B will undergo an isobaric jump, that is, the potential jump of the node B becomes V dd -V th +V data and keep this potential constant to prepare for the subsequent illumination phase.
  • the second scan signal input terminal (scan 2) and the control signal input terminal EM input a low-level signal, and the control unit 5, the compensation jumper unit 3, and the light-emitting unit 1 are turned on.
  • the states, that is, the third thin film transistor T3, the fifth thin film transistor T5, and the sixth thin film transistor T6 are in an on state; the first scan signal input terminal (scan 1) and the third scan signal input terminal (scan 3) input a high level
  • the signal, the reset unit 4 and the charging unit 2 are in an off state, that is, the first thin film transistor T1, the second thin film transistor T2 and the fourth thin film transistor T4 are in an off state, and the state of the pixel circuit in this stage can be as shown in FIG. Show.
  • the potential of the source of the driving thin film transistor DTFT is V dd , and the current passes through the fifth thin film transistor T5 ⁇ the driving thin film transistor DTFT ⁇ the sixth thin film transistor T6, so that the organic The light emitting diode OLED starts to emit light.
  • I OLED K (V GS -V th) 2
  • V GS is the gate-source voltage of the driving thin film transistor DTFT
  • K is a constant related to the manufacturing process and driving design of the driving thin film transistor DTFT.
  • the operating current I OLED is not affected by the threshold voltage V th of the driving thin film transistor DTFT, but only related to the data voltage V data , thereby completely solving the process and long process of driving the thin film transistor DTFT.
  • the operation of the time causes the problem that the threshold voltage Vth drifts, eliminating the influence on the I OLED , and ensuring the normal operation of the organic light emitting diode OLED in different pixel units. Thereby, the uniformity of the brightness of the organic light emitting display panel is improved, and the image display effect of the display device is improved.
  • the data voltage V data in the charging phase and the compensation hopping phase, is a negative voltage, and in the reset phase and the illuminating phase, the data voltage V data is a positive voltage.
  • an embodiment of the present disclosure further provides an organic light emitting display panel, which may specifically include the pixel circuit provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may specifically include the organic light emitting display panel provided by the embodiment of the present disclosure.
  • the display device may specifically be a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • the pixel circuit, the organic light emitting display panel and the display device described in the present disclosure are particularly suitable for the GOA circuit requirements under the LTPS (Low Temperature Polysilicon Technology) process, and are also applicable to the GOA circuit under the amorphous silicon process.
  • LTPS Low Temperature Polysilicon Technology
  • the pixel circuit and the driving method thereof, the organic light emitting display panel and the display device provided by the embodiment of the present disclosure by setting a potential for controlling the potential of the first end of the storage capacitor to be the input signal of the second level signal input end during the charging phase, a charging unit that controls a potential of the second end of the storage capacitor to be a difference between a potential of the input signal of the first level signal input terminal and a threshold voltage of the driving thin film transistor; for a compensation jump phase after the charging phase, controlling storage
  • the potential of the first end of the capacitor is a data voltage
  • the voltage of the second terminal of the storage capacitor is jumped to a sum of a difference between a data voltage and a potential of the input signal of the first level signal input terminal and a threshold voltage of the driving thin film transistor
  • the current can be prevented from passing through the organic light emitting diode OLED for a long time, thereby reducing the lifetime loss of the organic light emitting diode OLED and prolonging the service life of the organic light emitting diode OLED.
  • the pixel circuit provided by the embodiments of the present disclosure can be applied to a thin film transistor of a process of amorphous silicon, polysilicon, oxide, or the like.
  • the P-type thin is used as a single
  • the film transistor has been described as an example, however, the above circuit can be easily changed to a single N-type thin film transistor or CMOS transistor circuit.
  • the present disclosure is not limited to a display device using an active matrix organic light emitting diode, and can also be applied to a display device using other various light emitting diodes.

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Abstract

一种像素电路及其驱动方法、有机发光显示面板及显示装置。像素电路包括存储电容（Cs）、驱动薄膜晶体管（DTFT）、发光单元（1）、充电单元（2）和补偿跳变单元（3）。充电单元（2）用于在充电阶段，控制存储电容（Cs）第一端（A）的电位为第二电平信号输入端输入信号的电位，控制存储电容（Cs）第二端（B）的电位为第一电平信号输入端输入信号的电位和驱动薄膜晶体管（DTFT）阈值电压之间差值。补偿跳变单元（3）用于在充电阶段之后的补偿跳变阶段，控制存储电容（Cs）第一端（A）的电位为数据电压，使存储电容（Cs）第二端（B）电压跳变为数据电压与第一电平信号输入端输入信号的电位和驱动薄膜晶体管（DTFT）阈值电压之间差值的和，以便发光单元（1）在补偿跳变阶段之后的发光阶段，利用数据电压进行发光。

Description

像素电路及其驱动方法、有机发光显示面板及显示装置
相关申请的交叉引用
本申请主张在2014年5月29日在中国提交的中国专利申请号No.201410234464.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体涉及一种像素电路及其驱动方法、有机发光显示面板及显示装置。
背景技术
有机发光显示器(AMOLED)是当今平板显示器研究领域的热点之一，与液晶显示器相比，有机发光二极管(OLED)具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，目前，在手机、PDA、数码相机等显示领域OLED已经开始取代传统的LCD显示屏。像素驱动电路设计是AMOLED显示器核心技术内容，具有重要的研究意义。
与TFT-LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制发光。在原始的AMLOED两管像素单元电路(2T1C)，如附图1所示，该电路只有1个驱动薄膜晶体管(TFT)，一个开关薄膜晶体管TFT和一个存储电容Cs组成，当扫描线选择某一行时，Vscan为低，开关薄膜晶体管即T1导通，数据电压Vdata写入存储电容Cs，当该行扫描结束后，Vscan变高，T1关断，存储在Cs上的栅极电压驱动T2即驱动薄膜晶体管，使其产生电流来驱动OLED，保证OLED在一帧内持续发光，驱动薄膜晶体管饱和电流公式为IOLED＝K(VGS-Vth)2。
由于工艺制程和器件老化等原因，各像素点的驱动薄膜晶体管的阈值电压(Vth)会漂移，这样就导致了流过每个像素点OLED的电流因阈值电压的变化而变化，使得显示亮度不均，从而影响整个图像的显示效果。
发明内容
本公开提供一种像素电路及其驱动方法、有机发光显示面板及显示装置，可以消除驱动薄膜晶体管的阈值电压对发光驱动电流的影响，从而改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
本公开提供方案如下：
本公开实施例提供了一种像素电路，包括存储电容、驱动薄膜晶体管以及发光单元，其中，驱动薄膜晶体管的源极连接第一电平信号输入端，驱动薄膜晶体管的栅极连接存储电容的第二端，驱动薄膜晶体管的漏极连接发光单元；
所述像素电路还包括：
用于在充电阶段，控制存储电容的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的充电单元；
用于在所述充电阶段之后的补偿跳变阶段，控制存储电容的第一端的电位为数据电压，使存储电容的第二端的电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光的补偿跳变单元。
可选的，所述充电单元，分别与与第二电平信号输入端、第一扫描信号输入端、驱动薄膜晶体管的漏极、存储电容的第一端和第二端连接。
可选的，所述充电单元包括：
第一薄膜晶体管和第二薄膜晶体管；其中：
第一薄膜晶体管的源极与所述第二电平信号输入端连接，第一薄膜晶体管的栅极与第一扫描信号输入端连接，第一薄膜晶体管的漏极与存储电容的第一端连接；
第二薄膜晶体管的源极与驱动薄膜晶体管的漏极连接，第二薄膜晶体管的栅极与第一扫描信号输入端连接，第二薄膜晶体管的漏极与存储电容的第二端连接。
可选的，所述补偿跳变单元，分别与数据线、第二扫描信号输入端以及存储电容的第一端连接。
可选的，所述补偿跳变单元包括：
第三薄膜晶体管；
第三薄膜晶体管的源极与数据线连接，第三薄膜晶体管的栅极与第二扫描信号输入端连接，第三薄膜晶体管的漏极与存储电容第一端连接。
可选的，所述像素电路还包括：
用于在充电阶段之前的重置阶段，控制存储电容的第二端电位为第二电平信号输入端的输入信号的电位的重置单元；
重置单元分别与第二电平信号输入端、第三扫描信号输入端以及存储电容的第二端连接。
可选的，所述重置单元包括：
第四薄膜晶体管；
第四薄膜晶体管的源极与第二电平信号输入端连接，第四薄膜晶体管的栅极与第三扫描信号输入端连接，第四薄膜晶体管的漏极与存储电容的第二端连接。
可选的，所述像素电路还包括：
用于在充电阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至充电单元，以及在发光阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至发光单元的控制单元；
控制单元分别与第一电平信号输入端、控制信号输入端以及驱动薄膜晶体管连接。
可选的，所述控制单元包括：
第五薄膜晶体管；
第五薄膜晶体管的源极与第一电平信号输入端连接，第五薄膜晶体管的栅极与控制信号输入端连接，第五薄膜晶体管的漏极与驱动薄膜晶体管的源极连接。
可选的，所述发光单元包括：
第六薄膜晶体管以及有机发光二极管；其中：
第六薄膜晶体管的源极与驱动薄膜晶体管的漏极连接，第六薄膜晶体管的栅极与第二扫描信号输入端连接，第六薄膜晶体管的漏极与有机发光二极管的阳极连接；
有机发光二极管的阴极与第二电平信号输入端连接。
可选的，所述薄膜晶体管为P型薄膜晶体管；
第一电平信号输入端输入的信号为高电平信号；
第二电平信号输入端输入的信号为低电平信号。
本公开实施例还提供了像素驱动方法，用于驱动上述本公开实施例提供的像素电流，该方法包括：
在充电阶段，控制存储电容的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间差值；
在所述充电阶段之后的补偿跳变阶段，控制存储电容的第一端的电位为数据电压，使存储电容的第二端电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光。
可选的，所述方法还包括：
在充电阶段之前的重置阶段，控制存储电容的第二端的电位为第二电平信号输入端的输入信号的电位。
可选的，所述充电阶段还包括：
将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至存储电容的第二端；
所述发光阶段还包括：
将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至发光单元。
可选的，在重置阶段，第三扫描信号输入端输入低电平信号，重置单元 处于导通状态，第一、二扫描信号输入端和控制信号输入端输入高电平信号，充电单元、补偿跳变单元、发光单元和控制单元处于截止状态；
在充电阶段，控制信号输入端和第一扫描信号输入端输入低电平信号，控制单元和充电单元处于导通状态，第二、三扫描信号输入端输入高电平信号，重置单元、补偿跳变单元和发光单元处于截止状态；
在补偿跳变阶段，第二扫描信号输入端输入低电平信号，补偿跳变单元和发光单元处于导通状态，第一、三扫描信号输入端和控制信号输入端输入高电平信号，重置单元、充电单元和控制单元处于截止状态；
在发光阶段，第二扫描信号输入端和控制信号输入端输入低电平信号，控制单元、补偿跳变单元和发光单元处于导通状态，第一、三扫描信号输入端输入高电平信号，重置单元和充电单元处于截止状态。
可选的，在充电阶段和补偿跳变阶段，数据线传输信号的电位为负电压，在重置阶段和发光阶段，数据线传输信号的电位为正电压。
本公开实施例还提供了一种有机发光显示面板，包括上述本公开实施例提供的像素电路。
本公开实施例还提供了一种显示装置，包括上述本公开实施例提供的有机发光显示面板。
从以上所述可以看出，本公开实施例提供的像素电路及其驱动方法、有机发光显示面板及显示装置，通过设置用于在充电阶段，控制存储电容的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的充电单元；用于在所述充电阶段之后的补偿跳变阶段，控制存储电容的第一端的电位为数据电压，使存储电容的第二端电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光的补偿跳变单元。可以消除驱动薄膜晶体管的阈值电压对发光驱动电流的影响，从而改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
附图说明
图1为现有技术示意图。
图2为本公开实施例提供的像素电路示意图一；
图3为本公开实施例提供的像素电路示意图二；
图4为本公开实施例提供的像素电路示意图三；
图5为本公开实施例提供的像素电路示意图四；
图6为本公开实施例提供的像素电路示意图五；
图7为本公开实施例提供的像素电路示意图六；
图8为本公开实施例提供的像素电路示意图七；
图9为本公开实施例提供的像素驱动方法流程示意图；
图10为本公开实施例提供的信号时序示意图；
图11为本公开实施例提供的像素电路状态示意图一；
图12为本公开实施例提供的像素电路状态示意图二；
图13为本公开实施例提供的像素电路状态示意图三；
图14为本公开实施例提供的像素电路状态示意图四。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类 似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例提供了一种像素电路，如附图2所示，包括存储电容Cs、驱动薄膜晶体管DTFT以及发光单元1，其中，驱动薄膜晶体管DTFT的源极连接第一电平信号输入端，驱动薄膜晶体管DTFT的栅极连接存储电容Cs的第二端，驱动薄膜晶体管DTFT的漏极连接发光单元1；
所述像素电路还包括：
用于在充电阶段，控制存储电容Cs的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容Cs的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管DTFT的阈值电压Vth之间的差值的充电单元2；
用于在充电阶段之后的补偿跳变阶段，控制存储电容Cs的第一端的电位为数据电压Vdata，使存储电容Cs的第二端电压跳变为数据电压Vdata与第一电平信号输入端的输入信号的电位和驱动薄膜晶体管DTFT的阈值电压Vth之间的差值的和，以便发光单元1在补偿跳变阶段之后的发光阶段，利用数据电压Vdata进行发光的补偿跳变单元3。
本公开实施例所提供的像素电路，可以使有机发光二极管(OLED)的驱动电流IOLED不受驱动薄膜晶体管的阈值电压Vth的影响，从而使有机发光显示面板中的不同像素单元内的OLED驱动电流一致，可改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
在本公开实施例中，所涉及的第一电平信号输入端输入的信号，具体可为高电平信号，例如Vdd等。
而在本公开实施例中，第二电平信号输入端输入的信号具体可为低电平信号，也可以使第二电平信号输入端直接接地，从而使第二电平信号输入端输入零电位信号。
那么，上述存储电容Cs第二端在充电阶段的电位即可为Vdd-Vth，在补偿跳阶段的电位为Vdd-Vth+Vdata。
本公开实施例中，如附图2所示，充电单元2具体可分别与第二电平信号输入端、第一扫描信号输入端(扫描1)、驱动薄膜晶体管DTFT的漏极、存储电容Cs的第一端(节点A)和第二端(节点B)连接。
在一具体实施例中，如附图3所示，充电单元2具体可以包括：
第一薄膜晶体管T1和第二薄膜晶体管T2；其中：
第一薄膜晶体管T1的源极与第二电平信号输入端连接，第一薄膜晶体管T1的栅极与第一扫描信号输入端(扫描1)连接，第一薄膜晶体管T1的漏极与存储电容Cs的第一端连接；
第二薄膜晶体管T2的源极与驱动薄膜晶体管DTFT的漏极连接，第二薄膜晶体管T2的栅极与第一扫描信号输入端(扫描1)连接，第二薄膜晶体管T2的漏极与存储电容Cs的第二端连接。
在充电阶段，第一薄膜晶体管T1和第二薄膜晶体管T2在第一扫描信号输入端输入的第一扫描信号Vscan1的控制下处于导通状态，则第一薄膜晶体管T1将第二电平信号输入端的输入信号传输至存储电容Cs第一端即节点A，从而使节点A的电位为第二电平信号输入端的输入信号的电位，例如零，而第二薄膜晶体管T2将第一电平信号输入端的输入信号，例如Vdd传输至存储电容Cs的第二端即节点B(在充电阶段，驱动薄膜晶体管DTFT处于导通状态)，从而为节点B充电，直至节点B的电位为Vdd-Vth。此时，由于节点A的电位具体可为零，因此，存储电容Cs两端即节点A、B间的压差为(Vdd-Vth)。
本公开实施例中，如附图2所示，所述补偿跳变单元3，分别与数据线、第二扫描信号输入端(扫描2)以及存储电容Cs的第一端连接。
在一具体实施例中，如附图3所示，补偿跳变单元3具体可以包括：
第三薄膜晶体管T3；
第三薄膜晶体管T3的源极与数据线连接，第三薄膜晶体管T3的栅极与第二扫描信号输入端(扫描2)连接，第三薄膜晶体管T3的漏极与存储电容Cs的第一端连接。
在补偿跳变阶段，第三薄膜晶体管T3在第二扫描信号输入端输入的第二扫描信号Vscan2的控制下处于导通状态，从而将数据线所传输的信号传输至存 储电容Cs第一端，由于存储电容Cs第一端的电位为第二电平信号输入端的输入信号的电位，如零，从而使存储电容Cs第一端的电位由0变为Vdata。
由于在补偿跳变阶段，存储电容Cs的第二端即节点B为浮接状态，因此要维持存储电容Cs的两端即节点A、B原来的压差(Vdd-Vth)，那么在节点A的电位Vdata的情况下，节点B的电位会发生等压跳变，即节点B的电位跳变为Vdd--Vth+Vdata，并维持该电位不变，以为后续的发光阶段作准备。
在本公开的一个具体实施例中，为了确保存储电容Cs第二端(即节点B)的电位在充电阶段为第一电平信号输入端的输入信号Vdd的电位和驱动薄膜晶体管DTFT的阈值电压Vth之间的差值，可在充电阶段之前的重置阶段，对存储电容Cs第二端进行放电重置操作。
因此，本公开实施例所提供的像素电路，如附图4所示，具体还可以包括：
用于在充电阶段之前的重置阶段，控制存储电容Cs的第二端的电位为第二电平信号输入端的输入信号的电位的重置单元4。
具体的，如附图4所示，重置单元4分别与第二电平信号输入端、第三扫描信号输入端(扫描3)以及存储电容Cs的第二端连接。
在一具体实施例中，如附图5所示，重置单元4具体可以包括：
第四薄膜晶体管T4；
第四薄膜晶体管T4的源极与第二电平信号的输入端连接，第四薄膜晶体管T4的栅极与第三扫描信号输入端Scan3连接，第四薄膜晶体管T4的漏极与存储电容Cs的第二端连接。
由于第二电平信号输入端的输入信号的电位具体可为零，因此，在重置阶段可使存储电容Cs第二端的电位重置归零。
并且，存储电容Cs的第二端电位重置归零，还可使驱动薄膜晶体管DTFT处于导通状态直至在充电阶段，从而在充电阶段使第一电平信号输入端输入的信号(例如Vdd)可以经过驱动薄膜晶体管DTFT传输至充电单元2(具体可为第二薄膜晶体管T2的源极)，以便充电单元2在充电阶段利用第一电平信号输入端输入的信号(例如Vdd)，将存储电容Cs的第二端充电至Vdd-Vth。
在本公开实施例中，为了实现对第一电平信号输入端的输入信号的控制，如附图6所示，像素电路具体还可以包括：
用于在充电阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管DTFT，以使所述信号经过驱动薄膜晶体管DTFT传输至充电单元，以及在发光阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管DTFT，以使所述信号经过驱动薄膜晶体管DTFT传输至发光单元1的控制单元5。
具体的，如附图6所示，控制单元5可分别与第一电平信号输入端、控制信号输入端EM以及驱动薄膜晶体管DTFT连接。
在一具体实施例中，如附图7所示，控制单元5具体可以包括：
第五薄膜晶体管T5；
第五薄膜晶体管T5的源极与第一电平信号输入端连接，第五薄膜晶体管T5的栅极与控制信号输入端EM连接，第五薄膜晶体管T5的漏极与驱动薄膜晶体管DTFT的源极连接。
需要说明的是，在本公开实施例中，控制单元5可为可选器件，在本公开的其他实施例中，可通过控制第二电平信号的输入时序，以实现并替代控制单元5的作用。
本公开实施例中，如附图8所示，发光单元1具体可以包括：
第六薄膜晶体管T6以及有机发光二极管OLED；其中：
第六薄膜晶体管T6的源极与驱动薄膜晶体管DTFT的漏极连接，第六薄膜晶体管T6的栅极与第二扫描信号输入端(扫描2)连接，第六薄膜晶体管T6的漏极与有机发光二极管OLED的阳极连接；
有机发光二极管OLED的阴极与第二电平信号输入端连接。
由于在发光阶段，控制单元以及第六薄膜晶体管均处于导通状态，因此，第一电平信号输入端输入的信号如Vdd可以传输至驱动薄膜晶体管DTFT的源极，从而使驱动薄膜晶体管的栅源电压VGS＝Vdd-(Vdd-Vth+Vdata)。
由驱动薄膜晶体管DTFT的饱和电流公式可以得到：
IOLED＝K(VGS-Vth)2
＝K[Vdd-(Vdd-Vth+Vdata)-Vth]2
＝K(Vdata)2
其中，VGS为驱动薄膜晶体管DTFT的栅源电压，K为与驱动薄膜晶体管DTFT的生产工艺和驱动设计有关的常数。
通过上述计算结果可以看出，本公开实施例所提供的像素电路，可以使有机发光二极管OLED的驱动电流与驱动薄膜晶体管DTFT的阈值电压Vth无关，而只取决于数据电压Vdata，因此，本公开实施例提供的像素电路可以消除驱动薄膜晶体管的阈值电压对发光驱动电流的影响，从而改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
在本公开一可选实施例中，上述本公开实施例所涉及的薄膜晶体管，包括第一薄膜晶体管T1至第六薄膜晶体管T6，以及驱动薄膜晶体管DTFT，具体均可为P型晶体管，且上述晶体管中的源、漏极可互换。
那么，为了使P型的驱动薄膜晶体管DTFT在发光阶段处于导通状态，本公开实施例中所涉及的数据电压Vdata具体可为负电压，从而使计算公式Vdd-Vth+Vdata的值为负值，使P型的驱动薄膜晶体管DTFT在发光阶段为导通状态，以便有机发光二极管(OLED)的驱动电流IOLED经过驱动薄膜晶体管DTFT传输至有机发光二极管OLED，以使有机发光二极管OLED发光。
本公开实施例还提供了一种像素驱动方法，用于驱动上述本公开实施例提供的像素电路，如附图9所示，该方法具体可以包括：
在充电阶段，控制存储电容Cs第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容Cs第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管DTFT的阈值电压Vth之间差值；
在所述充电阶段之后的补偿跳变阶段，控制存储电容Cs第一端的电位为数据电压Vdata，使存储电容Cs第二端电压跳变为数据电压Vdata与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管DTFT的阈值电压Vth之间差值的和，以便发光单元1在补偿跳变阶段之后的发光阶段，利用所述数据电压Vdata进行发光。
本公开实施例所提供的像素电路，可以使有机发光二极管(OLED)的驱动电流IOLED不受驱动薄膜晶体管阈值电压Vth的影响，从而使有机发光显示 面板中不同像素单元内的OLED驱动电流一致，可改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
本公开实施例中，所涉及的第一电平信号输入端输入的信号，具体可为高电平信号，例如Vdd等。
而在本公开实施例中，第二电平信号输入端输入的信号具体可为低电平信号，也可以使第二电平信号输入端直接接地，从而使第二电平信号输入端输入零电位信号。
那么，上述存储电容Cs第二端在充电阶段的电位即可为Vdd-Vth，在补偿跳阶段的电位为Vdd-Vth+Vdata。
在一具体实施例中，所述方法还可以包括：
在充电阶段之前的重置阶段，控制存储电容Cs第二端电位为第二电平信号输入端的输入信号的电位。
在一具体实施例中，所述充电阶段具体还可以包括：
将第一电平信号输入端输入的信号传输至驱动薄膜晶体管DTFT，以使所述信号经过驱动薄膜晶体管DTFT传输至存储电容Cs第二端；
在一具体实施例中，所述发光阶段具体还可以包括：
将第一电平信号输入端输入的信号传输至驱动薄膜晶体管DTFT，以使所述信号经过驱动薄膜晶体管DTFT传输至发光单元1。
下面，对本公开实施例提供的像素驱动方法的一个具体实施例的实现过程进行详细的描述。
该实施例中，本公开实施例提供的像素驱动方法具体可应用于如附图8所示的像素电路中，且该电路中，所有的薄膜晶体管均为P型薄膜晶体管，第一电平信号输入端输入的信号为Vdd，第二电平信号输入端接地。该实施例所涉及的信号输入时序图可如附图10所示。
该实施例的具体实现过程可以包括：
在重置阶段(附图10中1阶段)，第三扫描信号输入端(扫描3)输入低电平信号，重置单元4处于导通状态，即第四薄膜晶体管T4处于导通状态，第一扫描信号输入端(扫描1)、第二扫描信号输入端(扫描2)和控制信号 输入端EM输入高电平信号，发光单元1、充电单元2、补偿跳变单元3和控制单元5处于截止状态，即第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第五薄膜晶体管T5和第六薄膜晶体管T6处于截止状态，此阶段中像素电路的状态示意图可如附图11所示。
由于在重置阶段，第四薄膜晶体管T4导通，因此，将存储电容Cs的第二端即节点B重置接地，节点B的电位为0V，从而实现将节点B之前的电压信号进行重置。
在充电阶段(附图10中2阶段)，控制信号输入端EM和第一扫描信号输入端(扫描1)输入低电平信号，控制单元5和充电单元2处于导通状态，即第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5处于导通状态，第二扫描信号输入端(扫描2)、第三扫描信号输入端(扫描3)输入高电平信号，重置单元4、补偿跳变单元3和发光单元1处于截止状态，即第三薄膜晶体管T3、第四薄膜晶体管T4和第六薄膜晶体管T6处于截止状态，此阶段中像素电路的状态示意图可如附图12所示。
由于在重置阶段节点B的电位已经接地，所以，在充电阶段，驱动薄膜晶体管DTFT处于导通状态，那么，Vdd信号通过第五薄膜晶体管T5→驱动薄膜晶体管DTFT→第二薄膜晶体管T2，开始对节点B进行充电，一直将节点B充电至Vdd-Vth为止(满足驱动薄膜晶体管DTFT的栅源两极之间的压差为Vth)，在充电过程中，由于节点A的电位始终为零，所以当充电阶段结束之后，节点B的电位会一直维持在Vdd-Vth。另外，由于在充电阶段第六薄膜晶体管T6始终处于关闭状态，使得电流不会通过有机发光二极管OLED，从而可降低有机发光二极管OLED的寿命损耗，延长了有机发光二极管OLED的使用寿命。
在补偿跳变阶段(附图10中3阶段)，第二扫描信号输入端(扫描2)输入低电平信号，补偿跳变单元3和发光单元1处于导通状态，即第三薄膜晶体管T3和第六薄膜晶体管T6处于导通状态，第一扫描信号输入端(扫描1)、第三扫描信号输入端(扫描3)和控制信号输入端EM输入高电平信号，重置单元4、充电单元2和控制单元5处于截止状态，即第一薄膜晶体管T1、 第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5处于截止状态，此阶段中像素电路的状态示意图可如附图13所示。
由于在补偿跳变阶段第三薄膜晶体管T3处于导通状态，因此，节点A的电位由零跳变至Vdata，而由于节点B为浮接状态，因此要维持存储电容Cs两端即节点A、B原来的压差(Vdd-Vth)，那么在节点A的电位Vdata的情况下，节点B的电位会发生等压跳变，即节点B的电位跳变为Vdd-Vth+Vdata，并维持该电位不变，以为后续的发光阶段作准备。
在发光阶段(附图10中4阶段)，第二扫描信号输入端(扫描2)和控制信号输入端EM输入低电平信号，控制单元5、补偿跳变单元3和发光单元1处于导通状态，即第三薄膜晶体管T3、第五薄膜晶体管T5和第六薄膜晶体管T6处于导通状态；第一扫描信号输入端(扫描1)和第三扫描信号输入端(扫描3)输入高电平信号，重置单元4和充电单元2处于截止状态，即第一薄膜晶体管T1、第二薄膜晶体管T2和第四薄膜晶体管T4处于截止状态，此阶段中像素电路的状态示意图可如附图14所示。
由于在发光阶段，第五薄膜晶体管T5处于导通状态，因此，驱动薄膜晶体管DTFT源极的电位为Vdd，电流通过第五薄膜晶体管T5→驱动薄膜晶体管DTFT→第六薄膜晶体管T6，使得有机发光二极管OLED开始发光。
由驱动薄膜晶体管DTFT饱和电流公式可以得到：
IOLED＝K(VGS-Vth)2
＝K[Vdd-(Vdd-Vth+Vdata)-Vth]2
＝K(Vdata)2
其中，VGS为驱动薄膜晶体管DTFT的栅源电压，K为与驱动薄膜晶体管DTFT生产工艺和驱动设计有关的常数。
由上式中可以看到此时工作电流IOLED已经不受驱动薄膜晶体管DTFT的阈值电压Vth的影响，而只与数据电压Vdata有关，从而彻底解决了驱动薄膜晶体管DTFT由于工艺制程及长时间的操作造成阈值电压Vth漂移的问题，消除其对IOLED的影响，保证不同像素单元内有机发光二极管OLED正常工作。从而改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
同时，从附图10中可以看出，本公开实施例中，在充电阶段和补偿跳变阶段，数据电压Vdata为负电压，在重置阶段和发光阶段，数据电压Vdata为正电压。
基于本公开实施例提供的像素电路，本公开实施例还提供了一种有机发光显示面板，该有机发光显示面板具体可以包括上述本公开实施例提供的像素电路。
本公开实施例还提供了一种显示装置，该显示装置具体可以包括上述本公开实施例提供的有机发光显示面板。
该显示装置具体可以为液晶面板、液晶电视、液晶显示器、OLED面板、OLED显示器、等离子显示器或电子纸等显示装置。
本公开所述的像素电路、有机发光显示面板与显示装置特别适合LTPS(低温多晶硅技术)制程下的GOA电路需求，也可适用于非晶硅工艺下的GOA电路。
本公开实施例提供的像素电路及其驱动方法、有机发光显示面板及显示装置，通过设置用于在充电阶段，控制存储电容第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间差值的充电单元；用于在所述充电阶段之后的补偿跳变阶段，控制存储电容第一端的电位为数据电压，使存储电容第二端电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光的补偿跳变单元。可以消除驱动薄膜晶体管的阈值电压对发光驱动电流的影响，从而改善有机发光显示面板亮度的均匀性，提高显示装置的图像显示效果。
同时，本公开实施例技术方案中，还可以避免电流长时间通过有机发光二极管OLED，从而可降低有机发光二极管OLED的寿命损耗，延长了有机发光二极管OLED的使用寿命。
需指出的是，本公开实施例所提供的像素电路可适用于非晶硅、多晶硅、氧化物等工艺的薄膜晶体管。同时，尽管上述实施例中，以单一采用P型薄 膜晶体管为例进行了说明，然而，上述电路还可以轻易的改成采用单一的N型薄膜晶体管或CMOS管电路。而且，尽管上述实施例中以有源矩阵有机发光二极管为例进行了说明，然而本公开不限于使用有源矩阵有机发光二极管的显示装置，也可以应用于使用其他各种发光二极管的显示装置。
以上所述仅是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (18)

  1. 一种像素电路，包括存储电容、驱动薄膜晶体管以及发光单元，其中，驱动薄膜晶体管的源极连接第一电平信号输入端，驱动薄膜晶体管的栅极连接存储电容的第二端，驱动薄膜晶体管的漏极连接发光单元；
    所述像素电路还包括：
    用于在充电阶段，控制存储电容的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的充电单元；
    用于在所述充电阶段之后的补偿跳变阶段，控制存储电容的第一端的电位为数据电压，使存储电容的第二端电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光的补偿跳变单元。
  2. 如权利要求1所述的像素电路，其中，所述充电单元分别与第二电平信号输入端、第一扫描信号输入端、驱动薄膜晶体管的漏极、存储电容的第一端和第二端连接。
  3. 如权利要求2所述的像素电路，其中，所述充电单元包括：
    第一薄膜晶体管和第二薄膜晶体管；其中：
    第一薄膜晶体管的源极与所述第二电平信号输入端连接，第一薄膜晶体管的栅极与第一扫描信号输入端连接，第一薄膜晶体管的漏极与存储电容的第一端连接；
    第二薄膜晶体管的源极与驱动薄膜晶体管的漏极连接，第二薄膜晶体管的栅极与第一扫描信号输入端连接，第二薄膜晶体管的漏极与存储电容的第二端连接。
  4. 如权利要求1所述的像素电路，其中，所述补偿跳变单元，分别与数据线、第二扫描信号输入端以及存储电容的第一端连接。
  5. 如权利要求4所述的像素电路，其中，所述补偿跳变单元包括：
    第三薄膜晶体管；
    第三薄膜晶体管的源极与数据线连接，第三薄膜晶体管的栅极与第二扫描信号输入端连接，第三薄膜晶体管的漏极与存储电容的第一端连接。
  6. 如权利要求1所述的像素电路，其中，还包括：
    用于在充电阶段之前的重置阶段，控制存储电容的第二端电位为第二电平信号输入端的输入信号的电位的重置单元；
    重置单元分别与第二电平信号输入端、第三扫描信号输入端以及存储电容的第二端连接。
  7. 如权利要求6所述的像素电路，其中，所述重置单元包括：
    第四薄膜晶体管；
    第四薄膜晶体管的源极与第二电平信号输入端连接，第四薄膜晶体管的栅极与第三扫描信号输入端连接，第四薄膜晶体管的漏极与存储电容的第二端连接。
  8. 如权利要求1所述的像素电路，其中，还包括：
    用于在充电阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至充电单元，以及在发光阶段将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至发光单元的控制单元；
    控制单元分别与第一电平信号输入端、控制信号输入端以及驱动薄膜晶体管连接。
  9. 如权利要求8所述的像素电路，其中，所述控制单元包括：
    第五薄膜晶体管；
    第五薄膜晶体管的源极与第一电平信号输入端连接，第五薄膜晶体管的栅极与控制信号输入端连接，第五薄膜晶体管的漏极与驱动薄膜晶体管的源极连接。
  10. 如权利要求1所述的像素电路，其中，所述发光单元包括：
    第六薄膜晶体管以及有机发光二极管；其中：
    第六薄膜晶体管的源极与驱动薄膜晶体管的漏极连接，第六薄膜晶体管 的栅极与第二扫描信号输入端连接，第六薄膜晶体管的漏极与有机发光二极管的阳极连接；
    有机发光二极管的阴极与第二电平信号输入端连接。
  11. 如权利要求1至10任一项所述的像素电路，其中，所述薄膜晶体管为P型薄膜晶体管；
    第一电平信号输入端输入的信号为高电平信号；
    第二电平信号输入端输入的信号为低电平信号。
  12. 一种用于驱动权利要求1-11中的任意一项所述的像素电路的像素驱动方法，包括：
    在充电阶段，控制存储电容的第一端的电位为第二电平信号输入端的输入信号的电位，控制存储电容的第二端的电位为第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值；
    在所述充电阶段之后的补偿跳变阶段，控制存储电容的第一端的电位为数据电压，使存储电容的第二端电压跳变为数据电压与所述第一电平信号输入端的输入信号的电位和驱动薄膜晶体管的阈值电压之间的差值的和，以便发光单元在补偿跳变阶段之后的发光阶段，利用所述数据电压进行发光。
  13. 如权利要求12所述的像素驱动方法，其中，还包括：
    在充电阶段之前的重置阶段，控制存储电容的第二端的电位为第二电平信号输入端的输入信号的电位。
  14. 如权利要求13所述的像素驱动方法，其中，所述充电阶段还包括：
    将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至存储电容的第二端；
    所述发光阶段还包括：
    将第一电平信号输入端输入的信号传输至驱动薄膜晶体管，以使所述信号经过驱动薄膜晶体管传输至发光单元。
  15. 如权利要求14所述的像素驱动方法，其中，在重置阶段，第三扫描信号输入端输入低电平信号，重置单元处于导通状态，第一、二扫描信号输入端和控制信号输入端输入高电平信号，充电单元、补偿跳变单元、发光单 元和控制单元处于截止状态；
    在充电阶段，控制信号输入端和第一扫描信号输入端输入低电平信号，控制单元和充电单元处于导通状态，第二、三扫描信号输入端输入高电平信号，重置单元、补偿跳变单元和发光单元处于截止状态；
    在补偿跳变阶段，第二扫描信号输入端输入低电平信号，补偿跳变单元和发光单元处于导通状态，第一、三扫描信号输入端和控制信号输入端输入高电平信号，重置单元、充电单元和控制单元处于截止状态；
    在发光阶段，第二扫描信号输入端和控制信号输入端输入低电平信号，控制单元、补偿跳变单元和发光单元处于导通状态，第一、三扫描信号输入端输入高电平信号，重置单元和充电单元处于截止状态。
  16. 如权利要求15所述的像素驱动方法，其中，在充电阶段和补偿跳变阶段，数据线传输信号的电位为负电压，在重置阶段和发光阶段，数据线传输信号的电位为正电压。
  17. 一种有机发光显示面板，其特征在于，包括所述权利要求1-11中的任意一项所述的像素电路。
  18. 一种显示装置，包括如权利要求17所述的有机发光显示面板。
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