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WO2015096723A1 - 一种增强型器件的制造方法 - Google Patents

一种增强型器件的制造方法 Download PDF

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Publication number
WO2015096723A1
WO2015096723A1 PCT/CN2014/094757 CN2014094757W WO2015096723A1 WO 2015096723 A1 WO2015096723 A1 WO 2015096723A1 CN 2014094757 W CN2014094757 W CN 2014094757W WO 2015096723 A1 WO2015096723 A1 WO 2015096723A1
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nitride
layer
barrier layer
manufacturing
gate
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PCT/CN2014/094757
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to EP14874311.5A priority Critical patent/EP3089201A4/en
Priority to JP2016542926A priority patent/JP2017502519A/ja
Publication of WO2015096723A1 publication Critical patent/WO2015096723A1/zh
Priority to US15/190,690 priority patent/US10026834B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present invention relates to the field of semiconductor electronic technology, and in particular to a method of fabricating an enhanced device.
  • the third-generation semiconductor material gallium nitride has the characteristics of large band gap, high electron saturation drift speed, high breakdown field strength and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable than silicon and gallium arsenide. Manufacturing high temperature, high frequency, high voltage and high power semiconductor devices.
  • the High Electron Mobility Transistor (HEMT) formed by the AlGaN/GaN heterojunction is a depletion device.
  • Devices are not easy to implement.
  • the application of depletion devices has certain limitations.
  • an enhanced (normally closed) switching device is required.
  • the enhanced GaN switching device is mainly used for high frequency devices, power switching devices and digital circuits, and its research is of great significance.
  • One method is to use an etched structure at the gate to locally thin the thickness of the aluminum gallium nitride layer under the gate to achieve the purpose of controlling or reducing the concentration of the two-dimensional electron gas under the gate, as shown in FIG. 11.
  • the gallium nitride layer 12 and the aluminum gallium nitride layer 13 are respectively disposed on the substrate 10.
  • the gate 14, the source 15 and the drain 16 are respectively located on the aluminum gallium nitride layer 13, wherein the aluminum gallium nitride layer is below the gate 4. It is partially etched to thin the thickness of the aluminum gallium nitride layer in the gate region.
  • Another method is to selectively retain p-type (Al) GaN under the gate and lift the conduction band level at the aluminum gallium nitride/gallium nitride heterojunction through p-type (Al) GaN to form a depletion region.
  • a local p-type nitride 17 is selectively retained under the gate 14'.
  • Another method is fluoride plasma treatment technology, which injects negatively charged ions such as fluoride ions into the barrier layer, and controls the concentration of the implanted ions to deplete the two-dimensional electron gas in the conductive channel, which needs to be pinched off with strong negative ions.
  • a channel as shown in FIG. 3, implants a negative ion in the barrier layer 13 below the gate 14" 18.
  • the threshold voltage is generally around 0V-1V, and the applied threshold voltage is not reached 3V-5V.
  • additional dielectric layers such as atomic layer deposition, are needed. Al2O3, however, how this interface between the dielectric layer and the aluminum gallium nitride surface is controlled is an unresolved big problem.
  • the second method it is necessary to selectively etch all areas except the underside of the gate, and how to achieve precise control of the etching thickness is also very challenging, in addition, due to defects in etching, and Residual magnesium atoms in p-type aluminum gallium nitride cause severe current collapse effects.
  • the density of two-dimensional electron gas in the AlGaN/GaN heterojunction is greatly affected. limits. If the density of electrons in the two-dimensional electron gas is too high, an enhanced device cannot be realized. Therefore, in the AlGaN/GaN heterojunction of the enhanced device, the aluminum content is usually less than 20%, such as about 15%.
  • fluoride plasma treatment destroys the lattice structure, and the process repeatability is also poor, which has a relatively large impact on the stability and reliability of the device.
  • the present invention discloses a method of fabricating an enhanced device that achieves the principle of pinching off a two-dimensional electron gas according to the characteristics of a group III nitride being a polar semiconductor, see FIG. 4 and FIG.
  • a group III nitride being a polar semiconductor
  • the present invention discloses a method of fabricating an enhanced device that achieves the principle of pinching off a two-dimensional electron gas according to the characteristics of a group III nitride being a polar semiconductor, see FIG. 4 and FIG.
  • the group III nitride being a polar semiconductor
  • the concentration of the two-dimensional electron gas may exceed 1E13/cm 2 .
  • the spontaneously polarized electric field and the piezoelectric electric field in the group III nitride exist only in the ⁇ 0002> direction, not the polarity direction, that is, the direction perpendicular to the ⁇ 0002> direction, including ⁇ 1-100>, ⁇ 11- 20> etc.
  • the semi-polar direction for example, in the direction between ⁇ 0002> and ⁇ 1-100> or ⁇ 11-20>, the built-in electric field strength in this direction is also much smaller than the ⁇ 0002> direction.
  • a two-dimensional electron gas having a high electron concentration can be generated without intentional doping.
  • a non-polar or semi-polar plane of a gallium nitride material since the polarization field strength is hardly or very low, a two-dimensional electron gas is not generated without being doped.
  • the gate region of the layer forms a non-planar structure, and the nitride non-polar surface, the semi-polar surface or a combination of the two generated in the non-planar structure causes the interruption of the two-dimensional electron gas in the gate region, thereby realizing the enhanced type. Device.
  • the gate region of the channel layer forms a non-planar structure, and the nitride non-polar surface and the half-pole are generated in the non-planar structure.
  • the nature of the face or the combination of the two can cause the interruption of the two-dimensional electron gas, so there is no need to etch the barrier layer, and the device performance degradation caused by the damage of the active region is avoided, such as low current density or current collapse.
  • the introduction of Mg atoms to achieve p-type nitride is not required, and contamination of the MOCVD or MBE cavity is avoided.
  • a method of fabricating an enhanced device comprising:
  • nitride channel layer on the substrate, wherein the nitride channel layer defines a gate region, a source region and a drain region, and a gate region of the nitride channel layer is formed At least one non-planar structure;
  • a nitride barrier layer on the nitride channel layer, the nitride barrier layer being formed with at least one non-planar structure, forming a nitride channel layer/nitride barrier layer heterojunction, a non-polar or semi-polar surface of the nitride at a non-planar structure or a combination thereof, wherein the two-dimensional electron gas in the nitride channel layer/nitride barrier layer heterojunction channel is at least partially interrupted;
  • step S1 further includes:
  • At least one non-planar structure is fabricated in the substrate.
  • step S1 further includes:
  • a nitride buffer layer is deposited on the substrate, and at least one non-planar structure is formed on the nitride buffer layer.
  • the non-planar structure includes grooves, protrusions, and steps.
  • the cross-sectional shape of the groove includes a combination of one or more of a rectangle, a triangle, a trapezoid, a zigzag, a polygon, a semicircle, and a U shape.
  • the cross-sectional shape of the protrusion includes a combination of one or more of a rectangle, a triangle, a trapezoid, a zigzag, a polygon, a semicircle, and a U shape.
  • the step of the step is a vertical surface, or a sloped surface, or a curved surface, or an irregularly shaped surface.
  • the step S1 further comprises depositing a nitride nucleation layer on the substrate.
  • the step S3 further comprises: depositing a dielectric layer on the nitride barrier layer.
  • the dielectric layer is a combination of one or more of SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO.
  • the step S3 further comprises: depositing a nitride layer on the nitride barrier layer, the nitride layer being gallium nitride or aluminum gallium nitride.
  • the step S2 further comprises: depositing an aluminum nitride intermediate layer on the nitride channel layer.
  • the method for fabricating the enhanced device of the present invention does not require etching the nitride barrier layer, thereby avoiding degradation of device performance due to damage of the active region, such as low current density or current collapse.
  • the introduction of Mg atoms to achieve p-type nitride is not required, and contamination of the MOCVD or MBE cavity is avoided.
  • 1 is a schematic view showing the structure of an enhanced device for controlling or reducing the concentration of two-dimensional electron gas under the gate by thinning the thickness of the aluminum gallium nitride layer under the gate;
  • FIG. 3 is a schematic structural view of an enhanced device using fluorine ion treatment under the gate in the prior art
  • Figure 4 is a schematic view of a nitride lattice structure
  • Figure 5 is a schematic diagram of the built-in electric field distribution in different directions in the nitride
  • FIGS. 6A-6G are schematic diagrams showing a manufacturing process of the enhanced device of the first embodiment of the present invention, wherein FIG. 6G is a schematic structural view of the enhanced device of the first embodiment;
  • FIGS. 7A-7G are schematic diagrams showing the manufacturing process of the enhanced device of the second embodiment of the present invention, wherein FIG. 7G is a schematic structural view of the enhanced device of the second embodiment;
  • FIGS. 8A-8G are schematic diagrams showing a manufacturing process of an enhanced device according to a third embodiment of the present invention, wherein FIG. 8G is a schematic structural view of the enhanced device in the third embodiment;
  • FIGS. 9A-9G are schematic diagrams showing the manufacturing process of the enhanced device of the fourth embodiment of the present invention, wherein FIG. 9G is a schematic structural view of the enhanced device of the fourth embodiment;
  • FIG. 10 is a schematic structural view of augmented device according to a fifth embodiment of the present invention.
  • FIG. 11 is a schematic structural view of augmented device of a sixth embodiment of the present invention.
  • FIG. 6A-6G are schematic diagrams showing a manufacturing process of the enhanced device according to the first embodiment of the present invention, wherein FIG. 6G is a schematic structural view of the enhanced device in the first embodiment.
  • the enhanced device in this embodiment includes:
  • nitride nucleation layer 2 on the substrate 1;
  • nitride buffer layer 3 on the nitride nucleation layer 2;
  • nitride channel layer 4 on the nitride buffer layer 3;
  • dielectric layer 6 on the nitride barrier layer 5, the dielectric layer 6 being a combination of one or more of SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO;
  • the nitride channel layer 4 and the nitride barrier layer 5 are provided with at least one non-planar structure in a region below the gate, and a non-polar or semi-polar surface of the nitride at a non-planar structure or a combination thereof.
  • the two-dimensional electron gas in the nitride channel layer 4/nitride barrier layer 5 heterojunction channel is at least partially interrupted in the region under the gate.
  • the substrate 1, the nitride nucleation layer 2, the nitride buffer layer 3, the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 are all provided with a non-planar structure, and The planar structure is set as a rectangular groove.
  • the method of manufacturing the enhanced device of this embodiment includes the steps of:
  • a substrate 1 is provided in which a rectangular recess is formed in the substrate 1.
  • the material of the substrate may be sapphire, silicon carbide, silicon, lithium niobate, SOI, gallium nitride and aluminum nitride. Wait.
  • a nitride nucleation layer 2 such as AlN or the like is deposited on the substrate 1.
  • a nitride buffer layer 3 such as AlGaN or the like is deposited on the nitride nucleation layer 2.
  • a nitride channel layer 4 such as GaN or the like is deposited on the nitride buffer layer 3, and the nitride channel layer 4 has a groove 41 transferred from the groove of the substrate, which The position of the groove 41 corresponds to a gate region defined on the epitaxial multilayer structure.
  • the surface of the nitride channel layer 4 is a polar plane, that is, a (0002) plane, and At least two sides of the groove 41 form an angle with the surface of the nitride channel layer 4, that is, the sides are in a non-0002 direction, such as a (1-100) plane, a (11-20) plane, (1) -101) Face, (11-22) face, etc.
  • a nitride barrier layer 5 is deposited on the nitride channel layer 4, and a portion of the nitride barrier layer 5 above the recess 41 also has a recess 51 corresponding to the recess 41, According to the above analysis, there is a non-polar or semi-polar plane of nitride or a combination thereof at the groove, and thus, two of the heterojunction channels formed in the nitride channel layer 4/nitride barrier layer 5 are formed.
  • the dimension electron gas is interrupted in the gate region, so that when the gate voltage is zero, the carrier concentration of the gate can be effectively controlled.
  • a dielectric layer 6 is deposited on the nitride barrier layer 5.
  • the dielectric layer 6 may be selected from SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO. One or more combinations.
  • the dielectric layer 6 can function as a passivation layer.
  • a gate electrode 7 is formed over the dielectric layer 6 of the gate region, and at least a portion of the gate electrode 6 may be formed in the channel such that the gate electrode 7 has a T-type structure, usually a gate electrode. 7 needs to form a MIS or MOSFET structure with the nitride barrier layer 5.
  • the source 8 and the drain 9 are formed in the source region and the drain region, respectively, and the source 8 and the drain 9 are in ohmic contact with the nitride barrier layer 5.
  • the groove 41 is a rectangular groove.
  • the groove 41 may have other shapes, such as one of a triangular shape, a trapezoidal shape, a zigzag shape, a polygonal shape, a semicircular shape, and a U shape. Combination of one or more kinds, and the like.
  • the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 in the present embodiment are optional. In other embodiments, the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 may not be grown. Or only a portion of the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 are grown. Further, a nitride layer may be grown on the nitride barrier layer, the nitride layer may be gallium nitride or aluminum gallium nitride; and aluminum nitride may be grown between the nitride barrier layer and the nitride channel layer. middle layer.
  • FIG. 7A-7G are schematic diagrams showing the manufacturing process of the enhanced device according to the second embodiment of the present invention, wherein FIG. 7G is a schematic structural view of the enhanced device in the second embodiment.
  • the enhanced device in this embodiment includes:
  • nitride nucleation layer 2 on the substrate 1;
  • nitride buffer layer 3 on the nitride nucleation layer 2;
  • nitride channel layer 4 on the nitride buffer layer 3;
  • dielectric layer 6 on the nitride barrier layer 5, the dielectric layer 6 being a combination of one or more of SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO;
  • the nitride channel layer 4 and the nitride barrier layer 5 are provided with at least one non-planar structure in a region below the gate, and a non-polar or semi-polar surface of the nitride at a non-planar structure or a combination thereof.
  • the two-dimensional electron gas in the nitride channel layer 4/nitride barrier layer 5 heterojunction channel is at least partially interrupted in the region under the gate.
  • the substrate 1, the nitride nucleation layer 2, the nitride buffer layer 3, the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 are all provided with a non-planar structure, and The planar structure is set to a rectangular projection.
  • the method of fabricating the enhanced device of this embodiment includes the steps of:
  • a substrate 1 is provided in which a rectangular bump is formed in the substrate 1.
  • the material of the substrate may be sapphire, silicon carbide, silicon, lithium niobate, SOI, gallium nitride, and aluminum nitride. Wait.
  • a nitride nucleation layer 2 such as AlN or the like is deposited on the substrate 1.
  • a nitride buffer layer 3 such as AlGaN or the like is deposited on the nitride nucleation layer 2.
  • a nitride channel layer 4 such as GaN or the like, is deposited on the nitride buffer layer 3, and the nitride channel layer 4 has protrusions 42 transferred from the protrusions of the substrate.
  • the position of the bump 42 corresponds to a gate region defined on the epitaxial multilayer structure.
  • the surface of the nitride channel layer 4 is a polar plane, that is, a (0002) plane, and at least two sides of the protrusion 42 and the nitride channel layer
  • the surfaces of 4 are formed at a certain angle, that is, the sides are in a non-0002 direction, such as a (1-100) plane, a (11-20) plane, a (1-101) plane, a (11-22) plane, and the like.
  • a nitride barrier layer 5 is deposited on the nitride channel layer 4, and a portion of the nitride barrier layer 5 above the bump 42 also has a protrusion 52 corresponding to the protrusion 42.
  • Root there are non-polar or semi-polar faces of nitride or a combination thereof at the protrusions, and thus, two of the heterojunction channels formed in the nitride channel layer 4/nitride barrier layer 5 are formed.
  • the dimension electron gas is interrupted in the gate region, so that when the gate voltage is zero, the carrier concentration of the gate can be effectively controlled.
  • a dielectric layer 6 is deposited on the nitride barrier layer 5.
  • the dielectric layer 6 may be selected from SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO. One or more combinations.
  • the dielectric layer 6 can function as a passivation layer.
  • a gate electrode 7 is formed over the dielectric layer 6 of the gate region, and at least a portion of the gate electrode 6 may be formed in the channel such that the gate electrode 7 has a T-type structure, usually a gate electrode. 7 needs to form a MIS or MOSFET structure with the nitride barrier layer 5.
  • the source 8 and the drain 9 are formed in the source region and the drain region, respectively, and the source 8 and the drain 9 are in ohmic contact with the nitride barrier layer 5.
  • the protrusion 42 is a rectangular protrusion.
  • the protrusion 42 may have other shapes, such as one of a triangular shape, a trapezoidal shape, a zigzag shape, a polygonal shape, a semicircular shape, and a U shape. Combination of one or more kinds, and the like.
  • the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 in the present embodiment are optional. In other embodiments, the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 may not be grown. Or only a portion of the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 are grown. Further, a nitride layer may be grown on the nitride barrier layer, the nitride layer may be gallium nitride or aluminum gallium nitride; and aluminum nitride may be grown between the nitride barrier layer and the nitride channel layer. middle layer.
  • FIG. 8A-8G are schematic diagrams showing a manufacturing process of an enhanced device according to a third embodiment of the present invention, wherein FIG. 8G is a schematic structural view of the enhanced device in the third embodiment.
  • the enhanced device in this embodiment includes:
  • nitride nucleation layer 2 on the substrate 1;
  • nitride buffer layer 3 on the nitride nucleation layer 2;
  • nitride channel layer 4 on the nitride buffer layer 3;
  • dielectric layer 6 on the nitride barrier layer 5, the dielectric layer 6 being a combination of one or more of SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO;
  • the nitride channel layer 4 and the nitride barrier layer 5 are provided with at least one non-planar structure in a region below the gate, and a non-polar or semi-polar surface of the nitride at a non-planar structure or a combination thereof.
  • the two-dimensional electron gas in the nitride channel layer 4/nitride barrier layer 5 heterojunction channel is at least partially interrupted in the region under the gate.
  • the substrate 1, the nitride nucleation layer 2, the nitride buffer layer 3, the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 are all provided with a non-planar structure, and The planar structure is set to a step.
  • the method of fabricating the enhanced device of this embodiment includes the steps of:
  • a substrate 1 is provided, and a stepped structure is formed in the substrate 1 so that the surface of the substrate 1 is stepped.
  • the material of the substrate may be sapphire, silicon carbide, silicon, lithium niobate. , SOI, gallium nitride and aluminum nitride.
  • a nitride nucleation layer 2 such as AlN or the like is deposited on the substrate 1.
  • a nitride buffer layer 3 such as AlGaN or the like is deposited on the nitride nucleation layer 2.
  • a nitride channel layer 4 such as GaN or the like is deposited on the nitride buffer layer 3, and the nitride channel layer 4 has a step transferred from the step of the substrate, the stepped
  • the nitride channel layer 4 has a first plane 43 and a second plane 44 at different heights.
  • An interface 45 is connected between the first plane 43 and the second plane 44. In this embodiment, the interface 45 is at an angle. Slope.
  • a nitride barrier layer 5 is deposited on the nitride channel layer 4, and a nonpolar or semipolar plane of nitride is present at the step or a combination thereof, so that it is formed in the nitride trench
  • the two-dimensional electron gas in the heterojunction channel of the channel layer 4/nitride barrier layer 5 is interrupted in the gate region, so that the carrier concentration of the gate electrode can be effectively controlled when the gate voltage is zero.
  • a dielectric layer 6 is deposited on the nitride barrier layer 5, and the dielectric layer 6 may be selected from SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO. One or more combinations.
  • the dielectric layer 6 can function as a passivation layer.
  • a gate electrode 7 is formed over the dielectric layer 6 of the gate region, the gate electrode 6 At least a portion of it may be formed in the channel such that the gate 7 has a T-type structure, and typically the gate 7 needs to form a MIS or MOSFET structure with the nitride barrier layer 5.
  • the source 8 and the drain 9 are formed in the source region and the drain region, respectively, and the source 8 and the drain 9 are in ohmic contact with the nitride barrier layer 5.
  • the engaging surface of the step is a sloped surface at an angle
  • the cross section of the step may also be other shapes, such as a vertical surface, or a curved surface, or an irregularly shaped surface, etc. .
  • the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 in the present embodiment are optional. In other embodiments, the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 may not be grown. Or only a portion of the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 are grown. Further, a nitride layer may be grown on the nitride barrier layer, the nitride layer may be gallium nitride or aluminum gallium nitride; and aluminum nitride may be grown between the nitride barrier layer and the nitride channel layer. middle layer.
  • FIG. 9A-9G are schematic diagrams showing the manufacturing process of the enhanced device according to the fourth embodiment of the present invention, wherein FIG. 9G is a schematic structural view of the enhanced device in the fourth embodiment.
  • the enhanced device in this embodiment includes:
  • nitride nucleation layer 2 on the substrate 1;
  • nitride buffer layer 3 on the nitride nucleation layer 2;
  • nitride channel layer 4 on the nitride buffer layer 3;
  • dielectric layer 6 on the nitride barrier layer 5, the dielectric layer 6 being a combination of one or more of SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO;
  • the nitride channel layer 4 and the nitride barrier layer 5 are provided with at least one non-planar structure in a region below the gate, and a non-polar or semi-polar surface of the nitride at a non-planar structure or a combination thereof.
  • the two-dimensional electron gas in the nitride channel layer 4/nitride barrier layer 5 heterojunction channel is at least partially interrupted in the region under the gate.
  • the substrate 1, the nitride nucleation layer 2, the nitride buffer layer 3, and the nitride A non-planar structure is disposed on the channel layer 4, the nitride barrier layer 5, and the dielectric layer 6, and the non-planar structure on the substrate 1, the nitride nucleation layer 2, and the nitride buffer layer 3 is set as a rectangular groove.
  • the non-planar structure on the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 is provided as a triangular groove.
  • the method of fabricating the enhanced device of this embodiment includes the steps of:
  • a substrate 1 is provided in which a rectangular recess is formed in the substrate 1.
  • the material of the substrate may be sapphire, silicon carbide, silicon, lithium niobate, SOI, gallium nitride, and aluminum nitride. Wait.
  • a nitride nucleation layer 2 such as AlN or the like, is deposited on the substrate 1, and the nitride nucleation layer 2 has grooves which are transferred from the grooves of the substrate.
  • a nitride buffer layer 3 such as AlGaN or the like is deposited on the nitride nucleation layer 2, and the nitride buffer layer 3 has grooves transferred from the grooves of the substrate.
  • a nitride channel layer 4 such as GaN or the like is deposited on the nitride buffer layer 3, and the nitride channel layer 4 has a groove 46 transferred from the groove of the substrate, the groove
  • the shape of the recess 46 is a triangle, and the transfer method of the recess 46 is to convert the rectangular recess in the nitride buffer layer 3 into the triangular recess 46 in the nitride channel layer 4 during the growth process by controlling the growth conditions.
  • the location of the recess 46 corresponds to a gate region defined on the epitaxial multilayer structure.
  • the surface of the nitride channel layer 4 is a polar plane, that is, a (0002) plane, and at least two sides of the recess 46 and the nitride channel layer
  • the surfaces of 4 are formed at a certain angle, that is, the sides are in a non-0002 direction, such as a (1-100) plane, a (11-20) plane, a (1-101) plane, a (11-22) plane, and the like.
  • a nitride barrier layer 5 is deposited on the nitride channel layer 4, and a portion of the nitride barrier layer 5 above the recess 46 also has a recess 56 corresponding to the recess 46.
  • the dimension electron gas is interrupted in the gate region, so that when the gate voltage is zero, the carrier concentration of the gate can be effectively controlled.
  • a dielectric layer 6 is deposited on the nitride barrier layer 5, and the dielectric layer 6 may be selected from SiN, SiCN, SiO 2 , SiAlN, Al 2 O 3 , AlON, SiON, HfO 2 , HfAlO. One or more combinations.
  • the dielectric layer 6 can function as a passivation layer.
  • a gate electrode 7 is formed over the dielectric layer 6 of the gate region, the gate electrode 6 At least a portion of it may be formed in the channel such that the gate 7 has a T-type structure, and typically the gate 7 needs to form a MIS or MOSFET structure with the nitride barrier layer 5.
  • the source 8 and the drain 9 are formed in the source region and the drain region, respectively, and the source 8 and the drain 9 are in ohmic contact with the nitride barrier layer 5.
  • the groove 46 is a triangular groove.
  • the groove 46 may also have other shapes, such as one or more of a rectangle, a trapezoid, a zigzag, a polygon, a semicircle, and a U shape. Kind of combination and so on.
  • the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 in the present embodiment are optional. In other embodiments, the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 may not be grown. Or only a portion of the nitride nucleation layer 2, the nitride buffer layer 3, and the dielectric layer 6 are grown. Further, a nitride layer may be grown on the nitride barrier layer, the nitride layer may be gallium nitride or aluminum gallium nitride; and aluminum nitride may be grown between the nitride barrier layer and the nitride channel layer. middle layer.
  • FIG. 10 is a schematic structural view of a enhancement device according to a fifth embodiment of the present invention.
  • the groove on the substrate 1 is rectangular, a nitride nucleation layer 2 and a nitride buffer layer.
  • the grooves in 3 are trapezoidal, and the grooves in the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 are triangular, and other manufacturing methods are the same as in the first embodiment.
  • FIG. 11 is a schematic structural diagram of a enhancement device according to a sixth embodiment of the present invention.
  • the groove on the substrate 1 is trapezoidal, a nitride nucleation layer 2, and a nitride buffer layer. 3.
  • the grooves in the nitride channel layer 4, the nitride barrier layer 5, and the dielectric layer 6 are all trapezoidal, and other manufacturing methods are the same as in the first embodiment.
  • the present invention provides a method for fabricating a reinforced device. Since the reinforced device is manufactured, the shape of the substrate is transferred to the nitride channel layer, so that the nitride channel layer
  • the gate region forms a non-planar structure, and the nitride non-polar surface, semi-polar surface or a combination of the two generated in the non-planar structure causes the interruption of the two-dimensional electron gas, so there is no need to make the nitride barrier layer.
  • the etching avoids the degradation of device performance caused by damage of the active region, such as low current density or current collapse.
  • the introduction of Mg atoms to achieve p-type nitride is not required, and contamination of the MOCVD or MBE cavity is avoided.

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Abstract

一种增强型器件的制造方法，该方法包括：提供一衬底（1）；在衬底上沉积氮化物沟道层（4），氮化物沟道层（4）上定义有栅极区、源极区和漏极区，氮化物沟道层（4）上的栅极区形成有至少一个非平面结构；在氮化物沟道层上沉积氮化物势垒层（5），氮化物势垒层形成有至少一个非平面结构；在氮化物势垒层（5）上形成栅极（7）、源极（8）和漏极（9）。本发明不需要对氮化物势垒层（5）做刻蚀，避免了有源区的损伤带来的器件性能下降，比如说低电流密度或者电流崩塌等效应。另外，也不需要用到引入Mg原子实现p型氮化物，避免了对MOCVD或者MBE腔体的污染。

Description

一种增强型器件的制造方法
本申请要求于2013年12月27日提交中国专利局、申请号为201310738667.7、发明名称为“一种增强型器件的制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体电子技术领域，特别是涉及一种增强型器件的制造方法。
背景技术
第三代半导体材料氮化镓具有禁带宽度大、电子饱和漂移速度高、击穿场强高、导热性能好等特点，在电子器件方面，氮化镓材料比硅和砷化镓更适合于制作高温、高频、高压和大功率的半导体器件。
由于AlGaN/GaN异质结构中存在较强的二维电子气，通常采用AlGaN/GaN异质结形成的高电子迁移率晶体管(High Electron Mobility Transistor；HEMT)都是耗尽型器件，对于增强型器件则不易实现。而在许多地方耗尽型器件的应用又具有一定的局限性，比如在功率开关器件的应用中，需要增强型(常关型)开关器件。增强型氮化镓开关器件主要用于高频器件、功率开关器件和数字电路等，它的研究具有十分重要的意义。
实现增强型氮化镓开关器件，需要找到合适的方法来降低零栅压时栅极下方的沟道载流子浓度。一种方法是在栅极处采用刻蚀结构，局部减薄栅极下面的铝镓氮层的厚度，达到控制或降低栅极下二维电子气浓度的目的，如图1所示，缓冲层11、氮化镓层12、铝镓氮层13分别位于衬底10上，栅极14、源极15以及漏极16分别位于铝镓氮层13上，其中在栅极4下方铝镓氮层被局部刻蚀，从而减薄了栅极区的铝镓氮层厚度。另外一种办法是在栅极下面选择性保留p型(Al)GaN，通过p型(Al)GaN来提拉铝镓氮/氮化镓异质结处的导带能级，形成耗尽区，从而实现增强型器件；如图2所示，在栅极14’下方通过选择性保留了局部p型氮化物17。还有一种办法是氟化物等离子处理技术，在势垒层中注入氟离子等带负电的离子，控制注入离子浓度可以耗尽导电沟道中的二维电子气，需要用很强的负离子来夹断沟道，如图3所示，在栅极14”下方的势垒层13中注入负电离子 18。
但是，这些办法都有一定的不足之处。在第一种方法中，阈值电压一般在0V-1V左右，未达到应用的阈值电压3V-5V，为了达到较高的阈值电压和工作电压，还需要增加额外的介质层，如原子层沉积的三氧化二铝，但是，这个介质层与铝镓氮表面的界面态如何控制，是一个悬而未决的大问题。在第二种方法中，需要选择性刻蚀掉除了栅极下面以外的所有区域，如何实现刻蚀厚度的精确控制，也是非常具有挑战性的，另外，由于刻蚀中带来的缺陷，以及p型铝镓氮中残余的镁原子，会引起严重的电流崩塌效应。还有就是由于空穴密度的不足(一般而言，p型氮化镓中空穴的浓度不会超过1E18/cm3)，AlGaN/GaN异质结中的二维电子气的密度会受到很大的限制。如果二维电子气中电子的密度过高，就无法实现增强型的器件了，所以增强型器件的AlGaN/GaN异质结中，铝的含量通常低于20％，如15％左右。在第三种方法中，氟化物等离子处理会破坏晶格结构，工艺重复控制性也较差，对器件的稳定性和可靠性造成了比较大的影响。
因此，针对上述技术问题及改进方法，有必要提供一种新的增强型器件的制造方法。
发明内容
正如背景技术中所述，氮化镓材料在运用到增强型器件中的时候，需要控制零栅压时沟道中的载流子浓度。然而现有的工艺中，无论是减薄栅极下方的氮化物势垒层的厚度，还是在栅极下方保留一层p型氮化物，或者在势垒层中注入负离子，都会因为工艺问题对器件的稳定性和可靠性产生比较大的影响。
因此，本发明公开了一种增强型器件的制造方法，该增强型器件实现夹断二维电子气的原理是根据III族氮化物是一种极性半导体的特点，请参见图4和图5，同传统的III-V族半导体不同，III族氮化物中存在很强的内建电场。如果在C(0002)平面形成AlInGaN/GaN异质结，即使在AlInGaN层不进行n型掺杂，在所述异质结当中也会产生浓度很高的二维电子气。其原因就是III族氮化物内的自发极化电场和由于应力引起的压电电场。此二维电子气的浓度可以超过1E13/cm2。但是，III族氮化物中的自发极化电 场和压电电场只存在于<0002>方向，而非极性方向，即与<0002>方向垂直的方向，包括<1-100>、<11-20>等则不存在自建电场。对于半极性方向来说，例如在<0002>与<1-100>或者<11-20>之间的方向，该方向上的内建电场强度也远远小于<0002>方向。
因此，在极化方向生长的氮化镓异质结结构中，不需要故意掺杂就可以生成电子浓度很高的二维电子气。但是，对于氮化镓材料的非极性面或者半极性面，由于极化场强几乎没有或者很低，在没有掺杂的情况下就不会生成二维电子气。利用氮化镓材料的此特点，在本发明中，我们通过在衬底中制作凹槽、凸起和台阶等形式，控制外延的参数，把衬底的形状转移到沟道层，使得沟道层的栅极区域形成了非平面结构，利用非平面结构中产生的氮化物非极性面、半极性面或者二者组合，造成栅极区域二维电子气的中断，从而实现了增强型器件。
由于这种增强型器件在制作时，把衬底的形状转移到了沟道层，使得沟道层的栅极区域形成了非平面结构，非平面结构中产生的氮化物非极性面、半极性面或者二者组合会引起二维电子气的中断，所以不需要对势垒层做刻蚀，避免了有源区的损伤带来的器件性能下降，比如说低电流密度或者电流崩塌等效应。另外，也不需要用到引入Mg原子实现p型氮化物，避免了对MOCVD或者MBE腔体的污染。
为了实现上述目的，本发明实施例提供的技术方案如下：
一种增强型器件的制造方法，所述方法包括：
S1、提供一衬底；
S2、在所述衬底上沉积氮化物沟道层，所述氮化物沟道层上定义有栅极区、源极区和漏极区，所述氮化物沟道层的栅极区形成有至少一个非平面结构；
S3、在所述氮化物沟道层上沉积氮化物势垒层，所述氮化物势垒层形成有至少一个非平面结构，形成氮化物沟道层/氮化物势垒层异质结，所述非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层/氮化物势垒层异质结沟道中的二维电子气至少部分形成中断；
S4、在所述氮化物势垒层上形成栅极、源极和漏极，栅极、源极和漏极分别位于氮化物沟道层上栅极区、源极区和漏极区的上方，所述栅极位 于源极和漏极之间。
作为本发明的进一步改进，所述步骤S1还包括：
在衬底中制作至少一个非平面结构。
作为本发明的进一步改进，所述步骤S1还包括：
在所述衬底上沉积氮化物缓冲层，在氮化物缓冲层上制作至少一个非平面结构。
作为本发明的进一步改进，所述非平面结构包括凹槽、凸起和台阶。
作为本发明的进一步改进，所述凹槽的截面形状包括矩形、三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合。
作为本发明的进一步改进，所述凸起的截面形状包括矩形、三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合。
作为本发明的进一步改进，所述台阶的截面为垂直面、或斜坡面、或弧形面、或非规则形状的面。
作为本发明的进一步改进，所述步骤S1还包括：在衬底上沉积氮化物成核层。
作为本发明的进一步改进，所述步骤S3后还包括：在氮化物势垒层上沉积介质层。
作为本发明的进一步改进，所述介质层为SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。
作为本发明的进一步改进，所述步骤S3后还包括：在氮化物势垒层上沉积氮化物冒层，所述氮化物冒层为氮化镓或铝镓氮。
作为本发明的进一步改进，所述步骤S2后还包括：在氮化物沟道层上沉积氮化铝中间层。
本发明增强型器件的制造方法不需要对氮化物势垒层做刻蚀，避免了有源区的损伤带来的器件性能下降，比如说低电流密度或者电流崩塌等效应。另外，也不需要用到引入Mg原子实现p型氮化物，避免了对MOCVD或者MBE腔体的污染。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中通过减薄栅极下面的铝镓氮层的厚度达到控制或降低栅极下二维电子气浓度的增强型器件结构示意图；
图2为现有技术中通过在栅极下面选择性保留p型(Al)GaN，以提拉铝镓氮/氮化镓异质结处的导带能级，形成耗尽区的增强型器件结构示意图；
图3为现有技术中在栅极下面采用氟离子处理的增强型器件结构示意图；
图4为氮化物晶格结构的示意图；
图5为氮化物中不同方向上的内建电场分布示意图；
图6A-6G本发明第一实施方式的增强型器件的制造流程示意图，其中，图6G为第一实施方式中增强型器件的结构示意图；
图7A-7G本发明第二实施方式的增强型器件的制造流程示意图，其中，图7G为第二实施方式中增强型器件的结构示意图；
图8A-8G本发明第三实施方式的增强型器件的制造流程示意图，其中，图8G为第三实施方式中增强型器件的结构示意图；
图9A-9G本发明第四实施方式的增强型器件的制造流程示意图，其中，图9G为第四实施方式中增强型器件的结构示意图；
图10为本发明第五实施方式的增强型器件的结构示意图；
图11为本发明第六实施方式的增强型器件的结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。
请参见图6，图6A-6G本发明第一实施方式的增强型器件的制造流程示意图，其中图6G为第一实施方式中增强型器件的结构示意图。
参图6G所示，本实施方式中增强型器件包括：
衬底1；
位于衬底1上的氮化物成核层2；
位于氮化物成核层2上的氮化物缓冲层3；
位于氮化物缓冲层3上的氮化物沟道层4；
位于氮化物沟道层4上的氮化物势垒层5，氮化物沟道层4和氮化物势垒层5形成氮化物沟道层4/氮化物势垒层5异质结；
位于氮化物势垒层5上的介质层6，介质层6为SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合；
位于介质层6上的栅极7、氮化物势垒层5上的源极8和漏极9，栅极8位于源极8和漏极9之间；
其中，氮化物沟道层4和氮化物势垒层5上位于栅极下方区域设有至少一个非平面结构，非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极下方区域至少部分形成中断。
在本实施方式中，衬底1、氮化物成核层2、氮化物缓冲层3、氮化物沟道层4、氮化物势垒层5以及介质层6上均设有非平面结构，且非平面结构设置为矩形凹槽。
参图6A-6G所示，该实施方式中增强型器件的制造方法包括步骤：
(1)参见图6A，提供一衬底1，在衬底1中制作矩形凹槽，该衬底的材料可以为蓝宝石、碳化硅、硅、铌酸锂、SOI、氮化镓和氮化铝等。
(2)参见图6B，在衬底1上沉积氮化物成核层2，如AlN等。
(3)参见图6C，在氮化物成核层2上沉积氮化物缓冲层3，如AlGaN等。
(4)参见图6D，在氮化物缓冲层3上沉积氮化物沟道层4，如GaN等，该氮化物沟道层4中有从衬底的凹槽中转移过来的凹槽41，该凹槽41的位置对应定义在外延多层结构上的栅极区域。根据III族氮化物的自发极化效应和压电效应，该氮化物沟道层4的表面为极性面，即(0002)面，而 凹槽41的至少两个侧面与氮化物沟道层4的表面形成一定的角度，即这些侧面处于非<0002>方向上，比如(1-100)面、(11-20)面、(1-101)面、(11-22)面等等。
(5)参见图6E，在氮化物沟道层4上沉积氮化物势垒层5，氮化物势垒层5位于该凹槽41上方的部分也具有与该凹槽41对应的凹槽51，根据上述分析，凹槽处存在氮化物的非极性面或半极性面或其组合，这样一来，形成在氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极区域形成中断，因而在栅压为零时，能够使栅极的载流子浓度得到有效的控制。
(6)参见图6F，在氮化物势垒层5上沉积介质层6，介质层6的选择可以是SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。该介质层6可以起到钝化层的作用。
(7)参见图6G，栅极7形成在该栅极区的介质层6之上，该栅极6的至少部分可以形成在沟道之中，使栅极7具有T型结构，通常栅极7需要与氮化物势垒层5形成MIS或者MOSFET结构。源极8和漏极9则分别形成在源极区和漏极区，该源极8和漏极9则与氮化物势垒层5形成欧姆接触。
在本实施方式中，凹槽41为矩形凹槽，在其他实施方式中凹槽41也可以为其它形状，比如截面形状为三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合等等。
本实施方式中的氮化物成核层2、氮化物缓冲层3和介质层6为可选的，在其他实施方式中可以不生长氮化物成核层2、氮化物缓冲层3和介质层6或仅生长氮化物成核层2、氮化物缓冲层3和介质层6中的部分。进一步地，氮化物势垒层上还可以生长氮化物冒层，氮化物冒层可为氮化镓或铝镓氮；氮化物势垒层和氮化物沟道层之间还可生长氮化铝中间层。
请参见图7，图7A-7G本发明第二实施方式的增强型器件的制造流程示意图，其中图7G为第二实施方式中增强型器件的结构示意图。
参图7G所示，本实施方式中增强型器件包括：
衬底1；
位于衬底1上的氮化物成核层2；
位于氮化物成核层2上的氮化物缓冲层3；
位于氮化物缓冲层3上的氮化物沟道层4；
位于氮化物沟道层4上的氮化物势垒层5，氮化物沟道层4和氮化物势垒层5形成氮化物沟道层4/氮化物势垒层5异质结；
位于氮化物势垒层5上的介质层6，介质层6为SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合；
位于介质层6上的栅极7、氮化物势垒层5上的源极8和漏极9，栅极8位于源极8和漏极9之间；
其中，氮化物沟道层4和氮化物势垒层5上位于栅极下方区域设有至少一个非平面结构，非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极下方区域至少部分形成中断。
在本实施方式中，衬底1、氮化物成核层2、氮化物缓冲层3、氮化物沟道层4、氮化物势垒层5以及介质层6上均设有非平面结构，且非平面结构设置为矩形凸起。
参图7A-7G所示，该实施方式中增强型器件的制造方法包括步骤：
(1)参见图7A，提供一衬底1，在衬底1中制作矩形凸起，该衬底的材料可以为蓝宝石、碳化硅、硅、铌酸锂、SOI、氮化镓和氮化铝等。
(2)参见图7B，在衬底1上沉积氮化物成核层2，如AlN等。
(3)参见图7C，在氮化物成核层2上沉积氮化物缓冲层3，如AlGaN等。
(4)参见图7D，在氮化物缓冲层3上沉积氮化物沟道层4，如GaN等，该氮化物沟道层4中有从衬底的凸起中转移过来的凸起42，该凸起42的位置对应定义在外延多层结构上的栅极区域。根据III族氮化物的自发极化效应和压电效应，该氮化物沟道层4的表面为极性面，即(0002)面，而凸起42的至少两个侧面与氮化物沟道层4的表面形成一定的角度，即这些侧面处于非<0002>方向上，比如(1-100)面、(11-20)面、(1-101)面、(11-22)面等等。
(5)参见图7E，在氮化物沟道层4上沉积氮化物势垒层5，氮化物势垒层5位于该凸起42上方的部分也具有与该凸起42对应的凸起52，根 据上述分析，凸起处存在氮化物的非极性面或半极性面或其组合，这样一来，形成在氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极区域形成中断，因而在栅压为零时，能够使栅极的载流子浓度得到有效的控制。
(6)参见图7F，在氮化物势垒层5上沉积介质层6，介质层6的选择可以是SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。该介质层6可以起到钝化层的作用。
(7)参见图7G，栅极7形成在该栅极区的介质层6之上，该栅极6的至少部分可以形成在沟道之中，使栅极7具有T型结构，通常栅极7需要与氮化物势垒层5形成MIS或者MOSFET结构。源极8和漏极9则分别形成在源极区和漏极区，该源极8和漏极9则与氮化物势垒层5形成欧姆接触。
在本实施方式中，凸起42为矩形凸起，在其他实施方式中凸起42也可以为其它形状，比如截面形状为三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合等等。
本实施方式中的氮化物成核层2、氮化物缓冲层3和介质层6为可选的，在其他实施方式中可以不生长氮化物成核层2、氮化物缓冲层3和介质层6或仅生长氮化物成核层2、氮化物缓冲层3和介质层6中的部分。进一步地，氮化物势垒层上还可以生长氮化物冒层，氮化物冒层可为氮化镓或铝镓氮；氮化物势垒层和氮化物沟道层之间还可生长氮化铝中间层。
请参见图8，图8A-8G本发明第三实施方式的增强型器件的制造流程示意图，其中图8G为第三实施方式中增强型器件的结构示意图。
参图8G所示，本实施方式中增强型器件包括：
衬底1；
位于衬底1上的氮化物成核层2；
位于氮化物成核层2上的氮化物缓冲层3；
位于氮化物缓冲层3上的氮化物沟道层4；
位于氮化物沟道层4上的氮化物势垒层5，氮化物沟道层4和氮化物势垒层5形成氮化物沟道层4/氮化物势垒层5异质结；
位于氮化物势垒层5上的介质层6，介质层6为SiN、SiCN、SiO2、 SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合；
位于介质层6上的栅极7、氮化物势垒层5上的源极8和漏极9，栅极8位于源极8和漏极9之间；
其中，氮化物沟道层4和氮化物势垒层5上位于栅极下方区域设有至少一个非平面结构，非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极下方区域至少部分形成中断。
在本实施方式中，衬底1、氮化物成核层2、氮化物缓冲层3、氮化物沟道层4、氮化物势垒层5以及介质层6上均设有非平面结构，且非平面结构设置为台阶。
参图8A-8G所示，该实施方式中增强型器件的制造方法包括步骤：
(1)参见图8A，提供一衬底1，在衬底1中制作台阶状结构，使衬底1的表面呈台阶状，该衬底的材料可以为蓝宝石、碳化硅、硅、铌酸锂、SOI、氮化镓和氮化铝等。
(2)参见图8B，在衬底1上沉积氮化物成核层2，如AlN等。
(3)参见图8C，在氮化物成核层2上沉积氮化物缓冲层3，如AlGaN等。
(4)参见图8D，在氮化物缓冲层3上沉积氮化物沟道层4，如GaN等，该氮化物沟道层4中有从衬底的台阶中转移过来的台阶，该台阶状的氮化物沟道层4具有位于不同高度上的第一平面43和第二平面44，第一平面43和第二平面44之间连接有衔接面45，本实施方式中衔接面45为呈一定角度的坡面。
(5)参见图8E，在氮化物沟道层4上沉积氮化物势垒层5，台阶处存在氮化物的非极性面或半极性面或其组合，这样以来，形成在氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极区域形成中断，因而在栅压为零时，能够使栅极的载流子浓度得到有效的控制。
(6)参见图8F，在氮化物势垒层5上沉积介质层6，介质层6的选择可以是SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。该介质层6可以起到钝化层的作用。
(7)参见图8G，栅极7形成在该栅极区的介质层6之上，该栅极6 的至少部分可以形成在沟道之中，使栅极7具有T型结构，通常栅极7需要与氮化物势垒层5形成MIS或者MOSFET结构。源极8和漏极9则分别形成在源极区和漏极区，该源极8和漏极9则与氮化物势垒层5形成欧姆接触。
在本实施方式中，台阶的衔接面为呈一定角度的坡面，在其他实施方式中该台阶的截面也可以为其它形状，比如垂直面、或弧形面、或非规则形状的面等等。
本实施方式中的氮化物成核层2、氮化物缓冲层3和介质层6为可选的，在其他实施方式中可以不生长氮化物成核层2、氮化物缓冲层3和介质层6或仅生长氮化物成核层2、氮化物缓冲层3和介质层6中的部分。进一步地，氮化物势垒层上还可以生长氮化物冒层，氮化物冒层可为氮化镓或铝镓氮；氮化物势垒层和氮化物沟道层之间还可生长氮化铝中间层。
请参见图9，图9A-9G本发明第四实施方式的增强型器件的制造流程示意图，其中图9G为第四实施方式中增强型器件的结构示意图。
参图9G所示，本实施方式中增强型器件包括：
衬底1；
位于衬底1上的氮化物成核层2；
位于氮化物成核层2上的氮化物缓冲层3；
位于氮化物缓冲层3上的氮化物沟道层4；
位于氮化物沟道层4上的氮化物势垒层5，氮化物沟道层4和氮化物势垒层5形成氮化物沟道层4/氮化物势垒层5异质结；
位于氮化物势垒层5上的介质层6，介质层6为SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合；
位于介质层6上的栅极7、氮化物势垒层5上的源极8和漏极9，栅极8位于源极8和漏极9之间；
其中，氮化物沟道层4和氮化物势垒层5上位于栅极下方区域设有至少一个非平面结构，非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极下方区域至少部分形成中断。
在本实施方式中，衬底1、氮化物成核层2、氮化物缓冲层3、氮化物 沟道层4、氮化物势垒层5以及介质层6上均设有非平面结构，且衬底1、氮化物成核层2和氮化物缓冲层3上的非平面结构设置为矩形凹槽，氮化物沟道层4、氮化物势垒层5以及介质层6上的非平面结构设置为三角形凹槽。
参图9A-9G所示，该实施方式中增强型器件的制造方法包括步骤：
(1)参见图9A，提供一衬底1，在衬底1中制作矩形凹槽，该衬底的材料可以为蓝宝石、碳化硅、硅、铌酸锂、SOI、氮化镓和氮化铝等。
(2)参见图9B，在衬底1上沉积氮化物成核层2，如AlN等，该氮化物成核层2中有从衬底的凹槽中转移过来的凹槽。
(3)参见图9C，在氮化物成核层2上沉积氮化物缓冲层3，如AlGaN等，该氮化物缓冲层3中有从衬底的凹槽中转移过来的凹槽。
(4)参见图9D，在氮化物缓冲层3上沉积氮化物沟道层4，如GaN等，氮化物沟道层4中有从衬底的凹槽中转移过来的凹槽46，凹槽46的形状为三角形，凹槽46的转移方法是通过控制生长的条件，在生长的过程中把氮化物缓冲层3中的矩形凹槽转换成氮化物沟道层4中的三角形凹槽46，该凹槽46的位置对应定义在外延多层结构上的栅极区域。根据III族氮化物的自发极化效应和压电效应，该氮化物沟道层4的表面为极性面，即(0002)面，而凹槽46的至少两个侧面与氮化物沟道层4的表面形成一定的角度，即这些侧面处于非<0002>方向上，比如(1-100)面、(11-20)面、(1-101)面、(11-22)面等等。
(5)参见图9E，在氮化物沟道层4上沉积氮化物势垒层5，氮化物势垒层5位于该凹槽46上方的部分也具有与该凹槽46对应的凹槽56，根据上述分析，凹槽处存在氮化物的非极性面或半极性面或其组合，这样一来，形成在氮化物沟道层4/氮化物势垒层5异质结沟道中的二维电子气在栅极区域形成中断，因而在栅压为零时，能够使栅极的载流子浓度得到有效的控制。
(6)参见图9F，在氮化物势垒层5上沉积介质层6，介质层6的选择可以是SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。该介质层6可以起到钝化层的作用。
(7)参见图9G，栅极7形成在该栅极区的介质层6之上，该栅极6 的至少部分可以形成在沟道之中，使栅极7具有T型结构，通常栅极7需要与氮化物势垒层5形成MIS或者MOSFET结构。源极8和漏极9则分别形成在源极区和漏极区，该源极8和漏极9则与氮化物势垒层5形成欧姆接触。
在本实施方式中，凹槽46为三角形凹槽，在其他实施方式中凹槽46也可以为其它形状，比如矩形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合等等。
本实施方式中的氮化物成核层2、氮化物缓冲层3和介质层6为可选的，在其他实施方式中可以不生长氮化物成核层2、氮化物缓冲层3和介质层6或仅生长氮化物成核层2、氮化物缓冲层3和介质层6中的部分。进一步地，氮化物势垒层上还可以生长氮化物冒层，氮化物冒层可为氮化镓或铝镓氮；氮化物势垒层和氮化物沟道层之间还可生长氮化铝中间层。
请参见图10，图10是本发明的第五实施方式中增强型器件的结构示意图，在本实施方式中，衬底1上的凹槽为矩形，氮化物成核层2和氮化物缓冲层3中的凹槽为梯形，氮化物沟道层4、氮化物势垒层5和介质层6中的凹槽为三角形，其他制造方法均与第一实施方式相同。
请参见图11，图11是本发明的第六实施方式中增强型器件的结构示意图，在本实施方式中，衬底1上的凹槽为梯形，氮化物成核层2、氮化物缓冲层3、氮化物沟道层4、氮化物势垒层5和介质层6中的凹槽都为梯形，其他制造方法均与第一实施方式相同。
由以上技术方案可以看出，本发明提供了一种增强型器件的制造方法，由于这种增强型器件在制造时，把衬底的形状转移到了氮化物沟道层，使得氮化物沟道层的栅极区域形成了非平面结构，非平面结构中产生的氮化物非极性面、半极性面或者二者组合会引起二维电子气的中断，所以不需要对氮化物势垒层做刻蚀，避免了有源区的损伤带来的器件性能下降，如低电流密度或者电流崩塌等效应。另外，也不需要用到引入Mg原子实现p型氮化物，避免了对MOCVD或者MBE腔体的污染。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性 的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (12)

  1. 一种增强型器件的制造方法，其特征在于，所述方法包括：
    S1、提供一衬底；
    S2、在所述衬底上沉积氮化物沟道层，所述氮化物沟道层上定义有栅极区、源极区和漏极区，所述氮化物沟道层的栅极区形成有至少一个非平面结构；
    S3、在所述氮化物沟道层上沉积氮化物势垒层，所述氮化物势垒层形成有至少一个非平面结构，形成氮化物沟道层/氮化物势垒层异质结，所述非平面结构处存在氮化物的非极性面或半极性面或其组合，氮化物沟道层/氮化物势垒层异质结沟道中的二维电子气至少部分形成中断；
    S4、在所述氮化物势垒层上形成栅极、源极和漏极，栅极、源极和漏极分别位于氮化物沟道层上栅极区、源极区和漏极区的上方，所述栅极位于源极和漏极之间。
  2. 根据权利要求1所述的增强型器件的制造方法，其特征在于，所述步骤S1还包括：
    在衬底中制作至少一个非平面结构。
  3. 根据权利要求1所述的增强型器件的制造方法，其特征在于，所述步骤S1还包括：
    在所述衬底上沉积氮化物缓冲层，在氮化物缓冲层上制作至少一个非平面结构。
  4. 根据权利要求1～3中任一项所述的增强型器件的制造方法，其特征在于，所述非平面结构包括凹槽、凸起和台阶。
  5. 根据权利要求4所述的增强型器件的制造方法，其特征在于，所述凹槽的截面形状包括矩形、三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合。
  6. 根据权利要求4所述的增强型器件的制造方法，其特征在于，所述凸起的截面形状包括矩形、三角形、梯形、锯齿形、多边形、半圆形、U形中的一种或多种的组合。
  7. 根据权利要求4所述的增强型器件的制造方法，其特征在于，所述 台阶的截面为垂直面、或斜坡面、或弧形面、或非规则形状的面。
  8. 根据权利要求1～3中任一项所述的增强型器件的制造方法，其特征在于，所述步骤S1还包括：在衬底上沉积氮化物成核层。
  9. 根据权利要求1～3中任一项所述的增强型器件的制造方法，其特征在于，所述步骤S3后还包括：在氮化物势垒层上沉积介质层。
  10. 根据权利要求9所述的增强型器件的制造方法，其特征在于，所述介质层为SiN、SiCN、SiO2、SiAlN、Al2O3、AlON、SiON、HfO2、HfAlO中的一种或多种的组合。
  11. 根据权利要求1～3中任一项所述的增强型器件的制造方法，其特征在于，所述步骤S3后还包括：在氮化物势垒层上沉积氮化物冒层，所述氮化物冒层为氮化镓或铝镓氮。
  12. 根据权利要求1～3中任一项所述的增强型器件的制造方法，其特征在于，所述步骤S2后还包括：在氮化物沟道层上沉积氮化铝中间层。
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