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WO2013033986A1 - 小尺寸鳍形结构的制造方法 - Google Patents

小尺寸鳍形结构的制造方法 Download PDF

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Publication number
WO2013033986A1
WO2013033986A1 PCT/CN2012/072983 CN2012072983W WO2013033986A1 WO 2013033986 A1 WO2013033986 A1 WO 2013033986A1 CN 2012072983 W CN2012072983 W CN 2012072983W WO 2013033986 A1 WO2013033986 A1 WO 2013033986A1
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WIPO (PCT)
Prior art keywords
mask layer
etching
layer pattern
mask
pattern
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PCT/CN2012/072983
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English (en)
French (fr)
Inventor
杨涛
赵超
李俊峰
卢一泓
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中国科学院微电子研究所
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Priority to US14/342,421 priority Critical patent/US20140227878A1/en
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2013033986A1 publication Critical patent/WO2013033986A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a small-sized fin structure. Background technique
  • the oxide layer 2 formed on the bulk silicon substrate 1 is selectively epitaxially grown, the substrate is re-filled with oxide or formed by using silicon nanowire technology.
  • a phase that protrudes perpendicularly to the substrate 1 Parallel fins (fm) or fin structure 3
  • an ultrathin gate oxide layer 4 is formed on the fin structure 3 and surrounds the channel region
  • the gate electrode 5 is formed on the oxide layer 2 to cover the gate oxide Layer 4 and surrounding the channel region, spanning a plurality of fin structures 3, doping the fin structures 3 on both sides of the gate 5 to form source and drain regions 3A/3B, and being gated 5 and gate oxide layer 4
  • a portion of the covered fin structure 3 becomes the channel region 3C, wherein the source and drain regions 3A/3B and the channel region 3C need to be thin enough to enhance the controllability of the gate.
  • One of the key technologies of the device structure is to form a fin-shaped single crystal grid on a corresponding bulk silicon wafer substrate, which will serve as the source and drain regions of the device.
  • a conventional process such as deposition, etching, etc.
  • new technologies such as silicon nanotubes are complicated, costly, and difficult to use. For large-scale production, and process uniformity needs to be improved.
  • the present invention provides a method of fabricating a small-sized fin structure, comprising the steps of: sequentially forming a first mask layer and a second mask layer on a substrate; etching the first mask layer and the second layer The mask layer forms a hard mask pattern, wherein the second mask layer pattern is wider than the first mask layer pattern; removing the second mask layer pattern; and dry etching the substrate by using the first mask layer pattern as a mask , forming a fin structure.
  • the first dry etching is performed to form a hard mask pattern and the second mask layer pattern is equal to the first mask layer pattern, and then the first mask layer pattern is wet etched to make the second mask layer pattern It is wider than the first mask layer pattern.
  • first mask layer and/or the second mask layer comprises silicon oxide, silicon nitride, silicon oxynitride.
  • the wet etching corrosion solution includes DHF, BOE, hot phosphoric acid, H 2 O 2 .
  • the substrate includes single crystal silicon, SOI, single crystal germanium, GeOI, SiGe, SiC, InSb, GaAs, GaN.
  • width of the first mask layer pattern and/or the fin structure is less than or equal to 100A.
  • a hard mask having a larger size is first prepared, and then a controllable small-size hard mask is prepared by wet etching, and finally a bulk silicon wafer is used.
  • the etching is performed to obtain the desired small-sized fin structure, which improves the electrical performance and integration of the device, and simplifies the process and reduces the cost.
  • Figure 1 shows a schematic view of a prior art fin gate device
  • FIGS 2 through 7 show, in order, schematic cross-sectional views of the various steps of the method in accordance with the present invention. detailed description
  • a hard mask material layer 20 composed of a first mask layer 21 and a second mask layer 22 is formed on a substrate 10, and the formation method is, for example, a conventional deposition method such as LPCVD, PECVD, or the like.
  • the substrate 10 can be made of various substrate materials according to the electrical performance requirements of the device, including, for example, single crystal silicon, silicon-on-insulator (SOI), single crystal germanium, germanium on insulator (GeOI), or SiGe, SiC, InSb, GaAs, Other compound semiconductor materials such as GaN, or epitaxial wafers.
  • the crystal orientation of the substrate 10 may be (100), (110) or (111) as required for carrier mobility control, or may have different crystals formed by selective epitaxial growth (SEG) on the underlying substrate. Multiple top substrate regions.
  • the first mask layer 21 and the second mask layer 22 may include silicon oxide, silicon nitride or silicon oxynitride for later use
  • the etched hard mask layer is made of different materials, such as silicon oxide 21 underneath and silicon nitride 22 on top, or inverted silicon nitride 21 under and silicon oxide 22 on, or can be used later
  • the rate of etching is different, especially the lower layer etching is faster than the middle layer and the middle layer is faster than the upper layer.
  • the first mask layer 21 has a thickness a of 400 to 1000 A and preferably 600 A
  • the second mask layer 22 has a thickness b of 100 to 400 A and preferably 200 A.
  • a vertical hard mask pattern having an upper and lower width is formed by etching. Applying a photoresist (not shown) on the second mask layer 22 and exposing it to a photoresist pattern, using a photoresist pattern as a mask, using a dry etching such as plasma etching, sequentially etching The second mask layer 22 and the first mask layer 21 are etched until the substrate 10 is exposed to form a hard mask pattern having a line width of, for example, 200 to 400 A and preferably 300 A.
  • the plasma etching gas may include a halogen-containing gas, for example, a fluorine-containing gas such as a fluorocarbon-based gas (CxHyFz), NF 3 or SF 6 , and other halogen-containing gases such as Cl 2 , Br 2 , HBr, and HC1. Oxidizing agents such as oxygen, ozone, and nitrogen oxides may be included. It is to be noted that the second mask layer 22 of the top layer is not completely removed in the plasma etching, but retains a certain residual thickness, for example, 100 A or more and preferably 150 A. After the etching is completed, wet cleaning such as deionized water or dry cleaning such as oxygen or fluorinated gas is used to completely remove the etching product.
  • a fluorine-containing gas such as a fluorocarbon-based gas (CxHyFz), NF 3 or SF 6
  • Oxidizing agents such as oxygen, ozone, and nitrogen oxides may be included.
  • selective etching forms a hard mask pattern that is narrower in width and width.
  • Different etching liquids are selected according to different materials of the first and second mask layers to selectively wet etch the first mask layer to form a hard mask pattern having an upper width and a lower width.
  • the first mask layer 21 is silicon oxide
  • a dry hydrofluoric acid (DHF, such as HF: H 2 0 1: 100) or a slow-release etching solution (BOE, a mixture of NH 4 F and HF, The ratio of the two is, for example, 2:1 to 4:1) of the HF-based chemical liquid, and the etching temperature is, for example, 25 ° C, since the etching rate of the second mask layer 22 of the silicon nitride for DHF is very slow for the silicon oxide
  • the first mask layer 21 has a faster etching rate, so that the lines of the first mask layer pattern 21 are laterally retracted to form a structure similar to the upper or lower width of the nut or T-shape as shown in FIG.
  • the first mask layer 21 is silicon nitride
  • hot phosphoric acid which does not react with the second mask layer 22 of silicon oxide
  • the process temperature may be 160 °C
  • the side mask layer 21 is etched back, and the structure shown in Fig. 4 is also formed.
  • HF and 3 ⁇ 40 2 can be used. In the case of a material, a mixture of HF and H 2 0 2 may be used for etching.
  • the line width of the second mask layer 22 in FIG. 4 is still kept close to or equal to the width of the hard mask pattern in FIG.
  • the line width c of the first mask layer pattern 21 is smaller than
  • the line width of the second mask layer pattern 22 is, for example, 100 A or less and preferably 50 A.
  • the second mask layer 22 has a suspended portion beyond the first mask layer 21, 125 A on the left and right sides.
  • the width of the overhanging portion or the remaining line width c of the first mask layer pattern 21 can be obtained by adjusting the etching solution ratio and temperature to control the lateral etching rate, thereby controlling the width of the final etched substrate to form the fin structure.
  • Si0 2 /Si 3 N 4 (SiON ) double-stacked hard-mask structure if only one layer of SiO 2 hard mask is used, in the process of wet lateral etching of SiO 2 , since there is no top layer Si 3 N 4 (SiON ) protection, the top and side of the single-layer Si0 2 hard mask will be simultaneously etched, so that the shape and lateral width of the SiO 2 hard mask cannot be effectively controlled.
  • a two-layer hard mask is employed to control the lateral width to form the final small-sized fin structure.
  • the second mask layer of the top layer is removed.
  • the second mask layer pattern 22 remaining on top of the hard mask pattern is removed using a wet etching process, leaving only the first mask layer pattern 21 on the substrate 10.
  • DHF dilute hydrofluoric acid
  • BOE slow-release etching solution
  • etching temperature for example, 25 ° C
  • the substrate is etched to form a fin structure.
  • the fin structure wherein the fin structure width is equal to the remaining width c of the first mask layer pattern, for example, both 100A and preferably 50A.
  • the remaining first mask layer pattern 21 is removed.
  • the remaining first mask layer pattern 21 is removed by etching with different wet etching solutions according to the material of the first mask layer 21, leaving a plurality of fin structures as shown in FIG.
  • the first mask layer 21 is silicon oxide
  • an HF-based etching liquid is used
  • when it is made of silicon nitride, hot phosphoric acid is used
  • when it is made of silicon oxynitride a mixture of HF and hydrogen peroxide is used.
  • Subsequent device fabrication may include depositing a gate dielectric layer and a gate material layer on the fin structure, source-drain ion implantation on the fin structures on both sides of the gate, depositing an insulating layer, and etching to form a contact hole, deposition contact Metal or the like, thereby completing the manufacture of the fin-shaped gate device. These processes are well known in the art and will not be described again.
  • a hard mask having a larger size is first prepared, and then a controllable small-size hard mask is prepared by wet etching, and finally a bulk silicon wafer is used.
  • the etching is performed to obtain the desired small-sized fin structure, which improves the electrical performance and integration of the device, and simplifies the process and reduces the cost.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供了一种小尺寸鳍形结构的制造方法，包括以下步骤：在衬底上依次形成第一掩模层和第二掩模层；刻蚀第一掩模层和第二掩模层形成硬掩模图形，其中第二掩模层图形比第一掩模层图形宽；去除第二掩模层图形；以第一掩模层图形为掩模，干法刻蚀衬底，形成鳍形结构。依照本发明的小尺寸鳍形结构制造方法，先制备较大尺寸的硬掩模，而后通过湿法腐蚀制备出宽度可控的、小尺寸硬掩模，最终利用在体硅晶圆的刻蚀上，从而得到所需的小尺寸鳍形结构，提高了器件的电学性能以及集成度，并简化了工艺降低了成本。

Description

小尺寸鳍形结构的制造方法
[0001】本 申 请要求 了 2011 月 9月 5 日 提交的 、 申 请号为 201110261527.6、 发明名称为 "小尺寸鰭形结构的制造方法" 的中 国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002】本发明涉及一种半导体器件的制造方法， 更具体地讲， 涉及 一种小尺寸鰭形结构的制造方法。 背景技术
[0003]随着半导体特征尺寸持续向着 22/15nm的等级不断缩小，栅极宽 度减小带来的负面效应越来越明显， 传统的平面型晶体管已不能满足 要求。 首先， 为了消除短沟道效应， 需要向沟道中重掺杂 P、 B， 使得 器件阈值电压上升， 还降低了沟道中载流子迁移率， 造成器件响应速 度下降， 且离子注入工艺控制较难， 容易造成阈值电压波动过大等不 良结果。 其次， 传统的 SiGe PMOS硅应变技术也面临瓶颈， 在 22nm制 程节点中， 源漏两极掺杂的 Ge元素含量已经占到 40 %左右， 难以再为 沟道提供更高程度的应变。 第三， 栅氧化物厚度发展也凸显瓶颈， 厚 度的减薄速度已经难以跟上栅极宽度缩小的步伐。
[0004]2011年 5月英特尔宣布 22纳米技术节点将采用 3维鰭型栅 (FinFET)的器件结构取代之前平面的 2维平面栅器件结构， 以满足 随器件尺寸缩小而带来的漏电， 高功耗等问题。 由于 2维平面栅在 22纳米技术节点以前一直可以维持摩尔定律的推进， 因此 3维鰭型 栅器件是否有必要引入， 以及在哪一个技术节点引入都是人们一直 关注的问题。 在 10多年前， 3维鰭型栅器件的原型及制作工艺的研 究就已展开。 3维鰭型栅器件结构见英特尔发表的示意图 1， 体硅衬 底 1上形成有的氧化物层 2， 选择性外延生长、 刻蚀衬底再填充氧 化物或者采用硅纳米线技术形成多个突出于衬底 1而垂直分布的相 互平行的鰭 （fm ) 形或翅形结构 3， 超薄的栅氧化物层 4形成在鰭 形结构 3上并包围了沟道区， 栅极 5形成在氧化物层 2而覆盖栅氧 化物层 4且包围沟道区、 横跨多个鰭形结构 3， 对栅极 5两侧的鰭 形结构 3掺杂使其形成源漏区 3A/3B， 而被栅极 5、栅氧化层 4覆盖 的鰭形结构 3的部分区域成为沟道区 3C，其中源漏区 3A/3B以及沟 道区 3C需要足够薄以增强栅的控制能力。
[0005】该器件结构的关键技术之一是在相应体硅晶圆衬底上形成鰭 型的单晶栅条， 此栅条将作为器件的源漏区。 然而现有的集成电路 工艺中， 难以在体衬底上通过已知的沉积、 刻蚀等常规工艺来制造 小尺寸的鰭形结构， 而硅纳米管等新技术工艺复杂、 成本高昂， 难 以用于大规模生产， 且工艺均匀性有待提高。
[0006]为此， 急需一种能高效低成本地制作小尺寸鰭形结构的方法。 发明内容
[οοοη因此， 本发明的目的在于提出一种小尺寸鰭形结构的制造方 法， 以便高效低成本地制作小尺寸鰭形结构， 提高器件性能的同时 还能有效降低成本。
[0008]本发明提供了一种小尺寸鰭形结构的制造方法， 包括以下步 骤： 在衬底上依次形成第一掩模层和第二掩模层； 刻蚀第一掩模层 和第二掩模层形成硬掩模图形， 其中第二掩模层图形比第一掩模层 图形宽； 去除第二掩模层图形； 以第一掩模层图形为掩模， 干法刻 蚀衬底， 形成鰭形结构。
[0009]其中， 先干法刻蚀形成硬掩模图形且使得第二掩模层图形与 第一掩模层图形等宽， 然后湿法腐蚀第一掩模层图形使得第二掩模 层图形比第一掩模层图形宽。
[0010】其中， 第一掩模层和 /或第二掩模层包括氧化硅、 氮化硅、 氮 氧化硅。
[0011】湿法腐蚀的腐蚀液包括 DHF、 BOE、 热磷酸、 H202。
[0012】衬底包括单晶硅、 SOI、 单晶锗、 GeOI、 SiGe、 SiC、 InSb、 GaAs、 GaN。
[0013]其中， 衬底晶向依照载流子迁移率控制而不同。
[0014]其中， 第一掩模层图形和 /或鰭形结构的宽度小于等于 100A。
[0015】依照本发明的小尺寸鰭形结构制造方法， 先制备较大尺寸的 硬掩模， 而后通过湿法腐蚀制备出宽度可控的、 小尺寸硬掩模， 最 终利用在体硅晶圆的刻蚀上， 从而得到所需的小尺寸鰭形结构， 提 高了器件的电学性能以及集成度， 并简化了工艺降低了成本。
[0016】本发明所述目的， 以及在此未列出的其他目的， 在本申请独 立权利要求的范围内得以满足。 本发明的实施例限定在独立权利要 求中， 具体特征限定在其从属权利要求中。 附图说明
[0017]以下参照附图来详细说明本发明的技术方案， 其中：
图 1显示了现有技术的鰭形栅器件的示意图；
图 2至图 7依次显示了依照本发明的方法各步骤的剖面示意图。 具体实施方式
[0018】以下参照附图并结合示意性的实施例来详细说明本发明技术 方案的特征及其技术效果，公开了一种小尺寸鰭形结构的制造方法。 需要指出的是， 类似的附图标记表示类似的结构。
[0019】首先参照图 2， 在衬底 10上形成由第一掩模层 21和第二掩模层 22构成的硬掩模材料层 20， 形成方法例如是 LPCVD、 PECVD等常规 沉积方法。 衬底 10依照器件电学性能需要而可采用各种衬底材料， 例如包括单晶硅、绝缘体上硅（SOI )、单晶锗、绝缘体上锗（GeOI )， 或者 SiGe、 SiC、 InSb、 GaAs、 GaN等其他化合物半导体材料， 或者 为外延晶片。 衬底 10的晶向依照载流子迁移率控制的需要而可以是 ( 100 ) , ( 110 )或 （ 111 ) ， 或者是在底层衬底上通过选择性外延 生长 （SEG ) 形成的具有不同晶向的多个顶部衬底区域。 第一掩模 层 21和第二掩模层 22可包括氧化硅、 氮化硅或氮氧化硅， 用于稍后 刻蚀的硬掩模层， 两者材质不同， 例如氧化硅 21在下而氮化硅 22在 上， 也可倒置为氮化硅 21在下而氧化硅 22在上， 或者还可以采用能 使得稍后刻蚀时速率不同的特别是下层刻蚀快于中层、 中层快于上 层的三层结构。 第一掩模层 21厚度 a为 400 ~ 1000A并优选 600A， 第 二掩模层 22厚度 b为 100 ~ 400A并优选 200A。
[0020】其次参照图 3， 刻蚀形成上下等宽的垂直硬掩模图形。 在第二 掩模层 22上涂敷光刻胶（未示出） 并曝光显影形成光刻胶图形， 以 光刻胶图形为掩模， 采用例如等离子体刻蚀的干法刻蚀， 依次刻蚀 第二掩模层 22以及第一掩模层 21直至露出衬底 10，形成硬掩模图形， 硬掩模图形的线条宽度例如为 200 ~ 400A并优选 300A。 其中， 等离 子体刻蚀气体可包括含卤素气体， 例如为碳氟基气体 （CxHyFz ) 、 NF3、 SF6等含氟气体， 以及 Cl2、 Br2、 HBr、 HC1等其他含卤素气体， 还可以包括氧气、 臭氧、 氮氧化物等氧化剂。 值得注意的是， 顶层 的第二掩模层 22在等离子体刻蚀中并未完全除去， 而是保留有一定 的剩余厚度， 例如为大于等于 100A并优选 150A。 刻蚀完成之后采用 去离子水等湿法清洗或通入氧气、 氟化气体等干法清洗， 完全去除 刻蚀产物。
[0021】再次参照图 4， 选择性刻蚀形成上宽下窄的硬掩模图形。 依照 第一和第二掩模层材质不同而选择不同的刻蚀液来对第一掩模层层 选择性地湿法刻蚀， 形成上宽下窄的硬掩模图形。 当第一掩模层 21 为氧化硅时， 采用例如为稀幹氢氟酸（DHF， 例如 HF:H20 = 1 : 100 ) 或緩释刻蚀液（BOE， NH4F与 HF混合物， 两者之比例如为 2: 1至 4: 1 ) 的 HF基化学液， 刻蚀温度例如为 25 °C， 由于 DHF对于氮化硅的第二 掩模层 22腐蚀速率很慢而对于氧化硅的第一掩模层 21腐蚀速率较 快， 因此第一掩模层图形 21的线条会横向缩进， 形成如图 4所示的类 似于螺帽或 T型的上宽下窄的结构。 当第一掩模层 21为氮化硅时， 可 采用不与氧化硅的第二掩模层 22反应的热磷酸（ H3P04:H20=85: 15， 工艺温度可举证为 160°C ) 来侧蚀第一掩模层 21， 也同样形成图 4所 示结构。同理地，当掩模层 21或 22使用氮氧化物时，可采用 HF与 ¾02 物时， 可采用 HF与 H202混合物来腐蚀。 图 4中第二掩模层 22的线条 宽度仍保持为接近或等于图 3中的硬掩模图形宽度， 例如为 200 ~ 400A并优选 300A， 但是第一掩模层图形 21的线条宽度 c小于第二掩 模层图形 22的线条宽度， 例如小于等于 100A并优选为 50A。 换言之， 第二掩模层 22具有超出第一掩模层 21的悬出部分， 左右各 125A。 悬 出部分的宽度或者第一掩模层图形 21的剩余的线条宽度 c可通过调 整腐蚀液配比以及温度来控制横向腐蚀速率而得到， 从而控制最终 刻蚀衬底形成鰭形结构的宽度。
[0022】上述的 Si02/Si3N4 ( SiON )双叠层的硬掩模结构， 如果只用一 层 Si02硬掩模， 那么在湿法横向腐蚀 Si02的过程中， 由于没有顶层 Si3N4 ( SiON )保护， 单层的 Si02硬掩模顶部和侧面将被同时腐蚀， 从而无法有效控制 Si02硬掩模的形状和横向宽度。 因此， 本发明有 鉴于此， 采用双层硬掩模来控制横向宽度， 从而形成最终的小尺寸 鰭形结构。
[0023】然后参照图 5， 去除顶层的第二掩模层。 使用湿法腐蚀工艺去 除掉硬掩模图形顶部残存的第二掩模层图形 22， 在衬底 10上仅留下 第一掩模层图形 21。 例如采用热磷酸（H3P04:H20=85: 15， 工艺温度 可举证为 160°C )腐蚀氮化硅的第二掩模层 22; 当第二掩模层 22为氧 化硅时， 采用 HF基化学液,例如为稀释氢氟酸 （DHF， 例如 HF:H20 = 1 : 100 ) 或緩释刻蚀液 （BOE， NH4F与 HF混合物， 两者之比例如 为 2: 1至 4: 1 ) 的 HF基化学液， 刻蚀温度例如为 25 °C ) 来腐蚀去除。 湿法腐蚀工艺完成后对晶圆进行清洗并干燥。
[0024】接着参照图 6， 刻蚀衬底形成鰭形结构。 采用与刻蚀硬掩模图 形相同或类似的干法刻蚀工艺， 例如等离子体刻蚀， 以留下的第一 掩模层图形 21为掩模对衬底刻蚀， 直至到达所需的深度， 例如 200 ~ 1000A， 未被第一掩模层图形 21阻挡的衬底 10将被刻蚀去除而位于 第一掩模层图形 21下的衬底 10得以保留而形成图 6所示的多条鰭形 结构， 其中鰭形结构宽度与第一掩模层图形剩余的宽度 c相等， 例如 均为小于等于 100A并优选 50A。 [0025】最后参照图 7， 去除剩余的第一掩模层图形 21。 依照第一掩模 层 21材料不同而采用不同的湿法刻蚀液腐蚀去除剩余的第一掩模层 图形 21， 留下图 7所示的多条鰭形结构。 例如， 当第一掩模层 21为氧 化硅时采用 HF基刻蚀液， 当其采用氮化硅时采用热磷酸， 当其采用 氮氧化硅时采用 HF与双氧水混合物。
[0026]后续的器件制造可以包括在鰭形结构上沉积栅介质层和栅极 材料层、 对栅极两侧的鰭形结构源漏离子注入、 沉积绝缘层并刻蚀 形成接触孔、 沉积接触金属等等， 从而完成鰭形栅器件的制造。 这 些工艺为本领域公知， 在此不再赘述。
[0027】依照本发明的小尺寸鰭形结构制造方法， 先制备较大尺寸的 硬掩模， 而后通过湿法腐蚀制备出宽度可控的、 小尺寸硬掩模， 最 终利用在体硅晶圆的刻蚀上， 从而得到所需的小尺寸鰭形结构， 提 高了器件的电学性能以及集成度， 并简化了工艺降低了成本。
[0028】尽管已参照一个或多个示例性实施例说明本发明， 本领域技 术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的 改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特定 情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施 例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的 所有实施例。

Claims

权 利 要 求
1. 一种小尺寸鰭形结构的制造方法， 包括以下步骤：
在衬底上依次形成第一掩模层和第二掩模层；
刻蚀第一掩模层和第二掩模层形成硬掩模图形， 其中第二掩模 层图形比第一掩模层图形宽；
去除第二掩模层图形；
以第一掩模层图形为掩模， 干法刻蚀衬底， 形成鰭形结构。
2. 如权利要求 1的方法， 其中， 先干法刻蚀形成硬掩模图形且 使得第二掩模层图形与第一掩模层图形等宽， 然后湿法腐蚀第一掩 模层图形使得第二掩模层图形比第一掩模层图形宽。
3. 如权利要求 1的方法， 其中， 第一掩模层和 /或第二掩模层包 括氧化硅、 氮化硅、 氮氧化硅。
4. 如权利要求 2或 3的方法，其中， 湿法腐蚀的腐蚀液包括 DHF、 BOE、 热磚酸、 H202。
5. 如权利要求 1的方法， 其中， 衬底包括单晶硅、 SOI、 单晶锗、 GeOI、 SiGe、 SiC、 InSb、 GaAs、 GaN。
6. 如权利要求 1的方法， 其中， 衬底晶向依照载流子迁移率控 制而不同。
7. 如权利要求 1的方法， 其中， 第一掩模层图形和 /或鰭形结构 的宽度小于等于 100A。
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