WO2012131701A2

WO2012131701A2 - Fpga system for processing radar based signals for aerial view display

Info

Publication number: WO2012131701A2
Application number: PCT/IN2012/000161
Authority: WO
Inventors: Raghukul DIKSHIT; Pradeep REDDY
Original assignee: The Tata Power Company Ltd.
Priority date: 2011-03-11
Filing date: 2012-03-07
Publication date: 2012-10-04
Also published as: WO2012131701A3

Abstract

A Field Programmable Gate Array (FPGA) system to read input radar signals and produce an output for plotting an aerial radar display on a pre-defined map to obtain a rendition of the position of a target being mapped. Analog radar signals received are converted to digital signals by an RSC. Received digital signal and radar control signal are used by PPI to create aerial scan video frames. The created frames are stored in a DDR2 SDRAM storage means via a DDR2 multiport controller having a pre-determined number of read/write ports, each port having a pre-defined priority. The created frames are positioned and resized in raster zoom-pan controller means and then blended with synthetic video generated by a host processor to produce a fused video by alpha blender using alpha blending technique. An alpha blender provides non-interlaced scanning for raster display of the fused video at a pre¬ determined resolution.

Description

FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS FOR AERIAL VIEW DISPLAY

FD2LD OF THE DISCLOSURE

This disclosure relates to a system for processing signals.

Particularly, this disclosure relates to a system for processing radar based signals.

BACKGROUND

Radar is an object detection system, typically employed to detect movement of targets by transmitting and receiving electromagnetic waves.

Modern radar systems typically use a raster scan display to produce a maplike image. Earlier radar displays were built using oscilloscopes adapted suitably for various inputs. In a general sense, oscilloscopes are cathode ray tubes with three input channels that are attached to sources of varying voltage. The voltages are amplified and sent to one of the deflection magnets or an intensity channel, which controls the brightness of the spot on the screen. All of these channels are also equipped with a bias voltage source that allows a zero point to be set. By varying the voltages sent to the channels, the cathode beam can be made to move around, appearing as a spot on the display.

Further developments have occurred in the form of A-scope, B-scope, E- scope, H-scope and C-scope displays. The original radar display was the A- scope, which displays the range to targets along a scale. These displays were also referred to as R-scope for range scope. A B-scope provides a 2-D "top down" representation of space, with the vertical axis typically representing range and the horizontal axis representing the azimuth (angle). An E-scope is essentially a B-scope displaying range versus elevation, rather than range versus azimuth. The H-scope is another modification of the B-scope concept, but displays elevation as well as azimuth and range. A C-scope displays a "bulls-eye" view of azimuth versus elevation. Almost identical to the C-scope is the G-scope, which overlays a graphical representation of the range to the target. This is typically represented by a horizontal line that "grows" out from the target indicator "blip" to form a wing-like diagram.

A Plan Position Indicator commonly knows as a PPI display provides a 2-D "all round" display of the airspace around a radar site. The distance out from the center of the display indicates a range, and the angle around the display is the azimuth to the target. The current position of the radar antenna is typically indicated by a line extending from the center to the outside of the display. It is essentially a B-scope extended to 360 degrees.

A compact, simple, cost effective dynamic system for processing radar signals and providing a real time aerial view display with practically no time delay is the need of the hour.

OBJECTS

Some of the objects of the present disclosure aimed to ameliorate one or more problems of the prior art or to at least provide a useful alternative are described herein below: An object of this disclosure is to provide an integrated system for processing radar signals and providing an aerial view display.

Another object of this disclosure is to provide a system for processing radar signals and providing an aerial view display in real time.

Yet another object of this disclosure is to provide a system for processing radar signals and providing an aerial view dynamic and interactive display with practically no time lag.

Still another object of this disclosure is to provide a compact and modular architecture based system for processing radar signals for an aerial view display.

An additional object of this disclosure is to provide a single chip system for all functionalities relating to signal processing and plotting of radar signals on an aerial view display.

Another object of this disclosure is to provide a robust system for processing radar signals with a relatively good efficiency.

Yet another object of this disclosure is to provide a cost effective system for processing radar signals.

Still another object of this disclosure is to provide a low power system for processing radar signals.

Other objects and advantages of the present disclosure will be more apparent from the following description when read in conjunction with the accompanying figures, which are not intended to limit the scope of the present disclosure.

SUMMARY

In accordance with the present disclosure, there is provided a Field Programmable Gate Array (FPGA) system for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar, the system comprising:

• receiver means adapted to receive at least one control signal and at least one analog radar video signal in the form of electromagnetic reflections from the target;

• a Radar Scan Converter (RSC) comprising:

- radar interfacing means comprising:

o radar control signal conditioning means adapted to condition the radar control signal;

o radar video conditioning and threshold detection means adapted to condition and detect a threshold of the analog radar video signal; o video gain controlling means adapted to control gain of the analog radar video signal;

o video multiplexing means adapted to select a radar analog video signal to be monitored from the radar analog video signals; o video adder means adapted to enable monitoring of the radar analog video signals; the video adder means being further adapted to precisely blend the radar analog video signals to a pre-determined magnitude; and o an Analog to Digital Converter(ADC) adapted to convert the selected radar analog video signal to a digital signal; and scan conversion means comprising:

o frame creation means adapted to receive the conditioned radar control signal and the digital signal and further adapted to create aerial scan video frames using a (Coordinate Rotation Digital Computer) CORDIC module co-operating with dynamic lookup tables;

o a Double Data Rate (DDR2) multiport controller with a predetermined number of read / write ports, each of the ports being provided with a pre-defined priority, the multiport controller being adapted to simultaneously initiate read / write requests on each of the ports;

o host processor means adapted to sequentially perform arithmetical, logical, and input/output operations of the system, the host processor being further adapted to generate a synthetic video;

o reader means adapted to be connected to one of the ports having a highest priority, the reader means being adapted to read the video frames in burst mode and store as First-in-First-Out (FIFO);

o a raster zoom pan controller means adapted to position and resize the created aerial scan video frames;

o blending means adapted to blend the positioned and resized video frames with the synthetic video in real time to generate a fused video; o Low Power Giga bit Transceiver (LPGTs) means adapted to transmit and receive Peripheral Component Interconnect Express (PCIe) signal for user interface; and

• a housing adapted to enclose the receiver means and the Radar Scan Converter (RSC);

• a Double Data Rate Synchronous dynamic random access memory (DDR2 SDRAM) storage means adapted to receive and store the created frames; and

• a display means adapted to display the fused video at a pre-determined resolution, the system adapted to generate a dynamic and interactive aerial view display of the position of the target with practically no time lag.

Typically, in accordance with the present disclosure, the radar analog video signals are blended to a magnitude of 5 V Peak-to peak.

Additionally, in accordance with the present disclosure, the blending means is an alpha blender.

Preferably, in accordance with this disclosure, the frame creation means is a Plan Position Indicator (PPI) co-operating with the raster zoom pan controller means and the blending means.

Typically, in accordance with this disclosure, the Field Programmable Gate Array (FPGA) system further comprises: • scan fader means adapted to erase the created video frames from the DDR2 SDRAM;

• I C Controller means adapted to send user defined gain and threshold of the radar analog video signal to the video gain controlling means and the video conditioning and threshold detection means;

• Digital Video Interface (DVI) transmitter means adapted to transmit the fused video in real time to the display means, the DVI transmitter means being further adapted to receive configuration data from the I C Controller means; and

• Peripheral Component Interconnect express (PCIe) core means adapted to receive and decode user commands via the host processor means.

Typically, in accordance with this disclosure, the control signal is selected from the group consisting of North Mark Indicator (NMI), Azimuth Change Pulse (ACP) Radar Sync Pulses (SYNC), Triggering pulses (TRIG) and digitized 8 bit video data.

Furthermore, in accordance with this disclosure, the Peripheral Component Interconnect express (PCIe) means is adapted to support 2.5 Gbps line speed with IX lane operation.

Additionally, in accordance with this disclosure, the Peripheral Component Interconnect express (PCIe) means is adapted to support standard user interface with easy-to-use packet-based protocol, full-duplex communication and flow control of data received.

Furthermore, in accordance with this disclosure, the Peripheral Component Interconnect express (PCIe) means is adapted to be compliant with PCI Express transaction ordering rules.

Additionally, in accordance with this disclosure, the frame creation means is adapted to perform real time 2D compression on the digital signal to create fixed sized frames for a 1600 x 1200 display.

In accordance with this disclosure, the reader means being an alpha display means is adapted to provide non-interlaced scanning for 1600 X 1200 resolution at 162MHz frequency.

Preferably, in accordance with this disclosure, the Double Data Rate (DDR2) multi port memory controller is adapted to have three ports with port 0 being adapted to have a highest priority and port 3 being adapted to have a lowest priority, the blending means being an alpha blender is connected to port 0, the frame creation means being a Plan Position Indicator (PPI) is connected to port 1 and a scan fader means is connected to port 2.

In accordance with the present disclosure, there is provided a method for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar, the method comprising the following steps: receiving at least one control signal and at least one analog radar video signal in the form of electromagnetic reflections from the target;

conditioning the radar control signal;

conditioning and detecting a threshold of the analog radar video signal; controlling gain of the analog radar video signal;

selecting a radar analog video signal to be monitored from the radar analog video signals;

blending the radar analog video signal to a pre-determined magnitude; converting the radar analog video signal to a digital signal;

receiving the conditioned radar control signal and the digital signal; creating aerial scan video frames using a (Coordinate Rotation Digital Computer) CORDIC algorithm co-operating with dynamic lookup tables;

assigning a pre-defined priority to a pre-determined number of read / write ports;

initiating read / write requests simultaneously on each of the ports;

sequentially performing arithmetical, logical, and input/output operations of the system;

generating a synthetic video;

reading the video frames in burst mode and storing as First-in-First-Out (FIFO);

receiving and storing the created frames;

positioning and resizing the created aerial scan video frames;

blending the positioned and resized video frames with the synthetic video in real time;

generating a fused video; and • displaying the fused video at a pre-determined resolution with practically no time lag.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS

The disclosure will now be explained in relation to the non-limiting accompanying drawings, in which:

FIGURE 1 illustrates an overall schematic layout of the components of a Field Programmable Gate Array (FPGA) system for processing radar signals for aerial view interactive display in accordance with the present disclosure;

FIGURE 2 illustrates a schematic flow diagram of a Field Programmable Gate Array (FPGA) that forms part of the Field Programmable Gate Array (FPGA) system of FIGURE 1;

FIGURE 3 illustrates a schematic flow diagram of a Plan Position Indicator (PPI) that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2;

FIGURE 4 illustrates a display frame of a Plan Position Indicator (PPI); FIGURE 5 illustrates a polar co-ordinate system for a Plan Position Indicator

(PPI);

FIGURE 6 represents CORDIC conversion;

FIGURE 7 illustrates a schematic flow diagram of a Memory ADDR Gen block that forms part of the Plan Position Indicator (PPI) of FIGURE 3; FIGURE 8 illustrates a schematic flow diagram of a Raster Zoom-Pan Controller that forms a part of the Field Programmable Gate Array (FPGA) of FIGURE 2;

FIGURE 9 illustrates a schematic representation of progressive scanning by the Raster Zoom-Pan Controller of FIGURE 8;

FIGURE 10 illustrates a single 32 words burst transfer with 64 Bit DDR2;

FIGURE 11 illustrates duplication of pixels in accordance with the present disclosure;

FIGURE 12 illustrates pixel graphics when Alpha is saturated and for moderate Alpha respectively;

FIGURE 13 illustrates a schematic flow diagram of an Alpha blender that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2;

FIGURE 14 illustrates DSP48 multipliers provided in the Field Programmable Gate Array (FPGA) of FIGURE 2; and

FIGURE 15 illustrates a schematic flow diagram of a Scan Fader that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2.

DETAILED DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The disclosure will now be described with reference to the accompanying drawings which do not limit the scope and ambit of the disclosure. The description provided is purely by way of example and illustration. The embodiments herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiments in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

Radar processing systems known in the art typically require a plurality of Field Programmable Gate Arrays (FPGAs) to implement a system for processing radar signals, thus increasing the number of components, making the interconnections complex and adding on to the cost.

In accordance with the present disclosure, a Field Programmable Gate Array (FPGA) system is envisaged to read input radar signals and generate an interactive aerial view display of the position of a target being mapped by the radar.

FIGURE 1 illustrates an overall schematic layout of the components of a Field Programmable Gate Array (FPGA) system for processing radar signals for aerial view interactive display in accordance with the present disclosure.

The main components of the Field Programmable Gate Array (FPGA) system for processing radar signals as illustrated in FIGURE 1 are referenced generally with numerals as indicated below: RSC (Radar Scan Converter) 10;

an FPGA (Field Programmable Gate Array) 12;

a hardwired memory control block 14;

a hardwired PCIe (Peripheral Component Interconnect Express) core 16 LPGTs (Low Power Giga bit Transceiver) 18;

DDR2 SDRAM (Double Data Rate Synchronous dynamic random memory) 20;

UART TXRX (Universal Asynchronous Receiver Transmitter) 22; clocks 24;

header 26;

PCIe (Peripheral Component Interconnect Express) IX connector 28;

Front end Piggyback card 30;

DVI (Digital Visual Interface) transmitter 32;

DVI (Digital Visual Interface) receiver 34;

DVI (Digital Visual Interface) connector 36;

radar video conditioning and threshold detection means 38;

video gain controlling means 40;

video multiplexing means 42;

video adder 44;

radar control signal conditioning means 46;

piggy card interface connector 48;

video input connector 50;

ADC(Analog to Digital Converter) 52;

DAC(Digital to Analog Converter) + buffer 54; and

power supply 56. RSC (Radar Scan Converter) is typically a PCIe (Peripheral Component Interconnect Express) based lx Gen 1.0 card. Preferably, Peripheral Component Interconnect express (PCIe) means is configured to support 2.5 Gbps line speed with IX lane operation. In accordance with another aspect, Peripheral Component Interconnect express (PCIe) means is configured to support standard user interface with easy-to-use packet-based protocol, full- duplex communication and flow control of data received. It is also configured to comply with PCI Express transaction ordering rules.

The RSC comprises two different card assemblies, namely an RTF (Radar interface) card, typically a Front end Piggyback card 30 and a Scan Converter card, typically an FPGA (Field Programmable Gate Array) 12. Radar videos are fed from the video input connector 50 to the RIF card 30. The received radar videos under go conditioning, threshold detection and multiplexing before digitization using the radar video conditioning and threshold detection means 38, the video gain controlling means 40, and the video multiplexing means 42 respectively.

During conditioning of the radar control signal using the radar control signal conditioning means 46, DC bias is removed by adding an inverse magnitude of offset from the video signal by the video adder 44. A user selectable variable gain is provided to the video signals before multiplexing to ensure lower intensity target fidelity. Video multiplexing enables a user to select the video which the user needs to monitor. The user can also monitor more than one radar video by mixing the input signals, provided the video is synchronized over one SYNC. User interface to the RSC is provided via a PCIe Bus. PCIe target is implemented in FPGA eliminating additional component requirements for PCIe interface. During scan conversion, DDR2 SDRAM 20 holds the video frames captured by a sampling analog video. These video frames are blended with synthetic video frames driven by host CPU graphics card (host processor). In accordance with an embodiment, the radar analog video signals are blended to a magnitude of 5V Peak-to peak. The CPU graphics card feeds the synthetic video frames to RSC through a DVI interface, the DVI (Digital Visual Interface) receiver 34. RSC blends the received frames with RADAR video and sends it to a display means through a DVI interface, the DVI (Digital Visual Interface) transmitter 32. This mechanism is completely transparent between the graphics card and the display means. The implementation is such that there is no loss in graphics due to frame dropping, changing resolution and reducing refresh rate. The FPGA 12 controls the DDR2 SDRAM 20, the PCIe, and graphics blending and provides necessary control signals to analog sections for gain and offset control.

FIGURE 2 illustrates a schematic flow diagram of a Field Programmable Gate Array (FPGA) that forms part of the Field Programmable Gate Array (FPGA) system of FIGURE 1. RSC has a coarse-grained architectural approach to suit the needs of embedded design with open bus architectures. In the design, various modules such as PPI (Plan Position Indicator), Scan Fader, Raster Zoom-Pan Controller and Alpha Blender are implemented as independent design entities. These entities with host interface are generic in nature and are not implemented specifically to meet applications like Scan conversions. As illustrated in FIGURE 1, PPI, Raster Zoom-Pan Controller and Alpha Blender are responsible for creating frames from raw video samples on DDR2 through a 'DDR2 Multiport Memory Controller', graphics mixing and finally displaying it on standard monitor. Scan fader eliminates the history of the scan and provides a smooth sweep over it. I²C controller is used to configure the DVI transmitter. A PCIe core communicates the user commands to the various modules.

The main components of the Field Programmable Gate Array (FPGA) that forms part of the Field Programmable Gate Array (FPGA) system of FIGURE 1, namely, the DDR2 Multiport Memory Controller, the PPI, the Raster Zoom-Pan Controller, the Alpha Blender, the I C Controller and the Scan Fader is described herein below with reference to FIGURE 3 to FIGURE 15 respectively.

DDR2 Multiport Memory Controller: DDR2 Multiport Memory Controller is a physical layer protocol for DDR2 memory which provides multiple read write access ports (portO to port4) to a single port memory. On each port of DDR2 Multiport Memory Controller, the user can initiate read and write requests simultaneously. These requests under go arbitration with a predefined priority to each port such that port 0 has a highest priority and port 4 has a lowest priority to service the user requests. In accordance with one embodiment, applications requesting real time performance such as an Alpha Display is connected to port 0 with decreasing priority to PPI and so on. In accordance with another embodiment, the Double Data Rate (DDR2) multi port memory controller is configured to have three ports with port 0 being configured to have a highest priority and port 3 being configured to have a lowest priority, the blending means being an alpha blender is connected to port 0, the frame creation means being a Plan Position Indicator (PPI) is connected to port 1 and a scan fader means is connected to port 2.

PPI (Plan Position Indicator): FIGURE 3 illustrates a schematic flow diagram of a Plan Position Indicator (PPI) that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2. PPI receives radar control signals such as ACP (Azimuth Change Pulse), SYNC (Radar Sync Pulses), NMI (North Mark Indicator), TRIG (Triggering pulses) and digitized 8 bit video data. ACP, NMI and TRIG are filtered and conditioned before further processing. TRIG signal is used to find a range of the target. Maximum range of the scan is dependent on the number samples between two consecutive active pulses on the TRIG signal. The number of samples is calculated by a range counter. The range counter gets incremented according to the enable signal generated by an RCP (Range Compression Processor) compression block and initializes to "0" on active pulse of either TRIG or NMI.

The RCP block performs compression by mapping 8k samples to a user defined sample size. This cascades to compress the video with respect to the TRIG signal. RCP compression can be configured by a user register and is defined mathematically in accordance with the following equation:

N = (No. of samples per trigger) / (RCP count)

This process continues till the count expires, latching the highest sample value from a number of samples defined by the counter. This process fuses the N samples to a distinct sample with a peak sample value in the window. This ensures none of the targets are suppressed during RCP compression. Compression ratio is determined by the count value. As the count increases, compression increases. On each set of compression, an enable signal with data is generated. In accordance with an aspect of the present disclosure, real time 2D compression is performed on the digital signal to create fixed sized f ames for a 1600 x 1200 display.

ACP signal is used to find the number of ACPs per scan. Number of ACPs of the scan is dependent on the ACP counter. This counter is incremented for every active pulse of ACP and initialized to "0" on an active pulse of NMI signal.

The NMI signal is used to initialize the range counter, ACP counter and to initialize a CORDIC (Coordinate Rotation Digital Computer) module.

The CORDIC module converts the radar reflections and addresses them on to the DDR2 SDRAM by creating a video frame. It gives a plan view of the area around the radar antenna. This type of display frame is known as a PPI, or Plan-Position Indicator, and is illustrated in FIGURE 4.

The PPI display is an example of a polar coordinate system. A point on the plane of the display is located by two measurements: the distance r from a fixed point in the plane, and the angle subtended by the point with respect to a fixed axis on the plane. FIGURE 5 illustrates how the polar coordinates of a point P are measured, with respect to a fixed point B and a fixed axis AC.

The coordinate system of the PPI display is a result of the geometry of the radar system. The antenna is at the fixed point B, and the fixed axis AC is typically North- South. For each cell, the range is the r coordinate and the azimuth is the ø coordinate. This presents a mathematical difficulty for the display system, because the computer display uses (x, y) coordinates. To display the radar data, the RSC must transform the position of each cell from (r, ø) to (x, y) coordinates by a process called scan-conversion. A 'Cordic core' is used to convert from (r, ø) to (x, y) coordinates.

CORDIC block performs the R,0 to X,Y conversion using lookup tables for sine and cos. Inputs of this block are 'Enable', 'Initial Address', 'Xin', 'Yin', 'Phase' and 'ACP select'. An output of this block is 'DDR Addr'. 'Enable' signal is generated by the RCP compression block. The 'Enable' signal is a pulse generated for every valid radar video data after compression. The 'Initial Address' is provided by the user and marked as a radar base. The output of the range counter is given as 'Xin'. 'Yin' is assigned to "0" to generate a 2-dimensional scan. The output of the ACP counter is given as 'Phase' to the CORDIC. 'ACP select' is the user selection signal.

The heart of the 'Cordic core' block is a trigonometric lookup table and a multiplier. The 'Cordic core' is used for conversion of 'R-θ' to 'X-Y'. 'R' is used to define a range of the scan and is represented by 'Xin'. 'θ' is used to define the angle of the ACP's and it is represented by 'Phase'. Polar to Rectangular Translation is implemented in the 'Cordic core' by setting the functional configuration to vector rotation, the input vector to (Mag, 0), and the rotation angle to 'θ' as shown in FIGURE 5.Vector rotation is linear with respect to magnitude, thus the range provided by the range counter is:

If (X, Y) rotated by angle = (Χ', Υ') then

K*(X, Y) rotated by angle = K*(X\ Y').

FIGURE 6 represents the CORDIC conversion. The outputs of the 'Cordic core' are 'Xout' and 'Yout'. These outputs are used to generate addresses of scan coordinate on DDR2 SDRAM. Xout and Yout are added with the values set by the user according to size and dimensions of the frame to be displayed on the raster. X-address is generated by adding ½ value of horizontal size of the frame to 'Xout'. Y-address is generated by adding ½ value of vertical size of the frame to 'Yout' and this added value is then multiplied with horizontal size of frame. The final address is generated by adding X-address and Y- address.

FIGURE 7 illustrates a schematic flow diagram of a Memory_ADDR_Gen block that forms part of the Plan Position Indicator (PPI) of FIGURE 3. The final address with 'RDY' (ReaDY) signal is fed to a 'hole filling' block. 'RDY' signal is used to validate the Address. During the R,0 to X,Y conversion due to quantization, there are visible holes in the PPI. These holes are identified and marked as the scan progresses. These holes are later filled by adjacent pixel values. This logic is controlled by the hole filling block. The hole filling block also receives the 'enable' and 'data' signals from the 'RCP' block.

On every active pulse of 'enable' signal, the data is pipelined into a 'data pipe' before getting written in the DDR2 memory. The depth of this data pipe depends on the 'cordic core' latency. This delay is fixed throughout the execution of the block. To control the video frame, the state machine (mathematical abstraction sometimes used to design digital logic) is designed to arbiter the read and write of memory by the PPI block. Before writing to any memory location, the existing value at the same location is first compared with the new value to be written. In case the new value is lower than the previous value, after reset, the machine goes to an 'idle state' and waits for the 'enable' and 'RDY' signal. If 'RDY' and 'enable' signals are active, it means there is valid data and address to be written to a video frame, then design state changes to 'read state'. The 'read state' activates the 'read enable' signal. In the 'read state', the machine issues 'read' instruction to read one word from the memory. After the 'read state' it changes to a 'read wait state'. The 'read wait state' waits for confirmation of completion of the read cycle. Completion of read is confirmed by a memory controller. The memory controller reads 32bit data. This 32bit data consists of 4 bytes data i.e 4 pixels. While reading the data from memory, LSB (Least Significant Bits) 2 bits address of the memory is set to "00" to read the 4 bytes data. According to the actual value of these 2 bits, the target data is found. LSB of every byte is used to mark the holes and fill the holes. Holes are the addresses of pixels which are not generated by the 'Cordic core' in the scan area. These addresses are written with the adjacent data by using LSB bit of data. The LSB bit of the valid data is written as ' 1 '. This '0' is found on the LSB bit of data and then it is written with the adjacent byte data. According to the position of address, the adjacent data is decided. This process is called as hole filling. The final data consists of 1 byte of present valid address and 3 bytes of processed data. The valid byte is compared with the present data from a 'data pipe' and the greatest among those is merged with remaining 3 bytes to form 32bit data. After completion of data formation, the design moves to 'write state'. This state activates the 'write cycle' of DDR2 by 'wr_enable' signal. After 'write state' the design moves to 'write wait state'. This state waits for the write confirmation from the memory controller. After write completion is received, the design moves to 'idle state' and waits for the next enable. This process continuous according to the radar signals. PPI finally creates and updates the Scan frame on DDR2 memory. Raster Zoom-Pan Controller: FIGURE 8 illustrates a schematic flow diagram of a Raster Zoom-Pan Controller that forms a part of the Field Programmable Gate Array (FPGA) of FIGURE 2. The Raster Zoom-Pan Controller is designed independent of the Radar control signals. This module is controlled by Raster control signals arid User controls. Raster control signals are provided by the DVT, typically, RX TPF401. User controls are provided by PCIe user registers.

The size and dimensions of the 'scan frame' are adjusted according to user control signals. The size and dimensions are controlled by a View Window controller block. Positioning of this frame on the raster is done by a Pan Controller. Zoom in of this frame on raster is controlled by a 'Zoom controller'.

The Raster Zoom-Pan Controller provides a progressive or non-interlaced scanning mechanism for 1600x1200 at 162MHz raster display. Progressive scanning is a method for displaying, moving images in which all the lines of each frame are drawn in sequence. Raster Zoom-Pan Controller is interfaced with DDR2 SDRAM to read the scan frame data formed by the PPL Rather than going directly to Raster, the frame data is blended with synthetic data from CPU graphics card. Progressive scan is implemented by pushing the pixel data to display FIFO, by issuing DDR2 burst read (by reader means) during blanking region as shown in FIGURE 9. In accordance with an aspect of the present disclosure, the reader means being an alpha display means is configured to provide non-interlaced scanning for 1600 X 1200 resolution at 162MHz frequency. DDR2 burst read and FIFO write is controlled by 'DDR read & FIFO write controller' block. This block generates DDR2 read cycles during a blanking period to ensure alignment of the two frames. Control signals HSYNC and VSYNC are provided by CPU graphics card during front porch and back porch DDR2 issues 32 words burst transfers to read the row information in advance before the first pixel is displayed. The row information is stored in FIFO and form there the blending block reads the pixel data, blends it with synthetic data, forms graphics and then displays it.

FIGURE 10 illustrates a single 32 words burst transfer with 64 Bit DDR2. For a 1600x1200 resolution display, each row contains 1600 pixels and the display is provided with 1200 such rows. To read 1600 pixels in a row ' 13' 32 words burst transfers cycles are issued during blanking region. This design ensures that FIFO can never exhaust while display is in progress. Pixel FIFO has constraints regarding the depth. Pixel FIFO Rd Clk is generated by the PPI block which depends on display resolution and refresh rate. ZOOM block generates FIFO read according to the zoom ratio provided by the user.

During zooming, the scan appears to increase its diameter and the tiny target starts to appear distinctly on the screen. The user can set the view window within the frame so that during the zooming, the scan does not overlap the statistics window sourced by graphics cards. This feature is controlled by user registers.

Zoom-in of a frame is done by duplicating the pixels as shown in FIGURE 11. The data of source pixel at (2,3) is duplicated at (0,0) to (2,2). In the same way, pixel duplication is done both horizontally and vertically. Horizontally this is done by controlling FIFO reads. On duplication of pixel, 'FIFO read' is deactivated to repeat the same data. Duplication of pixels is generally done by multiplying present address with the zoom-ratio. Here present means the position of pixel on the raster. Horizontally this is a continuous increment of pixel counter on active 'DE'(Data Enable) pulse of raster. This pixel counter is from 0 to 1600. Zoom-ratio is a fraction of 'selected scan frame width' by 'raster width'. This is a floating value. To find the actual position of scan data on the raster, the zoom-ratio should be multiplied by the pixel counter. But this approach needs a floating point multiplier. By using a floating point multiplier, the design becomes slower and does not achieve the required operating frequency. To be able to meet the timing requirements and floating point constraints, the design recursively uses subtraction in place of floating point division. A 'zoom_hor' register is used to calculate the duplication of pixels. This register is initialized with A horizontal difference value on every active pulse of 'HSYNC. The 'zoom_hor' is incremented continuously by a horizontal difference and compared with a 'Raster width'. When the 'zoom_hor' is greater than or equals the 'Raster width', then duplication of pixels is done. The 'zoom_hor' is updated with a greater value of 'Raster width' and incremented with the horizontal difference. This process continues till the end of the 'DE' pulse.

This process controls FIFO read of scan data according to the zoom-ratio. The same process is done to vertical zoom by a 'zoom_ver' register by controlling a 'incr_next_line' signal. This signal is used to increment the address of DDR2 memory to read the scan data. Vertically, zoom-in is done by duplicating the line data. The 'incr_next_line' is deactivated on every duplication of line. This causes the memory controller to read back the same data. The 'zoom_ver' register is initialized on every active pulse of 'VSYNC. A combination of horizontal and vertical zoom-in controls makes the scan frame to fit on the raster.

A PAN logic block uses 'left blank size' and 'top blank size' to maintain the position of scan on the raster. The scan position is given by the user. This is updated by the start address of the scan, 'left blank size' and 'top blank size'. The 'left blank size' is the blanking space on the left side of the scan on the raster. This data should be "0" to generate 100% transparency on blending with the synthetic frame. Horizontal panning is controlled by a counter 'hor_blank' and 'start address'. The 'start address' is directly updated by the user. The 'hor_blank' is used to create blank data. This counter is initialized with the 'left blank size' on every active pulse on HSYNC. This counter is decremented by a unit value for every clock pulse with active pulse on the 'incr_nxt_data' from the ZOOM logic block.

Once this counter value becomes zero, then the 'incr_nxt_data' is multiplexed to FIFO read. Similarly the 'ver_blank' counter is used to create a blank space vertically. This counter is initialized by the 'top blank size' on every active pulse of VSYNC. This counter is controlled by the 'incr_next_line' from ZOOM logic block.

The 'Raster controller' is designed to route the DVI controls signals to Zoom, Pan and Memory controller block. The scan data from FIFO is routed to the Alpha blender in sync with the DVI control signals and 24 bit RGB color data of synthetic frame. The scan frame data is passed through the 'view-window controller' block. This block is similarly designed as PAN controller with four sides blanking data. The blanking data of each size is updated according to the user registers. The final scan data is sent to the Alpha blender as an 8 bit alpha value.

Alpha Blender: Alpha-blending is a technique which is used when computer graphics are laid on top of each other and one or more of the objects contain a transparent, or semi-transparent, portion. It ensures that pixels of graphics which are underneath a transparent area are visible through it and that their color or brightness is adjusted according to the degree of transparency of an upper object.

CPU graphics card sources 24-bit per pixel graphics comprising of three primary additive colors red, green and blue. The red channel contains information about how much red is contained in each pixel of the image, the green channel contains information about how much green is contained and so on. Each channel takes up eight of the 24 bits used to represent each pixel. On other hand Alpha defines the partial transparency through the pixel. A minimum Alpha value implies pixel is completely transparent, and value is maximum implies pixel is opaque. Translucency is defined between the two extreme Alpha values. FIGURE 12 illustrates pixel graphics when Alpha is saturated and for moderate Alpha.

For two Graphics, G₀ and G_l5 with blend factor a where 0 < a < 1.0, the output G_f is expressed by an equation given below:

GPU graphics card sourcing one graphics stream and the display means sourcing the Alpha value, the other graphic stream is sourced by user registers for Red Green and Blue. This technique also permits the user to change the scan color while scan is progressing. Depending on the Alpha value, radar scan is overlaid or under laid on the synthetic screen.

FIGURE 13 illustrates a schematic flow diagram of an Alpha blender that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2. User configurable color registers Red, Green and Blue can be accessed by a PLB interface. The Display means provides an 8 Bit alpha value for each pixel in the video frame via a DVI 1.0 compatible 24Bit/Pixel DVI receiver interface. TPF401 decodes DVI data from the CPU graphics card and provides 8 Bit Red, Green and Blue pixel information with HSYNC and VSYNC control signals though the 'Raster Zoom-Pan Controller'. Every pixel received with color modality is blended with user specified color and alpha provided by the display means. To realize this DSP48 Multipliers are provided in the FPGA as illustrated in FIGURE 14. The incoming pixel color components are latched at pixel CLK and multiplied with (1 - a). On the other hand, user specified color components are multiplied with a. The output of the multiplier is added to get the radar B-scan imaged fused with the synthetic video.

With control signals generated by AD9887 (HSYNC, VSYNC, DE), the fused image is displayed on the raster. The fused frame is offset by some pixels due to latency of the multiplier. This is taken care by delaying control signals by a margin of latency from the multiplier. This aligns the fused frames with the raster margins.

I²C Controller IP: The I²C Controller is attached to a PLB local bus as a slave attachment. The I²C Controller acts as a I²C master or a I²C slave depending on the configuration. The I C Controller is configured as master. The I C Controller is used to access the registers of the DVI transmitter for each configuration. The I C Controller is also used to access video gain controlling means to adjust gain of the radar analog video. The I C Controller is also used to access video threshold controlling means to adjust threshold of the radar analog video.

Scan Fader: FIGURE 15 illustrates a schematic flow diagram of a Scan Fader that forms part of the Field Programmable Gate Array (FPGA) of FIGURE 2. The Scan Fader is independent of radar signals. It is controlled by the user though PCIe. As shown in FIGURE 15, DDR2 RD block read data from every address of the frame at 125 MHz through a Multiport Memory Controller. Data from the DDR2 RD block is fed to a DDR2 WR block after deducting a unit value. The deducted value is written back to the DDR2 through the Multiport Memory Controller. A Fade Delay Controller block controls the speed of fading by adding a delay between frames. This is done by controlling the 'enable' signals of the DDR2 RD and the DDR2 WR blocks with reference to the user input from the PCIe CORE.

As described herein above, the FPGA system in accordance with the present disclosure is achieved on a single chip that is independent of the operating system and thus provides a compact and modular architecture which is robust, results in a longer life for the system, of the order of about 20 years, provides a practically loss free signal conversion, consumes less power of the order of about 0.75W and eliminates the need for dedicated heat sinks. The systems known in the art use static tables for R,0 to X,Y conversion whereas, the present disclosure uses CORDIC algorithms implemented in a single FPGA for the conversion. The display in the systems known in the art was static. The present disclosure envisages a display means which can display on the fly. The PPI is the heart of the present disclosure which enables a dynamic and interactive aerial view display with practically no time lag as is the case with the systems known in the art. The dynamic / real time display of the position of the target with practically no time lag is achieved by implementing PPI and Raster Zoom Pan controller as parallel, independent modules. On reception of every sample of radar video, PPI module updates the aerial scan video frame on DDR2 SDRAM by using CORDIC algorithm. In parallel to this, the Raster Zoom-Pan Controller is interfaced with DDR2 SDRAM to read the scan frame data formed by the PPI and displayed on raster.

TECHNICAL ADVANCEMENTS

The technical advancements offered by the present disclosure include the realization of:

• an integrated display of objects determined by a system processing radar signals using a Field Programmable Gate Array (FPGA);

• an open architecture based system processing radar _' signals using a Field Programmable Gate Array (FPGA);

• a dynamic and interactive aerial view display of the position of a target being mapped with practically no time lag;

• a modular architecture for a system processing radar signals using a Field Programmable Gate Array (FPGA);

• an increased rate of data transmission and processing in a system processing radar signals using a Field Programmable Gate Array (FPGA); and • a single chip Field Programmable Gate Array (FPGA) for all the functionalities relating to signal processing and plotting in a system processing radar signals.

The numerical values mentioned for the various physical parameters, dimensions or quantities are only approximations and it is envisaged that the values higher/lower than the numerical values assigned to the parameters, dimensions or quantities fall within the scope of the disclosure, unless there is a statement in the specification specific to the contrary.

Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

The use of the expression "at least" or "at least one" suggests the use of one or more elements or ingredients or quantities, as the use may be in the embodiment of the disclosure to achieve one or more of the desired objects or results.

The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.

Claims

1. A Field Programmable Gate Array (FPGA) system for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar, said system comprising:

• a Radar Scan Converter (RSC) comprising:

- radar interfacing means comprising:

o radar video conditioning and threshold detection means adapted to condition and detect a threshold of the analog radar video signal;

o video gain controlling means adapted to control gain of the analog radar video signal;

o video multiplexing means adapted to select a radar analog video signal to be monitored from the radar analog video signals;

o video adder means adapted to enable monitoring of the radar analog video signals; said video adder means being further adapted to precisely blend the radar analog video signals to a pre-determined magnitude; and o an Analog to Digital Converter(ADC) adapted to convert the selected radar analog video signal to a digital signal; and

- scan conversion means comprising:

o a Double Data Rate (DDR2) multiport controller with a predetermined number of read / write ports, each of said ports being provided with a pre-defined priority, said multiport controller being adapted to simultaneously initiate read / write requests on each of said ports;

o host processor means adapted to sequentially perform arithmetical, logical, and input/output operations of said system, said host processor being further adapted to generate a synthetic video;

o* reader means adapted to be connected to one of said ports having a highest priority, said reader means being adapted to read said video frames in burst mode and store as First-in- First-Out (FIFO);

o a raster zoom pan controller means adapted to position and resize said created aerial scan video frames;

o blending means adapted to blend said positioned and resized video frames with said synthetic video in real time to generate a fused video; o Low Power Giga bit Transceiver (LPGTs) means adapted to transmit and receive Peripheral Component Interconnect Express (PCIe) signal for user interface; and

• a housing adapted to enclose said receiver means and said Radar Scan Converter (RSC);

• a Double Data Rate Synchronous dynamic random access memory (DDR2 SDRAM) storage means adapted to receive and store said created frames; and

• a display means adapted to display said fused video at a predetermined resolution, said system adapted to generate a dynamic and interactive aerial view display of the position of the target with practically no time lag.

The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said radar analog video signals are blended to a magnitude of 5 V Peak-to peak.

The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said frame creation means is a Plan Position Indicator (PPI) co-operating with said raster zoom pan controller means and said blending means.

The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said blending means is an alpha blender.

5. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, further comprising:

• scan fader means adapted to erase said created video frames from said DDR2 SDRAM;

• Digital Video Interface (DVI) transmitter means adapted to transmit said fused video in real time to said display means, said DVI transmitter means being further adapted to receive configuration data from said I C Controller means; and

• Peripheral Component Interconnect express (PCIe) core means adapted to receive and decode user commands via said host processor means.

6. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein the control signal is selected from the group consisting of North Mark Indicator (NMI), Azimuth Change Pulse (ACP) Radar Sync Pulses (SYNC), Triggering pulses (TRIG) and digitized 8 bit video data.

7. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said Peripheral Component Interconnect express (PCIe) means is adapted to support 2.5 Gbps line speed with IX lane operation.

8. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said Peripheral Component Interconnect express (PCIe) means is adapted to support standard user interface with easy- to-use packet-based protocol, full-duplex communication and flow control of data received.

9. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said Peripheral Component Interconnect express (PCIe) means is adapted to be compliant with PCI Express transaction ordering rules.

10. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said frame creation means is adapted to perform real time 2D compression on said digital signal to create fixed sized frames for a 1600 x 1200 display.

11. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said reader means being an alpha display means is adapted to provide non-interlaced scanning for 1600 X 1200 resolution at 162MHz frequency.

12. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said Double Data Rate (DDR2) multi port memory controller is adapted to have three ports with port 0 being adapted to have a highest priority and port 3 being adapted to have a lowest priority, said blending means being an alpha blender is connected to port 0, said frame creation means being a Plan Position Indicator (PPI) is connected to port 1 and a scan fader means is connected to port 2.

A method for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar, said method comprising the following steps:

• receiving at least one control signal and at least one analog radar video signal in the form of electromagnetic reflections from the target;

• conditioning the radar control signal;

• conditioning and detecting a threshold of the analog radar video signal;

• controlling gain of the analog radar video signal;

• selecting a radar analog video signal to be monitored from the radar analog video signals;

• blending the radar analog video signal to a pre-determined magnitude;

• converting the radar analog video signal to a digital signal;

• receiving the conditioned radar control signal and the digital signal;

• creating aerial scan video frames using a (Coordinate Rotation Digital Computer) CORDIC algorithm co-operating with dynamic lookup tables;

• assigning a pre-defined priority to a pre-determined number of read / write ports;

• initiating read / write requests simultaneously on each of said ports; sequentially performing arithmetical, logical, and input/output operations of said system;

generating a synthetic video;

reading said video frames in burst mode and storing as First-in- First-Out (FIFO);

receiving and storing said created frames;

positioning and resizing said created aerial scan video frames;

blending said positioned and resized video frames with said synthetic video in real time;

generating a fused video; and

displaying said fused video at a pre-determined resolution with practically no time lag.