WO2011077453A2

WO2011077453A2 - Fpga system for processing radar based signals

Info

Publication number: WO2011077453A2
Application number: PCT/IN2010/000833
Authority: WO
Inventors: Raghukul Bhushan Dikshit; Pradeep N. Reddy
Original assignee: The Tata Power Company Ltd.
Priority date: 2009-12-24
Filing date: 2010-12-21
Publication date: 2011-06-30
Also published as: WO2011077453A3

Abstract

A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.

Description

FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS

FIELD OF THE INVENTION

This invention relates to the field of instrumentation.

Particularly, this invention relates to a system for processing signals.

Still particularly, this invention relates to a system for processing radar based signals.

BACKGROUND

Radar is typically employed to detect movement of targets / vehicles / aircraft / ships by transmitting and receiving electromagnetic waves. A radar system has a transmitter that emits microwaves or radio waves. These waves are in phase when emitted; however, when they come in contact with a target, they are scattered in all directions. The signal is thus partly reflected back and it has a slight change of wavelength (and thus frequency) if the target is moving. The receiver is usually, but not always, in the same location as the transmitter. Although the signal returned is usually very weak, the signal can be amplified through use of electronic techniques in the receiver and in the antenna configuration. This enables the radar to detect targets at ranges where other emissions, such as sound or visible light, would be too weak to detect. Use of radar systems typically include meteorological detection of precipitation, measuring ocean surface waves, air traffic control, police detection of speeding traffic, determining the speed of base balls and use for defence purposes. Modern radar systems typically use some sort of raster scan display to produce a map-like image. All early radar displays were built using oscilloscopes adapted suitably for various inputs. In a general sense, oscilloscopes are cathode ray tubes with three input channels that are attached to sources of varying voltage. The voltages are amplified and sent to one of the deflection magnets or an intensity channel, which controls the brightness of the spot on the screen. All of these channels are also equipped with a bias voltage source that allows the zero point to be set. By varying the voltages sent to the channels, the cathode beam can be made to move around, appearing as a spot on the display.

Further developments have occurred in the form of A-scope, B-scope, E- scope, H-scope and C-scope displays.

The original radar display was the A-scope, which displays the range to targets along a scale. These displays were also referred to as R-scope for range scope.

To draw the A-scope display, a saw tooth voltage generator was attached to the X-axis to move the oscilloscope spot across the screen at a fixed speed. The start of the sweep was triggered to coincide with the start of a radar pulse being sent out of the antenna, and the speed of the sweep was set to make it reach the far end (typically right side) of the display at the end of the pulse's maximum return time. Any reflected signal was amplified and sent directly to the display's Y-axis input, displacing the beam upward, drawing a "blip" (or "pip"). Since the pip appeared deflected along the X-axis over time, and the signal's return time corresponded to the distance to the target, the distance of the pip along the X-axis directly indicated the range to the target, and was generally measured against a scale below the display. The size of the blip along the Y- axis gave some indication of the number and size of the targets.

A B-scope provides a 2-D "top down" representation of space, ^'with the vertical axis typically representing range and the horizontal axis representing the azimuth (angle). B-scope displays were common in airborne radars in the 1950s and 60s, which were mechanically scanned from side to side, and sometimes up and down as well. The B-scope's display represented a horizontal "slice" of the airspace on both sides of the aircraft to the tracking angles of the radar. The spot was swept up the Y-axis in a fashion similar to the A-scope's X-axis, with distances "up" the display indicating greater range. This signal was mixed with a varying voltage being generated by a mechanical device that depended on the current horizontal angle of the antenna. The result was essentially an A-scope whose range line was rotated to point up, and then rotated back and forth about a zero point at the bottom of the display. The radio signal was sent into the intensity channel, producing a bright spot on the display indicating returns.

An E-scope is essentially a B-scope. displaying range versus elevation, rather than range versus azimuth. They are identical in operation to the B-scope, the name simply indicating "elevation". E-scopes are typically used with "height finding radars", which are similar to airborne radars but turned to scan vertically instead of horizontally; they are also sometimes referred to as "nodding radars" due to their antenna's motion. The display tube was generally rotated 90 degrees to put the elevation axis vertical in order to provide a more obvious correlation between the display and the "real world". These displays are also referred to as a Range-Height Indicator, or RHI, but were also commonly referred to as a B-scope as well.

The H-scope is another modification of the B-scope concept, but displays elevation as well as azimuth and range. The elevation information is displayed by drawing a second "blip" offset from the target indicator by a short distance; the slope of the line between the two blips indicates the elevation relative to the radar. For instance, if the blip were displaced directly to the right this would indicate that the target is at the same elevation as the radar. The offset is created by dividing the radio signal into two, then slightly delaying one of the signals so it appears offset on the display. The angle was adjusted by delaying the time of the signal via a delay, the length of the delay being controlled by a voltage varying with the vertical position of the antenna. This sort of elevation display could be added to almost any of the other displays, and was often referred to as a "double dot" display.

A C-scope displays a "bulls-eye" view of azimuth versus elevation. The "blip" was displayed indicating the direction of the target off the centerline axis of the radar, or more commonly, the aircraft or gun it was attached to. They were also known as "moving spot indicators", the moving spot being the target blip. The range is typically displayed separately in these cases, often as a number at the side of the display.

Almost identical to the C-scope is the G-scope, which overlays a graphical representation of the range to the target. This is typically represented by a horizontal line that "grows" out from the target indicator "blip" to form a wing-like diagram.

The PPI display provides a 2-D "all round" display of the airspace around a radar site. The distance out from the center of the display indicates range, and the angle around the display is the azimuth to the target. The current position of the radar antenna is typically indicated by a line extending from the center to the outside of the display, which rotates along with the antenna in real-time. It is essentially a B-scope extended to 360 degrees.

As seen in the systems known in the art, there are no integrated systems that contain all the essential modules for processing radar signals in a single compact system. More specifically, there is a need for a system for processing radar signals in such a way that it is independent of the Operating System and the display means.

OBJECTS OF THE INVENTION

An object of this invention is to provide an integrated system for processing radar signals.

Another object of this invention is to provide an open architecture based system for processing radar signals.

Yet another object of this invention is to provide a compact and modular architecture based system for processing radar signals.

Still another object of this invention is to provide a system having an increased rate of data transmission and processing of radar signals. An additional object of this invention is to provide a single chip system for all the functionalities relating to signal processing and plotting of radar signals.

Another object of this invention is to provide a robust system for processing radar signals.

Yet another object of this invention is to provide a system for processing radar signals having a practically loss free signal conversion.

Still another object of this invention is to provide a cost effective system for processing radar signals.

An additional object of this invention is to provide a low power system for processing radar signals.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a Field Programmable Gate Array (FPGA) system for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar,

the system comprising within a housing:

• a receiver means adapted to receive at least one control signal and at least one analog radar signal in the form of electromagnetic reflections from the target;

• a Radar Scan Converter (RSC) adapted to convert the analog radar signals from the receiver means to digital signal; • a Constant False Alarm Rate (CFAR) means adapted to condition the digital signal and produce filtered digital signal in real time;

• frame creation means adapted to receive the filtered digital signal and further adapted to compress the filtered digital signal to create video frames;

• a Double Data Rate (DDR) arbiter with a pre-determined number of read I write access ports, each of the ports being provided with a predefined priority, the arbiter being adapted to simultaneously initiate read / write requests on each of the ports;

• host processor means adapted to sequentially perform arithmetical, logical, and input/output operations of said system;

• reader means adapted to be connected to one of the ports having a highest priority, the reader means being adapted to read the video frames in burst mode and store in as First-in-First-Out (FIFO);

• blending means adapted to blend the created video frames with a synthetic video in real time to generate a fused video;

• a Processor Local Bus (PLB) adapted to connect the frame creation means, the DDR arbiter, the alpha display means and the alpha blending means to the host processor means;

• a Processor Local Bus (PLB) to Peripheral Component Interconnect (PCI) bridge adapted to translate PCI I/O request on the local bus; and in close proximity to the housing:

• Double Data Rate (DDR) storage means adapted to receive and store the created video frames; and

• display means adapted to display the fused video at a predetermined resolution. Typically, in accordance with this invention, the Field Programmable Gate Array (FPGA) system further comprises:

video multiplexing means adapted to select the radar signal to be monitored;

adder means adapted to enable monitoring of more than one radar signals, the adder being adapted to precisely blend the radar signals to a magnitude of 5V Peak-to peak before generating the digital signal; and

a Digital Video Interface (DVI) transmitter means adapted to transmit the fused video in real time to the display means

in close proximity to the housing.

Typically, in accordance with this invention, the control signal is selected from the group consisting of North Mark Indicator (NMI), Azimuth Change Pulse (ACP) and Radar Sync Pulses (SYNC).

Preferably, in accordance with this invention, the frame creation means is a B-scope.

Additionally, in accordance with this invention, the blending means is an alpha blending means.

Furthermore, in accordance with this invention, the frame creation means is a Peripheral Component Interconnect (PCI) based card adapted to support both 3.3V and 5V standards with FET bus switches adapted to facilitate hot- swapping and level translation on the PCI bus. Additionally, in accordance with this invention, the frame creation means is adapted to perform real time 2D compression on the RSC data to form fixed sized video frames for a 1280 x 1024 display.

In accordance with this invention, the reader means being an alpha display means is adapted to provide non-interlaced scanning for 1280 X 1024 resolution at 108MHz frequency.

Preferably, in accordance with this invention, the Double Data Rate (DDR) arbiter is adapted to have three ports with port 0 being adapted to have a highest priority and port 3 being adapted to have a lowest priority, the means being an alpha display is connected to port 0, the frame creation means is connected to port 1 and Picture in Picture (PIP) means is connected to port 2.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS

The invention will now be described in relation to the accompanying drawings, in which:

FIGURE 1 illustrates an overall schematic layout of a radar processing unit using a Field Programmable Gate Array (FPGA) system in accordance with the present invention for processing the radar signals;

FIGURE 2 illustrates a schematic flow diagram of the Field Programmable Gate Array (FPGA) system for processing radar signals in accordance with the present invention;

FIGURE 3 illustrates a schematic flow diagram of a B-scope that is part of the Field Programmable Gate Array (FPGA) system of FIGURE 2; FIGURE 4 illustrates a schematic flow diagram of a Alpha display that is part of the Field Programmable Gate Array (FPGA) system of FIGURE 2; and

FIGURE 5 illustrates a schematic block diagram of the Alpha blending means that is part of the Field Programmable Gate Array (FPGA) system of FIGURE 2.

DETAILED DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The invention will now be described with reference to the embodiments shown in the accompanying drawings. The embodiments do not limit the scope and ambit of the invention. The description relates purely to the exemplary preferred embodiments of the invention and its suggested applications.

The diagrams and the description hereto are merely illustrative and only exemplify the invention and in no way limit the scope thereof.

In accordance with the present invention, there is provided a Field Programmable Gate Array (FPGA) system adapted to read input radar signals and produce an output for plotting a regular radar display on a predefined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar.

FIGURE 1 illustrates an overall schematic layout of a radar processing unit using a Field Programmable Gate Array (FPGA) system in accordance with the present invention for processing radar signals and is indicated generally by the numeral 100.

The radar processing unit 100 envisages an embedded design with open bus architecture for processing radar signals. Various modules such as Range Cell Processor (RCP), Constant False Alarm Rate (CFAR), Picture in Picture (PIP), Blending, Correlation and Integration are implemented as independent design entities connected with a host processor by using an open bus standard such as IBM - Core Connect (PLB) bus standard. These entities with host interface are generic in nature and are not implemented specifically to meet applications like scan conversions. Typically, Constant False Alarm Rate (CFAR) is a system with an adaptive algorithm used in radar systems to detect returns against a background of noise, clutter and interference. Picture in Picture (PIP) is a feature of display devices wherein one program (channel) is displayed on the full screen of the display device at the same time as one or more other programs are displayed in inset windows.

The main components of the radar processing unit 100 as illustrated in FIGURE 1 are referenced generally with numerals as indicated below: a Field Programmable Gate Array (FPGA) system 110;

a Digital Visual Interface (DVI) receiver 112;

a Digital Visual Interface (DVI) transmitter 114;

an I/O control means 116;

a test header 118;

a buffer and level controller block 120;

FET bus switches 122; Double Data Rate (DDR) storage means 124;

a programming header 126;

a configuration PROM 128;

AID conversion block with gain control 130;

a voltage test header 132;

power supply for DDR and FPGA 134;

a video multiplexing means 136;

a video gain control means 138;

a video adder 140;

a radar video conditioning and thresholding means 142;

a radar control signal conditioning means 144; and

an analog power supply 146.

FIGURE 2 illustrates a schematic flow diagram of the Field Programmable Gate Array (FPGA) system 110 for processing radar signals in accordance with the present invention. The FPGA system incorporates a receiver means, a Radar Scan Converter (RSC), a Constant False Alarm Rate (CFAR) mechanism, frame creation means, a Double Data Rate (DDR) arbiter, a host processor, reader means, blending means, a Processor Local Bus (PLB) and a Processor Local Bus (PLB) to Peripheral Component Interconnect (PCI) bridge integrated within a housing and Double Data Rate (DDR) storage means and display means in close proximity to the housing; functions of each of these components being described in detail herein below.

The present invention is described herein below with reference to FIGURE 2 to FIGURE 5. In accordance with an embodiment of this invention, there is provided a receiver (not shown) for receiving at least one control signal and at least one analog radar signal. The radar receiver generates an electrical response to electromagnetic reflections from targets (Radar Scan Converter data) as well as control signals such as North Mark Indicator (NMI), Azimuth Change Pulse (ACP), and SYNC.

Typically, a north reference signal called the North Mark Indicator (NMI) is used provide indication when the radar is pointing in the North direction. One full rotation of the radar is divided into 4096 Azimuth Change Pulses (ACPs). These pulses are transmitted serially during the antenna rotation to indicate the azimuth. A complete antenna rotation is called an antenna scan, and begins with an Azimuth Reference Pulse (ARP) and ends just before the next ARP. Radar Sync Pulses (SYNC) are used to synchronize the system hardware to the external inputs. The SYNC pulses indicate a beginning of the radar signal video. This is required to synchronize the targets with reference to the North direction.

A Radar Scan Converter (RSC) is provided to convert the analog radar signals from the receiver to digital signals. A Constant False Alarm Rate (CFAR) mechanism then conditions the digital signal to produce filtered digital signal in real time.

A frame creation means is provided to receive the filtered digital signal from the radar. The filtered digital signal is compressed to create video frames. The frame creation means is a B-scope according to one aspect of the present invention. FIGURE 3 illustrates a schematic flow diagram of the B- scope. The B-scope performs 2D compression on the incoming radar video to form fixed sized video frames for a 1280x1024 display. The compression works in real time on the incoming data rather than storing the data temporarily and processing it in blocks. This approach is utilized so that video real time integrity is maintained. After compression, the video frames are created and written to DDR storage means or DDR memory through a DDR Memory Arbiter. Typically, the B-Scope is a Peripheral Component Interconnect (PCI) based card supporting both 3.3V and 5V standards with FET bus switches adapted to facilitate hot-swapping and level translation on the PCI bus. Analog inputs are fed from the rear side of the card. Radar video undergoes conditioning for bias correction and gain control to limit the signals to +/- 5V. The radar can provide more than one video signal under normal operating conditions. Video multiplexing enables the user to select the video which the user needs to monitor. A provision is provided such that the user can monitor more than one video by mixing the input signals using an adder. Each video to the adder has independent user programmable gain control for precise blending of video signals. The final blended signal has approximately a magnitude of 5V Peak-Peak (0 - 5V) before Analog to Digital (A/D) conversion.

The user interface to the B-Scope is via the PCI Bus. The DDR storage means contains the created video frames. These video frames are blended with synthetic video generated by a host CPU graphics card in a host processor. The implementation is such that there is no loss in graphics due to frame dropping, changing resolution and reducing refresh rate. The FPGA controls the DDR, the PCI and the DVI blending and provides necessary control signals to the analog sections for gain and offset control. In accordance with the preferred embodiment of this invention, there is provided means to provide a plurality of read/write ports, simultaneously, with priority allocation. This allows the FPGA to multitask with a plurality of input/output means in a time-shared manner, and base its priority on the computational logic embedded in the FPGA. Typically, this is a DDR Memory Arbiter. The DDR Memory Arbiter is a physical layer protocol for the DDR storage means which provides multiple read write access ports (portO to port7) to a single port memory. Only 3 ports are used in the preferred embodiment shown in FIGURE 2 of which Port 0 is used for the application requesting real time performance such as a reader means, typically an Alpha Display, Port 1 is used for the B-Scope and Port 2 (not shown) is used for the Picture in Picture (PIP) feature. On each port of the DDR Memory Arbiter, a user can initiate read and write requests simultaneously. These requests undergo arbitration with predefined priority to each port such that Port 0 has highest priority and Port 7 has the lowest priority to service the user requests.

A Processor Local Bus (PLB) is provided to connect the various modules in the FPGA namely, the B-Scope, the DDR arbiter, the alpha display and the alpha blending means to the host processor.

FIGURE 4 illustrates a schematic flow diagram of the Alpha display that is part of the Field Programmable Gate Array (FPGA) system of FIGURE 2. The Alpha display provides a progressive or non-interlaced scanning mechanism. Typically, the specification for this output is 1280x1024 at 108MHz raster display. Preferably, the Alpha display will be connected to Port 0 of the DDR memory arbiter for minimum latency. For 1280x1024 resolution display, each row will contain 1280 pixels and display will have 1024 such rows.

A host processor generates synthetic video on which the radar video is overlaid using alpha blending algorithm. FIGURE 5 illustrates a schematic block diagram of the Alpha blending means that is part of the Field Programmable Gate Array (FPGA) system of FIGURE 2. Alpha-blending is a technique which is used when computer graphics are laid on top of each other and one or more of the objects contain a transparent, or semi- transparent, portion. It ensures that the pixels of the graphics which are underneath a transparent area are visible through it and that their color or brightness is adjusted according to the degree of transparency of the upper object. The Alpha display reads the pixel data for each row of the raster during horizontal blanking and stores it in FIFO format. The Alpha Blending means reads the FIFO at 108MHz (Pixel clock) from the Alpha display and blends it with the synthetic video. This mechanism ensures real time blending of the images and displays it on the raster without dropping resolution or refresh rate. The B-Scope and Alpha Display are connected to both the PLB as well as MIP (Memory Interface Port) buses. The B-Scope and Alpha Display require control registers to be set by the host processor which is done using the PLB bus. The B-Scope creates video frames and stores it in the DDR storage means which is done using the MIP bus. The MIP bus connects the B-Scope and the Alpha Display to the DDR Memory Arbiter. Thus the MIP bus is used wherever DDR interface is required. The Alpha display provides an 8 Bit alpha value for each pixel in the video frame. A DVI receiver provides DVI 1.0 compatible 24Bit/Pixel DVI receiver interface. The DVI receiver decodes DVI data form the CPU graphics card and provides 8 Bit Red, Green and Blue pixel information with HSYNC and VSY C control signals. The Alpha blending means blends every pixel which will be received by the DVI receiver with color modality, user specified color and alpha provided by the Alpha display. The fused video will be displayed on the raster having DVI interface using a DVI transmitter.

An Inter-Integrated Circuit Bus Controller (I C controller) is used to provide access to the registers of the DVI transmitter and receiver for its configuration. The I²C Controller is attached to the PLB local bus as a slave attachment. It is a multi-master serial computer bus that is used to attach low-speed peripherals to a motherboard, an embedded system, or a cell phone. The DVI is a display standard similar to VGA technology used in Desktop Computers wherein VGA deals with Analog signals and DVI deals with Digital signals. A Processor Local Bus (PLB) to Peripheral Component Interconnect (PCI) Bridge is used to provide full bridge functionality between the PLB and a PCI component. Typically, the PCI component is a 32-bit compliant Peripheral Component Interconnect (PCI) bus. The PCI32 core provides an interface with the PCI bus. Host Bridge configures Read and Write PCI commands which can be performed from the PLB-side of the bridge. The PLB to PCI Bridge supports 32-bit/33 MHz PCI bus only with parameters that will allow the bridge to suit the system in accordance with the preferred embodiment of the present invention disclosed herein above. As described herein above, the FPGA system in accordance with the present invention is achieved on a single chip that is independent of the operating system and thus provides a compact and modular architecture which is robust, results in a longer life for the system, of the order of about 20 years, provides a practically loss free signal conversion, consumes less power of the order of about 0.75 W and eliminates the need for dedicated heat sinks.

TECHNICAL ADVANCEMENTS

The technical advancements offered by the present invention include the realization of:

• an integrated system for processing radar signals;

• an open architecture based system for processing radar signals;

• a compact and modular architecture based system for processing radar signals;

• a system having an increased rate of data transmission and processing of radar signals;

• a single chip system for all the functionalities relating to signal processing and plotting of radar signals;

• a robust system for processing radar signals;

• a system for processing radar signals having a practically loss free signal conversion; • a cost effective system for processing radar signals; and

• a low power system for processing radar signals.

The numerical values given for various physical parameters, dimensions and quantities are only approximate values and it is envisaged that the values higher or lower than the numerical value assigned to the physical parameters, dimensions and quantities fall within the scope of the invention unless there is a statement in the specification to the contrary.

While considerable emphasis has been placed herein on the particular features of this invention, it will be appreciated that various modifications can be made, and that many changes can be made in the preferred embodiment without departing from the principles of the invention. These and other modifications in the nature of the invention or the preferred embodiments will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be interpreted merely as illustrative of the invention and not as a limitation.

Claims

Claims:

1. A Field Programmable Gate Array (FPGA) system for processing radar signals and generating an easy-to-read rendition of the position of a target being mapped by the radar,

said system comprising within a housing:

• a Radar Scan Converter (RSC) adapted to convert the analog radar signals from said receiver means to digital signal;

• a Constant False Alarm Rate (CFAR) means adapted to condition said digital signal and produce filtered digital signal in real time;

• frame creation means adapted to receive said filtered digital signal and further adapted to compress said filtered digital signal to create video frames;

• a Double Data Rate (DDR) arbiter with a pre-determined number of read / write access ports, each of said ports being provided with a pre-defmed priority, said arbiter being adapted to simultaneously initiate read / write requests on each of said ports;

• reader means adapted to be connected to one of said ports having a highest priority, said reader means being adapted to read said video frames m burst mode and store in as First-in- First-Out (FIFO);

• blending means adapted to blend said created video frames with a synthetic video in real time to generate a fused video;

• a Processor Local Bus (PLB) adapted to connect said frame creation means, said DDR arbiter, said alpha display means and said alpha blending means to said host processor means;

• a Processor Local Bus (PLB) to Peripheral Component Interconnect (PCI) bridge adapted to translate PCI I/O request on the local bus; and

in close proximity to said housing:

• Double Data Rate (DDR) storage means adapted to receive and store said created video frames; and

• display means adapted to display said fused video at a predetermined resolution.

2. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 further comprising:

video multiplexing means adapted to select the radar signal to be monitored;

adder means adapted to enable monitoring of more than one radar signals, said adder being adapted to precisely blend the radar signals to a magnitude of 5V Peak-to peak before generating said digital signal; and

a Digital Video Interface (DVI) transmitter means adapted to transmit said fused video in real time to said display means in close proximity to said housing.

3. The Field Programmable Gate Array (FPGA) system as claimed in. claim 1, wherein said control signal is selected from the group consisting of North Mark Indicator (NMI), Azimuth Change Pulse (ACP) and Radar Sync Pulses (SYNC).

4. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 , wherein said frame creation means is a B-scope.

5. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 , wherein said blending means is an alpha blending means.

6. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 , wherein said frame creation means is a Peripheral Component Interconnect (PCI) based card adapted to support both 3.3V and 5V standards with FET bus switches adapted to facilitate hot-swapping and level translation on the PCI bus.

7. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 , wherein said frame creation means is adapted to perform real time 2D compression on said RSC data to form fixed sized video frames for a 1280 x 1024 display.

8. The Field Programmable Gate Array (FPGA) system as claimed in claim 1 , wherein said reader means being an alpha display adapted to provide non-interlaced scanning for 1280 X 1024 resolution at 108MHz frequency. The Field Programmable Gate Array (FPGA) system as claimed in claim 1, wherein said Double Data Rate (DDR) arbiter is adapted to have three ports with port 0 being adapted to have a highest priority and port 3 being adapted to have a lowest priority, said means being an alpha display is connected to port 0, said frame creation means is connected to port 1 and Picture in Picture (PIP) means is connected to port 2.