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WO2011115041A1 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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Publication number
WO2011115041A1
WO2011115041A1 PCT/JP2011/055907 JP2011055907W WO2011115041A1 WO 2011115041 A1 WO2011115041 A1 WO 2011115041A1 JP 2011055907 W JP2011055907 W JP 2011055907W WO 2011115041 A1 WO2011115041 A1 WO 2011115041A1
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WO
WIPO (PCT)
Prior art keywords
redundant
electrode
hole
defective
position information
Prior art date
Application number
PCT/JP2011/055907
Other languages
French (fr)
Japanese (ja)
Inventor
春生 岩津
松本　俊行
Original Assignee
東京エレクトロン株式会社
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Filing date
Publication date
Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Publication of WO2011115041A1 publication Critical patent/WO2011115041A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device manufactured by the manufacturing method.
  • an electrical test is performed on a circuit formed on a semiconductor wafer of a semiconductor chip (hereinafter referred to as “wafer”), and a defective memory cell determined as defective in the electrical test is determined as a redundant memory. Relieving by replacing the cell.
  • Such a defective memory cell is remedied by, for example, a laser trimming process using a plurality of fuse elements that can be blown by a laser beam. Specifically, the address of the defective memory cell determined to be defective by the electrical test of the circuit is held by fusing a fuse element provided on the circuit side of the semiconductor chip with laser light. Based on the address of the defective memory cell, the defective memory cell is replaced with a redundant memory cell (Patent Document 1).
  • the semiconductor device to be manufactured becomes thick due to the thickness of the wafer. Therefore, for example, before stacking the semiconductor chips, a support substrate is provided on the circuit side of the semiconductor chips, and the wafer is thinned by polishing the back surface of the wafer.
  • the method for relieving a defective memory cell described in the above-mentioned conventional document 1 cannot be applied. That is, since the support substrate is provided on the circuit side of the semiconductor chip, the fuse element cannot be blown by the laser beam. Then, the address of the defective memory cell cannot be recorded, and the defective memory cell cannot be replaced with a redundant memory cell. For this reason, the yield of the semiconductor device is reduced.
  • the present invention has been made in view of the above points, and when a semiconductor device is manufactured by stacking semiconductor chips, a defective electronic element in a circuit of the semiconductor chip is relieved and the yield of the semiconductor device is improved. With the goal.
  • a normal element region in which a plurality of electronic elements are arranged, and a redundant electronic element for replacing a defective electronic element in the normal element region Forming a plurality of circuits having redundant element regions on the substrate surface, forming a device layer including the circuit on the substrate surface, and penetrating in a thickness direction of the substrate and the device layer
  • the through hole forming step a redundant through hole penetrating the substrate and the device layer is formed, and in the defective position information recording step, the position information of the defective electronic element is recorded in the defective position information recording unit. Yes. Therefore, for example, in the above-described three-dimensional integration technology, even when a support substrate is provided on the surface of the device layer on the substrate and a semiconductor device is manufactured by stacking semiconductor chips, the position of the defective electronic element from the back side of the substrate Information can be recorded. Then, in the redundant replacement step, based on the position information of the defective electronic element recorded in the defective position information recording unit, the defective electronic element is replaced with the redundant electronic element and repaired, thereby improving the yield of the semiconductor device. Can do. In addition, in the through hole forming step, the redundant through hole is formed together with the electrode through hole, so that it is not necessary to perform a separate step of forming the redundant through hole. Therefore, the semiconductor device can be manufactured efficiently.
  • each position information line corresponding to the plurality of redundant through holes may be connected to a ground line or a power line.
  • the plurality of redundant through holes are a pair of redundant through holes provided with a first redundant through hole for power supply line connection and a second redundant through hole for ground line connection.
  • a plurality of holes, and in the defect position information recording step, a power line and a position information line are connected via the first redundant through hole, or a ground line is connected via the second redundant through hole.
  • the position information line may be connected to record the position information of the defective electronic element in the defective position information recording unit.
  • the upper portion of the first redundant through hole is filled with a conductive material
  • the lower portion of the first redundant through electrode is filled with an insulating material.
  • the second redundant through hole is filled with an insulating material, and when the ground line and the position information line are connected, the upper portion of the second redundant through hole is filled with a conductive material, and
  • the insulating material may be filled in the lower part of the second redundant through electrode, and the insulating material may be filled in the first redundant through hole.
  • the plurality of electronic elements are arranged in a lattice shape so as to be specified by a row address and a column address, and in the redundant element region, the redundant electronic element is arranged for each row address, In the redundant replacement step, the defective electronic element may be replaced with the redundant electronic element for each row address.
  • the electronic element and the redundant electronic element may each have volatility.
  • the through hole forming step the plurality of electrode through holes and the plurality of redundant through holes are formed, and the substrate and the device layer are divided to form a plurality of semiconductor chips having the circuit.
  • the scribe line may be formed.
  • an electrical test of the circuit may be performed for each semiconductor chip.
  • the electrode through hole, the through electrode, the redundant through hole, and the scribe line are formed to extend from the surface of the device layer to the inside of the substrate, respectively.
  • a support substrate is provided on the surface of the device layer, and then the back surface of the substrate is polished to thereby form the through electrode, the redundant through hole, and the scribe.
  • Each line may be formed through the substrate in the thickness direction.
  • the semiconductor chips may be stacked and joined after the redundant replacement step.
  • the semiconductor chips may be stacked and bonded after the defect position information recording step and before the redundant replacement step.
  • the substrate and the device layer may be stacked and bonded, and then the bonded substrate and device layer may be divided for each semiconductor chip having the circuit.
  • the substrate and the device layer are stacked and bonded, and then the bonded substrate and device layer are provided for each semiconductor chip having the circuit. It may be divided.
  • the plurality of redundant electronic elements to be replaced may be arranged so as to be continuous in the redundant element region.
  • a probe In the circuit test process, a probe is used that is disposed at a position corresponding to the through electrode and has a conductive liquid attached to the tip thereof. In the circuit test process, the probe is brought close to the through electrode to conduct the conductive test. You may carry out in the state which made the property liquid contact the said penetration electrode.
  • the conductive liquid for example, a liquid having a nano-order diameter and diffusing conductive metal particles is used.
  • the present invention is a semiconductor device manufactured using a predetermined manufacturing method, wherein the predetermined manufacturing method includes a normal element region in which a plurality of electronic elements are arranged, and a normal element region in the normal element region.
  • the predetermined manufacturing method includes a normal element region in which a plurality of electronic elements are arranged, and a normal element region in the normal element region.
  • the A defective position information recording step for recording position information of defective electronic elements in the normal element region in the defective position information recording unit having the plurality of redundant through holes, and defective electrons recorded in the defective position information recording unit And a redundant replacement step of replacing the defective electronic element with the redundant electronic element based on the position information of the element.
  • the present invention when a semiconductor device is manufactured by stacking semiconductor chips, defective electronic elements in the circuit of the semiconductor chip can be remedied and the yield of the semiconductor device can be improved.
  • FIG. 1 shows a main processing flow of the semiconductor device manufacturing method according to the present embodiment.
  • a plurality of circuits 11 are formed on the surface of a wafer 10 as a substrate. Then, a device layer 12 including these circuits 11 is formed on the surface of the wafer 10 (step S1 in FIG. 1). In the device layer 12, in addition to the circuit 11, signal wiring (not shown) for power supply, grounding, and an address as position information is also formed.
  • the circuit 11 has a normal cell array region 20 as a normal element region and a redundant cell array region 21 as a redundant element region as shown in FIG.
  • a normal cell array region 20 In the normal cell array region 20, a plurality of memory cells 22 as volatile electronic elements are arranged.
  • the memory cells 22 are arranged in a lattice shape so as to be specified by a row address and a column address.
  • a plurality of redundant memory cells 23 as volatile redundant electronic elements for replacing defective memory cells as defective electronic elements in the normal cell array area 20 are arranged in the redundant cell array region 21. Redundant memory cells 23 are arranged for each row address, and are arranged in a line in the present embodiment.
  • Memory cell 22 and redundant memory cell 23 are connected to word line 24 and bit line 25, respectively.
  • the number of columns of redundant memory cells 23 in the redundant cell array region 21 is not limited to the present embodiment, and is determined according to the failure mode. That is, in the normal cell array region 20, for example, in the failure mode in which two defective memory cells are detected in one row address, the redundant memory cells 23 in the redundant cell array region 21 are arranged in two columns.
  • a plurality of electrode through holes 30 and a plurality of redundant holes are formed so as to extend from the surface of the device layer 12 to the inside of the wafer 10 as shown in FIGS.
  • a through-hole 31 for use and a scribe line 32 are respectively formed (step S2 in FIG. 1).
  • the electrode through-hole 30, the redundant through-hole 31, and the scribe line 32 are lower end positions of the wafer 10 that have been thinned by polishing the back surface of the wafer 10 so as to penetrate in the thickness direction of the wafer 10 in step S5 described later. Or deeper than its lower end position.
  • the electrode through-hole 30 is formed at a position corresponding to the circuit 11.
  • the redundant through holes 31 include the number of input matrix address buses 83 to be described later corresponding to the memory cells 22 of the circuit 11, the number (two) of redundant through holes 31 for power supply connection and ground line connection, and redundancy.
  • the plurality of redundant through holes 31 form a defective address recording portion 33 to be described later.
  • the scribe line 32 is formed such that the wafer 10 and the device layer 11 to be divided include at least one circuit 11.
  • the electrode through hole 30, the redundant through hole 31, and the scribe line 32 are simultaneously formed by, for example, a photolithography process and an etching process. That is, after a predetermined resist pattern is formed on the device layer 12 by photolithography, the device layer 12 and the wafer 10 are etched using the resist pattern as a mask, so that the electrode through hole 30, the redundant through hole 31, the scribe line are etched. A line 32 is formed. 4 and 5, the positions and sizes of the electrode through hole 30, the redundant through hole 31, the scribe line 32, and the defective address recording unit 33 as the defective position information recording unit make it easy to understand the technology. In order to give priority, it does not necessarily correspond to the actual position and size. These positions and sizes are not limited to the illustrated example and can be arbitrarily selected.
  • the electrode through hole 30, the redundant through hole 31, and the scribe line 32 do not penetrate in the thickness direction of the wafer 10 in the step S2, but the wafer 10 is thinned in the step S5 to be described later. Since it is formed so as to penetrate in the thickness direction of 10, it is expressed as penetration or scribe for convenience.
  • each electrode through hole 30 is filled with a conductive material to form a through electrode 34 as shown in FIG.
  • the through electrode 34 is formed so as to be electrically connected to the circuit 11 (step S3 in FIG. 1).
  • the through electrode 34 does not penetrate in the thickness direction of the wafer 10 at the stage of step S3, but is formed so as to penetrate in the thickness direction of the wafer 10 by thinning the wafer 10 in step S5 described later. Therefore, it is expressed as penetration for convenience.
  • a support wafer 40 as a support substrate is disposed on the surface of the device layer 12 (step S4 in FIG. 1).
  • the support wafer 40 is bonded to the device layer 12 by, for example, an adhesive.
  • the support substrate is not limited to a wafer, and for example, a glass substrate or the like may be used.
  • the back surface of the wafer 10 is polished to thin the wafer 10 (step S5 in FIG. 1).
  • the through electrode 34 electrode through hole 30
  • the redundant through hole 31 and the scribe line 32 penetrate in the thickness direction of the wafer 10.
  • the wafer 10 and the device layer 12 are divided by the scribe line 22 to form a plurality of semiconductor chips 50.
  • the inspection device 60 includes a tester 61 and a plurality of probes 62 supported on the tester 61 and having conductivity.
  • the probe 62 is disposed at a position corresponding to the through electrode 34.
  • a conductive liquid 63 is attached to the tip of the probe 62.
  • the conductive liquid 63 for example, a liquid having a nano-order diameter and diffusing conductive metal particles is used.
  • the inspection apparatus 60 When performing an electrical test using such an inspection apparatus 60, first, the inspection apparatus 60 is raised to the wafer 10 side and the probe 62 is brought close to the through electrode 34. Then, the conductive liquid 63 spreads by its surface tension and comes into contact with the through electrode 34. Subsequently, an electrical signal is sent from the tester 61 to the circuit 11 through the probe 62, the conductive liquid 63, and the through electrode 34, and an electrical test of the circuit 11 is performed.
  • the shape of the probe 62 is not limited to the illustrated example, and can take various shapes such as a cantilever shape.
  • the address of the defective memory cell is recorded by cutting the fuse from the device side. For this reason, two electrical tests are performed: a probe test performed in a state where the wafer and the device layer before the support wafer is bonded and a device layer are not divided, and a final test performed for each semiconductor chip.
  • the conventional probe test can be omitted.
  • the electrical test of the circuit 11 for each semiconductor chip 50 can be easily performed collectively.
  • the address of the defective memory cell is recorded in the defective address recording unit 33 (step S7 in FIG. 1).
  • the plurality of redundant through holes 31 are provided with a first redundant through hole 31a for power supply line connection and a second redundant through hole for ground line connection as shown in FIGS. And a hole 31b.
  • Each of the pair of redundant through holes 31a and 31b is formed by the number of (number of input matrix address bus 83) ⁇ (number of redundant memory cells 23).
  • the number of redundant through holes 31 is (number of input matrix address bus 83) ⁇ (two for power supply connection and ground line connection) ⁇ (number of redundant memory cells 23).
  • the device layer 12 of the defective address recording unit 33 is provided with an address line 70 and a power supply line 71 as position information lines for output on both sides of the first redundant through hole 31a. Further, an address line 72 and a ground line 73 as output position information lines are wired on both sides of the second redundant through hole 31b.
  • the address of the defective memory cell is recorded by signals “1” and “0”.
  • the address line 70 and the power supply line 71 are connected through the first redundant through hole 31a as shown in FIGS.
  • the upper portion of the first redundant through hole 31a is filled with the conductive material 74
  • the lower portion of the first redundant through hole 31a is filled with the insulating material 75
  • the second redundant through hole 31a is filled.
  • the through hole 31b is filled with an insulating material 75.
  • the upper portion of the second redundant through hole 31b is filled with the conductive material 74, and the lower portion of the second redundant through hole 31b is filled with the insulating material 75, and the first redundant through hole 31b is filled.
  • An insulating material 75 is filled in the through hole 31a.
  • the address of the defective memory cell is recorded in the defective address recording unit 33. Since the insulating material 75 is filled in the lower portions of the first redundant through hole 31a and the second redundant through hole 31b in this way, the semiconductor chip 50 is laminated and bonded in step S9 described later.
  • the address line 70, the power supply line 71, the address line 72, and the ground line 73 are electrically connected through the first redundant through hole 31a and the second redundant through hole 31b, respectively.
  • the filling of the conductive material 74 and the insulating material 75 into the redundant through hole 31 may be performed by, for example, an ink jet method.
  • a plurality of nozzles may be arranged corresponding to the formation pattern of the redundant through holes 31, and the conductive material 74 or the insulating material 75 may be supplied from each nozzle to the corresponding redundant through hole 31.
  • the defective memory cell is replaced with the redundant memory cell 23 in the redundant cell array region 21 based on the address of the defective memory cell (step of FIG. 1). S8).
  • an address input from the outside is latched in the address buffer 80.
  • the row address is output to the row address decoder 81.
  • the word line 24 is selected by decoding the row address.
  • the column address is output to the comparator 82. Further, the row address and column address of the defective memory cell recorded by the defective address recording unit 33 are input to the comparator 82.
  • the comparator 82 compares the input matrix address from the outside with the matrix address of the defective memory cell. As shown in FIG. 14, the comparator 82 includes an input matrix address bus 83 for transmitting the input matrix address A from the address buffer 80 and a defective matrix address bus 84 for transmitting the matrix address B of the defective memory cell. Have. Then, the input matrix address A and the matrix address B of the defective memory cell are compared, and if they match, “1” is output as the signal Y, and if they do not match, “0” is output as the signal Y.
  • the matrix address B of a plurality of defective memory cells is input to one comparator 82, but a comparator may be provided for each defective memory cell.
  • the comparator compares the input matrix address A from the address buffer 80 with the matrix address B of one defective memory cell.
  • the comparison result is output to the circuit, and in the circuit, it is determined which comparator matches the matrix addresses A and B. If they match, “1” is output as the signal Y, and if they do not match, “0” is output as the signal Y.
  • Subsequent replacement of the defective memory cell with the redundant memory cell 23 is as described above, and thus the description thereof is omitted.
  • a read / write circuit 86 is connected to the normal cell array region 20 and the redundant cell array region 21. By this read / write circuit 86, data can be exchanged between the data input / output buffer 87 and the normal cell array region 20 and the redundant cell array region 21.
  • the electrical test of the circuit 11 may be performed again in the same manner as in step S6.
  • the above-described processes of steps S1 to S8 are separately performed, and the non-defective semiconductor chip 50 after the redundant replacement of the defective memory cell is formed. Thereafter, as shown in FIG. 15, the semiconductor chip 50 supported by one support wafer 40 and the semiconductor chip 50 supported by another support wafer 40 are stacked and joined in the vertical direction (step S9 in FIG. 1). At this time, the semiconductor chips 50 are joined so that the through electrodes 34 are conductive.
  • the upper support wafer 40 is removed (step S10 in FIG. 1).
  • the removal of the upper support wafer 40 is performed, for example, by heating the support wafer 40 and the semiconductor chip 50 to weaken the adhesiveness of the adhesive.
  • step S7 the address line 70 and the power supply line 71 are connected via the first redundant through hole 31a, or the address line is connected via the second redundant through hole 31b.
  • the address of the defective memory cell can be recorded in the defective address recording unit 33. Therefore, in the three-dimensional integration technique, even when the support wafer 40 is disposed on the surface of the device layer 12 on the wafer 10 and the semiconductor device 100 is manufactured by stacking the semiconductor chips 50, the back surface side of the wafer 10.
  • the address of the defective memory cell can be recorded in the defective address recording unit 33.
  • step S8 based on the address of the defective memory cell recorded in the defective address recording unit 33, the defective memory cell is replaced by the redundant memory cell 23 and repaired. Therefore, the yield of the semiconductor device 100 is improved. Can do.
  • the address of the defective memory cell can be recorded in the defective address recording unit 33. Therefore, for example, a volatile semiconductor chip 50 such as a DRAM.
  • the non-volatile defective address recording unit 33 can be formed functionally.
  • the defective address recording unit 33 can be formed by a simple method. That is, in step S ⁇ b> 2, the redundant through hole 31 of the defective address recording unit 33 is formed together with the electrode through hole 30. For this reason, it is not necessary to perform the process of forming the redundant through-hole 31 separately.
  • the address line 70 and the power supply line 71 are connected via the first redundant through hole 31a by filling the redundant through hole 31 with the conductive material 74 or the insulating material 75 by, for example, an inkjet method.
  • the defective address recording section 33 can be formed by connecting the address line 72 and the ground line 73 through the second redundant through hole 31b.
  • the semiconductor device 100 can be manufactured efficiently.
  • step S8 the defective memory cells can be replaced with the redundant memory cells 23 on a one-to-one basis for each row address, so that the defective memory cells can be efficiently relieved.
  • step S2 the scribe line 32 is formed together with the electrode through hole 30 and the redundant through hole 31, so that the step of forming the scribe line 32, that is, the wafer 10 and the device layer 12 are divided to form the semiconductor chip 50. There is no need to perform the process of forming separately. Therefore, the semiconductor device 100 can be manufactured more efficiently.
  • step S6 the electrical test of the circuit 10 is performed for each semiconductor chip 50 in a state where the plurality of semiconductor chips 50 are supported by the support wafer 40. That is, a final test for each semiconductor chip 50 can be performed from the beginning without performing a conventional probe test. Therefore, the semiconductor device 100 can be manufactured more efficiently.
  • step S6 the electrical test of the circuit 11 is performed by causing the conductive liquid 63 and the through electrode 34 to conduct. Since the conductive liquid 63 spreads by the surface tension and contacts the penetrating electrode 34, the electrical test of the circuit 11 can be performed even if the probe 62 is not arranged with strict positional accuracy with respect to the penetrating electrode 34. Moreover, when the test is performed with the probe in direct contact with the through electrode, the contact load increases. However, in this embodiment, since the conductive liquid 63 contacts the through electrode 34, the contact load can be reduced. it can. Therefore, the electrical test of the circuit 11 can be performed efficiently.
  • the semiconductor chip 50 is stacked in step S9.
  • the defective memory cell is replaced with the redundant memory cell.
  • the cell 23 may be replaced.
  • the defective memory cell in the upper semiconductor chip 50 is relieved in a state where the upper support wafer 40 is removed.
  • the yield of the semiconductor device 100 can be improved.
  • the electrode through hole 30, the redundant through hole 31, and the scribe line 32 are formed in step S2, the through electrode 34 is formed in step S3, and then the surface of the device layer 12 in step S4.
  • the electrode through hole 30, the redundant through hole 31, the scribe line 32, and the through electrode 34 are formed. May be.
  • the other steps S1 and the steps S5 to S10 are the same as those in the above embodiment, and the description thereof is omitted.
  • the defective address recording unit 33 is provided with the first redundant through hole 31a for connecting the power supply line and the second redundant through hole 31b for connecting the ground line separately.
  • a redundant through-hole 110 that serves both as a power supply line connection and a ground line connection may be provided.
  • the address line 70 and the power supply line 71 are wired on both sides of the redundant through hole 110.
  • An address line 72 and a ground line 73 are wired on both sides of the redundant through hole 110 and above the address line 70 and the power supply line 71.
  • the address line 70 and the power supply line 71 are connected via the redundant through hole 110 as shown in FIG.
  • the portion corresponding to the power supply line 71 of the redundant through hole 110 is filled with the conductive material 74, and the portion corresponding to the ground line 73 and the portion corresponding to the power supply line 71 of the redundant through hole 110 are used.
  • An insulating material 75 is filled in the lower part.
  • the conductive material 74 is filled in the portion corresponding to the ground line 73 of the redundant through hole 110, and the insulating material 75 is formed in the portion corresponding to the power line 71 of the redundant through hole 110 and the lower portion thereof. Fill.
  • the number of redundant through holes 110 is half the number of redundant through holes 31 of the above embodiment, and the addresses of defective memory cells can be recorded using the redundant through holes 110.
  • the address line 72 and the ground line 73 are provided above the address line 70 and the power line 71.
  • the address line 70 and the power line 71 are provided above the address line 72 and the ground line 73. May be.
  • the scribe line 32 is formed in step S2 to divide the wafer 10 and the device layer 12, and then the semiconductor chip 50 is laminated and bonded in step S9. After laminating and bonding, the wafer 10 and the device layer 12 may be divided.
  • step S1 After forming the device layer 12 on the wafer 10 in step S1, a plurality of electrode through holes 30 and a plurality of redundant through holes 31 (not shown) are formed in step S2 as shown in FIG. To do. At this time, the scribe line 32 is not formed as in the above embodiment. Thereafter, in step S3, as shown in FIG. 21, each electrode through hole 30 is filled with a conductive material to form a through electrode 34. In step S4, the support wafer 40 is disposed on the surface of the device layer 12. Then, after the back surface of the wafer 10 is polished and thinned in step S5 as shown in FIG. 22, the circuit 11 is electrically tested using the inspection device 60 from the back surface side of the wafer 10 in step S6. .
  • step S7 the address of the defective memory cell is recorded in the defective address recording unit 33, and in step S8, the defective memory cell is replaced with the redundant memory cell 23 and repaired.
  • step S9 as shown in FIG. 23, the wafer 10 (and the device layer 12) from which the defective memory cell is relieved is stacked and bonded in the vertical direction.
  • step S10 the support wafer 40 is removed.
  • the wafers when the wafers are simply stacked in the conventional manner, it is difficult to relieve the defective memory cell with the redundant memory cell.
  • the laminated wafer is divided for each semiconductor chip, defective memory cells that cannot be relieved in one semiconductor chip remain, so that the laminated semiconductor chip itself becomes a defective product.
  • the yield of the semiconductor device 100 can be improved even when the wafer 10 and the device layer 12 are divided after being stacked. it can.
  • the method of the present invention is particularly useful when the wafer 10 and the device layer 12 are stacked and then divided as in the present embodiment.
  • the wafer 10 and the device layer 12 are stacked in step S9.
  • the wafer 10 and the device layer 12 are stacked.
  • the defective memory cell may be replaced with the redundant memory cell 23.
  • the wafer 10 (and the device layer 12) having the non-defective memory cells 22 can be stacked, the yield of the semiconductor device 100 can be improved.
  • the redundant cell array region 21 of the above embodiment may be shared by a plurality of blocks.
  • the semiconductor chip 50 (circuit 11) is provided with, for example, a plurality of blocks A1 and A2.
  • Each of the blocks A1 and A2 has a normal cell array region 20.
  • the redundant cell array region 21 that shares the word line 24 is provided in the blocks A1 and A2.
  • the configuration of other defective address recording unit 33, address buffer 80, row address decoder 81, comparator 82, column address recorder 85, read / write circuit 86, input / output buffer 87, and the like is the same as that of the above embodiment. Therefore, the description is omitted.
  • the defective memory cells 22a and 22b of the blocks A1 and A2 can be repaired by replacing them with the redundant memory cells 23a and 23b, respectively.
  • the yield of the apparatus 100 can be improved.
  • the number of redundant memory cells 23 in the redundant cell array region 21 is one column.
  • the number of columns is not limited to this embodiment, and the number of columns is two or more columns. May be.
  • the possibility that these defective memory cells can be replaced with the redundant memory cells 23 and repaired is improved. To do.
  • the semiconductor chip 50 (circuit 11) is provided with a plurality of, for example, four blocks B1, B2, B3, and B4.
  • Each of the blocks B1 to B4 has a normal cell array region 20 and a redundant cell array region 21, respectively.
  • Each block B1 to B4 is provided with a row address decoder 81, a column address recorder 85, a read / write circuit 86, and an input / output buffer 87.
  • step S8 of replacing the defective memory cell with the redundant memory cell 23 in the semiconductor chip 50 will be described.
  • the address (address map data) of the defective memory cell recorded in the defective address memory recording unit 33 in step S7 is output to the defective address buffer 120.
  • the address of the defective memory cell is latched and output to the comparator 82.
  • the address of the defective memory cell is also output from the defective address buffer 120 to the address conversion circuit 121.
  • an address input from the outside is latched and output to the comparator 82.
  • the comparator 82 compares the input matrix address from the outside with the matrix address of the defective memory cell. Specifically, it is determined whether or not the input matrix address matches the matrix address of the defective memory cell, and it is determined whether or not the memory cell 22 is a defective memory cell. Note that the comparison of addresses in the comparator 82 is the same as that in the above embodiment, so that the description thereof is omitted.
  • an address mismatch signal is output from the comparator 82 to the row address decoder 81 and the column address recorder 85 of each of the blocks B1 to B4.
  • an address match signal is output from the comparator 82 to the address conversion circuit 121 as indicated by a dotted arrow in FIG.
  • the address of the defective memory cell input from the defective address buffer 120 is used to access the redundant memory cell 23 to which the defective memory cell is replaced (hereinafter referred to as “redundant memory access address”). )).
  • the redundant memory access addresses correspond one-to-one in order from the lower to the higher address of the defective memory cell. Redundant memory address access addresses are associated in order from the bottom.
  • the redundant memory access address converted by the address conversion circuit 121 is output from the address conversion circuit 121 to the row address decoder 81 and the column address recorder 85 of each of the blocks B1 to B4. Is done.
  • the address conversion circuit 121 when an address of a predetermined defective memory cell is input, a circuit that generates “1” only at the address is created.
  • the redundant memory access address is output by this "1" signal. In such a case, the address for redundant memory access is not output because it is “0” in other cases. Therefore, a redundant memory access address corresponding to the defective memory cell on a one-to-one basis is output. Then, the redundant memory cell 23 is accessed based on the redundant memory access address, and the defective memory cell is replaced with the redundant memory cell 23 to be relieved.
  • the defective memory cell 22a of the block B1, the defective memory cell 22b of the block B2, and the defective memory cell 22c of the block B3 are respectively connected to the blocks B1 and B2.
  • B3 is replaced by the redundant memory cell 23 in the redundant cell array region 21, and is repaired.
  • the defective memory cell is relieved for each of the blocks B1, B2, and B3, for example, if all the redundant memory cells 23 in the redundant cell array region 21 of the block B1 are replaced, the normal cell array region 20 of the block B1 is replaced.
  • the defective memory cell cannot be relieved any more.
  • the defective memory cell of the block B1 cannot be relieved, and the semiconductor chip 50 becomes a defective product. That is, when viewed as a whole of the semiconductor chip 50, the semiconductor chip 50 becomes a defective product even though the redundant cell memory 23 remains.
  • defective memory cells 22a, 22b, and 22c in different blocks B1, B2, and B3 are replaced with redundant memory cells 23a, 23b, 23c is rearranged.
  • redundant memory cells 23a, 23b, and 23c are continuously arranged.
  • redundant memory cells 23 are continuously arranged in the redundant cell array region 21 in the blocks B2, B3, and B4.
  • the redundant memory cell 23 can be used effectively, the number of redundant memory cells 23 to be arranged in the circuit 11 can be reduced, and the semiconductor chip 50 can be reduced in size. It can also be converted.
  • the address conversion circuit 121 of the above embodiment may convert the address of the defective memory cell into an address for redundant memory address access using the same method as the defective address recording unit 33. That is, the redundant memory address access address corresponding one-to-one with the address of the defective memory cell may be recorded using the same method as the defective address recording unit 33. In such a case, the address conversion can be performed more efficiently. Note that the specific recording method of this address is the same as that in the above embodiment, and the description thereof will be omitted.
  • a memory (not shown) in which a redundant memory access address corresponding to the address of the defective memory cell is written in advance as data may be used.
  • the redundant memory access address data corresponding to the defective memory cell address is read from the memory. If the addresses compared by the comparator 82 do not match, the redundant memory 23 is accessed based on the read address data, and the defective memory cell is replaced with the redundant memory cell 23 to be relieved.
  • a memory cell memory element
  • the present invention can also be applied to other electronic elements such as a logic element. That is, by using the method of the present invention, a defective logic element can be replaced with a redundant logic element and repaired.
  • defective memory cells are relieved in units of memory cells, but defective aggregates may be relieved in units of memory cell aggregates.
  • a set of memory cells a set of arbitrary units is selected. For example, a so-called block which is a set of normal cell array regions 20 in which the same address is selected is used. In such a case, the defective block can be replaced with a redundant block and repaired using the method of the present invention.
  • the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood.
  • the present invention is not limited to this example and can take various forms.
  • the present invention can also be applied to a case where the substrate is another substrate such as an FPD (flat panel display) other than a wafer or a mask reticle for a photomask.
  • FPD flat panel display
  • the present invention is useful when a semiconductor device is manufactured by stacking semiconductor chips.

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Abstract

A device layer including a plurality of circuits is formed on a surface of a substrate. Thereafter, a plurality of electrode through-holes, a plurality of redundancy through-holes and scribe lines are formed in the substrate and device layer. Thereafter, feedthrough electrodes are formed in the electrode through-holes. Thereafter, a support board is provided on the device layer surface. Thereafter, the substrate is thinned. Thereafter, an electrical test of the circuits is performed. Thereafter, positional information of faulty electronic elements is recorded into a fault positional-information recording part having the plurality of redundancy through-holes. Thereafter, the faulty electronic elements are replaced by redundant electronic elements. Thereafter, semiconductor chips are jointed. Thereafter, the support board located on the upper side is removed.

Description

半導体装置の製造方法及び半導体装置Semiconductor device manufacturing method and semiconductor device
　本発明は、半導体装置の製造方法及びその製造方法で製造される半導体装置に関する。 The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufactured by the manufacturing method.
　半導体装置の製造工程では、半導体チップの半導体ウェハ（以下、「ウェハ」という。）上に形成された回路の電気的試験を行い、当該電気的試験において不良と判定された不良メモリセルを冗長メモリセルに置換して救済することが行われている。 In the manufacturing process of a semiconductor device, an electrical test is performed on a circuit formed on a semiconductor wafer of a semiconductor chip (hereinafter referred to as “wafer”), and a defective memory cell determined as defective in the electrical test is determined as a redundant memory. Relieving by replacing the cell.
　かかる不良メモリセルの救済は、例えばレーザ光で溶断可能な複数のヒューズ素子を用いたレーザトリミング処理によって行われる。具体的には、回路の電気的試験で不良と判定された不良メモリセルのアドレスが、半導体チップの回路側に設けられたヒューズ素子をレーザ光で溶断することによって保持される。そして、この不良メモリセルのアドレスに基づいて、不良メモリセルが冗長メモリセルに置換される（特許文献１）。 Such a defective memory cell is remedied by, for example, a laser trimming process using a plurality of fuse elements that can be blown by a laser beam. Specifically, the address of the defective memory cell determined to be defective by the electrical test of the circuit is held by fusing a fuse element provided on the circuit side of the semiconductor chip with laser light. Based on the address of the defective memory cell, the defective memory cell is replaced with a redundant memory cell (Patent Document 1).
日本国特開２００７－２９９９３９号公報Japanese Unexamined Patent Publication No. 2007-299939
　ところで、近年、半導体装置の高性能化が進んでいる。かかる状況下で、例えばＤＲＡＭ等の半導体チップを水平面内に複数配置し、これら半導体チップを配線で接続して半導体装置を製造する場合、配線長が増大し、それにより配線の抵抗が大きくなること、また配線遅延が大きくなることが懸念される。 By the way, in recent years, the performance of semiconductor devices has been improved. Under such circumstances, when a semiconductor device is manufactured by arranging a plurality of semiconductor chips such as DRAMs in a horizontal plane and connecting these semiconductor chips with wiring, the wiring length increases, thereby increasing the resistance of the wiring. Moreover, there is a concern that the wiring delay becomes large.
　そこで、半導体チップを３次元に積層する３次元集積技術を用いることが考えられている。この場合、単に半導体チップを積層すると、ウェハの厚みにより、製造される半導体装置も厚くなる。そこで、例えば半導体チップを積層する前に、半導体チップの回路側に支持基板を設け、ウェハの裏面を研磨して当該ウェハを薄化することが行われる。 Therefore, it is considered to use a three-dimensional integration technique in which semiconductor chips are stacked three-dimensionally. In this case, if the semiconductor chips are simply stacked, the semiconductor device to be manufactured becomes thick due to the thickness of the wafer. Therefore, for example, before stacking the semiconductor chips, a support substrate is provided on the circuit side of the semiconductor chips, and the wafer is thinned by polishing the back surface of the wafer.
　しかしながら、かかる３次元集積技術において、上述の従来文献１に記載された不良メモリセルの救済方法を適用することができない。すなわち、半導体チップの回路側には支持基板が設けられているため、ヒューズ素子をレーザ光で溶断することができない。そうすると、不良メモリセルのアドレスを記録することができず、さらに不良メモリセルを冗長メモリセルに置換することができない。このため、半導体装置の歩留まり低下が生じることになる。 However, in such a three-dimensional integration technique, the method for relieving a defective memory cell described in the above-mentioned conventional document 1 cannot be applied. That is, since the support substrate is provided on the circuit side of the semiconductor chip, the fuse element cannot be blown by the laser beam. Then, the address of the defective memory cell cannot be recorded, and the defective memory cell cannot be replaced with a redundant memory cell. For this reason, the yield of the semiconductor device is reduced.
　本発明は、かかる点に鑑みてなされたものであり、半導体チップを積層して半導体装置を製造する際に、当該半導体チップの回路の不良電子素子を救済し、半導体装置の歩留まりを向上させることを目的とする。 The present invention has been made in view of the above points, and when a semiconductor device is manufactured by stacking semiconductor chips, a defective electronic element in a circuit of the semiconductor chip is relieved and the yield of the semiconductor device is improved. With the goal.
　前記の目的を達成するため、本発明は、半導体装置を製造する方法において、複数の電子素子が配置された通常素子領域と、前記通常素子領域内の不良電子素子を置換するための冗長電子素子が配置された冗長素子領域とを備えた回路を基板表面に複数形成して、当該基板表面に前記回路を含むデバイス層を形成するデバイス形成工程と、前記基板及び前記デバイス層の厚み方向に貫通する、複数の電極用貫通孔と複数の冗長用貫通孔をそれぞれ形成する貫通孔形成工程と、前記電極用貫通孔に導電性材料を充填し、前記回路に電気的に接続される貫通電極を形成する電極形成工程と、前記基板の裏面側から前記貫通電極を介して前記回路の電気的試験を行う回路試験工程と、前記回路試験工程で検出された前記通常素子領域内の不良電子素子の位置情報を、前記複数の冗長用貫通孔を有する不良位置情報記録部に記録する不良位置情報記録工程と、前記不良位置情報記録部に記録された不良電子素子の位置情報に基づいて、当該不良電子素子を前記冗長電子素子に置換する冗長置換工程と、を有する。なお、本発明における電子素子は、例えばメモリ素子（メモリセル）やロジック素子である。また、本発明における位置情報は、例えば不良電子素子を識別するための情報であって、例えば電子素子のアドレスである。 To achieve the above object, according to the present invention, in a method of manufacturing a semiconductor device, a normal element region in which a plurality of electronic elements are arranged, and a redundant electronic element for replacing a defective electronic element in the normal element region Forming a plurality of circuits having redundant element regions on the substrate surface, forming a device layer including the circuit on the substrate surface, and penetrating in a thickness direction of the substrate and the device layer A through-hole forming step of forming a plurality of electrode through-holes and a plurality of redundant through-holes, respectively, and filling the electrode through-holes with a conductive material and electrically connecting the through-electrodes to the circuit An electrode forming step to be formed, a circuit test step for conducting an electrical test of the circuit from the back side of the substrate through the through electrode, and defective electrons in the normal element region detected in the circuit test step Based on the defect position information recording step for recording the child position information in the defect position information recording unit having the plurality of redundant through holes, and the position information of the defective electronic element recorded in the defect position information recording unit, A redundant replacement step of replacing the defective electronic element with the redundant electronic element. The electronic element in the present invention is, for example, a memory element (memory cell) or a logic element. Further, the position information in the present invention is information for identifying a defective electronic element, for example, and is an address of the electronic element, for example.
　本発明によれば、貫通孔形成工程において、基板及びデバイス層を貫通する冗長用貫通孔を形成し、不良位置情報記録工程において、不良位置情報記録部に不良電子素子の位置情報を記録している。したがって、例えば上述した３次元集積技術において、基板上のデバイス層表面に支持基板を設け、半導体チップを積層して半導体装置を製造する場合であっても、基板の裏面側から不良電子素子の位置情報を記録することができる。そして、冗長置換工程において、不良位置情報記録部に記録された不良電子素子の位置情報に基づいて、当該不良電子素子を冗長電子素子に置換して救済するので、半導体装置の歩留まりを向上させることができる。しかも、貫通孔形成工程において、冗長用貫通孔は電極用貫通孔と共に形成されるので、別途冗長用貫通孔を形成する工程を行う必要がない。したがって、半導体装置を効率よく製造することができる。 According to the present invention, in the through hole forming step, a redundant through hole penetrating the substrate and the device layer is formed, and in the defective position information recording step, the position information of the defective electronic element is recorded in the defective position information recording unit. Yes. Therefore, for example, in the above-described three-dimensional integration technology, even when a support substrate is provided on the surface of the device layer on the substrate and a semiconductor device is manufactured by stacking semiconductor chips, the position of the defective electronic element from the back side of the substrate Information can be recorded. Then, in the redundant replacement step, based on the position information of the defective electronic element recorded in the defective position information recording unit, the defective electronic element is replaced with the redundant electronic element and repaired, thereby improving the yield of the semiconductor device. Can do. In addition, in the through hole forming step, the redundant through hole is formed together with the electrode through hole, so that it is not necessary to perform a separate step of forming the redundant through hole. Therefore, the semiconductor device can be manufactured efficiently.
　前記不良位置情報記録工程において、前記複数の冗長用貫通孔に対応する各々の位置情報線を接地線又は電源線に接続してもよい。 In the defect position information recording step, each position information line corresponding to the plurality of redundant through holes may be connected to a ground line or a power line.
　前記不良位置情報記録部において、前記複数の冗長用貫通孔は、電源線接続用の第１の冗長用貫通孔と接地線接続用の第２の冗長用貫通孔を備えた一対の冗長用貫通孔を複数有し、前記不良位置情報記録工程において、前記第１の冗長用貫通孔を介して電源線と位置情報線を接続するか、あるいは前記第２の冗長用貫通孔を介して接地線と位置情報線を接続することで、前記不良位置情報記録部に前記不良電子素子の位置情報を記録してもよい。 In the defect position information recording section, the plurality of redundant through holes are a pair of redundant through holes provided with a first redundant through hole for power supply line connection and a second redundant through hole for ground line connection. A plurality of holes, and in the defect position information recording step, a power line and a position information line are connected via the first redundant through hole, or a ground line is connected via the second redundant through hole. And the position information line may be connected to record the position information of the defective electronic element in the defective position information recording unit.
　前記電源線と位置情報線を接続する際には、前記第１の冗長用貫通孔の上部に導電性材料を充填し、且つ第１の冗長用貫通電極の下部に絶縁性材料を充填すると共に、前記第２の冗長用貫通孔に絶縁性材料を充填し、前記接地線と位置情報線を接続する際には、前記第２の冗長用貫通孔の上部に導電性材料を充填し、且つ第２の冗長用貫通電極の下部に絶縁性材料を充填すると共に、前記第１の冗長用貫通孔に絶縁性材料を充填してもよい。 When the power supply line and the position information line are connected, the upper portion of the first redundant through hole is filled with a conductive material, and the lower portion of the first redundant through electrode is filled with an insulating material. The second redundant through hole is filled with an insulating material, and when the ground line and the position information line are connected, the upper portion of the second redundant through hole is filled with a conductive material, and The insulating material may be filled in the lower part of the second redundant through electrode, and the insulating material may be filled in the first redundant through hole.
　前記通常素子領域には、前記複数の電子素子が行アドレスと列アドレスで特定されるように格子状に配置され、前記冗長素子領域には、各行アドレス毎に前記冗長電子素子がそれぞれ配置され、前記冗長置換工程において、各行アドレス毎に不良電子素子を前記冗長電子素子に置換してもよい。 In the normal element region, the plurality of electronic elements are arranged in a lattice shape so as to be specified by a row address and a column address, and in the redundant element region, the redundant electronic element is arranged for each row address, In the redundant replacement step, the defective electronic element may be replaced with the redundant electronic element for each row address.
　前記電子素子と前記冗長電子素子は、それぞれ揮発性を有していてもよい。 The electronic element and the redundant electronic element may each have volatility.
　前記貫通孔形成工程において、前記複数の電極用貫通孔と前記複数の冗長用貫通孔を形成すると共に、前記基板及び前記デバイス層を分割して、前記回路を有する複数の半導体チップを形成するためのスクライブラインを形成してもよい。 In the through hole forming step, the plurality of electrode through holes and the plurality of redundant through holes are formed, and the substrate and the device layer are divided to form a plurality of semiconductor chips having the circuit. The scribe line may be formed.
　前記回路試験工程において、前記半導体チップ毎に前記回路の電気的試験を行ってもよい。 In the circuit test step, an electrical test of the circuit may be performed for each semiconductor chip.
　前記貫通孔形成工程と前記電極形成工程において、前記電極用貫通孔、前記貫通電極、前記冗長用貫通孔及び前記スクライブラインをそれぞれデバイス層の表面から前記基板の内部まで延伸するように形成し、前記電極形成工程後であって前記回路試験工程前に、前記デバイス層の表面に支持基板を設け、その後、前記基板の裏面を研磨することにより、前記貫通電極、前記冗長用貫通孔、前記スクライブラインをそれぞれ前記基板の厚み方向に貫通させて形成してもよい。 In the through hole forming step and the electrode forming step, the electrode through hole, the through electrode, the redundant through hole, and the scribe line are formed to extend from the surface of the device layer to the inside of the substrate, respectively. After the electrode forming step and before the circuit testing step, a support substrate is provided on the surface of the device layer, and then the back surface of the substrate is polished to thereby form the through electrode, the redundant through hole, and the scribe. Each line may be formed through the substrate in the thickness direction.
　前記冗長置換工程後に、前記半導体チップを積層して接合してもよい。あるいは、前記不良位置情報記録工程後であって前記冗長置換工程前に、前記半導体チップを積層して接合してもよい。 The semiconductor chips may be stacked and joined after the redundant replacement step. Alternatively, the semiconductor chips may be stacked and bonded after the defect position information recording step and before the redundant replacement step.
　また、前記冗長置換工程後において、前記基板及び前記デバイス層を積層して接合した後、前記回路を有する半導体チップ毎に前記接合された基板及びデバイス層を分割してもよい。あるいは、前記不良位置情報記録工程後であって前記冗長置換工程前において、前記基板及び前記デバイス層を積層して接合した後、前記回路を有する半導体チップ毎に前記接合された基板及びデバイス層を分割してもよい。 In addition, after the redundant replacement step, the substrate and the device layer may be stacked and bonded, and then the bonded substrate and device layer may be divided for each semiconductor chip having the circuit. Alternatively, after the defective position information recording step and before the redundant replacement step, the substrate and the device layer are stacked and bonded, and then the bonded substrate and device layer are provided for each semiconductor chip having the circuit. It may be divided.
　前記冗長置換工程において、複数の前記不良電子素子が前記冗長電子素子に置換された場合に、当該置換される複数の冗長電子素子は冗長素子領域内で連続するように配置されてもよい。 In the redundant replacement step, when a plurality of defective electronic elements are replaced with the redundant electronic elements, the plurality of redundant electronic elements to be replaced may be arranged so as to be continuous in the redundant element region.
　前記回路試験工程では、前記貫通電極に対応する位置に配置され、且つ先端に導電性液が付着したプローブが用いられ、当該回路試験工程は、前記プローブを前記貫通電極に近接させて、前記導電性液を前記貫通電極に接触させた状態で行われてもよい。なお、導電性液には、例えばナノオーダの径を有し、かつ導電性を有する金属粒子を拡散させた液が用いられる。 In the circuit test process, a probe is used that is disposed at a position corresponding to the through electrode and has a conductive liquid attached to the tip thereof. In the circuit test process, the probe is brought close to the through electrode to conduct the conductive test. You may carry out in the state which made the property liquid contact the said penetration electrode. As the conductive liquid, for example, a liquid having a nano-order diameter and diffusing conductive metal particles is used.
　別な観点による本発明は、所定の製造方法を用いて製造される半導体装置であって、前記所定の製造方法は、複数の電子素子が配置された通常素子領域と、前記通常素子領域内の不良電子素子を置換するための冗長電子素子が配置された冗長素子領域とを備えた回路を基板表面に複数形成して、当該基板表面に前記回路を含むデバイス層を形成するデバイス形成工程と、前記基板及び前記デバイス層の厚み方向に貫通する、複数の電極用貫通孔と複数の冗長用貫通孔をそれぞれ形成する貫通孔形成工程と、前記電極用貫通孔に導電性材料を充填し、前記回路に電気的に接続される貫通電極を形成する電極形成工程と、前記基板の裏面側から前記貫通電極を介して前記回路の電気的試験を行う回路試験工程と、前記回路試験工程で検出された前記通常素子領域内の不良電子素子の位置情報を、前記複数の冗長用貫通孔を有する不良位置情報記録部に記録する不良位置情報記録工程と、前記不良位置情報記録部に記録された不良電子素子の位置情報に基づいて、当該不良電子素子を前記冗長電子素子に置換する冗長置換工程と、を有する。 The present invention according to another aspect is a semiconductor device manufactured using a predetermined manufacturing method, wherein the predetermined manufacturing method includes a normal element region in which a plurality of electronic elements are arranged, and a normal element region in the normal element region. Forming a plurality of circuits on a substrate surface with a redundant element region in which redundant electronic elements for replacing defective electronic elements are arranged, and forming a device layer including the circuit on the substrate surface; A through hole forming step of forming a plurality of electrode through holes and a plurality of redundant through holes, respectively, penetrating in the thickness direction of the substrate and the device layer; and filling the electrode through holes with a conductive material, Detected in an electrode forming step of forming a through electrode electrically connected to the circuit, a circuit test step of performing an electrical test of the circuit from the back side of the substrate through the through electrode, and the circuit test step. The A defective position information recording step for recording position information of defective electronic elements in the normal element region in the defective position information recording unit having the plurality of redundant through holes, and defective electrons recorded in the defective position information recording unit And a redundant replacement step of replacing the defective electronic element with the redundant electronic element based on the position information of the element.
　本発明によれば、半導体チップを積層して半導体装置を製造する際に、当該半導体チップの回路の不良電子素子を救済し、半導体装置の歩留まりの向上させることができる。 According to the present invention, when a semiconductor device is manufactured by stacking semiconductor chips, defective electronic elements in the circuit of the semiconductor chip can be remedied and the yield of the semiconductor device can be improved.
半導体装置の製造方法の各工程を示したフローチャートである。It is the flowchart which showed each process of the manufacturing method of a semiconductor device. ウェハ上にデバイス層を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the device layer was formed on the wafer. 回路の構成の概略を示す説明図である。It is explanatory drawing which shows the outline of a structure of a circuit. ウェハ及びデバイス層に電極用貫通孔及びスクライブラインが形成された様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the through-hole for electrodes and the scribe line were formed in the wafer and the device layer. ウェハ及びデバイス層に電極用貫通孔、冗長用貫通孔及びスクライブラインが形成された様子を示す平面の説明図である。It is explanatory drawing of the plane which shows a mode that the through-hole for electrodes, the through-hole for redundancy, and the scribe line were formed in the wafer and the device layer. 電極用貫通孔に貫通電極を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the penetration electrode was formed in the through-hole for electrodes. デバイス層の表面に支持ウェハを配設した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the support wafer was arrange | positioned on the surface of a device layer. ウェハを薄化し、半導体チップを形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the wafer was thinned and the semiconductor chip was formed. 回路の電気的試験を行う様子を示す説明図である。It is explanatory drawing which shows a mode that the electrical test of a circuit is performed. 第１の冗長用貫通孔を介してアドレス線と電源線を接続した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the address line and the power supply line were connected via the 1st redundancy through-hole. 第１の冗長用貫通孔を介してアドレス線と電源線を接続した様子を示す横断面の説明図である。It is explanatory drawing of the cross section which shows a mode that the address line and the power supply line were connected via the 1st redundancy through-hole. 第２の冗長用貫通孔を介してアドレス線と接地線を接続した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the address line and the grounding line were connected via the 2nd redundancy through-hole. 第２の冗長用貫通孔を介してアドレス線と接地線を接続した様子を示す横断面の説明図である。It is explanatory drawing of the cross section which shows a mode that the address line and the grounding line were connected via the 2nd redundancy through-hole. コンパレータの構成の概略を示す説明図である。It is explanatory drawing which shows the outline of a structure of a comparator. 半導体チップを積層して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the semiconductor chip was laminated | stacked and joined. 上側の支持ウェハを除去した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the upper support wafer was removed. 半導体装置が製造された様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the semiconductor device was manufactured. 他の実施の形態にかかる冗長用貫通孔を介してアドレス線と電源線を接続した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the address line and the power supply line were connected through the redundant through-hole concerning other embodiment. 他の実施の形態にかかる冗長用貫通孔を介してアドレス線と接地線を接続した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the address line and the grounding line were connected via the redundant through-hole concerning other embodiment. 他の実施の形態において、ウェハ及びデバイス層に電極用貫通孔が形成された様子を示す縦断面の説明図である。In other embodiment, it is explanatory drawing of the longitudinal cross-section which shows a mode that the through-hole for electrodes was formed in the wafer and the device layer. 他の実施の形態において、電極用貫通孔に貫通電極を形成し、デバイス層の表面に支持ウェハを配設した様子を示す縦断面の説明図である。In other embodiment, it is explanatory drawing of the longitudinal cross-section which shows a mode that the penetration electrode was formed in the through-hole for electrodes, and the support wafer was arrange | positioned on the surface of the device layer. 他の実施の形態において、ウェハを薄化し、回路の電気的試験を行う様子を示す説明図である。In other embodiment, it is explanatory drawing which shows a mode that a wafer is thinned and an electrical test of a circuit is performed. 他の実施の形態において、ウェハを積層して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the wafer was laminated | stacked and joined in other embodiment. 他の実施の形態において、複数のウェハを積層して接合した様子を示す縦断面の説明図である。In other embodiment, it is explanatory drawing of the longitudinal cross-section which shows a mode that several wafers were laminated | stacked and joined. 他の実施の形態における回路の構成の概略を示す説明図である。It is explanatory drawing which shows the outline of a structure of the circuit in other embodiment. 他の実施の形態における回路の構成の概略を示す説明図である。It is explanatory drawing which shows the outline of a structure of the circuit in other embodiment. 他の実施の形態における冗長セルアレイ領域の構成の概略を示す説明図である。It is explanatory drawing which shows the outline of a structure of the redundant cell array area | region in other embodiment.
　以下、本発明の実施の形態について説明する。図１は、本実施の形態にかかる半導体装置の製造方法の主な処理フローを示している。 Hereinafter, embodiments of the present invention will be described. FIG. 1 shows a main processing flow of the semiconductor device manufacturing method according to the present embodiment.
　先ず、図２に示すように基板としてのウェハ１０の表面に複数の回路１１を形成する。そして、ウェハ１０の表面にこれら回路１１を含むデバイス層１２を形成する（図１の工程Ｓ１）。なお、デバイス層１２には、回路１１のほか、電源用、接地用、位置情報としてのアドレス等の信号用配線（図示せず）も形成されている。 First, as shown in FIG. 2, a plurality of circuits 11 are formed on the surface of a wafer 10 as a substrate. Then, a device layer 12 including these circuits 11 is formed on the surface of the wafer 10 (step S1 in FIG. 1). In the device layer 12, in addition to the circuit 11, signal wiring (not shown) for power supply, grounding, and an address as position information is also formed.
　なお、回路１１は、図３に示すように通常素子領域としての通常セルアレイ領域２０と冗長素子領域としての冗長セルアレイ領域２１を有している。通常セルアレイ領域２０内には、複数の揮発性の電子素子としてのメモリセル２２が配置されている。メモリセル２２は、行アドレスと列アドレスで特定されるように格子状に配置されている。冗長セルアレイ領域２１内には、通常セルアレイ領域２０内の不良電子素子としての不良メモリセルを置換するための揮発性の冗長電子素子としての冗長メモリセル２３が複数配置されている。冗長メモリセル２３は、各行アドレス毎に配置され、本実施の形態においては、一列に配置されている。メモリセル２２と冗長メモリセル２３は、ワード線２４とビット線２５にそれぞれ接続されている。なお、冗長セルアレイ領域２１における冗長メモリセル２３の列数は、本実施の形態に限定されず、不良モードに合わせて決定される。すなわち、通常セルアレイ領域２０において、例えば一行アドレス中に不良メモリセルが２つ検出される不良モードの場合、冗長セルアレイ領域２１内の冗長メモリセル２３は２列に配置される。 The circuit 11 has a normal cell array region 20 as a normal element region and a redundant cell array region 21 as a redundant element region as shown in FIG. In the normal cell array region 20, a plurality of memory cells 22 as volatile electronic elements are arranged. The memory cells 22 are arranged in a lattice shape so as to be specified by a row address and a column address. A plurality of redundant memory cells 23 as volatile redundant electronic elements for replacing defective memory cells as defective electronic elements in the normal cell array area 20 are arranged in the redundant cell array region 21. Redundant memory cells 23 are arranged for each row address, and are arranged in a line in the present embodiment. Memory cell 22 and redundant memory cell 23 are connected to word line 24 and bit line 25, respectively. Note that the number of columns of redundant memory cells 23 in the redundant cell array region 21 is not limited to the present embodiment, and is determined according to the failure mode. That is, in the normal cell array region 20, for example, in the failure mode in which two defective memory cells are detected in one row address, the redundant memory cells 23 in the redundant cell array region 21 are arranged in two columns.
　ウェハ１０の表面にデバイス層１２が形成されると、図４及び図５に示すようにデバイス層１２の表面からウェハ１０の内部に延伸するように、複数の電極用貫通孔３０、複数の冗長用貫通孔３１、及びスクライブライン３２をそれぞれ形成する（図１の工程Ｓ２）。電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２は、後述する工程Ｓ５においてウェハ１０の厚み方向に貫通するように、ウェハ１０の裏面を研磨して薄化されたウェハ１０の下端位置、又はその下端位置よりも深く形成される。また、電極用貫通孔３０は、回路１１に対応する位置に形成される。冗長用貫通孔３１は、回路１１のメモリセル２２に対応する後述の入力行列アドレスバス８３の本数と、電源接続用と接地線接続用の冗長用貫通孔３１の個数（２個）と、冗長メモリセル２３の個数と、を掛け合わせた個数形成される。すなわち、冗長用貫通孔３１の個数は、（入力行列アドレスバス８３の本数）×（電源接続用と接地線接続用の２個）×（冗長メモリセル２３の個数）となる。例えばメモリセル２２が８行×８列の６４個の場合、入力行列アドレスバス８３の本数は６本となる。そして、冗長メモリセル２３が２列の１６個である場合、冗長貫通孔３１の個数は、（６本）×（２個）×（１６個）＝１９２個となる。これら複数の冗長用貫通孔３１は、後述する不良アドレス記録部３３を形成している。スクライブライン３２は、分割されるウェハ１０及びデバイス層１１が少なくとも一つの回路１１を含むように形成される。 When the device layer 12 is formed on the surface of the wafer 10, a plurality of electrode through holes 30 and a plurality of redundant holes are formed so as to extend from the surface of the device layer 12 to the inside of the wafer 10 as shown in FIGS. A through-hole 31 for use and a scribe line 32 are respectively formed (step S2 in FIG. 1). The electrode through-hole 30, the redundant through-hole 31, and the scribe line 32 are lower end positions of the wafer 10 that have been thinned by polishing the back surface of the wafer 10 so as to penetrate in the thickness direction of the wafer 10 in step S5 described later. Or deeper than its lower end position. The electrode through-hole 30 is formed at a position corresponding to the circuit 11. The redundant through holes 31 include the number of input matrix address buses 83 to be described later corresponding to the memory cells 22 of the circuit 11, the number (two) of redundant through holes 31 for power supply connection and ground line connection, and redundancy. The number is formed by multiplying the number of memory cells 23. That is, the number of the redundant through holes 31 is (number of input matrix address buses 83) × (two for power supply connection and ground line connection) × (number of redundant memory cells 23). For example, when the number of memory cells 22 is 64 (8 rows × 8 columns), the number of input matrix address buses 83 is six. When the number of redundant memory cells 23 is 16 in two rows, the number of redundant through holes 31 is (6) × (2) × (16) = 192. The plurality of redundant through holes 31 form a defective address recording portion 33 to be described later. The scribe line 32 is formed such that the wafer 10 and the device layer 11 to be divided include at least one circuit 11.
　これら電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２は、例えばフォトリソグラフィー処理及びエッチング処理によって同時に形成される。すなわち、フォトリソグラフィー処理によってデバイス層１２上に所定のレジストパターンを形成した後、当該レジストパターンをマスクとしてデバイス層１２とウェハ１０をエッチングして、電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２が形成される。なお、図４及び図５における電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２、不良位置情報記録部としての不良アドレス記録部３３の位置及び大きさは、技術の理解の容易さを優先させるため、必ずしも実際の位置及び大きさに対応していない。これらの位置及び大きさは、図示の例に限定されず任意に選択することができる。また、電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２は、工程Ｓ２の段階ではウェハ１０の厚み方向に貫通していないが、後述する工程Ｓ５においてウェハ１０を薄化することによりウェハ１０の厚み方向に貫通するように形成されるので、便宜上貫通やスクライブ等と表現している。 The electrode through hole 30, the redundant through hole 31, and the scribe line 32 are simultaneously formed by, for example, a photolithography process and an etching process. That is, after a predetermined resist pattern is formed on the device layer 12 by photolithography, the device layer 12 and the wafer 10 are etched using the resist pattern as a mask, so that the electrode through hole 30, the redundant through hole 31, the scribe line are etched. A line 32 is formed. 4 and 5, the positions and sizes of the electrode through hole 30, the redundant through hole 31, the scribe line 32, and the defective address recording unit 33 as the defective position information recording unit make it easy to understand the technology. In order to give priority, it does not necessarily correspond to the actual position and size. These positions and sizes are not limited to the illustrated example and can be arbitrarily selected. Further, the electrode through hole 30, the redundant through hole 31, and the scribe line 32 do not penetrate in the thickness direction of the wafer 10 in the step S2, but the wafer 10 is thinned in the step S5 to be described later. Since it is formed so as to penetrate in the thickness direction of 10, it is expressed as penetration or scribe for convenience.
　その後、各電極用貫通孔３０内に導電性材料を充填して、図６に示すように貫通電極３４を形成する。貫通電極３４は、回路１１と電気的に接続されるように形成される（図１の工程Ｓ３）。なお、貫通電極３４についても、工程Ｓ３の段階ではウェハ１０の厚み方向に貫通していないが、後述する工程Ｓ５においてウェハ１０を薄化することによりウェハ１０の厚み方向に貫通するように形成されるので、便宜上貫通と表現している。 Thereafter, each electrode through hole 30 is filled with a conductive material to form a through electrode 34 as shown in FIG. The through electrode 34 is formed so as to be electrically connected to the circuit 11 (step S3 in FIG. 1). The through electrode 34 does not penetrate in the thickness direction of the wafer 10 at the stage of step S3, but is formed so as to penetrate in the thickness direction of the wafer 10 by thinning the wafer 10 in step S5 described later. Therefore, it is expressed as penetration for convenience.
　その後、図７に示すようにデバイス層１２の表面に支持基板としての支持ウェハ４０を配設する（図１の工程Ｓ４）。支持ウェハ４０は、例えば接着剤によってデバイス層１２と接着される。なお、支持基板はウェハに限定されず、例えばガラス基板等を用いてもよい。 Thereafter, as shown in FIG. 7, a support wafer 40 as a support substrate is disposed on the surface of the device layer 12 (step S4 in FIG. 1). The support wafer 40 is bonded to the device layer 12 by, for example, an adhesive. The support substrate is not limited to a wafer, and for example, a glass substrate or the like may be used.
　その後、図８に示すようにウェハ１０の裏面を研磨し、ウェハ１０を薄化する（図１の工程Ｓ５）。これによって、貫通電極３４（電極用貫通孔３０）、冗長用貫通孔３１、スクライブライン３２がウェハ１０の厚み方向に貫通する。そして、スクライブライン２２によりウェハ１０とデバイス層１２が分割され、複数の半導体チップ５０が形成される。 Thereafter, as shown in FIG. 8, the back surface of the wafer 10 is polished to thin the wafer 10 (step S5 in FIG. 1). As a result, the through electrode 34 (electrode through hole 30), the redundant through hole 31, and the scribe line 32 penetrate in the thickness direction of the wafer 10. Then, the wafer 10 and the device layer 12 are divided by the scribe line 22 to form a plurality of semiconductor chips 50.
　その後、図９に示すように検査装置６０を用いて、ウェハ１０の裏面側から回路１１の電気的試験を行う（図８の工程Ｓ６）。検査装置６０は、テスタ６１と、当該テスタ６１上に支持され、導電性を有する複数のプローブ６２とを有している。プローブ６２は、貫通電極３４に対応する位置に配置されている。また、プローブ６２の先端には、導電性液６３が付着している。導電性液６３には、例えばナノオーダの径を有し、かつ導電性を有する金属粒子を拡散させた液が用いられる。 Thereafter, an electrical test of the circuit 11 is performed from the back side of the wafer 10 using the inspection device 60 as shown in FIG. 9 (step S6 in FIG. 8). The inspection device 60 includes a tester 61 and a plurality of probes 62 supported on the tester 61 and having conductivity. The probe 62 is disposed at a position corresponding to the through electrode 34. A conductive liquid 63 is attached to the tip of the probe 62. As the conductive liquid 63, for example, a liquid having a nano-order diameter and diffusing conductive metal particles is used.
　かかる検査装置６０を用いて電気的試験を行う際には、先ず、検査装置６０をウェハ１０側に上昇させて、プローブ６２を貫通電極３４に近接させる。そうすると、導電性液６３は、その表面張力によって拡がり貫通電極３４と接触する。続いて、テスタ６１からプローブ６２、導電性液６３、貫通電極３４を通じて回路１１に電気信号が送られ、回路１１の電気的試験が行われる。なお、プローブ６２の形状は、図示の例に限定されず、例えばカンチレバー形状等、種々の形状を取り得ることができる。 When performing an electrical test using such an inspection apparatus 60, first, the inspection apparatus 60 is raised to the wafer 10 side and the probe 62 is brought close to the through electrode 34. Then, the conductive liquid 63 spreads by its surface tension and comes into contact with the through electrode 34. Subsequently, an electrical signal is sent from the tester 61 to the circuit 11 through the probe 62, the conductive liquid 63, and the through electrode 34, and an electrical test of the circuit 11 is performed. The shape of the probe 62 is not limited to the illustrated example, and can take various shapes such as a cantilever shape.
　ここで、従来はデバイス側からヒューズを切断することにより不良メモリセルのアドレスが記録される。そのため、支持ウェハが接着される前のウェハ及びデバイス層が分割されていない状態で行われるプローブ試験と、半導体チップ毎に行うファイナル試験の２度の電気的試験が行われている。本実施の形態では、最初から半導体チップ５０毎に回路１１の電気的試験を行うことができるので、従来のプローブ試験を省略することができる。しかも、ウェハ１０の裏面は研磨され平坦化しているので、半導体チップ５０毎の回路１１の電気的試験を一括して容易に行うことができる。 Here, conventionally, the address of the defective memory cell is recorded by cutting the fuse from the device side. For this reason, two electrical tests are performed: a probe test performed in a state where the wafer and the device layer before the support wafer is bonded and a device layer are not divided, and a final test performed for each semiconductor chip. In the present embodiment, since the electrical test of the circuit 11 can be performed for each semiconductor chip 50 from the beginning, the conventional probe test can be omitted. Moreover, since the back surface of the wafer 10 is polished and flattened, the electrical test of the circuit 11 for each semiconductor chip 50 can be easily performed collectively.
　回路１１の電気的試験を行って、通常セルアレイ領域２０内に不良メモリセルが検出されると、当該不良メモリセルのアドレスが不良アドレス記録部３３に記録される（図１の工程Ｓ７）。不良アドレス記録部３３において、複数の冗長用貫通孔３１は、図１０～図１３に示すように電源線接続用の第１の冗長用貫通孔３１ａと接地線接続用の第２の冗長用貫通孔３１ｂとを有している。これら一対の冗長用貫通孔３１ａ、３１ｂは、それぞれ（入力行列アドレスバス８３の本数）×（冗長メモリセル２３の個数）の個数形成される。すなわち、冗長用貫通孔３１の個数は、上述したように（入力行列アドレスバス８３の本数）×（電源接続用と接地線接続用の２個）×（冗長メモリセル２３の個数）となる。また、不良アドレス記録部３３のデバイス層１２には、第１の冗長用貫通孔３１ａの両側に、出力用の位置情報線としてのアドレス線７０と電源線７１が配線されている。さらに、第２の冗長用貫通孔３１ｂの両側には、出力用の位置情報線としてのアドレス線７２と接地線７３が配線されている。 When an electrical test of the circuit 11 is performed and a defective memory cell is detected in the normal cell array region 20, the address of the defective memory cell is recorded in the defective address recording unit 33 (step S7 in FIG. 1). In the defective address recording section 33, the plurality of redundant through holes 31 are provided with a first redundant through hole 31a for power supply line connection and a second redundant through hole for ground line connection as shown in FIGS. And a hole 31b. Each of the pair of redundant through holes 31a and 31b is formed by the number of (number of input matrix address bus 83) × (number of redundant memory cells 23). That is, as described above, the number of redundant through holes 31 is (number of input matrix address bus 83) × (two for power supply connection and ground line connection) × (number of redundant memory cells 23). The device layer 12 of the defective address recording unit 33 is provided with an address line 70 and a power supply line 71 as position information lines for output on both sides of the first redundant through hole 31a. Further, an address line 72 and a ground line 73 as output position information lines are wired on both sides of the second redundant through hole 31b.
　そして、不良アドレス記録部３３において、不良メモリセルのアドレスは“１”と“０”の信号で記録される。例えば“１”の信号を記録する際には、図１０及び図１１に示すように第１の冗長用貫通孔３１ａを介してアドレス線７０と電源線７１を接続する。具体的には、第１の冗長用貫通孔３１ａの上部に導電性材料７４を充填し、且つ第１の冗長用貫通孔３１ａの下部に絶縁性材料７５を充填すると共に、第２の冗長用貫通孔３１ｂに絶縁性材料７５を充填する。また、“０”の信号を記録する際には、図１２及び図１３に示すように第２の冗長用貫通孔３１ｂを介してアドレス線７２と接地線７３を接続する。具体的には、第２の冗長用貫通孔３１ｂの上部に導電性材料７４を充填し、且つ第２の冗長用貫通孔３１ｂの下部に絶縁性材料７５を充填すると共に、第１の冗長用貫通孔３１ａに絶縁性材料７５を充填する。こうして、不良アドレス記録部３３に不良メモリセルのアドレスが記録される。なお、このように第１の冗長用貫通孔３１ａ、第２の冗長用貫通孔３１ｂの下部には絶縁性材料７５が充填されているので、後述する工程Ｓ９で半導体チップ５０が積層され接合されても、積層された半導体チップ５０間において、第１の冗長用貫通孔３１ａや第２の冗長用貫通孔３１ｂを介してアドレス線７０、電源線７１、アドレス線７２、接地線７３がそれぞれ導通することはない。また、冗長用貫通孔３１への導電性材料７４、絶縁性材料７５の充填は、例えばインクジェット方式で行ってもよい。あるいは、冗長用貫通孔３１の形成パターンに対応して複数のノズルを配置し、各ノズルから対応する冗長用貫通孔３１に導電性材料７４又は絶縁性材料７５を供給してもよい。 In the defective address recording unit 33, the address of the defective memory cell is recorded by signals “1” and “0”. For example, when the signal “1” is recorded, the address line 70 and the power supply line 71 are connected through the first redundant through hole 31a as shown in FIGS. Specifically, the upper portion of the first redundant through hole 31a is filled with the conductive material 74, and the lower portion of the first redundant through hole 31a is filled with the insulating material 75, and the second redundant through hole 31a is filled. The through hole 31b is filled with an insulating material 75. When recording a signal of “0”, the address line 72 and the ground line 73 are connected via the second redundant through hole 31b as shown in FIGS. Specifically, the upper portion of the second redundant through hole 31b is filled with the conductive material 74, and the lower portion of the second redundant through hole 31b is filled with the insulating material 75, and the first redundant through hole 31b is filled. An insulating material 75 is filled in the through hole 31a. Thus, the address of the defective memory cell is recorded in the defective address recording unit 33. Since the insulating material 75 is filled in the lower portions of the first redundant through hole 31a and the second redundant through hole 31b in this way, the semiconductor chip 50 is laminated and bonded in step S9 described later. However, between the stacked semiconductor chips 50, the address line 70, the power supply line 71, the address line 72, and the ground line 73 are electrically connected through the first redundant through hole 31a and the second redundant through hole 31b, respectively. Never do. Further, the filling of the conductive material 74 and the insulating material 75 into the redundant through hole 31 may be performed by, for example, an ink jet method. Alternatively, a plurality of nozzles may be arranged corresponding to the formation pattern of the redundant through holes 31, and the conductive material 74 or the insulating material 75 may be supplied from each nozzle to the corresponding redundant through hole 31.
　不良アドレス記録部３３に不良メモリセルのアドレスが記録されると、この不良メモリセルのアドレスに基づいて、不良メモリセルが冗長セルアレイ領域２１内の冗長メモリセル２３に置換される（図１の工程Ｓ８）。 When the address of the defective memory cell is recorded in the defective address recording unit 33, the defective memory cell is replaced with the redundant memory cell 23 in the redundant cell array region 21 based on the address of the defective memory cell (step of FIG. 1). S8).
　具体的には、図３に示すようにアドレスバッファ８０において、外部から入力されるアドレスがラッチされる。この入力されたアドレスのうち、行アドレスは行アドレスデコーダ８１に出力される。行アドレスデコーダ８１では、行アドレスをデコードしてワード線２４が選択される。 Specifically, as shown in FIG. 3, an address input from the outside is latched in the address buffer 80. Of the input addresses, the row address is output to the row address decoder 81. In the row address decoder 81, the word line 24 is selected by decoding the row address.
　アドレスバッファ８０に入力されたアドレスのうち、列アドレスはコンパレータ８２に出力される。また、コンパレータ８２には、不良アドレス記録部３３で記録された不良メモリセルの行アドレスと列アドレスが入力される。コンパレータ８２では、外部からの入力行列アドレスと不良メモリセルの行列アドレスの比較が行われる。コンパレータ８２は、図１４に示すようにアドレスバッファ８０からの入力行列アドレスＡを伝送するための入力行列アドレスバス８３と、不良メモリセルの行列アドレスＢを伝送するための不良行列アドレスバス８４とを有している。そして、入力行列アドレスＡと不良メモリセルの行列アドレスＢとを比較し、一致している場合には信号Ｙとして“１”を出力し、一致していない場合には信号Ｙとして“０”を出力する。すなわち、行アドレスと列アドレスそれぞれの一致不一致を考慮して、信号Ｙとして“１”又は“０”を出力する。例えば信号Ｙが“１”であって、且つ行列アドレスＡ、Ｂが“１”の場合には、対応する行列アドレスのメモリセル２２が不良メモリセルと判定され、冗長メモリセル２３に置換されるようにする。一方、例えば信号Ｙが“１”であって、且つ行列アドレスＡ、Ｂが“０”の場合には、対応する行列アドレスのメモリセル２２が不良でないと判断され、当該メモリセル２２がそのまま用いられるようにする。このコンパレータ８２での比較結果は、図３に示すように列アドレスデコーダ８５に出力される。列アドレスレコーダ８５では、上述した行アドレスデコーダ８１で選択されたワード線２４毎に、コンパレータ８２での比較結果をデコードしてビット線２５が選択される。 Of the addresses input to the address buffer 80, the column address is output to the comparator 82. Further, the row address and column address of the defective memory cell recorded by the defective address recording unit 33 are input to the comparator 82. The comparator 82 compares the input matrix address from the outside with the matrix address of the defective memory cell. As shown in FIG. 14, the comparator 82 includes an input matrix address bus 83 for transmitting the input matrix address A from the address buffer 80 and a defective matrix address bus 84 for transmitting the matrix address B of the defective memory cell. Have. Then, the input matrix address A and the matrix address B of the defective memory cell are compared, and if they match, “1” is output as the signal Y, and if they do not match, “0” is output as the signal Y. Output. In other words, “1” or “0” is output as the signal Y in consideration of the match / mismatch between the row address and the column address. For example, when the signal Y is “1” and the matrix addresses A and B are “1”, the memory cell 22 of the corresponding matrix address is determined as a defective memory cell and is replaced with the redundant memory cell 23. Like that. On the other hand, for example, when the signal Y is “1” and the matrix addresses A and B are “0”, it is determined that the memory cell 22 of the corresponding matrix address is not defective, and the memory cell 22 is used as it is. To be able to. The comparison result in the comparator 82 is output to the column address decoder 85 as shown in FIG. In the column address recorder 85, the bit line 25 is selected by decoding the comparison result of the comparator 82 for each word line 24 selected by the row address decoder 81 described above.
　なお、本実施の形態では、１つのコンパレータ８２に複数の不良メモリセルの行列アドレスＢが入力されていたが、不良メモリセル毎にコンパレータを設けてもよい。かかる場合、コンパレータでは、アドレスバッファ８０からの入力行列アドレスＡと１つの不良メモリセルの行列アドレスＢとの比較が行われる。この比較結果は回路に出力され、当該回路において、どのコンパレータで行列アドレスＡ、Ｂが一致しているかが判断される。そして、一致している場合には信号Ｙとして“１”を出力し、一致していない場合には信号Ｙとして“０”を出力する。その後の不良メモリセルの冗長メモリセル２３への置換は、上述したとおりであるので説明を省略する。 In this embodiment, the matrix address B of a plurality of defective memory cells is input to one comparator 82, but a comparator may be provided for each defective memory cell. In such a case, the comparator compares the input matrix address A from the address buffer 80 with the matrix address B of one defective memory cell. The comparison result is output to the circuit, and in the circuit, it is determined which comparator matches the matrix addresses A and B. If they match, “1” is output as the signal Y, and if they do not match, “0” is output as the signal Y. Subsequent replacement of the defective memory cell with the redundant memory cell 23 is as described above, and thus the description thereof is omitted.
　通常セルアレイ領域２０及び冗長セルアレイ領域２１には、読み出し／書き出し回路８６が接続されている。この読み出し／書き出し回路８６により、データ入出力バッファ８７と通常セルアレイ領域２０及び冗長セルアレイ領域２１との間のデータのやり取りが可能となっている。 A read / write circuit 86 is connected to the normal cell array region 20 and the redundant cell array region 21. By this read / write circuit 86, data can be exchanged between the data input / output buffer 87 and the normal cell array region 20 and the redundant cell array region 21.
　なお、このように不良メモリセルが冗長メモリセル２３に置換された後、再度、工程Ｓ６と同様に回路１１の電気的試験を行ってもよい。 Note that after the defective memory cell is replaced with the redundant memory cell 23 in this manner, the electrical test of the circuit 11 may be performed again in the same manner as in step S6.
　回路１１において不良メモリセルが冗長メモリセル２３に置換されると、上述した工程Ｓ１～Ｓ８の処理を別途行い、不良メモリセルを冗長置換後の良品の半導体チップ５０を形成する。その後、図１５に示すよう一の支持ウェハ４０に支持された半導体チップ５０と他の支持ウェハ４０に支持された半導体チップ５０とを鉛直方向に積層し接合する（図１の工程Ｓ９）。このとき、半導体チップ５０同士は、貫通電極３４が導通するように接合される。 When the defective memory cell is replaced with the redundant memory cell 23 in the circuit 11, the above-described processes of steps S1 to S8 are separately performed, and the non-defective semiconductor chip 50 after the redundant replacement of the defective memory cell is formed. Thereafter, as shown in FIG. 15, the semiconductor chip 50 supported by one support wafer 40 and the semiconductor chip 50 supported by another support wafer 40 are stacked and joined in the vertical direction (step S9 in FIG. 1). At this time, the semiconductor chips 50 are joined so that the through electrodes 34 are conductive.
　その後、図１６に示すように、例えば上側の支持ウェハ４０が除去される（図１の工程Ｓ１０）。この上側の支持ウェハ４０の除去は、例えば支持ウェハ４０と半導体チップ５０とを加熱して接着剤の粘着性を弱めることによって行われる。 Thereafter, as shown in FIG. 16, for example, the upper support wafer 40 is removed (step S10 in FIG. 1). The removal of the upper support wafer 40 is performed, for example, by heating the support wafer 40 and the semiconductor chip 50 to weaken the adhesiveness of the adhesive.
　上述した工程Ｓ１～Ｓ１０を繰り返し行い、図１７に示すように複数の半導体チップ５０が鉛直方向に積層され、半導体装置１００が製造される。 The above-described steps S1 to S10 are repeated, and a plurality of semiconductor chips 50 are stacked in the vertical direction as shown in FIG. 17, and the semiconductor device 100 is manufactured.
　以上の実施の形態によれば、工程Ｓ７において、第１の冗長用貫通孔３１ａを介してアドレス線７０と電源線７１を接続するか、あるいは第２の冗長用貫通孔３１ｂを介してアドレス線７２と接地線７３を接続することで、不良アドレス記録部３３に不良メモリセルのアドレスを記録することができる。したがって、３次元集積技術において、ウェハ１０上のデバイス層１２の表面に支持ウェハ４０を配設し、半導体チップ５０を積層して半導体装置１００を製造する場合であっても、ウェハ１０の裏面側から不良アドレス記録部３３に不良メモリセルのアドレスを記録することができる。そして、工程Ｓ８において、不良アドレス記録部３３に記録された不良メモリセルのアドレスに基づいて、当該不良メモリセルを冗長メモリセル２３に置換して救済するので、半導体装置１００の歩留まりを向上させることができる。 According to the above embodiment, in step S7, the address line 70 and the power supply line 71 are connected via the first redundant through hole 31a, or the address line is connected via the second redundant through hole 31b. By connecting 72 and the ground line 73, the address of the defective memory cell can be recorded in the defective address recording unit 33. Therefore, in the three-dimensional integration technique, even when the support wafer 40 is disposed on the surface of the device layer 12 on the wafer 10 and the semiconductor device 100 is manufactured by stacking the semiconductor chips 50, the back surface side of the wafer 10. Thus, the address of the defective memory cell can be recorded in the defective address recording unit 33. In step S8, based on the address of the defective memory cell recorded in the defective address recording unit 33, the defective memory cell is replaced by the redundant memory cell 23 and repaired. Therefore, the yield of the semiconductor device 100 is improved. Can do.
　また、メモリセル２２と冗長メモリセル２３が揮発性を有している場合でも、不良アドレス記録部３３に不良メモリセルのアドレスを記録することができるので、例えばＤＲＡＭ等の揮発性の半導体チップ５０に、機能上、不揮発性の不良アドレス記録部３３を形成することができる。 In addition, even when the memory cell 22 and the redundant memory cell 23 are volatile, the address of the defective memory cell can be recorded in the defective address recording unit 33. Therefore, for example, a volatile semiconductor chip 50 such as a DRAM. In addition, the non-volatile defective address recording unit 33 can be formed functionally.
　しかも、かかる不良アドレス記録部３３は、簡易な方法で形成することができる。すなわち、工程Ｓ２において、不良アドレス記録部３３の冗長用貫通孔３１は、電極用貫通孔３０と共に形成される。このため、冗長用貫通孔３１を形成する工程を別途行う必要がない。また、工程Ｓ７において、例えばインクジェット方式で冗長用貫通孔３１に導電性材料７４や絶縁性材料７５を充填することにより、第１の冗長用貫通孔３１ａを介してアドレス線７０と電源線７１を接続するか、あるいは第２の冗長用貫通孔３１ｂを介してアドレス線７２と接地線７３を接続して、不良アドレス記録部３３を形成することができる。このように不揮発性の不良アドレス記録部３３を簡易な方法で形成できるので、半導体装置１００を効率よく製造することができる。 Moreover, the defective address recording unit 33 can be formed by a simple method. That is, in step S <b> 2, the redundant through hole 31 of the defective address recording unit 33 is formed together with the electrode through hole 30. For this reason, it is not necessary to perform the process of forming the redundant through-hole 31 separately. In step S7, the address line 70 and the power supply line 71 are connected via the first redundant through hole 31a by filling the redundant through hole 31 with the conductive material 74 or the insulating material 75 by, for example, an inkjet method. The defective address recording section 33 can be formed by connecting the address line 72 and the ground line 73 through the second redundant through hole 31b. Thus, since the non-volatile defective address recording part 33 can be formed by a simple method, the semiconductor device 100 can be manufactured efficiently.
　また、不良アドレス記録部３３に不良メモリセルのアドレスが記録されるので、冗長セルアレイ領域２１には不良モードに合わせた列数の冗長メモリセル２３を配置するだけでよい。したがって、冗長セルアレイ領域２１を小さくすることができる。また、工程Ｓ８において、行アドレス毎に不良メモリセルを冗長メモリセル２３に１対１で置換できるので、効率よく不良メモリセルを救済することができる。 Further, since the address of the defective memory cell is recorded in the defective address recording unit 33, it is only necessary to arrange the redundant memory cells 23 having the number of columns corresponding to the defective mode in the redundant cell array region 21. Therefore, the redundant cell array region 21 can be reduced. In step S8, the defective memory cells can be replaced with the redundant memory cells 23 on a one-to-one basis for each row address, so that the defective memory cells can be efficiently relieved.
　また、工程Ｓ２において、スクライブライン３２は電極用貫通孔３０と冗長用貫通孔３１と共に形成されるので、スクライブライン３２を形成する工程、すなわちウェハ１０及びデバイス層１２を分割して半導体チップ５０を形成する工程を別途行う必要がない。したがって、半導体装置１００をさらに効率よく製造することができる。 In step S2, the scribe line 32 is formed together with the electrode through hole 30 and the redundant through hole 31, so that the step of forming the scribe line 32, that is, the wafer 10 and the device layer 12 are divided to form the semiconductor chip 50. There is no need to perform the process of forming separately. Therefore, the semiconductor device 100 can be manufactured more efficiently.
　また、工程Ｓ６において、複数の半導体チップ５０が支持ウェハ４０に支持された状態で、当該半導体チップ５０毎に回路１０の電気的試験が行われる。すなわち、従来のプローブ試験を行うことなく、最初から半導体チップ５０毎のファイナル試験を行うことができる。したがって、半導体装置１００をさらに効率よく製造することができる。 In step S6, the electrical test of the circuit 10 is performed for each semiconductor chip 50 in a state where the plurality of semiconductor chips 50 are supported by the support wafer 40. That is, a final test for each semiconductor chip 50 can be performed from the beginning without performing a conventional probe test. Therefore, the semiconductor device 100 can be manufactured more efficiently.
　また、工程Ｓ６において、回路１１の電気的試験は、導電性液６３と貫通電極３４を導通させることによって行われる。導電性液６３はその表面張力によって拡がって貫通電極３４に接触するため、貫通電極３４に対してプローブ６２が厳密な位置精度で配置されていなくても回路１１の電気的試験を行うことできる。しかも、プローブを貫通電極に直接接触させて試験を行う場合には接触荷重が大きくなるが、本実施の形態では、導電性液６３が貫通電極３４に接触するため、接触荷重を小さくすることができる。したがって、回路１１の電気的試験を効率よく行うことができる。 In step S6, the electrical test of the circuit 11 is performed by causing the conductive liquid 63 and the through electrode 34 to conduct. Since the conductive liquid 63 spreads by the surface tension and contacts the penetrating electrode 34, the electrical test of the circuit 11 can be performed even if the probe 62 is not arranged with strict positional accuracy with respect to the penetrating electrode 34. Moreover, when the test is performed with the probe in direct contact with the through electrode, the contact load increases. However, in this embodiment, since the conductive liquid 63 contacts the through electrode 34, the contact load can be reduced. it can. Therefore, the electrical test of the circuit 11 can be performed efficiently.
　以上の実施の形態では、工程Ｓ８において不良メモリセルを冗長メモリセル２３に置換した後、工程Ｓ９において半導体チップ５０を積層していたが、半導体チップ５０を積層した後、不良メモリセルを冗長メモリセル２３に置換してもよい。かかる場合、例えば図１６に示したように上側の支持ウェハ４０を除去した状態で、上側の半導体チップ５０における不良メモリセルの救済が行われる。本実施の形態においても、良品の半導体チップ５０を積層することができるので、半導体装置１００の歩留まりを向上させることができる。 In the above embodiment, after replacing the defective memory cell with the redundant memory cell 23 in step S8, the semiconductor chip 50 is stacked in step S9. However, after stacking the semiconductor chip 50, the defective memory cell is replaced with the redundant memory cell. The cell 23 may be replaced. In such a case, for example, as shown in FIG. 16, the defective memory cell in the upper semiconductor chip 50 is relieved in a state where the upper support wafer 40 is removed. Also in the present embodiment, since good semiconductor chips 50 can be stacked, the yield of the semiconductor device 100 can be improved.
　また、以上の実施の形態では、工程Ｓ２で電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２を形成し、工程Ｓ３で貫通電極３４を形成した後、工程Ｓ４でデバイス層１２の表面に支持ウェハ４０を配設していたが、デバイス層１２の表面に支持ウェハ４０を配設した後、電極用貫通孔３０、冗長用貫通孔３１、スクライブライン３２、及び貫通電極３４を形成してもよい。なお、その他の工程Ｓ１及び工程Ｓ５～工程Ｓ１０の工程は、上記実施の形態と同様であるので説明を省略する。 In the above embodiment, the electrode through hole 30, the redundant through hole 31, and the scribe line 32 are formed in step S2, the through electrode 34 is formed in step S3, and then the surface of the device layer 12 in step S4. However, after the support wafer 40 is disposed on the surface of the device layer 12, the electrode through hole 30, the redundant through hole 31, the scribe line 32, and the through electrode 34 are formed. May be. The other steps S1 and the steps S5 to S10 are the same as those in the above embodiment, and the description thereof is omitted.
　また、以上の実施の形態では、不良アドレス記録部３３には電源線接続用の第１の冗長用貫通孔３１ａと接地線接続用の第２の冗長用貫通孔３１ｂとが別々に設けられていたが、図１８及び図１９に示すように電源線接続用と接地線接続用を兼ねる冗長用貫通孔１１０を設けてもよい。かかる場合、冗長用貫通孔１１０の両側にアドレス線７０と電源線７１が配線される。また、冗長用貫通孔１１０の両側であって、アドレス線７０と電源線７１の上方には、アドレス線７２と接地線７３が配線される。そして、例えば不良メモリセルのアドレスとして“１”の信号を記録する際には、図１８に示すように冗長用貫通孔１１０を介してアドレス線７０と電源線７１を接続する。具体的には、冗長用貫通孔１１０の電源線７１に対応する部分に導電性材料７４を充填すると共に、冗長用貫通孔１１０の接地線７３に対応する部分及び電源線７１に対応する部分より下部に絶縁性材料７５を充填する。また、例えば不良メモリセルのアドレスとして“０”の信号を記録する際には、図１９に示すように冗長用貫通孔１１０を介してアドレス線７２と接地線７３を接続する。具体的には、冗長用貫通孔１１０の接地線７３に対応する部分に導電性材料７４を充填すると共に、冗長用貫通孔１１０の電源線７１に対応する部分及びその下部に絶縁性材料７５を充填する。かかる場合、冗長用貫通孔１１０の個数は上記実施の形態の冗長用貫通孔３１の個数の半分となり、当該冗長貫通孔１１０を用いて不良メモリセルのアドレスを記録することができる。なお、本実施の形態では、アドレス線７０と電源線７１の上方にアドレス線７２と接地線７３を設けていたが、アドレス線７２と接地線７３の上方にアドレス線７０と電源線７１を設けてもよい。 In the above embodiment, the defective address recording unit 33 is provided with the first redundant through hole 31a for connecting the power supply line and the second redundant through hole 31b for connecting the ground line separately. However, as shown in FIGS. 18 and 19, a redundant through-hole 110 that serves both as a power supply line connection and a ground line connection may be provided. In such a case, the address line 70 and the power supply line 71 are wired on both sides of the redundant through hole 110. An address line 72 and a ground line 73 are wired on both sides of the redundant through hole 110 and above the address line 70 and the power supply line 71. For example, when a signal “1” is recorded as the address of the defective memory cell, the address line 70 and the power supply line 71 are connected via the redundant through hole 110 as shown in FIG. Specifically, the portion corresponding to the power supply line 71 of the redundant through hole 110 is filled with the conductive material 74, and the portion corresponding to the ground line 73 and the portion corresponding to the power supply line 71 of the redundant through hole 110 are used. An insulating material 75 is filled in the lower part. Further, for example, when a signal “0” is recorded as the address of the defective memory cell, the address line 72 and the ground line 73 are connected through the redundant through hole 110 as shown in FIG. Specifically, the conductive material 74 is filled in the portion corresponding to the ground line 73 of the redundant through hole 110, and the insulating material 75 is formed in the portion corresponding to the power line 71 of the redundant through hole 110 and the lower portion thereof. Fill. In this case, the number of redundant through holes 110 is half the number of redundant through holes 31 of the above embodiment, and the addresses of defective memory cells can be recorded using the redundant through holes 110. In this embodiment, the address line 72 and the ground line 73 are provided above the address line 70 and the power line 71. However, the address line 70 and the power line 71 are provided above the address line 72 and the ground line 73. May be.
　以上の実施の形態では、工程Ｓ２においてスクライブライン３２を形成してウェハ１０及びデバイス層１２を分割した後、工程Ｓ９において半導体チップ５０を積層して接合していたが、ウェハ１０及びデバイス層１２を積層して接合した後、当該ウェハ１０及びデバイス層１２を分割してもよい。 In the above embodiment, the scribe line 32 is formed in step S2 to divide the wafer 10 and the device layer 12, and then the semiconductor chip 50 is laminated and bonded in step S9. After laminating and bonding, the wafer 10 and the device layer 12 may be divided.
　かかる場合、工程Ｓ１においてウェハ１０上にデバイス層１２を形成した後、工程Ｓ２において、図２０に示すように複数の電極用貫通孔３０と複数の冗長用貫通孔３１（図示せず）を形成する。このとき、上記実施の形態のようにスクライブライン３２を形成しない。その後、工程Ｓ３において図２１に示すように各電極用貫通孔３０内に導電性材料を充填して貫通電極３４を形成し、工程Ｓ４においてデバイス層１２の表面に支持ウェハ４０を配設する。その後、工程Ｓ５において図２２に示すようにウェハ１０の裏面を研磨してウェハ１０を薄化した後、工程Ｓ６においてウェハ１０の裏面側から検査装置６０を用いて回路１１の電気的試験を行う。その後、工程Ｓ７において不良メモリセルのアドレスを不良アドレス記録部３３に記録し、工程Ｓ８において不良メモリセルを冗長メモリセル２３に置換して救済する。その後、工程Ｓ９において、図２３に示すように不良メモリセルが救済されたウェハ１０（及びデバイス層１２）を鉛直方向に積層し接合する。そして、工程Ｓ１０において支持ウェハ４０を除去する。これら工程Ｓ１～Ｓ１０を繰り返し行い、図２４に示すように複数のウェハ１０及びデバイス層１２が鉛直方向に積層される。その後、積層されたウェハ１０及びデバイス層１２を半導体チップ５０毎に分割し、図１７に示したように半導体装置１００が製造される。 In this case, after forming the device layer 12 on the wafer 10 in step S1, a plurality of electrode through holes 30 and a plurality of redundant through holes 31 (not shown) are formed in step S2 as shown in FIG. To do. At this time, the scribe line 32 is not formed as in the above embodiment. Thereafter, in step S3, as shown in FIG. 21, each electrode through hole 30 is filled with a conductive material to form a through electrode 34. In step S4, the support wafer 40 is disposed on the surface of the device layer 12. Then, after the back surface of the wafer 10 is polished and thinned in step S5 as shown in FIG. 22, the circuit 11 is electrically tested using the inspection device 60 from the back surface side of the wafer 10 in step S6. . Thereafter, in step S7, the address of the defective memory cell is recorded in the defective address recording unit 33, and in step S8, the defective memory cell is replaced with the redundant memory cell 23 and repaired. Thereafter, in step S9, as shown in FIG. 23, the wafer 10 (and the device layer 12) from which the defective memory cell is relieved is stacked and bonded in the vertical direction. In step S10, the support wafer 40 is removed. By repeating these steps S1 to S10, a plurality of wafers 10 and device layers 12 are laminated in the vertical direction as shown in FIG. Thereafter, the laminated wafer 10 and device layer 12 are divided for each semiconductor chip 50, and the semiconductor device 100 is manufactured as shown in FIG.
　ここで、上述したように従来において単にウェハを積層した場合、不良メモリセルを冗長メモリセルで救済することが困難である。そして、積層されたウェハを半導体チップ毎に分割する場合、一の半導体チップにおいて救済できなかった不良メモリセルが残存するため、積層された半導体チップ自体が不良品となる。この点、本実施の形態によれば、工程Ｓ９において不良メモリセルが適切に救済されるので、ウェハ１０及びデバイス層１２を積層した後に分割する場合でも、半導体装置１００の歩留まりを向上させることができる。換言すれば、本発明の方法は、本実施の形態のようにウェハ１０及びデバイス層１２を積層した後に分割する場合に特に有用である。 Here, as described above, when the wafers are simply stacked in the conventional manner, it is difficult to relieve the defective memory cell with the redundant memory cell. When the laminated wafer is divided for each semiconductor chip, defective memory cells that cannot be relieved in one semiconductor chip remain, so that the laminated semiconductor chip itself becomes a defective product. In this regard, according to the present embodiment, since defective memory cells are appropriately relieved in step S9, the yield of the semiconductor device 100 can be improved even when the wafer 10 and the device layer 12 are divided after being stacked. it can. In other words, the method of the present invention is particularly useful when the wafer 10 and the device layer 12 are stacked and then divided as in the present embodiment.
　なお、以上の実施の形態では、工程Ｓ８において不良メモリセルを冗長メモリセル２３に置換した後、工程Ｓ９においてウェハ１０及びデバイス層１２を積層していたが、ウェハ１０及びデバイス層１２を積層した後、不良メモリセルを冗長メモリセル２３に置換してもよい。かかる場合においても、良品のメモリセル２２を有するウェハ１０（及びデバイス層１２）を積層することができるので、半導体装置１００の歩留まりを向上させることができる。 In the above embodiment, after replacing the defective memory cell with the redundant memory cell 23 in step S8, the wafer 10 and the device layer 12 are stacked in step S9. However, the wafer 10 and the device layer 12 are stacked. Thereafter, the defective memory cell may be replaced with the redundant memory cell 23. Even in such a case, since the wafer 10 (and the device layer 12) having the non-defective memory cells 22 can be stacked, the yield of the semiconductor device 100 can be improved.
　以上の実施の形態の冗長セルアレイ領域２１は、複数のブロックに共有されて配置されていてもよい。例えば図２５に示すように半導体チップ５０（回路１１）には、例えば複数のブロックＡ１、Ａ２が設けられている。各ブロックＡ１、Ａ２は、それぞれ通常セルアレイ領域２０を有している。また、ブロックＡ１、Ａ２には、ワード線２４を共通とする冗長セルアレイ領域２１が設けられている。なお、その他の不良アドレス記録部３３、アドレスバッファ８０、行アドレスデコーダ８１、コンパレータ８２、列アドレスレコーダ８５、読み出し／書き出し回路８６、入出力バッファ８７などの構成は、上記実施の形態と同様であるため、説明を省略する。このように冗長セルアレイ領域２１が複数のブロックＡ１、Ａ２に共有されていても、各ブロックＡ１、Ａ２の不良メモリセル２２ａ、２２ｂをそれぞれ冗長メモリセル２３ａ、２３ｂに置換して救済できるので、半導体装置１００の歩留まりを向上させることができる。 The redundant cell array region 21 of the above embodiment may be shared by a plurality of blocks. For example, as shown in FIG. 25, the semiconductor chip 50 (circuit 11) is provided with, for example, a plurality of blocks A1 and A2. Each of the blocks A1 and A2 has a normal cell array region 20. In addition, the redundant cell array region 21 that shares the word line 24 is provided in the blocks A1 and A2. The configuration of other defective address recording unit 33, address buffer 80, row address decoder 81, comparator 82, column address recorder 85, read / write circuit 86, input / output buffer 87, and the like is the same as that of the above embodiment. Therefore, the description is omitted. Thus, even if the redundant cell array region 21 is shared by the plurality of blocks A1 and A2, the defective memory cells 22a and 22b of the blocks A1 and A2 can be repaired by replacing them with the redundant memory cells 23a and 23b, respectively. The yield of the apparatus 100 can be improved.
　なお、図２５の例においては、冗長セルアレイ領域２１における冗長メモリセル２３の列数は１列であったが、当該列数は本実施の形態に限定されず、２列以上の複数列であってもよい。冗長メモリセル２３が複数列設けられている場合、同一のワード線２４において複数の不良メモリセルが発生しても、これらの不良メモリセルを冗長メモリセル２３に置換して救済できる可能性が向上する。 In the example of FIG. 25, the number of redundant memory cells 23 in the redundant cell array region 21 is one column. However, the number of columns is not limited to this embodiment, and the number of columns is two or more columns. May be. In the case where a plurality of redundant memory cells 23 are provided, even if a plurality of defective memory cells occur on the same word line 24, the possibility that these defective memory cells can be replaced with the redundant memory cells 23 and repaired is improved. To do.
　以上の実施の形態の工程Ｓ８において、複数の不良メモリセルを冗長メモリセル２３に置換する場合、当該置換される複数の冗長メモリセル２３は冗長セルアレイ領域２１内で連続するように再配置されてもよい。例えば図２６に示すように半導体チップ５０（回路１１）には、複数、例えば４つのブロックＢ１、Ｂ２、Ｂ３、Ｂ４が設けられている。各ブロックＢ１～Ｂ４は、それぞれ通常セルアレイ領域２０と冗長セルアレイ領域２１を有している。また、各ブロックＢ１～Ｂ４には、行アドレスデコーダ８１、列アドレスレコーダ８５、読み出し／書き出し回路８６、入出力バッファ８７が設けられている。 In the step S8 of the above embodiment, when a plurality of defective memory cells are replaced with the redundant memory cells 23, the plurality of redundant memory cells 23 to be replaced are rearranged so as to be continuous in the redundant cell array region 21. Also good. For example, as shown in FIG. 26, the semiconductor chip 50 (circuit 11) is provided with a plurality of, for example, four blocks B1, B2, B3, and B4. Each of the blocks B1 to B4 has a normal cell array region 20 and a redundant cell array region 21, respectively. Each block B1 to B4 is provided with a row address decoder 81, a column address recorder 85, a read / write circuit 86, and an input / output buffer 87.
　次に、かかる半導体チップ５０において、不良メモリセルを冗長メモリセル２３に置換する工程Ｓ８について説明する。工程Ｓ７において不良アドレスメモリ記録部３３に記録された不良メモリセルのアドレス（アドレスマップデータ）は、不良アドレスバッファ１２０に出力される。不良アドレスバッファ１２０では、不良メモリセルのアドレスがラッチされ、コンパレータ８２に出力される。また、不良メモリセルのアドレスは、不良アドレスバッファ１２０からアドレス変換回路１２１にも出力される。 Next, step S8 of replacing the defective memory cell with the redundant memory cell 23 in the semiconductor chip 50 will be described. The address (address map data) of the defective memory cell recorded in the defective address memory recording unit 33 in step S7 is output to the defective address buffer 120. In the defective address buffer 120, the address of the defective memory cell is latched and output to the comparator 82. The address of the defective memory cell is also output from the defective address buffer 120 to the address conversion circuit 121.
　一方、アドレスバッファ８０では、外部から入力されるアドレスがラッチされ、コンパレータ８２に出力される。そして、コンパレータ８２では、外部からの入力行列アドレスと不良メモリセルの行列アドレスの比較が行われる。具体的には、入力行列アドレスと不良メモリセルの行列アドレスの一致不一致が判定され、メモリセル２２が不良メモリセルであるか否かが判定される。なお、コンパレータ８２におけるアドレスの比較は、上記実施の形態と同様であるので説明を省略する。 On the other hand, in the address buffer 80, an address input from the outside is latched and output to the comparator 82. The comparator 82 compares the input matrix address from the outside with the matrix address of the defective memory cell. Specifically, it is determined whether or not the input matrix address matches the matrix address of the defective memory cell, and it is determined whether or not the memory cell 22 is a defective memory cell. Note that the comparison of addresses in the comparator 82 is the same as that in the above embodiment, so that the description thereof is omitted.
　アドレスが不一致の場合、メモリセル２２が不良でないと判定され、当該メモリセル２２がそのまま用いられるようにする。かかる場合、図２５の実線矢印で示すように、コンパレータ８２から各ブロックＢ１～Ｂ４の行アドレスデコーダ８１と列アドレスレコーダ８５にアドレス不一致の信号が出力される。 If the addresses do not match, it is determined that the memory cell 22 is not defective, and the memory cell 22 is used as it is. In such a case, as indicated by a solid line arrow in FIG. 25, an address mismatch signal is output from the comparator 82 to the row address decoder 81 and the column address recorder 85 of each of the blocks B1 to B4.
　一方、アドレスが一致している場合、メモリセル２２が不良と判定され、当該不良メモリセルが冗長メモリセル２３に置換される。かかる場合、図２５の点線矢印で示すように、コンパレータ８２からアドレス変換回路１２１にアドレス一致の信号が出力される。 On the other hand, if the addresses match, the memory cell 22 is determined to be defective, and the defective memory cell is replaced with the redundant memory cell 23. In such a case, an address match signal is output from the comparator 82 to the address conversion circuit 121 as indicated by a dotted arrow in FIG.
　そして、アドレス変換回路１２１では、不良アドレスバッファ１２０から入力された不良メモリセルのアドレスが、当該不良メモリセルが置換される冗長メモリセル２３にアクセスするためのアドレス（以下、「冗長メモリアクセス用アドレス」）に変換される。ここで、アドレス変換回路１２１では、例えば不良メモリセルのアドレスの下位から上位の順に冗長メモリアクセス用アドレスが一対一で対応している。また、冗長メモリアドレスアクセス用アドレスは下位から順番に対応付けされている。そして、図２５の点線矢印で示すように、アドレス変換回路１２１で変換された冗長メモリアクセス用アドレスが、当該アドレス変換回路１２１から各ブロックＢ１～Ｂ４の行アドレスデコーダ８１と列アドレスレコーダ８５に出力される。このとき、例えばアドレス変換回路１２１として、所定の不良メモリセルのアドレスが入力された際、そのアドレスでのみ“１”を発生させる回路を作成しておく。この“１”の信号で冗長メモリアクセス用アドレスを出力する。かかる場合、それ以外の場合は“０”なので、冗長メモリアクセス用アドレスは出力されない。したがって、不良メモリセルに一対一に対応する冗長メモリアクセス用アドレスが出力される。そして、この冗長メモリアクセス用アドレスに基づいて冗長メモリセル２３にアクセスし、不良メモリセルが当該冗長メモリセル２３に置換されて救済される。 In the address conversion circuit 121, the address of the defective memory cell input from the defective address buffer 120 is used to access the redundant memory cell 23 to which the defective memory cell is replaced (hereinafter referred to as “redundant memory access address”). )). Here, in the address conversion circuit 121, for example, the redundant memory access addresses correspond one-to-one in order from the lower to the higher address of the defective memory cell. Redundant memory address access addresses are associated in order from the bottom. 25, the redundant memory access address converted by the address conversion circuit 121 is output from the address conversion circuit 121 to the row address decoder 81 and the column address recorder 85 of each of the blocks B1 to B4. Is done. At this time, for example, as the address conversion circuit 121, when an address of a predetermined defective memory cell is input, a circuit that generates “1” only at the address is created. The redundant memory access address is output by this "1" signal. In such a case, the address for redundant memory access is not output because it is “0” in other cases. Therefore, a redundant memory access address corresponding to the defective memory cell on a one-to-one basis is output. Then, the redundant memory cell 23 is accessed based on the redundant memory access address, and the defective memory cell is replaced with the redundant memory cell 23 to be relieved.
　ここで、上記実施の形態の方法と同様の方法を用いた場合、例えばブロックＢ１の不良メモリセル２２ａ、ブロックＢ２の不良メモリセル２２ｂ、ブロックＢ３の不良メモリセル２２ｃは、それぞれのブロックＢ１、Ｂ２、Ｂ３の冗長セルアレイ領域２１の冗長メモリセル２３に置換されて救済される。このようにブロックＢ１、Ｂ２、Ｂ３毎に不良メモリセルを救済した場合、例えばブロックＢ１の冗長セルアレイ領域２１内の冗長メモリセル２３がすべて置換されると、当該ブロックＢ１の通常セルアレイ領域２０内の不良メモリセルをそれ以上救済できなくなる。そうすると、例えばブロックＢ２、Ｂ３、Ｂ４の冗長セルアレイ領域２１内に冗長メモリセル２３が残存している場合でも、上記ブロックＢ１の不良メモリセルを救済できず、半導体チップ５０が不良品となる。すなわち、半導体チップ５０全体で見た場合に、冗長セルメモリ２３が残存しているにも関わらず、当該半導体チップ５０が不良品となる。 Here, when a method similar to the method of the above embodiment is used, for example, the defective memory cell 22a of the block B1, the defective memory cell 22b of the block B2, and the defective memory cell 22c of the block B3 are respectively connected to the blocks B1 and B2. , B3 is replaced by the redundant memory cell 23 in the redundant cell array region 21, and is repaired. In this way, when the defective memory cell is relieved for each of the blocks B1, B2, and B3, for example, if all the redundant memory cells 23 in the redundant cell array region 21 of the block B1 are replaced, the normal cell array region 20 of the block B1 is replaced. The defective memory cell cannot be relieved any more. Then, for example, even when the redundant memory cell 23 remains in the redundant cell array region 21 of the blocks B2, B3, and B4, the defective memory cell of the block B1 cannot be relieved, and the semiconductor chip 50 becomes a defective product. That is, when viewed as a whole of the semiconductor chip 50, the semiconductor chip 50 becomes a defective product even though the redundant cell memory 23 remains.
　これに対して、本実施の形態では、異なるブロックＢ１、Ｂ２、Ｂ３の不良メモリセル２２ａ、２２ｂ、２２ｃが、図２７に示すようにブロックＢ１の冗長セルアレイ領域２１の冗長メモリセル２３ａ、２３ｂ、２３ｃに再配置される。こうして冗長メモリセル２３ａ、２３ｂ、２３ｃが連続して配置される。同様に、ブロックＢ２、Ｂ３、Ｂ４における冗長セルアレイ領域２１にも冗長メモリセル２３が連続して配置される。このようにすべての冗長メモリセル２３を有効に使用することができるので、冗長メモリセル２３を使用する自由度が向上する。したがって、半導体チップ５０の歩留まりを向上させることができる。また、本実施の形態によれば、冗長メモリセル２３を有効に使用することができるので、回路１１に配置しておくべき冗長メモリセル２３の数を減少させることもでき、半導体チップ５０を小型化することもできる。 On the other hand, in this embodiment, defective memory cells 22a, 22b, and 22c in different blocks B1, B2, and B3 are replaced with redundant memory cells 23a, 23b, 23c is rearranged. Thus, redundant memory cells 23a, 23b, and 23c are continuously arranged. Similarly, redundant memory cells 23 are continuously arranged in the redundant cell array region 21 in the blocks B2, B3, and B4. As described above, since all the redundant memory cells 23 can be used effectively, the degree of freedom in using the redundant memory cells 23 is improved. Therefore, the yield of the semiconductor chip 50 can be improved. Further, according to the present embodiment, since the redundant memory cell 23 can be used effectively, the number of redundant memory cells 23 to be arranged in the circuit 11 can be reduced, and the semiconductor chip 50 can be reduced in size. It can also be converted.
　以上の実施の形態のアドレス変換回路１２１は、不良アドレス記録部３３と同様の方法を用いて、不良メモリセルのアドレスを冗長メモリアドレスアクセス用アドレスに変換してもよい。すなわち、不良メモリセルのアドレスと一対一に対応する冗長メモリアドレスアクセス用アドレスを、不良アドレス記録部３３と同様の方法を用いて記録してもよい。かかる場合、より効率よくアドレスの変換を行うことができる。なお、このアドレスの具体的な記録方法は、上記実施の形態と同様であるので説明を省略する。 The address conversion circuit 121 of the above embodiment may convert the address of the defective memory cell into an address for redundant memory address access using the same method as the defective address recording unit 33. That is, the redundant memory address access address corresponding one-to-one with the address of the defective memory cell may be recorded using the same method as the defective address recording unit 33. In such a case, the address conversion can be performed more efficiently. Note that the specific recording method of this address is the same as that in the above embodiment, and the description thereof will be omitted.
　また、以上の実施の形態のアドレス変換回路１２１に代えて、予め不良メモリセルのアドレスに対応した冗長メモリアクセス用アドレスがデータとして書き込まれたメモリ（図示せず）を用いてもよい。そして、不良アドレスバッファ１２０からコンパレータ８２に不良メモリのアドレスを出力する際、その不良メモリセルのアドレスに対応した冗長メモリアクセス用アドレスのデータをメモリから読み出す。そして、コンパレータ８２で比較されたアドレスが不一致の場合、読み出したアドレスデータに基づいて冗長メモリ２３にアクセスし、不良メモリセルが当該冗長メモリセル２３に置換されて救済される。 Further, instead of the address conversion circuit 121 of the above embodiment, a memory (not shown) in which a redundant memory access address corresponding to the address of the defective memory cell is written in advance as data may be used. When a defective memory address is output from the defective address buffer 120 to the comparator 82, the redundant memory access address data corresponding to the defective memory cell address is read from the memory. If the addresses compared by the comparator 82 do not match, the redundant memory 23 is accessed based on the read address data, and the defective memory cell is replaced with the redundant memory cell 23 to be relieved.
　以上の実施の形態では、電子素子としてメモリセル（メモリ素子）を用いた場合について説明したが、他の電子素子、例えばロジック素子などに対しても本発明を適用することができる。すなわち、本発明の方法を用いて、不良ロジック素子を冗長ロジック素子に置換して救済することができる。 In the above embodiment, the case where a memory cell (memory element) is used as an electronic element has been described. However, the present invention can also be applied to other electronic elements such as a logic element. That is, by using the method of the present invention, a defective logic element can be replaced with a redundant logic element and repaired.
　また、以上の実施の形態では、メモリセル単位で不良メモリセルを救済していたが、メモリセルの集合体の単位で不良な集合体を救済するようにしてもよい。メモリセルの集合体には、任意の単位の集合体が選択されるが、例えば同じアドレスが選択される通常セルアレイ領域２０の集合である、いわゆるブロックが用いられる。かかる場合、本発明の方法を用いて、不良ブロックを冗長ブロックに置換して救済することができる。 In the above embodiment, defective memory cells are relieved in units of memory cells, but defective aggregates may be relieved in units of memory cell aggregates. As a set of memory cells, a set of arbitrary units is selected. For example, a so-called block which is a set of normal cell array regions 20 in which the same address is selected is used. In such a case, the defective block can be replaced with a redundant block and repaired using the method of the present invention.
　以上、添付図面を参照しながら本発明の好適な実施の形態について説明したが、本発明はかかる例に限定されない。当業者であれば、特許請求の範囲に記載された思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。本発明はこの例に限らず種々の態様を採りうるものである。本発明は、基板がウェハ以外のＦＰＤ（フラットパネルディスプレイ）、フォトマスク用のマスクレチクルなどの他の基板である場合にも適用できる。 The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood. The present invention is not limited to this example and can take various forms. The present invention can also be applied to a case where the substrate is another substrate such as an FPD (flat panel display) other than a wafer or a mask reticle for a photomask.
　本発明は、半導体チップを積層して半導体装置を製造する際に有用である。 The present invention is useful when a semiconductor device is manufactured by stacking semiconductor chips.
　　１０　ウェハ
　　１１　回路
　　１２　デバイス層
　　２０　通常セルアレイ領域
　　２１　冗長セルアレイ領域
　　２２　メモリセル
　　２３　冗長メモリセル
　　２４　ワード線
　　２５　ビット線
　　３０　電極用貫通孔
　　３１　冗長用貫通孔
　　３１ａ　第１の冗長用貫通孔
　　３１ｂ　第２の冗長用貫通孔
　　３２　スクライブライン
　　３３　不良アドレス記録部
　　３４　貫通電極
　　４０　支持ウェハ
　　５０　半導体チップ
　　６０　検査装置
　　６１　テスタ
　　６２　プローブ
　　６３　導電性液
　　７０、７２　アドレス線
　　７１　電源線
　　７３　接地線
　　７４　導電性材料
　　７５　絶縁性材料
　　１００　半導体装置
　　１１０　冗長用貫通孔
　　１２０　不良アドレスバッファ
　　１２１　アドレス変換回路 DESCRIPTION OF SYMBOLS 10 Wafer 11 Circuit 12 Device layer 20 Normal cell array area 21 Redundant cell array area 22 Memory cell 23 Redundant memory cell 24 Word line 25 Bit line 30 Electrode through hole 31 Redundant through hole 31a First redundant through hole 31b Second Redundant through hole 32 Scribe line 33 Defective address recording section 34 Through electrode 40 Support wafer 50 Semiconductor chip 60 Inspection device 61 Tester 62 Probe 63 Conductive liquid 70, 72 Address line 71 Power line 73 Ground line 74 Conductive material 75 Insulation Material 100 Semiconductor device 110 Redundant through hole 120 Defective address buffer 121 Address conversion circuit

Claims (16)

  1. 半導体装置の製造方法において、
    複数の電子素子が配置された通常素子領域と、前記通常素子領域内の不良電子素子を置換するための冗長電子素子が配置された冗長素子領域とを備えた回路を基板表面に複数形成して、当該基板表面に前記回路を含むデバイス層を形成するデバイス形成工程と、
    前記基板及び前記デバイス層の厚み方向に貫通する、複数の電極用貫通孔と複数の冗長用貫通孔をそれぞれ形成する貫通孔形成工程と、
    前記電極用貫通孔に導電性材料を充填し、前記回路に電気的に接続される貫通電極を形成する電極形成工程と、
    前記基板の裏面側から前記貫通電極を介して前記回路の電気的試験を行う回路試験工程と、
    前記回路試験工程で検出された前記通常素子領域内の不良電子素子の位置情報を、前記複数の冗長用貫通孔を有する不良位置情報記録部に記録する不良位置情報記録工程と、
    前記不良位置情報記録部に記録された不良電子素子の位置情報に基づいて、当該不良電子素子を前記冗長電子素子に置換する冗長置換工程と、を有する。     In a method for manufacturing a semiconductor device,
    A plurality of circuits including a normal element region in which a plurality of electronic elements are arranged and a redundant element region in which redundant electronic elements for replacing defective electronic elements in the normal element region are formed are formed on the substrate surface. A device forming step of forming a device layer containing the circuit on the substrate surface;
    A through hole forming step of forming a plurality of electrode through holes and a plurality of redundant through holes, respectively, penetrating in the thickness direction of the substrate and the device layer;
    An electrode forming step of filling the electrode through-hole with a conductive material and forming a through-electrode electrically connected to the circuit;
    A circuit test process for conducting an electrical test of the circuit from the back side of the substrate through the through electrode;
    A defect position information recording step of recording position information of a defective electronic element in the normal element region detected in the circuit test step in a defect position information recording unit having the plurality of redundant through holes;
    A redundant replacement step of replacing the defective electronic element with the redundant electronic element based on the position information of the defective electronic element recorded in the defective position information recording unit.
  2. 請求項１に記載の半導体装置の製造方法であって、
    前記不良位置情報記録工程において、前記複数の冗長用貫通孔に対応する各々の位置情報線を接地線又は電源線に接続する。     A method of manufacturing a semiconductor device according to claim 1,
    In the defect position information recording step, each position information line corresponding to the plurality of redundant through holes is connected to a ground line or a power line.
  3. 請求項１に記載の半導体装置の製造方法であって、
    前記不良位置情報記録部において、前記複数の冗長用貫通孔は、電源線接続用の第１の冗長用貫通孔と接地線接続用の第２の冗長用貫通孔を備えた一対の冗長用貫通孔を複数有し、
    前記不良位置情報記録工程において、前記第１の冗長用貫通孔を介して電源線と位置情報線を接続するか、あるいは前記第２の冗長用貫通孔を介して接地線と位置情報線を接続することで、前記不良位置情報記録部に前記不良電子素子の位置情報を記録する。     A method of manufacturing a semiconductor device according to claim 1,
    In the defect position information recording section, the plurality of redundant through holes are a pair of redundant through holes provided with a first redundant through hole for power supply line connection and a second redundant through hole for ground line connection. Have multiple holes,
    In the defect position information recording step, the power supply line and the position information line are connected through the first redundant through hole, or the ground line and the position information line are connected through the second redundant through hole. Thus, the position information of the defective electronic element is recorded in the defect position information recording unit.
  4. 請求項３に記載の半導体装置の製造方法であって、
    前記電源線と位置情報線を接続する際には、前記第１の冗長用貫通孔の上部に導電性材料を充填し、且つ第１の冗長用貫通電極の下部に絶縁性材料を充填すると共に、前記第２の冗長用貫通孔に絶縁性材料を充填し、
    前記接地線と位置情報線を接続する際には、前記第２の冗長用貫通孔の上部に導電性材料を充填し、且つ第２の冗長用貫通電極の下部に絶縁性材料を充填すると共に、前記第１の冗長用貫通孔に絶縁性材料を充填する。     A method of manufacturing a semiconductor device according to claim 3,
    When the power supply line and the position information line are connected, the upper portion of the first redundant through hole is filled with a conductive material, and the lower portion of the first redundant through electrode is filled with an insulating material. Filling the second redundant through hole with an insulating material;
    When connecting the ground line and the position information line, the upper portion of the second redundant through hole is filled with a conductive material, and the lower portion of the second redundant through electrode is filled with an insulating material. The first redundant through hole is filled with an insulating material.
  5. 請求項１に記載の半導体装置の製造方法であって、
    前記通常素子領域には、前記複数の電子素子が行アドレスと列アドレスで特定されるように格子状に配置され、
    前記冗長素子領域には、各行アドレス毎に前記冗長電子素子がそれぞれ配置され、
    前記冗長置換工程において、各行アドレス毎に不良電子素子を前記冗長電子素子に置換する。     A method of manufacturing a semiconductor device according to claim 1,
    In the normal element region, the plurality of electronic elements are arranged in a lattice shape so as to be specified by a row address and a column address,
    In the redundant element region, the redundant electronic elements are arranged for each row address,
    In the redundant replacement step, the defective electronic element is replaced with the redundant electronic element for each row address.
  6. 請求項１に記載の半導体装置の製造方法であって、
    前記電子素子と前記冗長電子素子は、それぞれ揮発性を有する。     A method of manufacturing a semiconductor device according to claim 1,
    The electronic element and the redundant electronic element each have volatility.
  7. 請求項１に記載の半導体装置の製造方法であって、
    前記貫通孔形成工程において、前記複数の電極用貫通孔と前記複数の冗長用貫通孔を形成すると共に、前記基板及び前記デバイス層を分割して、前記回路を有する複数の半導体チップを形成するためのスクライブラインを形成する。     A method of manufacturing a semiconductor device according to claim 1,
    In the through hole forming step, the plurality of electrode through holes and the plurality of redundant through holes are formed, and the substrate and the device layer are divided to form a plurality of semiconductor chips having the circuit. Form a scribe line.
  8. 請求項７に記載の半導体装置の製造方法であって、
    前記回路試験工程において、前記半導体チップ毎に前記回路の電気的試験を行う。     A method of manufacturing a semiconductor device according to claim 7,
    In the circuit test step, an electrical test of the circuit is performed for each semiconductor chip.
  9. 請求項７に記載の半導体装置の製造方法であって、
    前記貫通孔形成工程と前記電極形成工程において、前記電極用貫通孔、前記貫通電極、前記冗長用貫通孔及び前記スクライブラインをそれぞれデバイス層の表面から前記基板の内部まで延伸するように形成し、
    前記電極形成工程後であって前記回路試験工程前に、前記デバイス層の表面に支持基板を設け、その後、前記基板の裏面を研磨することにより、前記貫通電極、前記冗長用貫通孔、前記スクライブラインをそれぞれ前記基板の厚み方向に貫通させて形成する。     A method of manufacturing a semiconductor device according to claim 7,
    In the through hole forming step and the electrode forming step, the electrode through hole, the through electrode, the redundant through hole, and the scribe line are formed to extend from the surface of the device layer to the inside of the substrate, respectively.
    After the electrode forming step and before the circuit testing step, a support substrate is provided on the surface of the device layer, and then the back surface of the substrate is polished to thereby form the through electrode, the redundant through hole, and the scribe. Each line is formed through the substrate in the thickness direction.
  10. 請求項７に記載の半導体装置の製造方法であって、
    前記冗長置換工程後に、前記半導体チップを積層して接合する。     A method of manufacturing a semiconductor device according to claim 7,
    After the redundant replacement step, the semiconductor chips are stacked and bonded.
  11. 請求項７に記載の半導体装置の製造方法であって、
    前記不良位置情報記録工程後であって前記冗長置換工程前に、前記半導体チップを積層して接合する。     A method of manufacturing a semiconductor device according to claim 7,
    The semiconductor chips are stacked and bonded after the defective position information recording step and before the redundant replacement step.
  12. 請求項１に記載の半導体装置の製造方法であって、
    前記冗長置換工程後において、前記基板及び前記デバイス層を積層して接合した後、前記回路を有する半導体チップ毎に前記接合された基板及びデバイス層を分割する。     A method of manufacturing a semiconductor device according to claim 1,
    After the redundant replacement step, the substrate and the device layer are stacked and bonded, and then the bonded substrate and device layer are divided for each semiconductor chip having the circuit.
  13. 請求項１に記載の半導体装置の製造方法であって、
    前記不良位置情報記録工程後であって前記冗長置換工程前において、前記基板及び前記デバイス層を積層して接合した後、前記回路を有する半導体チップ毎に前記接合された基板及びデバイス層を分割する。     A method of manufacturing a semiconductor device according to claim 1,
    After the defect position information recording step and before the redundant replacement step, the substrate and the device layer are stacked and bonded, and then the bonded substrate and device layer are divided for each semiconductor chip having the circuit. .
  14. 請求項１に記載の半導体装置の製造方法であって、
    前記冗長置換工程において、複数の前記不良電子素子が前記冗長電子素子に置換された場合に、当該置換される複数の冗長電子素子は冗長素子領域内で連続するように配置される。     A method of manufacturing a semiconductor device according to claim 1,
    In the redundant replacement step, when a plurality of defective electronic elements are replaced with the redundant electronic elements, the plurality of redundant electronic elements to be replaced are arranged to be continuous in the redundant element region.
  15. 請求項１に記載の半導体装置の製造方法であって、
    前記回路試験工程では、前記貫通電極に対応する位置に配置され、且つ先端に導電性液が付着したプローブが用いられ、
    当該回路試験工程は、前記プローブを前記貫通電極に近接させて、前記導電性液を前記貫通電極に接触させた状態で行われる。     A method of manufacturing a semiconductor device according to claim 1,
    In the circuit test step, a probe that is disposed at a position corresponding to the through electrode and has a conductive liquid attached to the tip is used.
    The circuit test step is performed in a state where the probe is brought close to the through electrode and the conductive liquid is in contact with the through electrode.
  16. 所定の製造方法を用いて製造される半導体装置であって、
    前記所定の製造方法は、
    複数の電子素子が配置された通常素子領域と、前記通常素子領域内の不良電子素子を置換するための冗長電子素子が配置された冗長素子領域とを備えた回路を基板表面に複数形成して、当該基板表面に前記回路を含むデバイス層を形成するデバイス形成工程と、
    前記基板及び前記デバイス層の厚み方向に貫通する、複数の電極用貫通孔と複数の冗長用貫通孔をそれぞれ形成する貫通孔形成工程と、
    前記電極用貫通孔に導電性材料を充填し、前記回路に電気的に接続される貫通電極を形成する電極形成工程と、
    前記基板の裏面側から前記貫通電極を介して前記回路の電気的試験を行う回路試験工程と、
    前記回路試験工程で検出された前記通常素子領域内の不良電子素子の位置情報を、前記複数の冗長用貫通孔を有する不良位置情報記録部に記録する不良位置情報記録工程と、
    前記不良位置情報記録部に記録された不良電子素子の位置情報に基づいて、当該不良電子素子を前記冗長電子素子に置換する冗長置換工程と、を有する。     A semiconductor device manufactured using a predetermined manufacturing method,
    The predetermined manufacturing method is:
    A plurality of circuits including a normal element region in which a plurality of electronic elements are arranged and a redundant element region in which redundant electronic elements for replacing defective electronic elements in the normal element region are formed are formed on the substrate surface. A device forming step of forming a device layer containing the circuit on the substrate surface;
    A through hole forming step of forming a plurality of electrode through holes and a plurality of redundant through holes, respectively, penetrating in the thickness direction of the substrate and the device layer;
    An electrode forming step of filling the electrode through hole with a conductive material and forming a through electrode electrically connected to the circuit;
    A circuit test process for conducting an electrical test of the circuit from the back side of the substrate through the through electrode;
    A defect position information recording step of recording position information of a defective electronic element in the normal element region detected in the circuit test step in a defect position information recording unit having the plurality of redundant through holes;
    A redundant replacement step of replacing the defective electronic element with the redundant electronic element based on the position information of the defective electronic element recorded in the defective position information recording unit.
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