JP2011100898A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for detecting a failure in a path between a data input/output pad and a test pad and a failure in a circuit in the middle of the path. <P>SOLUTION: A micro-bump pad (a first pad 21) for data input/output is arranged in a connection path between the test pad (second pad 22) used for testing a semiconductor device and an internal circuit 23. Consequently, it is possible to detect a connection failure and a circuit failure of all the paths to the internal circuit 23 when executing a test using the second pad 22. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a first pad for data input / output and a second pad for test.

In order to form data input / output terminals using micro bumps or the like, a semiconductor memory having a minute and narrow pitch pad (terminal) is known (for example, see Patent Document 1).
In such a semiconductor memory, the wafer test probe card cannot cope with the narrow pitch of the micro bumps. For this reason, Patent Document 1 discloses a configuration for preparing a test pad for a probe separately from a fine, narrow-pitch pad, and performing a test on the semiconductor memory under control of the probe.

  Specifically, in the semiconductor memory described in Patent Document 1, a switching circuit unit that switches a signal input / output path between a small and narrow pitch pad side and a test pad side with respect to an internal circuit and its control circuit (logic control). Part). During the inspection, the switching circuit unit operates so that a predetermined number of signals that are normally input to the fine, narrow-pitch pads used for normal operation are transmitted to the internal circuit (output circuit unit) via the inspection pad. Is controlled. During normal operation, the switching circuit unit is controlled so that a predetermined number of signal input / output paths are cut off from the inspection pad side and connected to the fine and narrow pitch pad side.

In the configuration of this switching control circuit, the control circuit controls the switching circuit unit during the wafer test so that the test pad is connected to the internal circuit, and the external tester performs various tests of the internal circuit via the test pad. Is possible.
Generally, in a test at the time of manufacturing, in addition to checking the operation of the internal circuit itself, a path test for checking the quality of the signal input / output path is also important.

JP 2005-340343 A

  However, the configuration described in Patent Document 1 has a disadvantage in that even if there is a defect in the path from a fine and narrow pitch pad (for example, a pad corresponding to a micro bump) to the switching circuit unit, the defect in the path cannot be detected. is there.

  In this case, the path failure from the minute and narrow pitch pad to the switching circuit can be determined only in a form close to a finished product in which the minute and narrow pitch pad is connected to another chip or the like. When a defect is detected in the path of the micro bump pad, at this time, the chip is stacked or the package is accommodated in a package. For this reason, when a defective chip is discarded, other stacked normal chips, and in addition to this, a package member is also discarded. As a result, the material cost associated with the disposal of defective products increases, and the manufacturing cost (man-hours) consumed up to that point is wasted, which increases the product cost.

  In the present invention, when a second pad for testing is provided in addition to the first pad for data input / output, it is possible to detect a defect in a circuit between the first and second pads and a circuit in the middle of the path. A semiconductor device having a configuration in which defective products can be eliminated in a chip state is provided.

A semiconductor device according to the present invention includes a semiconductor substrate, a plurality of second pads, and a plurality of first pads.
The plurality of second pads are test pads formed on the semiconductor substrate.
The plurality of first pads are pads for data input / output, which are formed on the semiconductor substrate, and are respectively disposed in a connection path between the corresponding second pad and the internal circuit.

In such a configuration, a data (or test) signal is input to the internal circuit using the plurality of second pads during a test. Alternatively, a data signal from the internal circuit (or indicating the response of the input test signal) is output to the outside using the plurality of second pads.
If a data (or test) signal is input from a plurality of second pads when a signal is input during a test, the signal is sent from the second pad to the internal circuit via the first pad. At the time of signal output at the time of testing, on the contrary, a signal is taken out from the second pad via the first pad from the internal circuit.

In both cases of signal input and output, the signal passes through a path between pads, that is, a path between the first and second pads. If there is a connection failure or a resistance abnormality failure in the path between the pads, this appears in the signal waveform or the like, and these failures are detected.
When the signal processing circuit exists in the inter-pad path, the quality of the signal processing circuit is detected along with such a connection failure and a resistance abnormality failure. Further, such a connection or circuit failure is simultaneously detected between the path of the first pad and the internal circuit.

  According to the present invention, when there is a second pad for testing in addition to the first pad for data input / output, it is possible to detect a defect in the circuit between the first and second pads and a circuit in the middle of the path. Thus, it is possible to provide a semiconductor device having a configuration in which defective products can be eliminated in a chip state.

FIG. 4 is an explanatory diagram of the stacking of chips and the pad layout of each chip in the chip stacking type semiconductor device according to the first embodiment. It is a block diagram which shows the 1st connection form of the pad with respect to an internal circuit which can be employ | adopted by 1st Embodiment. It is a block diagram which shows the 2nd connection form. It is a block diagram which shows the 3rd connection form. FIG. 6 is a circuit block diagram of a semiconductor device related to the second embodiment and including a detailed configuration of an IF circuit. It is a circuit block diagram of a data compression circuit. It is a block diagram which shows the connection form of a comparative example. It is a circuit block diagram of a semiconductor device relating to a comparative example and including a detailed configuration of an IF circuit. FIG. 6 is an in-chip layout diagram of IF circuits according to a first modification.

Embodiments of the present invention will be described in the following order with reference to the drawings.
1. 1st Embodiment: It is embodiment which shows the kind of connection aspect of a pad.
2. Second Embodiment: A more specific embodiment including details of the IF circuit.
3. First modification: a modification regarding the arrangement of the IF circuit in the chip.
4). Second modified example: Other modified examples.

<1. First Embodiment>
[Chip stacked structure]
FIG. 1 is an explanatory diagram of the stacking of chips and the pad layout of each chip in the chip stacking type semiconductor device according to the first embodiment.
The semiconductor device according to the present embodiment includes a first semiconductor device and a second semiconductor device that is placed on one main surface of the first semiconductor device and is electrically connected to the first semiconductor device. For this reason, FIG. 1 discloses a configuration example of a chip stacked semiconductor device. Here, for example, an upper layer second semiconductor chip discloses a configuration example of a semiconductor device of a single chip type.
As will be mentioned in a later-described modification, there is no limit to the number of chips stacked (the number of stacked stages) and the number of chips included in the entire device.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 by taking a two-chip multi-chip module as an example. Here, a case where a memory chip is mounted on a logic chip is taken as an example, but the distinction between logic and memory is not essential, as will be mentioned in a modification described later.

  FIG. 1B is a perspective view of the laminated structure of the entire module seen from the side. FIG. 1A is a diagram showing the types of pads provided on the lower surface of the memory chip 2 (opposite connection surface with the logic chip 3). FIG. 1C is a diagram illustrating the types of pads provided on the upper surface of the logic chip 3 (the connection surface facing the memory chip 2). 1A and 1C only show the types of pads, and the arrangement, size (area), or number thereof is not limited.

A chip stack type semiconductor device 1 illustrated in FIG. 1 includes a logic chip 3 as a first semiconductor chip and a memory chip 2 as a second semiconductor chip mounted on the logic chip 3.
The semiconductor device 1 is formed by stacking a memory chip 2 in which a memory is integrated on a logic chip 3 in which a control unit such as a system controller and a logic unit are integrated, for example, when configuring a system LSI. Has been.

  It is assumed that the memory chip 2 is controlled by the logic chip 3. For this reason, the memory chip 2 and the logic chip 3 have the following pad connection structure.

The semiconductor device 1 has a module substrate 11, and the logic chip 3 is fixed on the module substrate 11 by an existing die bond connection method.
On one main surface of the logic chip 3, in addition to data signals to be written to or read from the memory chip 2, a plurality of relatively small signals for inputting / outputting control signals such as clocks, commands, addresses, etc. An area pad (hereinafter referred to as a laminated connection pad 31) is arranged. There is no limitation on the number and arrangement position of the stacked connection pads 31, but the stacked connection pads 31 are collectively arranged at least in a region where the memory chips 2 are stacked. In the case of this example, the laminated connection pad 31 has a micro bump structure.

  In addition, a relatively large bonding pad 32 for wire bonding is disposed on the same surface as the surface on which the stacked connection pads 31 of the logic chip 3 are provided, for example, in a region near the periphery thereof. The number and arrangement positions of the bonding pads 32 are not limited, but the bonding pads 32 are arranged at positions where wire bonding can be performed with at least the required characteristics, for example, near the periphery as shown. Each bonding pad 32 is electrically connected to a wiring portion (not shown) of the laminated connection pad 31 by a wire 33.

  On the other hand, a plurality of first pads 21 are arranged on one main surface of the memory chip 2 for inputting / outputting data signals and control signals. In addition, a predetermined number of second pads 22 for testing are arranged on the periphery of the same memory chip surface as the surface on which the first pads 21 are formed. The memory array (not shown in FIG. 1) is formed by a semiconductor process on the surface side on which the first pad 21 and the second pad 22 are formed.

  Desirably, the first pad 21 is a pad that is smaller than the second pad 22 and can be arranged at high density. Further, assuming that the first pad 21 is used for input / output of data signals and control signals of the memory device and the second pad 22 is used for testing as in this example, the first pad 21 is arranged more than the second pad 22. It is desirable. The first pad 21 is electrically and mechanically connected to a pad 31 formed on the surface (element formation surface) of the logic chip 3.

The arrangement of the first pads 21 is basically not limited, but at least the number and arrangement correspond to the stacked connection pads 31 of the logic chip 3 to be connected.
Also, the arrangement and number of the second pads 22 are not limited, but in the case of a test, the arrangement and number are determined according to the specifications.

  For example, the first pad 21 and the stacked connection pad 31 for chip stack connection can be constituted by bumps made of solder or the like and lands formed in the same manner as the wiring layer on the other. Alternatively, both may have a bump structure.

  Note that the solder bumps may be semicircular or substantially spherical ball bumps. Moreover, the form which the 1st pad 21 and the lamination | stacking connection pad 31 can take other than a bump uses various connection terminal bodies, such as an electroconductive contact bonding layer (what ensures the conduction | electrical_connection state by crimping | compression-bonding), instead of a bump. It is also possible to adopt a configuration in which this connection terminal body is crimped to a land to make electrical connection.

  The second pad 22 having a relatively large size in the illustrated example of FIG. 1 is provided at a ratio of one to a plurality of the first pads 21. In addition, in the example shown in FIG. 1, the probe and the test pin are in contact with each other in the example shown in FIG.

  In addition, since the probe and the test pin come into contact with the second pad 22 during the test, it is desirable that no element be formed thereunder. If an element such as a transistor is formed under the second pad 22, the element may be damaged when a probe or a test pin is pressed against the second pad 22. In order to avoid such damage introduction, the arrangement position of the second pad 22 is limited to some extent.

  Unlike the second pad 22, the first pad 21 is formed in an arbitrary region on the main surface of the chip, the probe and the test pin do not come into contact with each other, and the element is not damaged. Therefore, the first pad 21 can be formed in an arbitrary region, and as a result, the number of pads can be increased as compared with the case where the pads are disposed in the peripheral portion.

The memory chip 2 does not directly exchange signals with the outside. Therefore, an external connection pad for exchanging signals with the outside need only be provided on the logic chip 3 like the bonding pad 32.
Therefore, the memory chip 2 is connected to the logic chip 3 by micro bumps (first pads 21 and stacked connection pads 31).

  A wire 33 is connected to the logic chip 3 at the time of wire bonding in a state where the memory chip 2 is stacked. Therefore, a space is required so that the memory chip 2 does not get in the way during wire bonding. Therefore, in this example, the logic chip 3 has a larger area (footprint) in plan view than the memory chip 2. In addition, although connection between chips can also be performed by Si through vias (so-called TSV), in that case, there is no restriction on the chip area. However, generally, the area of the chip on the side of the module substrate 11 disposed below is larger than the area of the chip stacked thereon.

  As shown in FIG. 1, the memory chip 2 is stacked on the logic chip 3, and the side of the module substrate 11 connected to the logic chip 3 via the wires 33 is sealed with the package member 12. External terminals are provided on the outer surface of the package member 12 at locations not shown.

[Pad connection form]
2 to 4 are diagrams showing pad connection forms with respect to internal circuits that can be employed in the present embodiment in the memory chip 2 (or logic chip 3). This pad connection form can also be adopted in the logic chip 3, but hereinafter it is assumed that it is adopted in the memory chip 2.

The first pad connection form shown in FIG. 2 is between the second pad 22 (bonding pad 32 in the case of the logic chip 3) and the internal circuit 23 such as a memory array (logic unit in the case of the logic chip 3). This shows the signal path.
In this embodiment, the first IF circuit (IF circuit 1) 4, the first pad 21, and the second IF circuit (IF circuit 2) 5 are arranged in this order between the second pad 22 and the internal circuit 23. Connected in series.

The first IF circuit 4 constitutes an example of a signal processing circuit for a test having a function of switching between a used state and an unused state. The first IF circuit 4 can further be provided with input / output functions such as a driver and a receiver.
The first pad 21 has a micro bump structure in this example.
The second IF circuit 5 is, for example, a circuit having a function for input / output with respect to amplification and signal waveform shaping, such as a driver or a receiver. If such a function is not necessary, the second IF circuit 5 can be omitted. The function for input / output can be omitted from the first IF circuit 4.

  As described above, the semiconductor device 1 according to the present embodiment has a circuit configuration in which the relatively small first pad 21 is connected in series between the relatively large second pad 22 and the internal circuit 23. It is the above feature. With this configuration, in particular, the connection path between the second pad 22 and the first IF circuit 4 is included as a signal path at the time of the test. Can be detected.

  Here, since the second pad 22 is assumed to be used for testing, the first IF circuit 4 is essential, but the first IF circuit 4 can be omitted in cases other than testing. Even when the first IF circuit 4 is omitted, there is an advantage that the connection path between the second pad 22 and the first IF circuit 4 can be examined using the second pad 22.

  The first IF circuit 4 and the second IF circuit 5 can be any of three types of input / output such as 1-bit input / output, 1-bit input, and 1-bit output.

FIG. 3 shows a second bad connection configuration.
In the second pad connection form shown in FIG. 3, two micro bump pads (first pads 21) are connected in series to one probe pad (second pad 22). The first IF circuit (IF circuit 1) 4 has signal processing and input / output functions for testing. The two second IF circuits (IF circuits 2 and 3) 5 have a function for input / output. When the function for input / output is unnecessary, the function can be omitted from the first IF circuit 4 and the two second IF circuits 5 themselves can be omitted as in the first pad connection mode.

According to the second pad connection mode, for example, the second IF circuit (IF circuit 2) 5 is used for signal input, and the other second IF circuit (IF circuit 3) 5 is used for signal output. Can be allocated. In this case, the circuit of the signal input path and the signal output path and the test of the path can be tested from one probe pad (second pad 22).
At this time, a path test between the first pad 21 and the second pad 22 can be performed in each of the two systems.

FIG. 4 shows a third bad connection configuration.
In the third pad connection form shown in FIG. 4, N (≧ 3) micro-bump pads (first pads 21) are connected in series to one probe pad (second pad 22). . The first IF circuit (IF circuit 1) 4 has signal processing and input / output functions for testing. The two second IF circuits (IF circuits 2 and 3) 5 have a function for input / output. When the function for input / output is unnecessary, the function can be omitted from the first IF circuit 4 and the two second IF circuits 5 themselves can be omitted as in the first pad connection mode.

According to the third pad connection mode, for example, each of the N second IF circuits (IF circuits 2) 5 may be used for signal input / output, some of which may be used for signal input, and the rest for signal output. It may be used.
In any case, a test at the time of signal input, output or input / output can be executed from one probe pad. As a case where such a configuration is required, it is preferable to compress or expand a data signal and convert it into a test signal during a test, as will be described in other embodiments described later. This configuration is useful when it is desired to reduce the test cost by increasing the batch test number of chips by a tester or the like, reducing the tact time of the test, and effectively using the hard wafer resources of the test apparatus.

According to the embodiment described above, one first pad 21 is always connected in series between one second pad 22 and the internal circuit 23. For this reason, it is possible to send and receive signals to the internal circuit 23 via the first pad 21 during actual operation. On the other hand, during the test, the path from the second pad 22 to the first pad 21 (in this example, the first IF circuit 4) and the path 8 from the first pad 21 to the internal circuit 23 (in this example) The path test of the second IF circuit 5) can be performed collectively from the second pad 22.
Therefore, since there is no portion that is not subject to the path test, the reliability of the test is increased. Further, since the reliability of the test is high, it is not known after assembling that the chip that has passed the test is defective after all, and the cost can be reduced without wasting material.

<2. Second Embodiment>
The present embodiment is an embodiment that discloses a more specific circuit having both the form of FIG. 3 and FIG. 4 and the form of FIG.
FIG. 5A shows a circuit block diagram of a semiconductor device including a detailed configuration of the first and second IF circuits having a data compression / decompression function. FIG. 5B shows an example of an IF circuit arrangement location in the memory chip 2.

  As shown in FIG. 5B, the semiconductor device 1 has an arbitrary number of memory arrays. There is no limitation on the number of memory arrays, here two. The two memory arrays correspond to the internal circuit 23 in FIGS.

  FIG. 5A shows only seven systems of connection paths with the internal circuit (memory array). This connection path is indicated by reference numerals “RT1 to RT7” in FIG. Although there are more connection paths between the actual memory array and the IF circuit, here, representatively, the 1: 1 connection type in FIG. 2 is indicated by the first paths R1 to RT3, and the remaining path RT4 in FIG. ~ Shown at RT7.

  The three 1: 1 type paths RT1 to RT3 that exist here are RT1 for the clock CLK, RT2 for the command CMD, and RT3 for the address ADD. When there are a plurality of memory arrays (internal circuits 23), each of these 1: 1 type paths R1 to R3 is required at least as many as the number. These 1: 1 type paths are hereinafter referred to as a clock path RT1, a command path RT2, and an address path RT3.

A clock pad 22CK as the second pad 22 and a first pad 21 (micro bump pad) are provided on the clock path RT1. A receiver 51, a repeater buffer 41, a driver 42, and a switch circuit 43 are connected in series in this order between the clock pad 22CK and the first pad 21. A receiver 44 is connected to the memory cell array side of the first pad 21.
Here, the switch circuit 43 is an example of the “switch” in the present invention. The repeater buffer 41 can be omitted when signal degradation due to wiring is slight.

  An ESD protection element 52 is disposed at a connection point between the clock pad 22CK and the receiver 51. Similarly, an ESD protection element 45 is disposed at a connection location between the second pad 22 and the receiver 44. The ESD protection elements 52 and 45 are elements that protect the internal circuit side from static electricity input to the pad by performing electrostatic discharge (ESD). As the ESD protection element, a diode, a diode-connected transistor, a GGMOS (Gate Grounded MOS FET), or a combination thereof is used.

The switch circuit 43 is a circuit that disconnects the circuit and the wiring from the first pad 21 to the clock pad 22CK during the normal operation using the first pad 21 when the operation load is to be reduced. . Although it is preferable to provide the switch circuit 43 in this sense, the switch circuit 43 may be omitted when load reduction is not necessary in terms of characteristics.
The switch circuit 43 may be composed of one transistor, but here, a so-called transfer gate switch in which a PMOS transistor and an NMOS transistor are connected to each other between drains and sources is included in the switch circuit 43. In addition to this, the switch circuit 43 has an inverter for driving the NMOS transistor and the PMOS transistor with the same control signal.

  The above path configuration is the same for the command path RT2 using the command pad 2CM as the second pad and the address path RT3 using the address pad 2AD as the second pad.

On the other hand, the remaining four routes RT4 to RT7 form a one-to-one polymorphic route (see FIG. 4) as a whole, and routes RT4 and RT5 are for data input, and routes RT6 and RT7 are for data output. The function is allocated.
A receiver 53 common to two input paths and a driver 54 common to two output paths are connected in parallel to one data pad 22DT which is an example of the second pad 22. Further, the ESD protection element 52 similar to the other paths is connected to the input / output path of the data pad 22DT.

The circuit units constituting the paths RT4 and RT5 are connected in parallel to the output of the receiver 53.
This circuit unit includes a data decompression circuit 46, a driver 42, a switch circuit 43, an ESD protection element 45, and a receiver 44 from the receiver 53 side. Basically, this circuit unit is obtained by replacing the repeater buffer 41 of the 1: 1 type paths RT1 to RT3 with a data expansion circuit 46.
A data compression circuit 47 is connected to the input of the driver 54. The data compression circuit 47 is an example of a “data signal conversion circuit” that converts an 8-bit data signal into a 1-bit test signal when the data width is 8 bits.

The input side of the data compression circuit 47 is a circuit portion of paths RT6 and RT7 for inputting 1-bit data.
This circuit section is configured to include a reset transistor RT for resetting the input of the data compression circuit 47, a switch circuit 43 similar to other paths, the first pad 21, the ESD protection element 45, and a receiver 48. .
The reset transistor RT is composed of, for example, one NMOS transistor, the drain is connected to the input of the data compression circuit 47, and the source is grounded. In this example, the gate of the reset transistor RT is driven by an inverted signal of a control signal (selection signal SEL) that collectively controls the switch circuit 43.

FIG. 6 shows a circuit configuration example of the data compression circuit 47.
In the data compression circuit 47 shown in FIG. 6, the negation (XNOR) of the exclusive OR gate at the first stage is connected to the output from the switch circuit 43. Eight exclusive OR gate negations (XNOR) are provided corresponding to the number of output bits. In the second stage, the third stage,..., And the final stage, the number of outputs is reduced by the AND circuit AND, and is finally collected into one test data TDQ.
Since the expected value is given to the negation (XNOR) of the exclusive OR gate in the first stage, if the expected value and the logic differ even by 1 bit in the read data, the test data TDQ indicates a test failure, for example “0”, If all bits match, for example, a logic “1” indicating that the test has passed is output.

  Such a data compression circuit 47 is not essential when the present invention is applied. However, since a large number of first pads 21 are arranged, considering the case where the same number of second pads 22 cannot be arranged, a configuration in which test results are output by such data compression is desirable.

On the other hand, although details of the data decompression circuit 46 are omitted, this circuit is configured to include an exclusive OR gate negation (XNOR) that performs an exclusive OR with the scramble signal. This is a configuration suitable for a scramble test in which logic “1” and “0” of the data pattern are exchanged in adjacent columns of the memory array. In the memory, a random data pattern is input or output at the time of actual use. However, if the test pattern is used in all combinations, the test load increases. The scramble test reduces the test load by changing the logic.
Such a data decompression circuit 46 is not essential when applying the present invention. However, in the configuration in which the number of the second pads 22 is reduced as compared with the first pads 21, it is desirable to incorporate the data decompression circuit 46 in order to contribute to reducing the test load.

  As described above, in the second embodiment, the clock, command, and address input paths include the micro bump (first pad 21) and the probe pad (second pad 22) as a set. On the other hand, the configuration for data test is realized by reducing the number of pins of the probe card by connecting in parallel to one data pad 22DT (second pad 22) common for data input / output. Can do.

Specifically, the data pad 22DT is an input / output common pad at the time of testing, and the two first pads 21 are independent pads to which individual data D0 and D1 are supplied during normal operation in the data input paths RT4 and RT5. .
Instead of individual input data D0 and D1 input during normal operation, XNOR of a test data signal input from the data pad 22DT and a scramble signal input from a second pad (not shown) is expanded during the test. The signal is supplied to the internal circuit. As a result, two columns of the memory array can be tested using one test pad. It should be noted that a multi-bit column test such as 8, 16,... Can be executed with a single input / output common pad, for example, by configuring the data expansion circuit 46 in a multi-stage configuration like the compression circuit of FIG.

Similarly, in the data output paths RT6 and RT7, the data pad 22DT is an input / output common pad at the time of testing, and the two first pads 21 are independent pads that output individual output data Q0 and Q1 at the time of normal operation. .
Instead of the individual data Q0 and D1 output during normal operation, the output data Q0, Q1,... Output from the memory array are compared with expected values input from the second pad (not shown) during the test. Compress the results to generate test data. The generated test data can be output from the data pad 22DT to an external tester or the like.
As can be seen from the above configuration and operation, in the present embodiment, four micro bump pads can be replaced with one probe pad.

  Next, the advantage of providing the first pad 21 so as to be inserted in the middle of the series connection path of the second pad 22 and the internal circuit is further clarified by comparing with the comparative example in which this advantage cannot be obtained. To.

[Comparative example]
7 and 8 are a connection path diagram between blocks of a comparative example, and a circuit block diagram showing a more detailed example of an IF circuit. 7 corresponds to FIGS. 2 to 4 to which the present invention is applied, and FIG. 8 corresponds to FIG.

  The connection path diagram of the comparative example of FIG. 7 is basically a path between the probe pad (first pad 21) and the second pad 22 (micro bump pad) and the internal circuit 23, as is apparent from comparison with FIG. Not in the middle, but connected to the IF circuit 40 in the same row (in parallel). As described in Patent Document 1, the IF circuit 40 always has a role of a (path) selection switch, and input / output of the selected signal with the internal circuit is permitted. Therefore, the path from the probe pad to the micro bump pad could not be tested.

In FIG. 8, the same components as those in FIG.
In FIG. 5A, a switch circuit 43 is provided to control connection and disconnection of the route, but in FIG. 8, a selector 49 is arranged as a route selection switch instead. In the selector 49, the input selector is indicated by a circuit block and the output selector is indicated by an AND circuit. However, the selector 49 is different in whether the input side is switched or the output side is switched, and the basic functions are the same. .

The (input) selector 49 provided in the paths RT1 to RT5 has a receiver 44, an ESD protection element 45, and a first pad 21 connected in series to the first input. The output of the driver 42 is connected to the second input. The (input) selector 49 exclusively connects the first input side and the second input side to the output according to the logic of the selection signal SEL to be applied.
In the (output) selector provided in the paths RT6 and RT7, the receiver 48, the ESD protection element 45, and the first pad 21 are connected in series to the first output. The second output is connected to the data input terminal of the data compression circuit 47. The (output) selector 49 exclusively connects the first output side and the second output side to the input according to the logic of the selection signal SEL to be applied.
Other configurations are common to FIGS. 8 and 5A.

In the comparative example of FIG. 8, when the test is performed from the probe pad (second pad such as the data pad 22DT), the path test from the first pad 21 of the micro bump path to the selector 49 cannot be performed. For this reason, the disconnection of the pad, the failure of the driver and the receiver, the failure of one side portion of the selector, etc. cannot be found.
On the other hand, in the configuration of the present embodiment disclosed in FIGS. 2 to 4 and 5A, this problem does not occur by connecting the path from the probe pad and the path from the micro bump pad in series. .

  In the first and second embodiments described above, the following modifications can be implemented.

<First Modification>
The first modification relates to the chip arrangement position of the test circuit (IF circuit).

  Since the micro bump pad (first pad 21) is relatively small, the degree of freedom in arrangement is high. Therefore, the micro bump pad may be disposed at any place in the chip. For this reason, in order to reduce the parasitic capacitance attached to the micro bump via the micro bump, the micro bump pad is close to the circuit that separates the interface circuit (receiver, driver, ESD protection circuit, etc.) from the path of the probe pad (second pad 22). It is desirable to arrange.

However, the interface circuit itself including the function of the test circuit may be arranged at an arbitrary place for the convenience of the floor plan.
Since the probe pad is relatively large and has an arrangement restriction depending on the test environment (the number of probe card needles and the number of simultaneous measurements), the probe pad cannot always be arranged near the path of the micro bump.

  The above restrictions vary depending on the types and number of internal circuits, customer requests, and design policies. Therefore, there are various arrangements of interface circuits and test circuits that satisfy the restrictions.

9A to 9D are layout diagrams that can be used instead of FIG. 5B.
The IF circuit in the path including the micro bump pad (first pad 21) and the IF circuit in the path including the probe pad (second pad 22) may be arranged in a T shape as shown in FIG. The internal circuit is divided and arranged in two areas (blank areas in FIG. 9A) divided by the IF circuit arrangement.
Alternatively, the two IF circuits may be arranged in a cross shape as shown in FIG. 9B, and the internal circuit may be divided and arranged in four regions divided by the IF circuit.
When the internal circuit is divided into two, in addition to FIG. 5 (B) and FIG. 9 (A), it may be as shown in FIG. 9 (D). In this case, the path IF circuit including the micro bump pad (first pad 21) and the path IF circuit including the probe pad (second pad 22) are arranged adjacent to each other.
Further, the two IF circuits can be arranged close to one side of the chip as shown in FIG.

<Second Modification (Other Modifications)>
In the first and second embodiments, the embodiments of the present invention are described in the case of a two-chip stacked semiconductor device.
However, the number of stacked chips is not limited and may be a stack of 3 chips or more. In that case, three or more layers may be stacked, or one or a plurality of chips may be stacked in different regions of one base chip.
In any case, the pad connection structure that eliminates the path that cannot be tested as described in the first and second embodiments may be applied to any one or more chips. Also, the internal circuit need not be a memory array. The chip on which the chip to which the present invention is applied is not necessarily the logic chip 3.

In FIG. 1, the case where the logic chip 3 is larger than the memory chip 2 as an area is illustrated, but the size relationship may be reversed.
Further, it is not always necessary to take out the external terminal by the wire 33 from the pad of the logic chip 3. For example, external connection may be achieved by the back surface BGA of the logic chip 3 or a Si through via.

  1 assumes a mold resin encapsulation or a hollow package structure, the memory chip 2 may be mounted on the logic chip 3 and conversely, the logic chip 3 may be mounted on the memory chip 2 in a bare chip. .

When a memory chip is mounted, the memory element of the memory array may be any of DRAM, SRAM, nonvolatile memory, and other memories. The nonvolatile memory may be anything such as a memory transistor having a charge storage capability as a memory element, a resistance variable element as a memory element, or a magnetic element as a memory element.
There are various memory systems that require a one-to-many interface, such as the DDR system, and the memory system is not limited.

  According to the first and second embodiments and the first and second modifications, the following advantages can be obtained.

Since the path from the probe pad to the micro bump pad can be tested in the wafer state, the operation state after assembling with another chip can be simulated in the wafer state with the micro bump. Thereby, when the present invention is not applied, a defective chip area that can be confirmed only after assembly can be found in a wafer state, and the cost associated with disposal of defective products can be reduced.
After lamination, the probe pad path can be separated by a separation circuit, so that the characteristics when used via micro bumps are hardly affected.
In addition, since an IF circuit or test circuit can be inserted between the probe pad and the micro bump pad, for example, a compression / expansion circuit can be inserted to reduce the number of probe pads or a repeater buffer to insert a probe. Pads can be placed at the chip edges.
The above effect can also be obtained when the Si through electrode is provided in the path from the micro bump pad (between the separation circuit and the receiver or driver for the micro bump pad).

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Memory chip, 3 ... Logic chip, 4 ... 1st IF circuit, 5 ... 2nd IF circuit, 11 ... Module substrate, 12 ... Package member, 21 ... 1st pad (micro bump pad) ), 22 ... second pad (probe pad), 23 ... internal circuit, 40 ... IF circuit, 41 ... repeater buffer, 43 ... switch circuit, 45 ... ESD protection element, 46 ... data decompression circuit, 47 ... data compression circuit, 49. Selector.

Claims (11)

A semiconductor substrate;
An internal circuit formed on the semiconductor substrate;
A plurality of second pads for testing formed on the semiconductor substrate;
A plurality of first pads for data input / output, each formed on a connection path between the corresponding second pad and the internal circuit, formed on the semiconductor substrate;
A semiconductor device having: The switch for electrically disconnecting or conducting each of the plurality of first pads from the corresponding second pad is disposed between the plurality of first pads and the plurality of second pads. 2. The semiconductor device according to 1. The semiconductor device according to claim 2, wherein a signal processing circuit for a test is disposed between the plurality of switches and the plurality of second pads. The semiconductor device according to claim 3, wherein the number of the first pads is equal to or more than the number of the second pads. The semiconductor device according to claim 4, wherein the signal processing circuit includes a data signal conversion circuit that converts a data signal input / output to / from the internal circuit and a smaller number of test data signals during a test. The semiconductor device according to claim 5, wherein the first pad has a smaller area than the second pad. The semiconductor device according to claim 6, wherein the first pad is a microbump pad, and the second pad is a test probe pad. The semiconductor device according to claim 1, wherein the number of the first pads is equal to or greater than the number of the second pads. The semiconductor device according to claim 1, wherein the first pad has a smaller area than the second pad. A first semiconductor chip having a plurality of internal connection pads and a plurality of external connection pads on one main surface;
A second semiconductor chip placed on the one main surface of the first semiconductor chip and electrically connected to the first semiconductor chip;
Have
The second semiconductor chip is
A semiconductor substrate;
An internal circuit formed on the semiconductor substrate;
A plurality of second pads for testing formed on the semiconductor substrate;
Formed on the main surface of the semiconductor substrate facing the first semiconductor chip to connect to the plurality of internal connection pads, and each disposed in a connection path between the corresponding second pad and the internal circuit A plurality of first pads for data input / output;
A semiconductor device having: The semiconductor device according to claim 10, wherein the internal circuit includes a memory array.

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