WO2011100051A1

WO2011100051A1 - Silicon wafers prepared from a beam having a plurality of wafers

Info

Publication number: WO2011100051A1
Application number: PCT/US2011/000231
Authority: WO
Inventors: Narayanan Srinivasamohan
Original assignee: Narayanan Srinivasamohan
Priority date: 2010-02-12
Filing date: 2011-02-09
Publication date: 2011-08-18

Abstract

Disclosure of a silicon beam having a plurality of silicon wafers. Disclosure of silicon wafers singulated from the silicon beam having the plurality of silicon wafers. Disclosure of a process to obtain a partially cut silicon ingot, i.e., a silicon beam having a plurality of silicon wafers attached to the silicon beam. Disclosure of a method for cleaning the silicon beam having the plurality of silicon wafers. Disclosure of a process to obtain individual silicon wafers the silicon beam having the plurality of silicon wafers. Disclosure of a solar cell process which includes processing the silicon beam having plurality of wafers and completing the cell process after singulation.

Description

SILICON WAFERS PREPARED FROM A BEAM HAVING A PLURALITY OF WAFERS

FIELD

[1] This PCT Application claims priority from U.S. Application Serial No. 61/282,433, filed February 12, 2010.

[2] This disclosure relates to a crystalline silicon wafer, a crystalline silicon cell, a method of manufacturing the crystalline silicon wafer and method of manufacture of the crystalline silicon solar cell. The present invention further relates to the processing of monocrystalline and multi- crystalline silicon ingots into wafers and cells by a new wafering and cell process that reduces wafer breakage, substantially improves equipment utilization, and enables very thin wafer and cell fabrication.

BACKGROUND

[3] Solar cells convert sunlight into electricity via Photovoltaic effect.

The photovoltaic (PV) effect was first reported in 1839 by Becquerel when he observed a light dependent voltage between electrodes immersed in an electrolyte. After more than a century, silicon photovoltaic cells as a power source were demonstrated. Photovoltaic industry has grown from producing a few kilo watts to a multi GW production per year. More than 80% of solar cells manufactured are based on crystalline silicon (single crystalline or muticrystalline) substrate.

[4] Incident sun light, falling on the solar cell, is absorbed in the cell.

The photon energy is transferred to the semiconductor material and a photovoltage is generated. The solar cell is a p/n junction, like a large- area diode with metal contacts on either side. High purity polysilicon is converted into silicon wafers (substrate) by process of casting or crystal growing followed by a wire sawing process. The silicon substrate is converted into solar cells using technologies based on semiconductor device processing and surface mount technology (SMT). The individual solar cells are connected and assembled into finished product PV Modules. The modules are integrated with system components, inverters, charge conditioners, batteries etc. and then installed at the site.

[5] There is a critical need to reduce the cost of the Photovoltaic cells (also referred to as solar cells) to accelerate the use of the solar energy as an alternate form of energy. There is a huge addressable demand for PV products. However, the high cost of the PV devices is the major road block to a rapid expansion of PV market. A substantial reduction in cost of PV devices will increase the demand by many folds. Due to the abundance of silicon in earth, silicon based solar cells are most suited to meet the demand in a sustainable manner. Hence any decrease in the cost of PV device based on crystalline silicon will be very desirable. Silicon wafer cost is one of the dominating costs of PV devices. Hence approaches to use less silicon wafer, improve the process yield, reduce in consumable cost, improve the capital efficiency will be help in the reduction of the cost of the PV devices.

[6] The crystalline silicon wafer accounts for about 40% of the cost of PV module. There have been ongoing efforts to reduce the cost of PV modules: the use of thinner substrates to save the cost of silicon, device research to increase conversion efficiency of the module, etc.

[7] The process of converting poly silicon into Photovoltaic (solar) module consist of forming block of silicon (known as crystal growth), slicing the block into plurality of wafers( known as wafering), converting the wafers in to solar cells ( known as cell processing) and interconnecting the solar cells into PV module ( known as module making). The wafer making and cell processing is described in more detail below.

[8] The current practice is to use wafers up to 180 micrometer in

thickness on 156 x 156 mm wafers (up to 140 microns on 125 mm pseudo-square mono wafers). Though crystalline solar cells made on wafers with 50 micrometers can perform, but due to the limitation of the high volume manufacturing process for handing the ultrathin wafers the thickness of wafers are kept much higher. While only a few years ago the wafer thickness was about 220 micrometers, automation, improved wet chemistry process equipment have enabled to reduce the wafer thickness while maintaining high yield >95%. However any further reduction in the wafer thickness, though will reduce the silicon cost / watt and will enable use of different cell device design, is hindered by the increased breakages during the wafering and cell process steps. As wafer cost is a significant component of the PV cell cost, any increase in breakage will add to the cost of cell.

[9] Wire saw device is used extensively for slicing hard and brittle

materials such as ceramics, synthetic sapphire, magnetic, photonic , optoelectronic materials, semiconductor materials such as mono crystalline and multi crystalline silicon

[10] Referring to Figures 1 , 2 and 4 the silicon block to be sawed (10), fixed on a support table (15), is pressed against a layer of wires (13) which are placed on the grooves of the rotating cylinders referred as wire guides (14). The block to be cut (10) is placed on glass plate (or beam) (1 1), which is positioned on a metal mounting plate and support table (15). The mounting plate slides into a fixture in the wire saw with provision to move perpendicularly to the plane of the wires.

Alternatively the block is glued to an epoxy beam, which in turn mechanically fixed to mounting plate. The mounting plate slides into the fixture of the wire saw. The speed of the vertical movement determines the cutting speed. The pitch of the grooves defines the interval between the wires and consequently the thickness of the wafers. The wires are made of high tensile strength materials with diameters on the order of 0.1 to 0.2 millimeters. The actual cutting of the block is done by free abrasive slurry made up of silicon carbide and oil or poly ethylene glycol wire web. The slurry is spayed on the wires and the block. Very high wire speed is essential to maintain a uniform coating of the slurry on the wire web which results in significant forces applied on the wafers being cut. Another method of cutting is with the use of fixed abrasive technique. In this method a diamond coated wire web is used. Though the wire speed is much slower, still high level of stress is applied to the block in the case of fixed abrasive method.

] As described by Fig 3, the block (10) is cut by the free abrasive aided by the wire and table movements. Each wire (13) of the wire web provides corresponding cut or section through the block. When after cutting through the block 10, the cutting is continued to up to half of glass plate (1 1) thicknesses to obtain plurality of wafers (22). The cutting process may take about 5-7 hours and a typical block could be about 300-800 mm.

] As the thickness of the wafers is much smaller than the block size, the sawing action causes vibration of the already cut portions of the wafers (23). This deleterious effect increases as the wires cuts through the block and then into the glass/ or the beam. This leads to significant deformation of wafers, undulations and surface irregularities, hence putting a limit of the thickness of the slices which can be produced on large scale. [13] The process steps of the wafer slicing are described in Figure 1 to 4. The wafer process starts by mounting the silicon block on to a sacrificial plate, sawing the silicon block, cleaning the block; releasing and singulating the wafers. The detailed process sequence is described in Figure 4. The process starts by gluing the glass plate to the metal mounting plate, which is attached to the wire saw. Then the silicon beam to be sliced in glued to the other side of the glass plate. The assembly comprising of the above is clamped and cured for several hours. The assembly is loaded into the wire saw table. The slurry flow is stabilized and the silicon beam is brought to the position close to the wire web. The cutting operation is stated and all the critical parameters are closely monitored. The sawing process initiates from the top of the ingot, continues to the bottom of the ingot which is glued to the glass plate, and is cutting is further continued till up to half of the glass beam is cut. Plurality of wafers thus formed, are held individually by the glue to the glass plate which in turn is glued to the metal mounting plate. The cutting process may take about 4-8 hours and a typical block is about 200-800 mm in size and may comprise of smaller blocks glued to the same glass plate depending on the capability of the wire saw. The silicon wafers -glass beam-metal plate assembly is released from the cutting table and removed from the wire saw device. The above assembly is then cleaned to remove remaining slurry and kerf coated on the surfaces of the wafers and the assembly. Most of the slurry and kerf is removed from the wafer surfaces while held in the glass beam using, e.g., repeated water jet cycles. Finally, the sliced wafers are deglued from the sacrificial glass beam and the metal mounting plate by the process described below. The metal mounting plate with semi-cut glass beam and fully-cut wafers are placed in a suitable fixture and soaked in a hot water bath and/or an acetic acid bath for an extended period of time (typically 1-5 hours) to soften the glue between the cut wafers and the sacrificial glass beam. Ultrasonic agitation may be used in conjunction. When the glue gets softened, the wafers can be easily released from the sacrificial glass beam while they lean on each other to form a stack of wafers, which are carefully removed by the mechanical device or operator.

[14] The stack of the individual wafers is placed in cassettes or placed on belt for further cleaning of the wafer surfaces. During this cleaning process etch solutions containing hot water, detergent, mild caustic solution are used, may be with the presence of ultrasonic / pneumatic agitation and dried. The singulated wafers are stacked and thus competing the wafering operation.

[15] The multiple handing steps and transport of the individual thin wafers increases the potential for higher breakages. Beyond 180 micrometer thickness, the use of expensive wafer handling tools may be required. The cleaned wafers are then packed and marketed or sent for cell processing. Due to yield and capital constraints, majority of commercial wafers (area > 165 sq cm) are limited to 180 micrometers in thickness.

[16] These wafers are then tested and packed according to the wafer quality specification. The packed cells are sold by (wafer suppliers) or sent to cell line in the case of vertically integrated manufactures.

[17] Two different sequences of processing the silicon wafer into solar cell are described. As described in Figure 5, 6 and 7 the p type crystalline silicon wafer (100) (typically 180 micrometers thick and 156 x 156 mm in size) is used as the base substrate. After cleaning and or texturing surfaces (101), n- type emitter (102) is formed on the surfaces by diffusion process (junction depth of about 0.3 micrometers). The thin layer of phosphorus silicate glass formed during the diffusion process on the wafer surfaces is removed. For preventing shorting, the front and back side are isolated by plasma or chemical etching. Alternatively, this step can be preformed by laser scribing at the end of the cell process. An anti reflection (AR) coating (103) Silicon Nitride (SiN, about 75 nm thick and refractive index of about 2.10) is deposited using Plasma enhanced chemical vapor, low pressure chemical vapor deposition or physical vapor deposition tools. A rear back surface field 105 is formed by screen printing and sintering. The front (silver) and rear contacts (silver) (not shown in Figure 6) are screen printed with metallic inks and subsequently sintered to achieve good mechanical and electrical contact. The completed cells are then tested and classified according to the cell parameters. The commercial cell efficiencies of solar cell based on multi and mono crystalline silicon are in the range 14.5-16.5% and 16.0-18.0% respectively. Each of the process steps are described in detail below.

[18] Surface damage removal and texturing:

[19] In this step, the surface damage on the wafers caused during the sawing operation are etched off by placing the wafers, in hot concentrated (10- 30%) sodium hydroxide solution. Approximately 10 micrometers of silicon is removed during the process which takes about 20-90 sec. About 200 wafers are loaded into cassettes and etched in a wet chemistry equipment. Monocrystalline silicon substrates are subsequently textured using a low concentrated etch containing 1-5 % sodium hydroxide or potassium hydroxide and isopropyl alcohol. Tiny pyramids of about 3-5 micrometer are formed on the surfaces of the wafer. This process removes an additional 10 micrometers of silicon. In some cases the saw damage steps are not performed separately, instead saw damage removal is combined with texturing. Other chemicals hydrochloric acid, hydrogen fluoride and specialty chemicals to improve the texturing process are also used. [20] An acid based etching technique, iso-chemical texturing, has been commercialized for saw damage removal and texturing for wafers especially muticrystalline wafers. The process involves use of acid based etch solution (hydrofluoric and nitric acid) maintained at a constant temperature range. Only about 10 micrometers of silicon is removed, resulting in a substantial saving in raw material, Texturing of multicrystalline silicon wafer increases the conversion efficiency of the cell by reducing the reflection and enabling better cell parameters. A special feature of the process is that it can be performed as an in-line process hence enabling the use of thinner silicon substrates. This process can be adapted for etching monocrystalline wafers also.

[21] After saw damage and texturing the next step is emitter formation:

In this step, the semiconductor junction is formed by phosphorus diffusion across the entire front surface. The process is carried out in a tube furnace using POCl₃ as the dopant source at about temperature > 850 °C. The semiconductor junction of the majority of commercial solar cells is about 0.2 to 0.5 micrometers. The sheet resistivity (a measure of lateral resistance in the n type doped layer) of the commercial cells is about 45-65 Ω/square. During this step the wafers are loaded into tubes and processed at precisely controlled high temperature regime. The wafers are individually placed into slots in the quartz carrier (or made of similar high temperature material) and then loaded into the quartz tubes of the furnace. The spacing between the slots in which wafers are placed in the carriers during the high temperature processing is many times the thickness of the wafers. The spacing between slots directly impacts the throughput of the furnace.

[22] Excess phosphorus beyond the solid solubility limit is precipitated as inactive phosphorus in silicon region called "dead layer". In this region the minority carrier life time is significantly reduced or the generated carriers get recombined instantly. The high surface concentration of phosphorus and low sheet resistivity are not optimum conditions for maximizing the generation of carriers. However, wide spread use of this approach is due to the compatibility with high volume manufacturing tools like screen printing metallization practiced in surface mounted assembly industry. There are several approaches are being actively investigated to enhance the performance of solar cells by reducing the dead layer and developing screen printing paste compatible for higher sheet resistivity and lower surface concentration of phosphorus, different type of metallization- spraying, plating etc.

[23] During the diffusion step, the edge and the rear surfaces of the

wafers also gets diffused. Hence to prevent leakage paths, the front and the rear need to be isolated. There are several techniques used to achieve this junction isolation in commercial solar cell manufacturing. One of the widely used techniques is plasma etching by which the edges of coins stacked wafers are etched. Due to the textured surface of the wafer, some active area of the cell in the front surface may also get etched. Another technique involves use of a laser system, where the edges of the wafers (front or rear) are trenched or cleaved at the end of cell process. An alternate method involves etching the rear side in an inline equipment where the entire or part of rear side is etched by an acid etch. After the junction isolation step the phosphorus silicate glass is removed. In this step, the phosphorus glass formed during the diffusion step is removed using dilute hydrofluoric acid etch in a batch or in line equipment.

[24] The next step is deposition of an anti reflection film on the front surfaces. A thin layer of coating is provided to minimize the reflection of the incident light thereby increasing PV effect. By texturing the surface the reflection can be reduced to about 10% in order further

( decrease the reflectance, an anti reflection (AR) coating is applied to the solar cells. By selecting the appropriate film thickness and refractive index (RI) of the AR coating, the reflection can be reduced below 4%. Apart from ability to reduce the refection, AR coating must be transparent; should not absorb the incident sunlight.

[25] The most widely used antireflection coating is silicon nitride film (about 75nm and about 2.10 R.I.), deposited by plasma enhanced chemical vapor deposition technique. In addition to providing the anti reflective properties, the silicon nitride deposition process introduces hydrogen which diffuses into silicon bulk. The hydrogenation improves the electronic quality by surface and bulk silicon by means of passivation.

[26] The next step following the silicon nitride deposition step is to

provide the metallization contacts. Most widely used technique to deposit metal paste is screen printing. In this step, both top and rear contacts are printed and sintered. The top contact is a paste containing silver, organic and glass binders. In the rear, an aluminum paste is printed in all area except where silver paste is applied to make contacts for the external circuit. The aluminum paste after sintering provides a p+ surface (back surface field) and additional gettering of impurities in the bulk silicon. The pastes are applied sequentially with a drying step in between each printing step. The printed wafers are then fired to make contact with the silicon. The front paste fires through the silicon nitride layer and makes contact to the n- type layer. This step determines many of the cell parameters and long term performance of the solar cell. This completes the cell fabrication. The next step is to measure the electrical performance and perform visual inspection. In this last step the solar cell is measured using a sun simulator at standard testing conditions (STC) - (irradiance of 1000W/m2, an air mass 1.5 spectrum (AM 1.5) at 250 °C). STC is selected as it is easy to reproduce in the laboratory. The cell is tested against a calibrated cell. The cells are sorted and binned according to the electrical performance and into various mechanical and visual defects such cosmetics, color non-uniformity, edge chips etc. The finished cells are packed for further processing into modules.

[27] Apart from the commercial sequence described above, a brief

description of an advanced cell processing sequence as described in Figure 6 and the limitations are described, below. The incorporation of a surface passivation layer will enhance the beneficial effects of the higher emitter sheet resistivity cells and thin cells. In addition, the cells (less than 160 micrometers) require a back surface filed which does not bow the cells.

[28] Several versions of this sequence are at various stages of

commercialization. However, cost effectiveness of many of the sequences is yet to be demonstrated as the sequences involve steps with increase capital requirement, increase in number of process step thereby increasing the yield loss and consumable costs. Many of the sequences involve some of high temperature processing steps including masking oxide growth, diffusion, passivating oxide growth, silicon nitride deposition. During these process steps the wafers are loaded into quartz (or similar high temperature material) tubes and processed at precisely controlled high temperature. The wafers are individually placed into slots in the quartz carrier (or similar high temperature material) and then loaded into the quartz tubes of the furnace. The spacing between the wafers while placed in the carriers during these high temperature processing is many times the thickness of the wafers. This is necessary to avoid the contact between wafers during the process step. However this practice limits the throughput capacity of the tube furnaces. [29] Many steps in the solar cell process involve multiple handing of the wafers to be picked and placed into wafer carriers- plastic or quartz, graphite or on to belt. The repeated handling steps during the cell process steps also increase the chances of breakages.

[30] Other publications describe cell processing of 2 mm thick wafers containing many thin slivers (50 micron thick) held to the sides. (K. Weber and A. Blakers, Semiconductor Processing PCT/AU01/01546 (2001), A.W. Blakers, M.J. Stocks, K.J. Weber, V. Everett, J. Babaei, P. Verlinden, M. Kerr, M. Stuckings and P. Mackey, "Sliver Solar Cells", 13th NREL workshop on Crystalline Si Materials and Processing, Vail Colorado, (August 2003), A.W. Blakers, P.N.K. Deenapanray, V.

Everett, E. Franklin, W. Jellett and K.J. Weber, Recent Developments in Sliver Cell Technology, 20th EC PV Solar Energy Conf, Barcelona (April 2005).

SUMMARY

[31] In some embodiments, the disclosed teachings provide a process including selecting a silicon ingot based on the size required for an individual silicon wafer. Then a metal frame is glued to one side (bottom side) of a sacrificial member. The silicon ingot is glued to another side (top side) of the sacrificial member. The resulting product is cured and loaded in a wire saw equipment by connecting the metal frame to the wire saw table. The wire sawing process is started and terminated to obtain a partially cut silicon beam. A silicon beam having a plurality of silicon wafers is obtained. The silicon beam remains having the plurality of silicon wafers remains attached to the sacrificial member.

[32] In some embodiments, the process includes removing the sacrificial member with the attached silicon beam having the plurality of silicon wafers from the wire saw. It is cleaned and treated to separate the sacrificial member from the silicon beam having the plurality of silicon wafers. The silicon beam having the plurality of silicon wafers is cleaned. In some embodiments, the process includes singulating individual silicon wafers from the silicon beam having the plurality of silicon wafers by laser scribing the plurality of silicon wafers near the interface of the silicon beam. Individual silicon wafers are obtained.

[33] In some embodiments, the disclosure provides, a silicon beam

having a plurality of silicon wafers. In some embodiments, the silicon beam having the plurality of silicon wafers is diffused with an opposite polarity. In some embodiments, the silicon beam having the plurality of silicon wafers is diffused with an opposite polarity followed by oxide growth to form the product.

BRIEF DESCRIPTION OF THE DRAWINGS

[34] The above objectives and advantages of the disclosed teachings will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

[35] Fig. 1 provides a front view of the wire saw apparatus including the block to be sliced.

[36] Figure 2 is an enlarged view of the wire web and the block.

[37] Figure 3 is a side view showing the slicing the wafers in

conventional methods.

[38] Figure 4 is flow chart of the ingot slicing process as per

conventional methods.

[39] Figure 5 is flow chart of the cell making process as per conventional methods.

[40] Figure 6 cross section view of a conventional solar cell.

[41] Figure 7 is flow chart of a typical sequence of an advanced solar cell sequence. [42] Figure 8 provides a front view of the conventional wafer loading process in the wafer carrier.

[43] Figure 9 provides a side view of the first embodiment showing the slicing of the wafers.

[44] Figure 10 provides a side view of the wafers attached to the beam at one end based on the first embodiment.

[45] Figure 1 1 provides a side view of the laser cutting of the wafers from the beam.

[46] Figure 12 provides a flow chart of the wafering process as per first embodiment.

[47] Figure 13 provides a flow chart of the cell making process as per the second embodiment.

[48] Figure 14 is the side view of the wafers connected to the beam

loaded into diffusion furnaces of the cell process.

[49] Figure 15 provides a cross section view wafers connected to the beam after oxidation step in a tube furnace as per the second

embodiment.

[50] Figure 16 provides a flow chart of the cell making process as per a variation in the second embodiment.

[51 ] Figure 17 provides a flow chart of the cell making process as per the third embodiment.

[52] Figure 18 provides a flow chart of the cell making process as per the fourth embodiment.

[53] Figure 19 provides a flow chart of the cell making process as per the fifth embodiment.

DETAILED DESCRIPTION

[54] The object of the present invention is to overcome the forgoing limitations and disadvantages of inherent in the conventional wire sawing process for cutting very thin silicon and the processing of the wafers into solar cells. After analyzing various ways of making very thin silicon wafers and the difficulties in processing these wafers, it was found that by making suitable changes to the wire saw and cell process, many of the disadvantages of conventional wire sawing process can be eliminated. Depending on the size of the saw and the wafer size requirement, the ingot or the silicon block is selected. The wafer slicing, cleaning and the device processing can be done on wafer with areas 10 - 500 sq cms. In one embodiment, the invention provides for the manufacturing of ultrathin silicon wafers < 200 micrometer.

[55] A typical block is about 200-800 mm in length and may comprise of smaller blocks glued to the same glass plate depending on the capability of the wire saw. The width of the ingot will be corresponding to the width of the wafers say 156+/-0.5 mm. The height of the block will be a sum of the the desired height of the wafer, for example, 156/-0.5 mm and the width of the beam about 3 +5/-2 mm. Instead of cutting the ingots completely through the silicon ingot and part of the sacrificial glass beam, the cutting is stopped a few mm before reaching the end of the silicon ingot as described in Figure 9 and Figure 12. This process of partially cutting of the silicon ingot results in a beam of silicon with plurality of wafers vertically connected to the silicon beam as described in Figure 10. The silicon beam having the plurality of silicon wafers has dimensions of about 180 micrometer in thickness on 156 x 156 mm wafers. The width of the integrated unit will be 156+/-0.5 mm and the height including the wafers will be 159+5/-3 depending on the capability of the wafer singulation process used. At this stage, if the silicon ingot were completely cut as in conventional processes, the singulated silicon wafers would be about 156 x 156 +/- 0.5 mm.

However, instead of separating individual silicon wafers from a sacrificial glass beam as in conventional processes, here the silicon beam with the plurality of silicon wafers is separated as one integrated unit from the glass beam. Subsequent operations of wafer cleaning are performed to this integrated unit. After processing of the silicon beam having the plurality of silicon wafers, individual silicon wafers are singulated from the integrated unit. Manufacturing of PV modules consists of several value streams, such as, growing crystals from poly silicon, transforming the crystals into individual wafers, converting wafers into solar cells and finally assembling the cells into modules. A company which participates in all the value streams is referred to as vertically integrated PV company. In some cases the vertically integrated company may not have the all facilities in one geographic location. In this case the product of one value stream say wafers will be transported to another facility in a different location. Manufacturers who are non-integrated PV companies who deal in one of the PV value stream e.g. wafering, or have cell processing in another facility can follow the steps described below. The individual wafers after cleaning off the remnants of slurry, are singulated by cutting with a laser with the top edge used for the alignment. The singulated wafers are inspected and packed for shipping. The beam is cleaned and sent to the crystal growth facility for recycling.

[56] In the case of a vertically integrated PV facility, which converts block of silicon into solar cells, the silicon beam with the wafers (referred to as SBW) attached vertically is transported to the cell manufacturing facility. SBW undergoes the steps of saw damage removal, texturing, emitter diffusion, diffusion oxide etch, oxide passivation (in the case of advanced sequence). The SBW is then placed in a laser cutting unit to separate the individual wafers from the beam. The cell process is continued as per standard process - silicon nitride deposition by plasma enhanced chemical vapor deposition followed by metallization and sintering. This novel procedure decreases the handing of individual wafers hence increase the yield. By avoiding the wafer carrier and cassettes, the wafers are densely packed resulting in increased throughput by nearly a factor of 4. The invention applicable to the advanced sequences, e.g. high efficiency sequence step oxide passivation, masking oxide formation can be done without multiple units of the tube furnaces. In the case of monocrystalline substrate, the PECVD SiN can be substituted by low pressure chemical vapor deposited SiN so that the SiN deposition step could be done prior to singulation.

[57] In some embodiments, the disclosed teachings provide a process including selecting a silicon ingot based on the size required for an individual silicon wafer. Then a metal frame is glued to one side (bottom side) of a sacrificial member. The silicon ingot is glued to another side (top side) of the sacrificial member. The resulting product is cured and loaded in a wire saw equipment by connecting the metal frame to the wire saw table. The wire sawing process is started and terminated to obtain a partially cut silicon beam. A silicon beam having a plurality of silicon wafers is obtained. The silicon beam remains having the plurality of silicon wafers remains attached to the sacrificial member.

[58] In some embodiments, a process of making a silicon beam having a plurality of silicon wafers includes removing the sacrificial member with the attached silicon beam having the plurality of silicon wafers from the wire saw. It is cleaned and treated to separate the sacrificial member from the silicon beam having the plurality of silicon wafers. The silicon beam having the plurality of silicon wafers is cleaned. In some embodiments, the process includes singulating individual silicon wafers from the silicon beam having the plurality of silicon wafers by laser scribing the plurality of silicon wafers near the interface of the silicon beam. Individual silicon wafers are obtained. In the process, the silicon beam is partially cut through the silicon layer to obtain the plurality of silicon wafers that are attached at one end. The product obtained is also referred to as silicon beam with wafers (SBW). The sacrificial member can be a glass plate or epoxy beam.

[59] In some embodiments, the process of preparing the silicon wafer includes terminating the wafering process before full slicing, and singulating the SBW into wafers, as provided in Figure 11. In some embodiments, the SBW undergo further processing. In some embodiments, further steps in the processing of the SBW include removing the sacrificial member with the attached silicon beam having the plurality of silicon wafers from the wire saw and cleaning it. The sacrificial member with the attached silicon beam having the plurality of silicon wafers is treated to separate the sacrificial member, such as the glass plate, from the silicon beam having the plurality of silicon wafers. The separated silicon beam having the plurality of silicon wafers is cleaned.

[60] In some embodiments, the process of preparing individual silicon wafers includes saw damage and texturing the separated and cleaned silicon beam having the plurality of silicon wafers, doping the resulting product with opposite polarity, etching, and, singulating individual silicon wafers from the silicon beam having the plurality of silicon wafers by laser cutting. In some embodiments, the process further includes depositing SiN on the front surface of the individual silicon wafers by Plasma enhanced Chemical vapor deposition method, metalizing and sintering the resulting product, edge isolation by laser scribing, and, testing the product.

[61] In some embodiments, the process of preparing individual silicon wafers includes saw damage and texturing the silicon beam having the plurality of silicon wafers. Next, the silicon beam with wafers is doped with opposite polarity, followed by etching, and growing silicon dioxide on the surface of the plurality of silicon wafers by loading the silicon beam with wafers into a tube furnace in an ambient oxygen containing atmosphere. This is followed by singulating individual silicon wafers from the SBW by laser cutting. In some embodiments, the process of preparing individual silicon wafers further includes depositing SiN on the front surface of silicon wafers after singulation, by plasma enhanced chemical vapor deposition method, metalizing and sintering, edge isolation by Laser scribing, and, testing the resultant silicon wafers.

[62] In some embodiments, the process of preparing silicon wafers

includes, saw damage removal and texturing the silicon beam having the plurality of silicon wafers, which is attached to the sacrificial member, doping with opposite polarity, etching, growing silicon dioxide on the surface of the plurality of silicon wafers by loading into a tube furnace in an ambient oxygen containing atmosphere, depositing antireflection coating (AR) Silicon Nitride (SiN) coating on the front and rear surfaces of the plurality of silicon wafers present on the silicon beam having the plurality of silicon wafers by low pressure chemical vapor deposition technique, singulating individual silicon wafers by laser cutting, and, opening windows in the SiN layer in the front surface by masking and etching/ laser ablation and cleaning. This process is more suitable for monocrystalline silicon. In some embodiments, the process further includes heavily diffusing open areas on the front surface with phosphorous dopant, opening windows in the rear surface by etching SiN in localized areas, metalizing the front and the rear surfaces, edge isolation by laser scribing, and, testing the individual silicon wafers.

[63] In some embodiments, the processing of SBW includes singulating individual silicon wafers from the silicon beam having the plurality of silicon wafers, which is attached to the sacrificial member by laser scribing the plurality of silicon wafers near the interface of the silicon beam. In some embodiments, the process further includes inspecting and packing of the individual silicon wafers.

[64] Other methods of junction isolation include laser isolation by

scribing after metallization and firing step and, plasma etching. Other methods of depositing anti-reflection coating include atmospheric pressure chemical vapor deposition, physical vapor deposition, and solgel deposition. Other methods of singulating the individual silicon wafers include water (or other liquid) jet with or without laser, mechanical cutting by dicing saw or wires.

[65] For preparation of the silicon beam with wafers, as seen in Figures 1 and 2, the slicing of the ingot requires a block of silicon or other material (10) to be sliced. The silicon ingot is mounted to a glass beam (1 1) and metal plate (12) is fixed to a support table (15). The support table can be moved perpendicular to the web to press the block against the web of metal wire. The web of wire (13) is formed by wire wound on the grooved outer surface of the rotating wire guides (14) with their axis parallel to each other. The distance between the adjacent wires is determined by the pitch of the grooves on the wire guides and hence the thickness of the wafers. The wires are made of high tensile strength materials with diameters on the order of 0.1 to 0.2 millimeters. The actual cutting of the block is done by free abrasive slurry made up of silicon carbide and oil or poly ethylene glycol wire web. The slurry is spayed on the wires and the block. Very high wire speed is essential to maintain a uniform coating of the slurry on the wire web which results in significant forces applied on the wafers being cut.

[66] In some embodiments, as shown in Fig 9, 10, 1 1 and 12, instead of cutting the ingots completely through the silicon ingot and part of the sacrificial glass beam, the cutting is stopped a few mm before the end of the ingot (see for example, Figure 9). This result in a beam of silicon with plurality of wafers vertically connected to the beam (Figure 10). Instead of separating individual wafers from the sacrificial glass beam, the silicon beam with wafers (SBW) is separated as one integrated unit from the glass beam. Subsequent operations of wafer cleaning are performed to this integrated unit. Manufacturers who are non- integrated PV company who deal in one of the PV value stream e.g. wafering, or have cell processing in another facility will follow the steps described below. The individual wafers after cleaning off the remnants of slurry, are singulated by cutting with a laser with the top edge used for the alignment (as described, for example, in Figure 1 1). The singulated wafers are inspected and packed for shipping. The beam is cleaned and sent to the crystal growth facility for recycling.

[67] In the some embodiments, instead of the free abrasives, fixed

abrasive can be substituted by the fixed abrasive diamond coated wire. In addition, the gluing of the bean and silicon block can be substituted by high powered vacuum chuck.

[68] In some embodiments, a silicon beam having a plurality of silicon wafers is provided. In some embodiments, the silicon beam having the plurality of silicon wafers is diffused with an opposite polarity. In some embodiments, the silicon beam having a plurality of silicon wafers is diffused with an opposite polarity followed by growth of oxide to form a product. In some embodiments, the silicon beam having a plurality of silicon wafers is diffused with an opposite polarity followed by silicon nitride deposition to form a product. In some embodiments, the silicon beam having a plurality of silicon wafers diffused with the opposite polarity, followed by oxide growth, is followed by silicon nitride deposition to form the product. In some embodiments, the silicon beam having a plurality of silicon wafers diffused with opposite polarity and having silicon nitride deposited over the product, after singulation of individual wafers includes silicon layers exposed in localized areas of the singulated wafers. In some embodiments, the silicon beam having a plurality of silicon wafers diffused with opposite polarity and having oxide grown over it, and having silicon nitride deposited over the product, after singulation has silicon layers exposed in localized areas of the singulated wafers. In one embodiment the silicon beam having a plurality of silicon wafers has oxide grown on it.

[69] Some embodiments provide a solar cell process which includes processing the silicon beam having plurality of wafers and completing the cell process after singulation. In one embodiment, some of the process steps for preparing the silicon wafers into solar cells occurs while the wafers are still in the beam (on the SBW) and edge isolatior step is carried out by laser while the silicon wafers are still in the bear An example process is described in Figure 13. After cleaning of the silicon beam with the wafers (SBW) step, the SBW is placed loaded i to the saw damage and texturing equipment. As the spacing between wafers are less that 250 micron instead of several mm in case of the present practice, the throughput of the machine increases by factor of 10. The loading and lifting arm of the equipment is suitably modified handle the silicon beam with wafers. Next, the entire beam with wafei is loaded into the diffusion furnace as shown in Figures 13 and 14. P the quartz boat is eliminated the packing factor increases by a factor c 5-10 when compared to the present practice. This process results in substantial saving in space, capital and consumable cost. After the diffusion step the beam with the wafers are etched in chemical etch station to remove the phosphorus silicate glass formed during the diffusion. The throughput of this wet etching equipment also is increased due to increased packing factor. Next using a laser, along tl three free edges of the wafer are scribed within one mm from the edg< of the top surface of the wafer and then using the laser the wafer is singulated from the beam by cutting at close to the interface of the wafer and the beam. During the laser step, the block can preferably be held at an angle or other means so that the wafer after laser singulation will slide down and form a stack. The remaining cell process steps - silicon nitride deposition, metallization (screen print or other methods) and testing are done on individual wafers as per the standard procedure. One embodiment of the process the junction isolation step is formed by rear etching and is shown in Figure 16.

[70] In one embodiment, the beam with wafers is processed into solar cells. The cell process is described in Figure 17. After cleaning of the silicon beam with the wafers (SBW) step, the SBW is placed loaded in to the saw damage and texturing equipment. As the spacing between wafers are less that 250 micron instead of several mm in case of the present practice, the throughput of the machine increases by factor of 5- 10. The loading and lifting arm of the equipment is suitably modified to handle the silicon beam with wafers. Next, the entire beam with wafers is loaded into the diffusion furnace as shown, for example, in Figures 14 and 17. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process will result in substantial saving in space, capital and consumable cost. After the diffusion step the beam with the wafers are etched in chemical etch station to remove the phosphorus silicate glass formed during the diffusion. The throughput of this equipment also is increased due to increased packing factor. The block with wafers is then loaded into the tube furnace. At temperature 750 to 1 100 °C and a gas stream of oxygen, nitrogen, argon and steam or a combination of above a thin oxide is grown 4 to 20 nanometers thick. As shown in Figure 15, an oxide layer (101) is formed on the wafer (22) connected to the beam. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process results in substantial saving in space, capital and consumable cost. Next using a laser, along the three free edges of the wafer are scribed within one mm from the edge of the top surface of the wafer and then using the laser the wafer is singulated from the beam by cutting at close to the interface of the wafer and the beam. During the laser step, the block will be held at an angle or other means so that the wafer after laser singulation will slide down and form a stack. The remaining cell process steps - silicon nitride deposition, metallization (screen print or other methods) and testing are done on individual wafers as per the standard procedure. In some embodiments, the process involves substituting the junction isolation prior to singulation by rear etching in chemical bath or laser at the end of the cell process.

[71] In some embodiments, the beam with wafers is processed into solar cells. An embodiment of the process is described in Figure 18. After cleaning of the silicon beam with the wafers (SBW) step, the SBW is placed loaded in to the saw damage and texturing equipment. As the spacing between wafers are less that 250 micron instead of several mm as in conventional methods, the throughput of the machine increases by factor of 5-10. The loading and lifting arm of the equipment is suitably modified to handle the silicon beam with wafers. Next, the entire beam with wafers is loaded into the diffusion furnace as shown in Figures 14. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process results in substantial saving in space, capital and consumable cost. After the diffusion step the beam with the wafers are etched in chemical etch station to remove the phosphorus silicate glass formed during the diffusion. The throughput of this wet etching equipment also is increased due to increased packing factor. The block with wafers is then loaded into the tube furnace. At temperature 750 to 1 100 ⁰ C and a gas stream of oxygen, nitrogen, argon and steam or a combination of above a thin oxide is grown 4 to 20 nanometers thick. As shown in Figure 15, an oxide layer (101) is formed on the wafer (22) connected to the beam. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process results in substantial saving in space, capital and consumable cost. Next the silicon beam with the wafers is loaded in a low pressure chemical vapor deposition (LPCVD) system. During this step a SiN coating is formed on both the surfaces of the wafers and on beam. Next using a laser, SiN layer, oxide are removed in localized areas from the front surface and then using the laser the wafer is singulated from the beam by cutting at close to the interface of the wafer and the beam. During the laser step, the block will be held at an angle or other means so that the wafer after laser singulation will slide down and form a stack. The singulated wafers obtained from the last step are cleaned. In the next step the exposed areas of the front surface of individual wafers are diffused heavily with phosphorus dopant. Next the SiN coating is removed in localized areas in the rear surface by masking/etching or laser ablation. The wafers are then etched to remove the phosphorus silicate glass formed on the front surface during diffusion and clean laser damage or any remnants and contamination during the masking/ etching . Metallization of the front and rear can be done by screen printing, plating or other techniques alone or a combination. The front metal paste will contact the silicon in the heavy diffused areas and rest of the areas will form a mechanical contact with the SiN and form the electrical contact with the metallization which is above the heavily diffused region. The cells are then scribed by laser for edge junction isolation. A variation of the embodiment can involve substituting the junction isolation prior to singulation by rear etching in chemical bath or laser at the end of the cell process. Next the cells are tested. This completes the cell processing. [72] In one embodiment, the beam with wafers is processed into solar cells. The cell process is described in Figure 19. After cleaning of the silicon beam with the wafers (SBW) step, the SBW is placed loaded in to the saw damage and texturing equipment. As the spacing between wafers are less that 250 micron instead of several mm in case of the present practice, the throughput of the machine increases by factor of 5- 10. The loading and lifting arm of the equipment is suitably modified to handle the silicon beam with wafers. Next, the entire beam with wafers is loaded into the diffusion furnace as shown, for example, in Figures 14 and 19. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process will result in substantial saving in space, capital and consumable cost. After the diffusion step the beam with the wafers are etched in chemical etch station to remove the phosphorus silicate glass formed during the diffusion. In addition during this step the surface of the diffused layer is etched very carefully to remove the outer layers of the diffused area called "dead layer" to improve the performance of the solar cells. The dead layer is a region of high recombination where the generated carriers combine without being collected. The etchant could contain nitric acid, hydrofluoric acid, De ionized water, other buffering agents. The throughput of this equipment also is increased due to increased packing factor. The block with wafers is then loaded into the tube furnace. At temperature 750 to 1 100 °C and a gas stream of oxygen, nitrogen, argon and steam or a combination of above a thin oxide is grown 4 to 20 nanometers thick. As shown in Figure 15, an oxide layer (101) is formed on the wafer (22) connected to the beam. As the quartz boat is eliminated the packing factor increases by a factor of 5-10 when compared to the present practice. This process results in substantial saving in space, capital and consumable cost. Next, using a laser the wafers are singulated from the beam by cutting at close to the interface of the wafer and the beam. During the laser step, the block will be held at an angle or other means so that the wafer after laser singulation will slide down and form a stack. Next phosphorus dopant is deposited on to specific areas (defined where the front metal contact will be later placed). The deposition method could be screen printed, ink jet, spray or can be laser assisted doping and diffusion. The individual wafers are then dried and then loaded in to tube furnace or in line horizontal furnaces (where wafers move on a belt or rollers) to form a heavily phosphorus diffused region in the specific areas (where the dopant was deposited). The wafers are then etched to remove the phosphorus silicate glass and the rear junction. The remaining cell process steps - silicon nitride deposition, metallization (screen print or other methods) and testing are done on individual wafers as per the procedure described in Figure 19. In some embodiments, the process involves substituting the rear etching in chemical bath by laser at the end of the cell process.

[73] It will be readily understood by the skilled artisan that numerous alterations may be made to the examples and instructions given herein. These and other objects and features of present invention will be made apparent from the following examples. The following examples as described are not intended to be construed as limiting the scope of the present invention.

[74] Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure and teachings. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.

Claims

WHAT IS CLAIMED IS

1. A process comprising:

(a) selecting a silicon ingot based on the size required for an

individual silicon wafer;

(b) gluing one side (side A) of a sacrificial member to a metal frame;

(c) gluing the silicon ingot from step (a), to another side (side B) of the sacrificial member of step (b);

(d) curing the product of step (c);

(e) loading the product of step (d) in a wire saw equipment,

wherein the metal frame of step (b) connects to wire saw table;

(f) starting the wire sawing process on the product of step (e), and, terminating the wire sawing process when the silicon beam having the plurality of silicon wafers is obtained, whereby the silicon beam having the plurality of silicon wafers remains attached to the sacrificial member of step (c).

2. The process of claim 1 , further comprising:

(g) removing the product of step (f) from the wire saw;

(h) cleaning the product of step (g);

(i) treating the product of step (h) to separate the sacrificial

member from the silicon beam having the plurality of silicon wafers; and,

(j) cleaning the product of step (i).

3. The process of claim 2, further comprising:

(k) singulating individual silicon wafers from the product of step (j) by laser scribing the plurality of silicon wafers near the interface of the silicon beam, whereby individual silicon wafers are obtained.

4. The process of claim 3, further comprising:

(1) inspecting and packing of the product of step (k).

5. A silicon beam having a plurality of silicon wafers prepared by the process of claim 1.

6. The silicon beam having the plurality of silicon wafers of claim 5, wherein the silicon beam having the plurality of silicon wafers is diffused with an opposite polarity to form a product (a).

7. The silicon beam having the plurality of silicon wafers of claim 6, further comprising oxide grown over the product (a) to form product (b).

8. The silicon beam having the plurality of silicon wafers of claim 6, further comprising Silicon nitride deposited over product (a) to form a product (d).

9. The silicon beam having the plurality of silicon wafers of claim 7, further comprising Silicon nitride deposited over product (b) to form a product.

10. A silicon beam having the plurality of silicon wafers of claim 5, further comprising oxide grown over the silicon beam having the plurality of silicon wafers.

1 1. A silicon beam having a plurality of silicon wafers.

12. The process of claim 2 further comprising:

(1) saw damage and texturing the product of step (j); (2) doping the product of step (1) with opposite polarity;

(3) etching the product of (2); and,

(4) singulating individual silicon wafers from the product of step (3) by laser cutting, whereby individual silicon wafers are obtained.

13. The process of claim 12 further comprising:

(5) depositing SiN on the front surface of the product of step (4) by Plasma enhanced Chemical vapor deposition method;

(6) metalizing and sintering the product of step (5);

(7) edge isolation of the product of step (5) by Laser scribing; and,

(8) testing the product of step (7).

14. The process of claim 2, further comprising:

(1) saw damage and texturing the product of step (j);

(2) doping the product of step (1) with opposite polarity;

(3) etching the product of step (2);

(4) growing silicon dioxide on the surface of the plurality of silicon wafers by loading the product of step (3) into a tube furnace in an ambient oxygen containing atmosphere;

(5) singulating individual silicon wafers from the product of step (4) by laser cutting, whereby individual silicon wafers are obtained.

15. The process of claim 14, further comprising:

(6) depositing SiN on the front surface of the product of step (5) by Plasma enhanced Chemical vapor deposition method;

(7) metalizing and sintering the product of step (6);

(8) edge isolation of the product of step (7) by Laser scribing; and,

(9) testing the product of step (8).

16. The process of claim 2, further comprising:

(1) saw damage removal and texturing the product of step (j); (2) doping the product of step (1) with opposite polarity;

(3) etching the product of step (2);

(5) depositing antireflection coating (AR) Silicon Nitride (SiN) coating on the front and rear surfaces of the plurality of silicon wafers present on the silicon beam having the plurality of silicon wafers by Low pressure Chemical vapor deposition technique;

(6) singulating individual silicon wafers from the product of step (5) by laser cutting; and,

(7) opening windows in the SiN layer in the front surface of the product of step (6) by masking and etching/ laser ablation and cleaning.

17. The process of claim 16, further comprising:

(8) heavily diffusing open areas on the front surface of the product of step (7) with phosphorous dopant;

(9) opening windows in the rear surface of the product of step (8) by etching SiN in localized areas;

(10) metal izing the front and the rear surfaces of the product of step (9);

(11) edge isolation of the product of step (10) by Laser scribing; and,

(12) testing the product of step (1 1).

18. The process of claim 1, wherein the sacrificial member is selected from the group consisting of glass.

19. A silicon beam having the plurality of silicon wafers of claim 6, further comprising of a diffused layer devoid of a dead layer by etching the product (a) to form product (X).

20. A silicon beam having the plurality of silicon wafers of claim 19, further comprising oxide grown over the product (X) to form product (XI).

21. The process of claim 2, further comprising:

(1) saw damage and texturing the product of step (j);

(2) doping the product of step (1) with opposite polarity;

(3) etching the product of step (2) and removing the outer diffused layer (dead layer);

(4) growing silicon dioxide on the surface of the plurality of silicon wafers by loading the product of step (3) into a tube furnace in an ambient oxygen containing atmosphere; and,

22. The process of claim 21, further comprising:

(6) depositing phosphorus dopant and diffusing on specific areas (where front contact metallization will be deposited subsequently) of the front surface of the product of step (5);

(7) etching the product of step (6);

(8) depositing SiN on the front surface of the product of step (7) by Plasma enhanced Chemical vapor deposition method;

(9) metalizing and sintering the product of step (8);

(10) edge isolation of the product of step (9) by Laser scribing; and,

(1 1) testing the product of step (10).