WO2011081309A3 - Resistance change memory device, and manufacturing method and driving method for same - Google Patents
Resistance change memory device, and manufacturing method and driving method for same Download PDFInfo
- Publication number
- WO2011081309A3 WO2011081309A3 PCT/KR2010/008634 KR2010008634W WO2011081309A3 WO 2011081309 A3 WO2011081309 A3 WO 2011081309A3 KR 2010008634 W KR2010008634 W KR 2010008634W WO 2011081309 A3 WO2011081309 A3 WO 2011081309A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory device
- wirings
- manufacturing
- conductive patterns
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/10—Phase change RAM [PCRAM, PRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
Abstract
The present relates to a variable resistance memory device, and to a manufacturing method and driving method for same. A variable resistance memory device according to embodiments of the present invention comprises: a plurality of first wirings arranged in one direction; a plurality of conductive patterns formed on the first wirings; a variable resistance layer formed on the conductive patterns; a plurality of second wirings arranged in a direction intersecting the first wirings so as to pass through a portion of the conductive patterns; and a plurality of third wirings arranged in a direction intersecting the first wirings so as to pass through a remaining portion of the conductive patterns. According to embodiments of the present invention, a fine pattern of 1F or less, preferably 0.1F, is formed using double patterning and a sidewall spacer, and multiple-bit data can be stored in an area of 4F2 using the fine pattern.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2009-0134088 | 2009-12-30 | ||
| KR1020090134088A KR101041742B1 (en) | 2009-12-30 | 2009-12-30 | Resistance change memory device, manufacturing method and driving method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2011081309A2 WO2011081309A2 (en) | 2011-07-07 |
| WO2011081309A3 true WO2011081309A3 (en) | 2011-09-22 |
Family
ID=44226944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2010/008634 Ceased WO2011081309A2 (en) | 2009-12-30 | 2010-12-03 | Resistance change memory device, and manufacturing method and driving method for same |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR101041742B1 (en) |
| WO (1) | WO2011081309A2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8295335B2 (en) | 2009-12-31 | 2012-10-23 | Intel Corporation | Techniques to control uplink power |
| KR101257365B1 (en) | 2011-07-22 | 2013-04-23 | 에스케이하이닉스 주식회사 | Resistive RAM of having threshold switching operation and Method of fabricating the same |
| KR101929246B1 (en) * | 2012-09-14 | 2018-12-14 | 삼성전자주식회사 | Variable Resistance memory device and method of forming the same |
| KR102079599B1 (en) * | 2013-11-29 | 2020-02-21 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
| KR102155783B1 (en) * | 2014-01-17 | 2020-09-15 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
| KR102087744B1 (en) | 2014-03-17 | 2020-03-11 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000023395A (en) * | 1998-09-24 | 2000-04-25 | 칼 하인쯔 호르닝어 | Memory cell arrangement and method for the production thereof |
| KR20030082240A (en) * | 2002-04-17 | 2003-10-22 | 삼성전자주식회사 | Phase changeable memory cells and methods of fabricating the same |
| KR20040107487A (en) * | 2002-04-04 | 2004-12-20 | 가부시끼가이샤 도시바 | Phase-change memory device |
| JP2005101535A (en) * | 2003-08-27 | 2005-04-14 | Nec Corp | Semiconductor device |
| KR20070062435A (en) * | 2005-12-12 | 2007-06-15 | 히다치 글로벌 스토리지 테크놀로지스 네덜란드 비.브이. | Unipolar resistive ram unit and vertical stack structure |
| KR100734317B1 (en) * | 2006-05-16 | 2007-07-02 | 삼성전자주식회사 | Non-volatile memory device for 2-bit operation and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4973876B2 (en) * | 2007-08-22 | 2012-07-11 | 信越化学工業株式会社 | Pattern forming method and pattern surface coating material used therefor |
| JP5236983B2 (en) * | 2007-09-28 | 2013-07-17 | 東京エレクトロン株式会社 | Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, control program, and program storage medium |
-
2009
- 2009-12-30 KR KR1020090134088A patent/KR101041742B1/en active Active
-
2010
- 2010-12-03 WO PCT/KR2010/008634 patent/WO2011081309A2/en not_active Ceased
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000023395A (en) * | 1998-09-24 | 2000-04-25 | 칼 하인쯔 호르닝어 | Memory cell arrangement and method for the production thereof |
| KR20040107487A (en) * | 2002-04-04 | 2004-12-20 | 가부시끼가이샤 도시바 | Phase-change memory device |
| KR20030082240A (en) * | 2002-04-17 | 2003-10-22 | 삼성전자주식회사 | Phase changeable memory cells and methods of fabricating the same |
| JP2005101535A (en) * | 2003-08-27 | 2005-04-14 | Nec Corp | Semiconductor device |
| KR20070062435A (en) * | 2005-12-12 | 2007-06-15 | 히다치 글로벌 스토리지 테크놀로지스 네덜란드 비.브이. | Unipolar resistive ram unit and vertical stack structure |
| KR100734317B1 (en) * | 2006-05-16 | 2007-07-02 | 삼성전자주식회사 | Non-volatile memory device for 2-bit operation and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101041742B1 (en) | 2011-06-16 |
| WO2011081309A2 (en) | 2011-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2011081309A3 (en) | Resistance change memory device, and manufacturing method and driving method for same | |
| TW200729462A (en) | Phase-change random access memory device and method of operating the same | |
| WO2010111153A3 (en) | Display device with openings between sub-pixels and method of making same | |
| WO2009075073A1 (en) | Nonvolatile memory device and fabrication method therefor | |
| WO2006127586A3 (en) | Methods for forming arrays of small, closely spaced features | |
| WO2008105155A1 (en) | Nonvolatile memory device and method for writing data in nonvolatile memory device | |
| EP2048713A3 (en) | Multi-layer electrode, cross point memory array and method of manufacturing the same | |
| WO2008019349A3 (en) | Thin film solar cell with finger pattern | |
| JP2008172236A5 (en) | ||
| WO2011056529A3 (en) | Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning | |
| WO2009085775A3 (en) | Touch pad electrode design | |
| WO2007120697A3 (en) | Methods and apparatus for integrated circuit having multiple dies with at least one on chip capacitor | |
| WO2007127496A8 (en) | Topography directed patterning | |
| WO2011108869A3 (en) | Capacitive touch panel and manufacturing method for same | |
| WO2012169850A3 (en) | 3-dimensional non-volatile memory device and method of manufacturing same | |
| TW200721253A (en) | Method of forming pitch multipled contacts | |
| ATE463784T1 (en) | SINGLE-LAYER TOUCH-SENSITIVE DISPLAY DEVICE | |
| EP1710804A3 (en) | Line layout structure, semiconductor memory device, and layout method | |
| DE602007008762D1 (en) | DOUBLE ORIENTATION CIRCUITS COMPREHENSIVE RUNNING ROOF | |
| WO2007135076A3 (en) | Patterning nanowires on surfaces for fabricating nanoscale electronic devices | |
| TW200733156A (en) | Three-dimensional capacitor structure | |
| TW200705616A (en) | Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same | |
| WO2012177955A3 (en) | Capcitive sensor pattern | |
| WO2011159080A3 (en) | Capacitive touch sensor | |
| JP2010123963A (en) | Semiconductor device and layout method for the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10841141 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 10841141 Country of ref document: EP Kind code of ref document: A2 |