WO2010093238A1

WO2010093238A1 - Method and system for removal of a surface layer of a silicon solar cell substrate

Info

Publication number: WO2010093238A1
Application number: PCT/NL2010/050061
Authority: WO
Inventors: Gerard Paul Wyers; Martien Koppes; Arno Ferdinand Stassen
Original assignee: Stichting Energieonderzoek Centrum Nederland
Priority date: 2009-02-10
Filing date: 2010-02-10
Publication date: 2010-08-19
Also published as: NL2002512C2

Abstract

A method of manufacturing a solar cell from a silicon wafer includes -formation of a dopant containing silicon layer, based on doping with dopant from a diffusion source, on at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to a dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of an ineffective conductive silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant, -back-etching of the dopant containing silicon layer by a back-etch etchant, the back- etch etchant having a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the dopant containing silicon layer into an oxide top layer by the first component and a dissolution reaction to remove the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back-etch process.

Description

Method and system for removal of a surface layer of a silicon solar cell substrate

Field of the invention

The present invention relates to a method and system for manufacturing a solar cell from a silicon wafer.

Background

During fabrication of a solar cell based on silicon wafer or substrate, an emitter layer is formed on a surface of the silicon wafer. Typical emitter forming processes on p-type silicon involve a diffusion process of a dopant during thermal treatment. During annealing the silicon is in contact with the dopant that for example contains phosphor as donor element. Typically, for p-type silicon phosphor is used as dopant and diffused into the silicon wafer from a phosphor containing glassy or dopant layer such as a phospho silicate layer. Alternative dopants for p-type silicon are arsenic and antimony. For n-type silicon the dopant is typically boron as acceptor element. To diffuse the dopant atoms into silicon, a surface of the silicon substrate that requires to be doped below that surface, is covered by the phosphor containing glassy layer. Such a phosphor containing glassy layer can be deposited by use of various techniques such as vapor deposition, wet chemical and sputtering.

Next, during thermal treatment, phosphor from the phosphor containing glassy layer, can diffuse into the silicon substrate into the surface of the silicon wafer to form a phosphor doped silicon layer with a phosphor concentration profile.

After diffusing-in phosphor, the glassy layer is removed, typically by a wet etching process or a plasma-assisted etching process. It is known that in practice removal of the glassy layer is not complete. A portion of the phosphor doped silicon layer has a suitable concentration of phosphor that allows to form an n-type doped silicon layer which will become the emitter of the solar cell. Adversely, at the surface of the silicon wafer the phosphor doped silicon layer can have a ineffective (or at least less effective) zone with a relatively high (excessive) concentration of phosphor. As a result of the high concentration, the phosphor atoms may be in substitutional and interstitial positions in the silicon lattice. The presence of an ineffective zone typically concurs with a reduced efficiency of the solar cell, which is explained by the fact that the interstitial dopant elements are not electrically active as n-type donor or p-type acceptor and cause an undesirable recombination of charge carriers within the emitter layer.

Summary of the invention

It is an object of the present invention to provide a method that overcomes at least one of the drawbacks from the prior art.

The object is achieved by a method of manufacturing a solar cell from a silicon wafer comprising :

- providing a diffusion source comprising a dopant containing substance;

- formation of a dopant containing silicon layer, based on doping from the diffusion source, on at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to the dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of an ineffective conductive silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant,

- back-etching of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer by a back-etch etchant, the back-etch etchant comprising a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer into an oxide top layer by the first component and a dissolution reaction to remove the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back- etch process.

Advantageously, the method provides an etching process in which the back-etching of the ineffective conductive silicon layer can be done in a controlled manner, due to rate-limitation of the back-etch process by the dissolution reaction. The improved control of the back-etching process allows controlling the removal rate and the removed layer thickness with increased precision.

Moreover, a manufacturing method as described above allows to implement the stages of the method as an in-line process along a track to be followed by the silicon wafer. Furthermore, a manufacturing method as described above allows to implement the stages of the method as batch type process in which the wafer is transported along a consecutive stations.

The present invention provides a system of manufacturing a solar cell from a silicon wafer comprising a production track provided with :

- a diffusion furnace, the diffusion furnace being arranged for providing a diffusion source comprising a dopant containing substance and forming a dopant containing silicon layer, based on doping from the diffusion source, on at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to the dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of a less effective conductive silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant;

- a back-etch etching reactor disposed in the production track after the etching station, being arranged for back-etching of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer by a back-etch etchant, the back- etch etchant comprising a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer into an oxide top layer by the first component and a dissolution reaction to dissolve the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back-etching process.

Advantageously, an in-line process allows a reduction of handling events during the manufacturing of the solar cell. Next to that, the process as described above can also be applied in a batch process.

Further embodiments are defined by the dependent claims as appended.

Brief description of drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

Figure 1 shows a system for manufacturing a solar cell in accordance with an embodiment of the present invention;

Figure 2 shows a silicon wafer in a first stage of the manufacturing; Figure 3 shows a silicon wafer in a second stage of the manufacturing; Figure 4 shows a silicon wafer in a third stage of the manufacturing; Figure 5 shows a silicon wafer in a fifth stage of the manufacturing; Figure 6 shows a flow diagram of a method of manufacturing a solar cell in accordance with an embodiment of the present invention;

Figure 7 shows an alternative system for manufacturing a solar cell in accordance with an embodiment of the present invention;

Figure 8 shows an alternative system for manufacturing a solar cell in accordance with an embodiment of the present invention; and Figure 9 shows an alternative system for manufacturing a solar cell in accordance with an embodiment of the present invention;

Description of embodiments

Figure 1 shows a system 1 for manufacturing a solar cell from a silicon wafer. The system 1 comprises an in-line diffusion furnace 2, a first etch bath 3, a second etch bath 4, and a wafer transport mechanism 5.

The in-line diffusion furnace 2, the first etch bath 3, the second etch bath 4 are arranged along the path of the wafer transport mechanism.

The in-line diffusion furnace 2 is positioned at a first position, the first etch bath 3 is positioned at second position and the second etch bath 4 is positioned at third position along the path of the wafer transport mechanism.

A silicon wafer W on the path of the wafer transport mechanism 5 first enters the in-line diffusion furnace 2. A cross-sectional view of a fresh silicon wafer W (i.e., bare possibly after a cleaning step) is shown in Figure 2.

In the in-line diffusion furnace 2 the silicon wafer is annealed and simultaneously exposed on at least one surface to a phosphor containing dopant to grow a phosphor containing dopant layer on the at least one surface, such a dopant layer may be a glassy layer such as a phosphor-silicate layer. Due to the thermal treatment phosphor diffuses from the phosphor containing dopant layer into the silicon wafer. As a result a phosphor containing silicon layer is formed at the interface of the phosphor containing dopant layer and the exposed surface of the silicon wafer W.

Due to the diffusion kinetics, the phosphor containing silicon layer will show a concentration profile of phosphor that will show a relatively high concentration of phosphor at the surface contacting the phosphor containing dopant layer that gradually decreases as a function of depth from the exposed surface.

A cross-sectional view of the silicon wafer W after the diffusion process will be described below in more detail with reference to Figure 3. Typically, the phosphor concentration in the phosphor containing silicon layer shows a gradient in which the concentration of phosphor at the surface of the wafer is relatively high in comparison to the concentration of phosphor at some depth below the surface of the wafer. The concentration at the surface may be so high that an electrically less efficient zone is present at the surface of the wafer. In this zone phosphor atoms may be in substitutional and interstitial positions in the silicon lattice. Below that less efficient zone, in a region where the concentration of phosphor is relatively reduced in comparison to the concentration of phosphor in the less efficient zone, an n-type doped silicon layer (i.e. an n-type conductive silicon layer) is formed. Next, the wafer is transported to a first etch bath 3 at a second location along the transportation path. The first etch bath contains an etchant 8 for etching the phosphor containing dopant layer so as to remove the phosphor containing dopant layer from the wafer in a back-etch process.

To allow a controlled back etching of the less efficient zone layer, the wafer is transported to a second etch bath 4, which contains a back-etch etchant 9. The back- etch etchant 9 comprises a first component and a second component. The first component is arranged for carrying out an oxidation reaction of the silicon surface to transform the top of the phosphor containing silicon layer into an oxide top layer. The second component is arranged for carrying out a dissolution reaction to dissolve (or etch) the oxide top layer. Examples of the back-etch etchant are: a mixture of a caustic solution as first component and a hydrogen peroxide based second component, and a mixture of a buffered HF solution as first component and a hydrogen peroxide based second component. A caustic solution is for example, Tetramethylammonium hydroxide. As soon as the silicon dioxide is removed by the second component, the unreacted silicon exposed to the etchant will be oxidized by the first component to form silicon dioxide. To have a control over the removal rate, the dissolution reaction is rate-limiting in the back-etch process. Thus, the reaction rate of the oxidation reaction is arranged to be higher than the reaction rate of the dissolution reaction.

In a further embodiment, the first component is a selective oxidizer of silicon. Also, the second component may be a selective solvent for silicon dioxide.

The oxidation reaction may be arranged for creating an oxide top layer which substantially is homogenous without pores or voids so as to encapsulate the silicon to overcome non-uniform oxidation of the surface.

Due to the rate limiting character of the dissolution reaction and the uniformity of the oxidation the invention allows that a back-etch can be performed to remove the phosphor containing silicon layer to a pre-determined thickness. In this manner, the invention allows to controllably remove the inefficient zone layer.

The thickness of the phosphor containing silicon layer to be removed can be determined from the reaction rate of the dissolution reaction and a reaction time during which the wafer is to be in contact with the back-etch etchant.

In an embodiment, the wafer is transported through the second (back-etch) etch bath 4 at a transportation speed in such a way that the time the wafer stays in the second etch bath and contacts the back etch etchant, corresponds with the required reaction time to remove a pre-determined thickness of the phosphor containing silicon layer while a remaining phosphor containing silicon layer remains as n-type silicon layer on the surface of the silicon wafer so as to create the emitter layer. On top of the remaining n-type silicon layer an oxide layer is present. Due to the controllable manner of etching, a thickness of the remaining n-type silicon layer may be pre-determined. A cross-sectional view of the silicon wafer W after etching in the first etch bath will be described below in more detail with reference to Figure 4.

After removal of the wafer from the second etch bath, the reaction to remove the phosphor containing silicon layer is stopped.

After removal of the wafer from the second etch bath, the silicon wafer may be further processed 7 in-line or in batch for manufacturing a solar cell. Such further process steps 7 will be known to the skilled in the art and are not discussed here.

Figure 3 shows a cross-sectional view of the silicon wafer W after exposure to the phosphor containing dopant. At this stage, the silicon wafer comprises a top layer 22 consisting of the phosphor containing silicon layer 22 with a diffusion controlled concentration profile of phosphor.

The phosphor concentration in the silicon layer 22 shows a gradient in which the concentration of phosphor at the surface of the wafer is relatively high in comparison to the concentration of phosphor at some depth below the surface. The gradient is typically controlled by the kinetics of the diffusion process. At the surface of the n-type silicon layer 22 an electrically less efficient zone layer 24 is present. On top of the electrically inefficient zone layer 24 the phosphor containing dopant layer 20 is present. The phosphor containing dopant layer 20 is to be removed by the etching process in the first etch bath 3 using the etchant 8 for etching the phosphor containing dopant layer's material.

Figure 4 shows a cross-sectional view of the silicon wafer W after removal of the phosphor containing dopant layer 20. On the substrate the n-type silicon layer 22 is present. The n-type silicon layer 22 is covered by the electrically less efficient zone layer 24.

Figure 5 shows a cross-sectional view of the silicon wafer W after etching in the second etch bath 4. After etching the silicon wafer in the back-etch etchant 9, the surface layer of the wafer is oxidized and subsequently dissolved, with the dissolution reaction being the rate-limiting reaction. Thus, the electrically less efficient zone layer 24 is etched back either partially or fully in a controllable manner. After this etching process, the silicon wafer comprises a remaining n-type silicon layer 26 covered by an oxide layer 28.

Figure 6 shows a flow diagram of a method 100 of manufacturing a solar cell from a silicon wafer in accordance with an embodiment of the present invention.

The method comprises in a first stage 101, a structural etch and surface preparation of the silicon wafer.

Next in a second stage 102, the method comprises an anneal of the silicon wafer while exposing at least one surface to a phosphor containing dopant. From the exposed surface phosphor diffuses into the silicon wafer and forms a phosphor containing silicon layer.

Subsequently, in a third stage 103, the method comprises a first etch process for removal of the phosphor containing dopant layer. The first etch process applies an etchant 8 for etching the phosphor containing dopant layer from the surface of the silicon wafer. The etchant 8 comprises a component that substantially removes the phosphorous silicate layer.

The second etch process applies a back-etch etchant 9. The back-etch etchant comprises a first component and a second component. The first component is arranged for carrying out an oxidation reaction of the silicon surface to transform the n-type silicon layer into an oxide top layer. The second component is arranged for carrying out a dissolution reaction to dissolve the oxide top layer. The dissolution reaction is rate limiting for the first etch process: in this manner a removal of a predetermined thickness of the inefficient zone layer can be controlled.

In a fourth stage 104, which illustrates a further embodiment, the method may comprise a third etch process, in which the silicon wafer is exposed to a third etchant 10 that is arranged for removal of the remaining oxide top layer of the wafer.

In a fifth stage 105, the method comprises further processes for manufacturing a solar cell from the silicon wafer as processed in the preceding first to fourth stages.

Figure 7 shows a system 50 for manufacturing a solar cell in accordance with another embodiment of the present invention.

In Figure 7 entities with the same reference number as shown in the preceding figures refer to corresponding entities. In this embodiment, system 50 comprises an in-line diffusion furnace 2, a first etch chamber 30, a second etch chamber 40, and a wafer transport mechanism 5.

The in-line diffusion furnace 2, the first etch chamber 30, the second etch chamber 40 are arranged along the path of the wafer transport mechanism.

The in-line diffusion furnace 2 is positioned at a first position, the first etch chamber 30 is positioned at second position and the second etch chamber 40 is positioned at third position along the path of the wafer transport mechanism.

After processing in the in-line diffusion furnace 2, the silicon wafer W is covered on at least one surface with the phosphor containing dopant layer and the phosphor containing silicon layer (i.e. the top layer of the silicon wafer). The processing is substantially similar as described with reference to Figure 1.

In a process step not shown here, the phosphor containing dopant layer's material is removed by a suitable etching process in an etching station. Next, the wafer is transported into a first etch chamber 30. In this embodiment, the first etch chamber is a reactor chamber for gaseous reactants. During use, the first etch chamber contains a first gaseous etchant 80 for removing the inefficient zone layer from the wafer in a back-etch process. To allow a controlled removal of the inefficient zone layer, the first gaseous etchant 80 comprises a first gaseous component 81 and a second gaseous component 82. The first gaseous component is arranged for carrying out an oxidation reaction of the silicon surface to transform the top of the phosphor containing silicon layer into an oxide top layer. The second gaseous component is arranged for carrying out a dissolution reaction to remove (or etch) the oxide top layer.

As soon as the silicon dioxide is removed by the second gaseous component, the unreacted silicon exposed to the second gaseous component 82 will be oxidized by the first gaseous component 81 to form silicon dioxide.

To have a control over the removal rate, the dissolution reaction is rate-limiting in the back-etch process. Thus, the reaction rate of the oxidation reaction is arranged to be higher than the reaction rate of the dissolution reaction.

After back etching of the inefficient layer of the phosphor containing silicon layer, the wafer can possible be transported to the further etch chamber 40 where any remaining oxide layer is removed (etched) from the at least one surface of the wafer. The etching of the remaining oxide layer is done using a second gaseous etchant 90.

It is noted that alternatively, the etching of the remaining oxide layer may be done using the second gaseous etchant 90 in the first etch chamber 30 after completion of the removal of the inefficient layer of the phosphor containing silicon layer. In such a case, the second etch chamber may be omitted. Another possibility is that the etching of the remaining oxide layer does not take place at all and that the wafer is further processed without further etching to remove the remaining oxide layer.

In another alternative embodiment, the etching of the remaining oxide layer may be done using a liquid etchant contained in a bath 4. In another alternative embodiment, the dopant is applied using a tube oven and gasses such as POCI3 or BBr₃ act as n-type or p-type dopant source respectively in combination with oxygen or water vapour. Figure 8 shows a system 51 for manufacturing a solar cell in accordance with another embodiment of the present invention.

In this embodiment, system 51 comprises an in-line diffusion furnace 2, a etching station 35, a first etch chamber 30 which acts as back-etch etching reactor, a second etch chamber 4, and a wafer transport mechanism 5.

The in-line diffusion furnace 2, the etching station 35, the first etch chamber 30, the second etch chamber 40 are arranged along the path of the wafer transport mechanism.

The in-line diffusion furnace 2 is positioned at a first position, the etching station 35 is at second position, the first etch chamber 30 is positioned at third position and the second etch chamber 40 is positioned at fourth position along the path of the wafer transport mechanism.

The etching station 35 is disposed between the diffusion furnace 2 and first etch chamber 30 which acts as the back-etch etching reactor. The first etching station is adapted for removing the dopant containing doping layer by an etchant for etching the substance of the dopant containing doping layer.

Figure 9 shows a system 52 for manufacturing a solar cell in accordance with another embodiment of the present invention.

In this embodiment, system 52 comprises an in-line diffusion furnace 2, a etching station 35, an oxidation reactor 36, a further etching station 37, a first etch chamber 30 as back-etch etching reactor, a second etch chamber 4, and a wafer transport mechanism 5.

The in-line diffusion furnace 2 is positioned at a first position, the etching station 35 is at second position.

Along the production track after the etching station an oxidation reactor is disposed that is adapted for oxidation of the surface of the silicon wafer that is exposed by the etchant in the etching station. After the oxidation reactor a further etching station is disposed that is adapted for etching of the silicon dioxide layer that is formed in the oxidation reactor. Next along the production track, the first etch chamber 30 is positioned. The second etch chamber 40 is positioned after the first etch chamber 30 along the path of the wafer transport mechanism 5. The etching station 35 is disposed between the diffusion furnace 2 and first etch chamber 30 as the back-etch etching reactor. The first etching station is adapted for removing the dopant containing doping layer by an etchant for etching the substance of the dopant containing doping layer. The oxidation reactor 36 is adapted for oxidation of the surface of the silicon wafer that is exposed by the etchant in the etching station. The further etching station 37 is adapted for etching of the silicon dioxide layer that is formed in the oxidation reactor 36.

It is realized that in the embodiments of the system 51, 52 as shown in figures 8 and 9, the etch chambers may relate to etching devices for etching by gaseous chemicals or alternatively to etching devices for etching by liquid chemicals. Likewise, the etching stations may use either gaseous or liquid chemicals.

It will be apparent to the person skilled in the art that other alternative and equivalent embodiments of the invention can be conceived and reduced to practice without departing from the true spirit of the invention, the scope of the invention being limited only by the appended claims.

Claims

1. method of manufacturing a solar cell from a silicon wafer comprising:

- providing a diffusion source comprising a dopant containing substance;

- formation of a dopant containing silicon layer, based on doping from the diffusion source, on at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to the dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of an ineffective conductive silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant, - back-etching of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer by a back-etch etchant, the back-etch etchant comprising a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer into an oxide top layer by the first component and a dissolution reaction to remove the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back- etch process.

2. Method according to claim 1, wherein the diffusion source is a dopant containing doping layer, and the dopant containing doping layer is removed by means of an etchant for etching the substance of the dopant containing doping layer preceding the back-etching of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer.

3. Method according to claim 2, wherein the removal of the dopant containing doping layer by the etchant for etching the substance of the dopant containing doping layer precedes an oxidation of the surface of the silicon wafer as exposed by the etchant to form a silicon dioxide layer, and subsequently etching of the silicon dioxide layer.

4. Method according to claim 1, wherein a reaction rate of the oxidation reaction is larger than a reaction rate of the dissolution reaction.

5. Method according to claim 1, wherein the first component is a selective agent for oxidation of silicon.

6. Method according to claim 1, wherein the second component is a selective agent for etching silicon dioxide.

7. Method according to any one of the preceding claims, wherein the oxidation reaction is arranged for forming an oxide top layer which substantially is homogenous and encapsulating.

8. Method according to to any one of the preceding claims, wherein the back- etching is performed to remove the upper layer of the ineffective conductive silicon layer comprised in the phosphor containing silicon layer to a pre-determined thickness.

9. Method according to claim 8, wherein a reaction time for back-etching the upper layer of the ineffective conductive silicon layer comprised in the phosphor containing silicon layer is determined from the reaction rate of the dissolution reaction.

10. Method according to any one of the preceding claims, wherein the etchant for back-etching is a liquid.

11. Method according to claim 1 - 10, wherein the etchant for back-etching is gaseous.

12. Method according to any one of the preceding claims, wherein the dopant comprises at least one of phosphor, arsenic, and antimony, and the conductive silicon layer is n-type.

13. Method according to claim 12, wherein the diffusion source is a silicate layer comprising at least one of phosphor, arsenic, and antimony as the dopant.

14. Method according to any one of the preceding claims, wherein the dopant comprises boron, and the conductive silicon layer is p-type.

15. Method according to claim 12, the diffusion source is a silicate layer comprising boron as the dopant.

16. System of manufacturing a solar cell from a silicon wafer comprising a production track provided with :

17. System according to claim 16, wherein an etching station is disposed between the diffusion furnace and the back-etch etching reactor, the etching station being adapted for removing the dopant containing doping layer by an etchant for etching the substance of the dopant containing doping layer.

18. System according to claim 17, wherein along the production track after the etching station an oxidation reactor is disposed for oxidation of the surface of the silicon wafer that is exposed by the etchant in the fetching station, and wherein after the oxidation reactor a further etching station is disposed for etching of the silicon dioxide layer that is formed in the oxidation reactor.

19. System according to claim 16, wherein the system comprises a transportation means for transporting the silicon wafer through at least the back-etch etching reactor, a transportation speed of the silicon wafer through at least the back- etch etching reactor being determined from a pre-determined thickness of the upper layer of the ineffective conductive silicon layer comprised in the dopant containing silicon layer that is to be removed.

20. System according to any one of the preceding claims 16 - 19, wherein the system comprises a further etching reactor, disposed in the production line after the back-etch etching reactor; the further etching reactor being adapted for removal by a further etchant of a remaining oxide top layer after being exposed to the back-etch etchant.

21. System according to any one of the preceding claims 16 - 20, wherein the back-etch etching reactor is an etching bath and the back-etch etchant is an etching liquid.

22. System according to any one of the preceding claims 16 - 20, wherein the back-etch etching reactor is a gas reactor system, and the back-etch etchant is gaseous.

23. System according to claim 20,wherein the further etching reactor is an etching bath and the further etchant is an etching liquid.

24. System according to claim 20, wherein the further etching reactor is a gas reactor system and the further etchant is gaseous.