NL2002512C2

NL2002512C2 - Method and system for removal of a surface layer of a silicon solar cell substrate.

Info

Publication number: NL2002512C2
Application number: NL2002512A
Authority: NL
Inventors: Arno Ferdinand Stassen; Gerard Paul Wyers; Martien Koppes
Original assignee: Stichting Energie
Priority date: 2009-02-10
Filing date: 2009-02-10
Publication date: 2010-08-11
Also published as: WO2010093238A1

Description

Method and system for removal of a surface layer of a silicon solar cell substrate

Field of the invention

The present invention relates to a method and system for manufacturing a solar cell 5 from a silicon wafer.

Background

During fabrication of a solar cell based on silicon wafer or substrate, an emitter layer is formed on a surface of the silicon wafer. Typical emitter forming processes on p-typc silicon involve a diffusion process of a dopant during thermal treatment, During 10 annealing the silicon is in contact with the dopant that for example contains phosphor as donor element. Typically, for p-type silicon phosphor is used as dopant and diffused into the silicon wafer from a phosphor containing glassy or dopant layer such as a phosphosilicate layer. Alternative dopants for p-type silicon are arsenic and antimony. For n-type silicon the dopant is typically boron as acceptor element.

15 To diffuse the dopant atoms into silicon, a surface of the silicon substrate that requires to be doped below that surface, is covered by the phosphor containing glassy layer. Such a phosphor containing glassy layer can be deposited by use of various techniques such as vapor deposition, wet chemical and sputtering.

Next, during thermal treatment, phosphor from the phosphor containing glassy 20 layer, can diffuse into the silicon substrate into the surface of the silicon wafer to form a phosphor doped silicon layer with a phosphor concentration profile.

After diffusing-in phosphor, the glassy layer is removed, typically by a wet etching process or a plasma-assisted etching process. It is known that in practice removal of the glassy layer is not complete.

25 A portion of the phosphor doped silicon layer has a suitable concentration of phosphor that allows to form an n-type doped silicon layer which will become the emitter of the solar cell. Adversely, at the surface of the silicon wafer the phosphor doped silicon layer can have a ineffective (or at least less effective) zone with a relatively high (excessive) concentration of phosphor. As a result of the high 30 concentration, the phosphor atoms may be in substitutional and interstitial positions in 2 the silicon lattice. The presence of an ineffective zone typically concurs with a reduced efficiency of the solar cell, which is explained by the fact that the interstitial dopant elements are not electrically active as n-type donor or p-type acceptor and cause an undesirable recombination of charge carriers within the emitter layer.

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Summary of the invention

It is an object of the present invention to provide a method that overcomes at least one of the drawbacks from the prior art.

The object is achieved by a method of manufacturing a solar cell from a silicon 10 wafer comprising: - formation of a dopant containing silicon layer, based on doping with dopant from a diffusion source, on at least one side of the silicon water, by exposing the at least one side of the silicon wafer to a dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of an ineffective conductive 15 silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant, - back-etching of the dopant containing silicon layer by a back-etch etchant, the back-etch etchant comprising a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the dopant containing 20 silicon layer into an oxide top layer by the first component and a dissolution reaction to remove the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back-etch process.

Advantageously, the method provides an etching process in which the back-etching of the ineffective conductive silicon layer can be done in a controlled manner, due to 25 rate-limitation of the back-etch process by the dissolution reaction. The improved control of the back-etching process allows controlling the removal rate and the removed layer thickness with increased precision.

Moreover, a manufacturing method as described above allows to implement the stages of the method as an in-line process along a track to be followed by the silicon 30 wafer.

Furthermore, a manufacturing method as described above allows to implement the stages of the method as batch type process in which the wafer is transported along a consecutive stations.

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The present invention provides a system of manufacturing a solar cell from a silicon wafer comprising a production track provided with: - a diffusion furnace, the diffusion furnace being arranged for forming a dopant containing silicon layer, based on doping with a dopant from a dopant containing 5 diffusion source, on at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to a dopant containing substance from the diffusion source, the dopant containing silicon layer comprising an upper layer of a less effective conductive silicon layer having a relatively high concentration of dopant and a lower buried layer of a conductive silicon layer having a lower concentration of dopant; 10 - a back-etch etching reactor disposed in the production track after the etching station, being arranged for back-etching of the dopant containing silicon layer by a back-etch etchant, the back-etch etchant comprising a first component and a second component, the back-etching comprising an oxidation reaction to transform a top layer of the dopant containing silicon layer into an oxide top layer by the first component and a 15 dissolution reaction to dissolve the oxide top layer by the second component; the dissolution reaction being rate-limiting in the back-etching process.

Advantageously, an in-line process allows a reduction of handling events during the manufacturing of the solar cell. Next to that, the process as described above can also be applied in a batch process.

20 Further embodiments are defined by the dependent claims as appended.

Brief description of drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which: 25 Figure 1 shows a system for manufacturing a solar cell in accordance with an embodiment of the present invention;

Figure 2 shows a silicon wafer in a first stage of the manufacturing;

Figure 3 shows a silicon wafer in a second stage of the manufacturing;

Figure 4 shows a silicon wafer in a third stage of the manufacturing; 30 Figure 5 shows a silicon wafer in a fifth stage of the manufacturing;

Figure 6 shows a flow diagram of a method of manufacturing a solar cell in accordance with an embodiment of the present invention; 4

Figure 7 shows an alternative system for manufacturing a solar cell in accordance with an embodiment of the present invention.

Description of embodiments

Figure 1 shows a system 1 for manufacturing a solar cell from a silicon wafer. The 5 system 1 comprises an in-line diffusion furnace 2, a first etch bath 3, a second etch bath 4, and a wafer transport mechanism 5.

The in-line diffusion furnace 2, the first etch bath 3, the second etch bath 4 are arranged along the path of the wafer transport mechanism.

The in-line diffusion furnace 2 is positioned at a first position, the first etch bath 3 10 is positioned at second position and the second etch bath 4 is positioned at third position along the path of the wafer transport mechanism.

A silicon wafer W on the path of the wafer transport mechanism 5 first enters the in-line diffusion furnace 2. A cross-sectional view of a fresh silicon wafer W (i.e., bare possibly after a cleaning step) is shown in Figure 2.

15 In the in-line diffusion furnace 2 the silicon wafer is annealed and simultaneously exposed on at least one surface to a phosphor containing dopant to grow a phosphor containing dopant layer on the at least one surface, such a dopant layer may be a glassy layer such as a phosphor-silicate layer. Due to the thermal treatment phosphor diffuses from the phosphor containing dopant layer into the silicon wafer. As a result a 20 phosphor containing silicon layer is formed at the interface of the phosphor containing dopant layer and the exposed surface of the silicon wafer W.

Due to the diffusion kinetics, the phosphor containing silicon layer will show a concentration profile of phosphor that will show a relatively high concentration of phosphor at the surface contacting the phosphor containing dopant layer that gradually 25 decreases as a function of depth from the exposed surface.

A cross-sectional view of the silicon wafer W after the diffusion process will be described below in more detail with reference to Figure 3.

Typically, the phosphor concentration in the phosphor containing silicon layer shows a gradient in which the concentration of phosphor at the surface of the wafer is 30 relatively high in comparison to the concentration of phosphor at some depth below the surface of the wafer. The concentration at the surface may be so high that an electrically less efficient zone is present at the surface of the wafer. In this zone phosphor atoms may be in substitutional and interstitial positions in the silicon lattice.

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Below that less efficient zone, in a region where the concentration of phosphor is relatively reduced in comparison to the concentration of phosphor in the less efficient zone, an n-type doped silicon layer (i.e. an n-type conductive silicon layer) is formed.

Next, the wafer is transported to a first etch bath 3 at a second location along the 5 transportation path. The first etch bath contains an etchant 8 for etching the phosphor containing dopant layer so as to remove the phosphor containing dopant layer from the wafer in a back-etch process.

To allow a controlled back etching of the less efficient zone layer, the wafer is transported to a second etch bath 4, which contains a back-etch etchant 9. The back-10 etch etchant 9 comprises a first component and a second component. The first component is arranged for carrying out an oxidation reaction of the silicon surface to transform the top of the phosphor containing silicon layer into an oxide top layer. The second component is arranged for carrying out a dissolution reaction to dissolve (or etch) the oxide top layer.

15 Examples of the back-etch etchant are: a mixture of a caustic solution as first component and a hydrogen peroxide based second component, and a mixture of a buffered HF solution as first component and a hydrogen peroxide based second component. A caustic solution is for example, Tetramethylammonium hydroxide.

As soon as the silicon dioxide is removed by the second component, the unreacted 20 silicon exposed to the etchant will be oxidized by the first component to form silicon dioxide.

To have a control over the removal rate, the dissolution reaction is rate-limiting in the back-etch process. Thus, the reaction rate of the oxidation reaction is arranged to be higher than the reaction rate of the dissolution reaction.

25 In a further embodiment, the first component is a selective oxidizer of silicon.

Also, the second component may be a selective solvent for silicon dioxide.

The oxidation reaction may be arranged for creating an oxide top layer which substantially is homogenous without pores or voids so as to encapsulate the silicon to overcome non-uniform oxidation of the surface, 30 Due to the rate limiting character of the dissolution reaction and the uniformity of the oxidation the invention allows that a back-etch can be performed to remove the phosphor containing silicon layer to a pre-determined thickness. In this manner, the invention allows to controllably remove the inefficient zone layer.

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The thickness of the phosphor containing silicon layer to be removed can be determined from the reaction rate of the dissolution reaction and a reaction time during which the wafer is to be in contact with the back-etch etchant.

In an embodiment, the wafer is transported through the second (back-etch) etch 5 bath 4 at a transportation speed in such a way that the time the wafer stays in the second etch bath and contacts the back etch etchant, corresponds with the required reaction time to remove a pre-determined thickness of the phosphor containing silicon layer while a remaining phosphor containing silicon layer remains as n-type silicon layer on the surface of the silicon wafer so as to create the emitter layer. On top of the 10 remaining n-type silicon layer an oxide layer is present. Due to the controllable manner of etching, a thickness of the remaining n-type silicon layer may be pre-determined.

A cross-sectional view of the silicon wafer W after etching in the first etch bath will be described below in more detail with reference to Figure 4.

After removal of the wafer from the second etch bath, the reaction to remove the 15 phosphor containing silicon layer is stopped.

After removal of the wafer from the second etch bath, the silicon wafer may be further processed 7 in-line or in batch for manufacturing a solar cell. Such further process steps 7 will be known to the skilled in the art and are not discussed here.

Figure 3 shows a cross-sectional view of the silicon wafer W after exposure to the 20 phosphor containing dopant.

At this stage, the silicon wafer comprises a top layer 22 consisting of the phosphor containing silicon layer 22 with a diffusion controlled concentration profile of phosphor.

The phosphor concentration in the silicon layer 22 shows a gradient in which the 25 concentration of phosphor at the surface of the wafer is relatively high in comparison to the concentration of phosphor at some depth below the surface. The gradient is typically controlled by the kinetics of the diffusion process. At the surface of the n-type silicon layer 22 an electrically less efficient zone layer 24 is present. On top of the electrically inefficient zone layer 24 the phosphor containing dopant layer 20 is present. 30 The phosphor containing dopant layer 20 is to be removed by the etching process in the first etch bath 3 using the etchant 8 for etching the phosphor containing dopant layer’s material.

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Figure 4 shows a cross-sectional view of the silicon wafer W after removal of the phosphor containing dopant layer 20, On the substrate the n-type silicon layer 22 is present, The n-type silicon layer 22 is covered by the electrically less efficient zone layer 24.

5 Figure 5 shows a cross-sectional view of the silicon wafer W after etching in the second etch bath 4. After etching the silicon wafer in the back-etch etchant 9, the surface layer of the wafer is oxidized and subsequently dissolved, with the dissolution reaction being the rate-limiting reaction. Thus, the electrically less efficient zone layer 24 is etched back either partially or fully in a controllable manner. After this etching 10 process, the silicon wafer comprises a remaining n-type silicon layer 26 covered by an oxide layer 28.

Figure 6 shows a flow diagram of a method 100 of manufacturing a solar cell from a silicon wafer in accordance with an embodiment of the present invention.

The method comprises in a first stage 101, a structural etch and surface preparation 15 of the silicon wafer.

Next in a second stage 102, the method comprises an anneal of the silicon wafer while exposing at least one surface to a phosphor containing dopant. From the exposed surface phosphor diffuses into the silicon wafer and forms a phosphor containing silicon layer.

20 Subsequently, in a third stage 103, the method comprises a first etch process for removal of the phosphor containing dopant layer. The first etch process applies an etchant 8 for etching the phosphor containing dopant layer from the surface of the silicon wafer. The etchant 8 comprises a component that substantially removes the phosphorous silicate layer.

25 The second etch process applies a back-etch etchant 9. The back-etch etchant comprises a first component and a second component. The first component is arranged for carrying out an oxidation reaction of the silicon surface to transform the n-type silicon layer into an oxide top layer. The second component is arranged for carrying out a dissolution reaction to dissolve the oxide top layer. The dissolution reaction is rate 30 limiting for the first etch process: in this manner a removal of a predetermined thickness of the inefficient zone layer can be controlled.

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In a fourth stage 104, which illustrates a further embodiment, the method may comprise a third etch process, in which the silicon wafer is exposed to a third etchant 10 that is arranged for removal of the remaining oxide top layer of the wafer.

In a fifth stage 105, the method comprises further processes for manufacturing a 5 solar cell from the silicon wafer as processed in the preceding first to fourth stages.

Figure 7 shows a system 50 for manufacturing a solar cell in accordance with another embodiment of the present invention.

In Figure 7 entities with the same reference number as shown in the preceding figures refer to corresponding entities.

10 In this embodiment, system 50 comprises an in-line diffusion furnace 2, a first etch chamber 30, a second etch chamber 4, and a wafer transport mechanism 5.

The in-line diffusion furnace 2, the first etch chamber 30, the second etch chamber 40 are arranged along the path of the wafer transport mechanism.

The in-line diffusion furnace 2 is positioned at a first position, the first etch 15 chamber 30 is positioned at second position and the second etch chamber 40 is positioned at third position along the path of the wafer transport mechanism.

After processing in the in-line diffusion furnace 2, the silicon wafer W is covered on at least one surface with the phosphor containing dopant layer and the phosphor containing silicon layer (i.e. the top layer of the silicon wafer). The processing is 20 substantially similar as described with reference to Figure 1.

In a process step not shown here, the phosphor containing dopant layer’s material is removed by a suitable etching process in an etching station.

Next, the wafer is transported into a first etch chamber 30. In this embodiment, the first etch chamber is a reactor chamber for gaseous reactants. During use, the first etch 25 chamber contains a first gaseous etchant 80 for removing the inefficient zone layer from the wafer in a back-etch process.

To allow a controlled removal of the inefficient zone layer, the first gaseous etchant 80 comprises a first gaseous component 81 and a second gaseous component 82. The first gaseous component is arranged for carrying out an oxidation reaction of 30 the silicon surface to transform the top of the phosphor containing silicon layer into an oxide top layer. The second gaseous component is arranged for carrying out a dissolution reaction to remove (or etch) the oxide top layer.

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As soon as the silicon dioxide is removed by the second gaseous component, the unreacted silicon exposed to the second gaseous component 82 will be oxidized by the first gaseous component 81 to form silicon dioxide.

To have a control over the removal rate, the dissolution reaction is rate-limiting in 5 the back-etch process. Thus, the reaction rate of the oxidation reaction is arranged to be higher than the reaction rate of the dissolution reaction.

After back etching of the inefficient layer of the phosphor containing silicon layer, the wafer can possible be transported to the further etch chamber 40 where any remaining oxide layer is removed (etched) from the at least one surface of the wafer.

10 The etching of the remaining oxide layer is done using a second gaseous etchant 90.

It is noted that alternatively, the etching of the remaining oxide layer may be done using the second gaseous etchant 90 in the first etch chamber 30 after completion of the removal of the inefficient layer of the phosphor containing silicon layer. In such a case, the second etch chamber may be omitted.

15 Another possibility is that the etching of the remaining oxide layer does not take place at all and that the wafer is further processed without further etching to remove the remaining oxide layer.

In another alternative embodiment, the etching of the remaining oxide layer may be done using a liquid etchant contained in a bath 4.

20 In another alternative embodiment, the dopant is applied using a tube oven and gasses such as POC H or BBr3 act as n-type or p-type dopant source respectively in combination with oxygen or water vapour.

It will be apparent to the person skilled in the art that other alternative and equivalent embodiments of the invention can be conceived and reduced to practice 25 without departing from the tme spirit of the invention, the scope of the invention being limited only by the appended claims.

Claims

A method for manufacturing a solar cell from a silicon wafer, comprising: 5. forming a dopant-containing silicon layer in the silicon wafer based on doping from a diffusion source of the dopant on at least one side of the silicon wafer by exposing the at least one side of the silicon wafer to a dopant-containing substance from the diffusion source, the dopant-containing silicon layer being an upper layer of an inefficient conductive silicon zone with a relatively high concentration of dopant and a lower buried layer of conductive silicon with a lower dopant concentration; - etching back the dopant-containing silicon layer using a back etching etchant, wherein the back etching etchant comprises a first and a second component, and wherein the etching back comprises an oxidation reaction by the first component of the back etching etching etchant for converting a top layer of the dopant-containing silicon layer into an oxide top layer, and a dissolution reaction by the second component of the back etching etchant for dissolving the formed oxide top layer, the dissolution reaction determining speed for etching it back.

2. A method according to claim 1, wherein the dopant diffusion source is a dopant-containing dopant layer, and the dopant-containing dopant layer is removed by an etchant for etching the material from the dopant-containing dopant layer prior to tamping. A method according to claim 1, wherein a reaction rate of the oxidation reaction is greater than a reaction rate of the dissolution reaction.

The method of claim 1, wherein the first component is a selective oxidizing agent for silicon.

The method of claim 1, wherein the second component is a selective reagent for etching silica.

The method of any one of the preceding claims, wherein the oxidation reaction is adapted to form an oxide top layer that is substantially homogeneous and occlusive. 10

The method of any one of the preceding claims, wherein the tamping is performed until a predetermined thickness of the dopant-containing silicon layer is removed.

The method of claim 7, wherein a reaction time for etching back the dopant-containing silicon layer is determined from the reaction rate of the dissolution reaction.

The method of any one of the preceding claims wherein the back etching agent is a liquid.

The method of any one of claims 1 to 9, wherein the tcrug etching agent is gaseous. 25

The method of any one of the preceding claims, wherein the dopant contains at least one of phosphorus, arsenic, and antimony, and the conductive silicon is of the n-type.

The method of claim 11, wherein the diffusion source is a silicate layer containing at least one of phosphorus, arsenic and antimony as a dopant.

The method of any one of the preceding claims, wherein the dopant contains boron, and the conductive silicon is of the p-type.

14. A method according to claim 11, wherein the diffusion source is a silicate layer containing a dopant boron.

15. An assembly for manufacturing a solar cell from a silicon wafer, comprising a production line comprising: - a diffusion furnace wherein the furnace is adapted to form a dopant-containing silicon layer based on doping from a dopant diffusion source, at at least one side of the silicon wafer, by exposing the at least one side of the silicon wafer to a dopant-containing dopant, wherein the dopant-containing silicon layer is an upper layer of an inefficient conductive silicon zone with a relatively high concentration of dopant and a lower buried conductive silicon layer having a lower dopant concentration; - a back-etching etching reactor placed in the production line after the diffusion oven, adapted to etch back the dopant-containing silicon layer with the aid of a back-etching etchant, wherein the back-etching etchant comprises a first and a second component, and wherein the etching back comprises: an oxidation reaction by the first component of the back etching agent for converting a top layer of the dopant-containing silicon layer into an oxide top layer on, and a dissolution reaction by the second component of the back etching agent for dissolving the formed oxide top layer, the dissolution reaction determining the speed for the back etching.

16. An assembly according to claim 15, wherein an etching station is placed in the production line between the diffusion furnace and the back-etching etching reactor, arranged for removing the dopant-containing dopant layer by an etchant for etching the material from the dopant-containing dopant layer.

17. Assembly as claimed in claim 15, wherein the assembly comprises a transport means for transporting the silicon wafer through at least the back-etching etching reactor, wherein a transport speed of the silicon wafer through at least the back-etching etching reactor is determined from a predetermined thickness of the silicon layer containing dopant 5 to be removed.

18. Assembly as claimed in any of the foregoing claims 15-17, wherein the assembly comprises a further etching reactor, placed in the production line after the back-etching reactor, adapted for removal by a further etchant of the remaining oxide top layer after residence in the back-etching etchant.

Assembly according to any of the preceding claims 15-18, wherein the back-etching etching reactor is an etching bath and the back-etching etchant is an etching liquid.

An assembly according to any of the preceding claims 15-18, wherein the back etch etching reactor is a gas reaction system and the back etch etching agent is gaseous.

An assembly according to claim 18, wherein the further etching reactor is an etching bath and the further etchant is an etching liquid. 20

The assembly of claim 18, wherein the further etching reactor is a gas reaction system and the further etchant is gaseous.