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WO2010028550A1 - 一种提高时钟稳定度的方法及设备 - Google Patents

一种提高时钟稳定度的方法及设备 Download PDF

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Publication number
WO2010028550A1
WO2010028550A1 PCT/CN2009/071506 CN2009071506W WO2010028550A1 WO 2010028550 A1 WO2010028550 A1 WO 2010028550A1 CN 2009071506 W CN2009071506 W CN 2009071506W WO 2010028550 A1 WO2010028550 A1 WO 2010028550A1
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WO
WIPO (PCT)
Prior art keywords
difference
timestamp
receiving
sending
time stamp
Prior art date
Application number
PCT/CN2009/071506
Other languages
English (en)
French (fr)
Inventor
孙文华
王晓波
王继辉
徐文广
阳生丙
邓友好
李丙博
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP09165310.5A priority Critical patent/EP2164194B1/en
Priority to US12/501,861 priority patent/US20100067552A1/en
Publication of WO2010028550A1 publication Critical patent/WO2010028550A1/zh
Priority to US12/938,123 priority patent/US7924887B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0664—Clock or time synchronisation among packet nodes using timestamps unidirectional timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a method and device for improving clock stability.
  • the adaptive method is a common method for recovering the clock, and the receiving end extracts timing information from the time stamp carried by the packet and the packet arrival interval. This method does not require an additional reference clock and is ideal for use in packet networks.
  • the process of adaptive clock recovery is shown in Figure 1.
  • the function of the service adaptation module in Figure 1 is to complete the adaptation of TDM streams and packets.
  • the sender service adaptation module obtains a clock signal from the TDM device and drives the counter to count. When a certain amount of TDM stream data is received, the data encapsulation packet is sent. At the same time, the counter value when the packet is sent, that is, the time stamp, is loaded into the packet header.
  • the receiving end service adaptation module receives the packet, uses the timestamp to recover the service clock of the transmitting end, and uses the clock to send the TDM data in the packet payload in the form of a bit stream.
  • the key to the adaptive method is how to effectively filter out the damage caused by PDV (Packet Delay var iance) and recover the clock signal from the transmitting end.
  • the prior art provides a method for reducing packet delay jitter damage to clock recovery, including the following steps: performing traffic shaping on a received data packet to output a write signal; and reading a clock based on the write signal and the digital oscillator output The amount of data buffered by the first-in first-out buffer is obtained; the filter parameter is calculated according to the write signal and the obtained buffer data amount; and the restored read clock is obtained according to the filter parameter.
  • the prior art mainly reduces the damage of the packet delay jitter to the clock recovery by filtering, and causes a lot of reasons for the change of the timestamp interval at the receiving end.
  • the filtering method is difficult to adapt to various situations, especially when a packet experiences a large delay in the network, and the receiving time stamp will cause a sudden change, which will seriously damage the clock recovery.
  • Embodiments of the present invention provide a method and a device for improving clock stability to improve clock recovery stability.
  • an embodiment of the present invention provides a method for improving clock stability, which includes the following steps:
  • the sending timestamp and the receiving timestamp are preprocessed;
  • the time division multiplexed data is transmitted according to the service clock.
  • An embodiment of the present invention provides an apparatus for improving clock stability, including: a determining unit, configured to determine whether a difference between a sending timestamp and a receiving timestamp is a sudden value; receiving a timestamp;
  • a service clock obtaining unit configured to acquire a service clock according to the sending timestamp and the receiving timestamp after the processing unit is preprocessed
  • a data sending unit configured to send time-multiplexed data according to the service clock acquired by the service clock acquiring unit.
  • An embodiment of the present invention further provides an apparatus for improving clock stability, wherein the apparatus for improving clock stability is connected to a data receiving apparatus and a data transmitting apparatus, and the data sending apparatus is configured to use
  • the service clock obtained by the device for improving the clock stability transmits the time division multiplexed data received by the data receiving device, and the device for improving the clock stability includes:
  • a determining module configured to determine whether the difference between the sending timestamp and the receiving timestamp is a sudden value
  • the processing module configured to preprocess the sending timestamp and the receiving timestamp according to the determining result of the determining module
  • the service clock acquisition module is configured to obtain a service clock according to the sending timestamp and the receiving timestamp after the processing module is preprocessed.
  • the embodiment of the invention has the following advantages:
  • the packet delay jitter is smoothed by the mutation processing of the time stamp, the damage of the packet delay jitter to the clock recovery is reduced, the clock recovery quality is improved, and the clock synchronization problem is solved.
  • Figure 1 is a flow chart of adaptive clock recovery
  • FIG. 2 is a flowchart of a method for improving clock stability according to Embodiment 1 of the present invention
  • Figure 3 is a schematic diagram showing the time difference value of the time difference value and the non-mutation value
  • Embodiment 4 is a flowchart of a method for improving clock stability in Embodiment 2 of the present invention.
  • FIG. 5 is a flowchart of a method for detecting and repairing a sudden value according to an embodiment of the present invention
  • FIG. 6 is a structural diagram of an apparatus for improving clock stability in an embodiment of the present invention.
  • FIG. 7 is a structural diagram of a determining unit in an embodiment of the present invention.
  • FIG. 8 is a structural diagram of a service clock acquiring unit according to an embodiment of the present invention.
  • FIG. 9 is a structural diagram of an apparatus for improving clock stability according to an embodiment of the present invention.
  • the first embodiment of the present invention provides a method for improving clock stability.
  • the application background is to use an adaptive method to recover a service clock. As shown in FIG. 2, the method includes the following steps:
  • Step s201 Determine whether the difference between the sending timestamp ST (Sender Timestamp) and the receiving timestamp RT (Receiver Timestamp) is a sudden value, and when the difference is a sudden value, pre-processing the sending timestamp and the receiving timestamp.
  • ST Send Timestamp
  • RT Receiveiver Timestamp
  • the process of determining whether the difference between the sending timestamp ST and the receiving timestamp RT is a sudden value includes: comparing whether the difference between the current sending and receiving timestamp difference and the average sending and receiving timestamp difference exceeds a limited range, and if yes, detecting Then, whether the difference between the difference between the N transmit and receive time stamp differences and the average transmit and receive time stamp difference is out of range, N is a variable, and can be flexibly configured according to the requirement of the algorithm; if the subsequent N transmit and receive time stamp differences and the average send and receive time If the difference in the difference between the stamp values does not remain outside the limit, it is a sudden value.
  • the current transmission and reception time stamp difference is a non-mutation value; or, the current transmission and reception time stamp difference and the average transmission and reception time stamp difference
  • the difference amplitude is out of the limited range, and the difference between the next N transmission and reception time stamps and the average transmission and reception time stamp difference is out of the limited range, and the current transmission and reception time stamp difference is a non-mutation value.
  • RT-ST send and receive timestamp difference
  • Any delay in the transmission delay and clock offset off set will result in a change in the timestamp difference.
  • Possible reasons for the ⁇ change may include one or more of the following:
  • the first three cases can cause the packet transmission delay to change, and the last case can cause the clock skew of the transceiver to be changed. Only the first two cases cause a sudden change in the timestamp difference.
  • the sudden change in the timestamp difference means that, among all the timestamp differences, a small portion of the timestamp difference that statistically deviates from the majority of the timestamp difference is severely deviated.
  • the timestamp difference of the nth packet in the left figure is far from other values, and the value is significantly increased, while the surrounding values remain basically unchanged, so the timestamp difference of the nth packet in the left figure belongs to the sudden value. .
  • the timestamp difference of the nth packet in the right figure also shows a numerical increase, but the subsequent packets all exhibit statistical regularity of numerical increase, so the timestamp difference of the nth packet in the right figure does not belong to the mutation value. .
  • preprocessing the sending timestamp and the receiving timestamp which may be: when the difference between the sending timestamp and the receiving timestamp is a sudden value, the current sending timestamp and the current receiving time
  • the current sending and receiving timestamp difference corresponding to the timestamp is replaced by the average sending and receiving timestamp difference, and the new average sending and receiving timestamp difference is calculated according to the replaced current sending and receiving timestamp difference.
  • the pre-processed send timestamp and receive timestamp include: original transmit timestamp ST, original receive timestamp RT, and new average send/receive timestamp difference.
  • Step s 202 Acquire a service clock according to the pre-processed sending timestamp and the receiving timestamp.
  • the phase-in-time calculation of the transmission timestamp, the reception timestamp, and the average transmission and reception timestamp difference after the pre-processing of the mutation value restores the service clock of the sender.
  • Step s 203 Send time division multiplexed data according to the service clock.
  • the packet delay jitter is smoothed by the mutation processing of the time stamp, the damage of the packet delay jitter to the clock recovery is reduced, the clock recovery quality is improved, and the clock synchronization problem is solved.
  • a second embodiment of the present invention provides a method for improving clock stability.
  • the application background is to use an adaptive method to recover a service clock. As shown in FIG. 4, the method includes the following steps:
  • Step s401 Receive packet data, record a current receiving timestamp, and separate TDM data and a sending timestamp from the packet data.
  • the TDM data, the transmission timestamp, and the reception timestamp are respectively stored in the order of the transmission timestamps from small to large, and the TDM data, the transmission timestamp, and the reception stamp remain in a corresponding relationship.
  • the sending timestamp, the receiving timestamp, and the TDM data correspond to the timestamp buffer and the data buffer stored at the receiving end, respectively.
  • Step s 402 the data sending mechanism completes the previous data packet transmission, and reads the TDM data of the current packet from the data buffer, and the timestamp buffer sends the corresponding sending timestamp and the receiving timestamp to the judgment sum. Processing unit.
  • Step s 403 detecting and repairing the abrupt value of the sending timestamp and the receiving timestamp difference. It is judged whether the difference between the transmission time stamp and the reception time stamp is a sudden value, and when it is a sudden value, the transmission time stamp and the reception time stamp are preprocessed. Comparing whether the difference between the current transmission and reception time stamp difference and the average transmission and reception time stamp difference exceeds a limited range, and if yes, detecting whether a difference between the subsequent N time stamp difference values and the average transmission and reception time stamp difference value is beyond a limited range; If the amplitude of the difference between the subsequent N timestamp difference values and the average transmission and reception time stamp difference does not remain outside the defined range, it is a sudden value.
  • the current transmission and reception time stamp difference and the average transmission and reception time stamp difference is within a limited range, or the difference between the current transmission and reception time stamp difference and the average transmission and reception time stamp difference is not within the limited range, and then N If the difference between the timestamp difference and the average send/receive timestamp difference is beyond the limit, the current send and receive timestamp difference is a non-mutation value. Based on the judgment result, the average time stamp difference value is calculated.
  • Step s 404 Obtain a service clock according to the pre-processed sending timestamp and the receiving timestamp. PLL
  • (Pha se Locked Loop) receives the timestamp of the pre-processed mutation value, including the transmission timestamp, the reception timestamp, and the average transmission and reception timestamp difference, and confirms the timestamp based on the received mutation value.
  • the frequency difference or phase difference between the output clock signal and the received clock signal smoothing the frequency difference or phase difference between the output clock signal and the received clock signal, filtering out the influence of data changes and other unstable factors on the entire module;
  • the difference or phase difference inversely adjusts the frequency or phase of the output clock signal, and fixes the frequency difference or phase difference between the output clock signal and the received clock signal to recover the service clock of the transmitting end.
  • Step s 405 The data sending mechanism receives the service clock of the transmitting end recovered by the PLL, and according to the service clock, the driving data sending mechanism pushes out the TDM bit stream.
  • Step s 501 Receive and detect an nth packet timestamp pair, including a sending timestamp ST and a receiving timestamp RT, and calculating The transmit and receive time stamp difference ⁇ of the nth packet timestamp pair.
  • Step s 502 determining whether the difference between the transmission and reception time stamp difference ⁇ of the nth packet timestamp pair and the average transmission and reception time stamp difference ATaverage exceeds a predetermined range, and if yes, executing step s 503; if not, executing step s 507.
  • Step s 504 determining whether the difference between the sending and receiving time stamp difference value ATMm of the mth timestamp pair and the average sending and receiving time stamp difference value ATaverage exceeds a predetermined range, if yes, executing step s 505; if not, executing step s 508 .
  • Step s 506 determining whether m is greater than n, if yes, performing step s 504, calculating a transceiving time stamp difference ATm of the mth packet timestamp pair; otherwise, performing step s507.
  • Step s 507 determining that the transmission and reception time stamp difference ⁇ of the nth packet timestamp pair is a non-mutation value, and calculating an average transmission and reception time stamp difference.
  • Step s 508 determining that the transmit and receive timestamp difference ⁇ of the nth packet timestamp pair is a sudden value, and replacing the transmit and receive timestamp difference ⁇ of the nth timestamp with the average transmit/receive timestamp difference.
  • a method for improving clock stability detects a sudden change in a packet, and abruptly processes the time stamp to smooth the packet delay jitter, thereby reducing the damage of the packet delay jitter to the clock recovery, and improving the The clock recovery quality solves the clock synchronization problem.
  • An embodiment of the present invention further provides an apparatus for improving clock stability. As shown in FIG. 6, the method includes: a determining unit 61 0 configured to analyze a timestamp from a buffer, and determine a difference between a sending timestamp and a receiving timestamp. Whether the difference between the value and the average transmission and reception time stamp difference is out of the limited range.
  • the difference between the subsequent transmission and reception time stamp difference and the average transmission and reception time stamp difference remains beyond the limited range, if the difference between the subsequent transmission and reception time stamp difference and the average transmission and reception time stamp difference is not maintained. If it is outside the limit, it is a sudden value. If the difference between the current transmission and reception time stamp difference and the average transmission and reception time stamp difference does not exceed the limited range, or the difference between the current transmission and reception time stamp difference and the average transmission and reception time stamp difference is out of the limited range, and then the transmission and reception time Poke difference and flat The difference between the sent and received timestamp differences is kept out of the limited range, and the current send and receive timestamp difference is a non-mutated value.
  • the processing unit 620 is configured to process the sending timestamp and the receiving timestamp according to the judgment result of the determining unit 610, calculate an average sending and receiving timestamp difference, and update the original average sending and receiving timestamp difference.
  • the service clock obtaining unit 630 is configured to calculate a sending timestamp, a receiving timestamp, and an average sending and receiving timestamp difference that are preprocessed by the abrupt value, and recover the service clock of the sending end.
  • Receiving a timestamp of the preprocessing of the mutation value including a sending timestamp, a receiving timestamp, and an average sending and receiving timestamp difference, and preprocessing the timestamp according to the received abrupt value to determine a frequency difference or a difference between the output clock signal and the receiving clock signal Smoothing the frequency difference or phase difference between the output clock signal and the received clock signal, filtering out the influence of data changes and other unstable factors on the entire module; adjusting the frequency of the output clock signal according to the frequency difference or phase difference of the output Or phase, the fixed output clock signal and the received clock signal frequency difference or phase difference amplitude, recover the service clock of the transmitting end.
  • the data sending unit 640 is configured to send a TDM bit stream according to the clock signal recovered by the service clock acquiring unit 630.
  • the determining unit 610 is configured as shown in FIG. 7, and further includes: a receiving subunit 611, a detecting subunit 612, and a judging subunit 613.
  • the receiving subunit 611 is configured to receive a timestamp pair from the data receiving unit 650, including sending a timestamp and receiving a timestamp.
  • the detecting sub-unit 612 is configured to detect, according to the timestamp pair received by the receiving subunit 611 and the average transceiving timestamp difference stored by the detecting subunit 612, whether the difference between the current transceiving timestamp difference and the average transceiving timestamp difference is within a limited range. The detection result is sent to the judgment subunit 613. Whether the difference is a sudden value.
  • the structure of the service clock obtaining unit 630 is as shown in FIG. 8, and includes: a phase detecting sub-unit 631, a filtering sub-unit 632, and a phase-modulating sub-unit 633.
  • the phase detector sub-unit 631 is configured to receive a timestamp of the mutation value pre-processing, including a sending time stamp, a receiving timestamp, and an average sending and receiving timestamp difference, and determining an output clock signal according to the timestamp preprocessed according to the received mutation value.
  • the filtering sub-unit 632 is configured to smooth filter the frequency difference or phase difference between the output clock signal and the receiving clock signal of the phase detecting sub-unit 631, and filter out the influence of data changes and other unstable factors on the entire module.
  • the phase modulation sub-unit 633 is configured to adjust a frequency or a phase of the output clock signal according to a frequency difference or a phase difference of the output of the filter sub-unit 632, and fix a frequency difference or a phase difference between the output clock signal and the reception clock signal, and recover the transmission end.
  • Business clock is configured to adjust a frequency or a phase of the output clock signal according to a frequency difference or a phase difference of the output of the filter sub-unit 632, and fix a frequency difference or a phase difference between the output clock signal and the reception clock signal, and recover the transmission end.
  • Business clock is configured to adjust a frequency or a phase of the output clock signal according to a frequency difference or a phase difference of the output of the filter sub-unit 632, and fix a frequency difference or a phase difference between the output clock signal and the reception clock signal, and recover the transmission end.
  • Business clock is configured to adjust a frequency or a phase of the output clock signal according to a frequency difference or a phase difference of the output of the
  • the device for improving the clock stability of the embodiment of the present invention further includes: a data receiving unit 650, configured to receive packet data, record a receiving timestamp, separate TDM data and send a timestamp, and send the TDM data to the
  • the data sending unit 640 sends the sending time stamp and the receiving time stamp to the determining unit 610.
  • the sending timestamp, the receiving timestamp, and the TDM data are respectively stored in the timestamp buffer and the data buffer, and the data and timestamp are respectively stored in the order of sending timestamps from small to large.
  • the TDM data and the transmission timestamp and the reception timestamp remain - the corresponding relationship.
  • the sorting mechanism can effectively reduce the damage of packet out-of-order to clock recovery.
  • An embodiment of the present invention further provides an apparatus for improving clock stability.
  • the apparatus for improving clock stability is connected to a data receiving apparatus and a data transmitting apparatus, and the data sending apparatus is configured to improve according to the foregoing.
  • the service clock obtained by the device of the clock stability sends the time division multiplexed data received by the data receiving device, and the device for improving the clock stability includes:
  • the determining module 710 is configured to determine whether the difference between the sending timestamp and the receiving timestamp is a sudden value; the processing module 720 is configured to preprocess the sending timestamp and the receiving timestamp according to the determining result of the determining module 710;
  • the service clock acquisition module 730 is configured to obtain a service clock according to the transmission time stamp and the reception time stamp preprocessed by the processing module 720.
  • the determining module 710 further includes:
  • a receiving submodule 711 configured to receive the sending timestamp and the receiving timestamp from the data receiving apparatus
  • the detecting sub-module 712 is configured to detect the current sending and receiving time stamp difference according to the sending timestamp and the receiving timestamp received by the receiving sub-module 71 1 and the average sending and receiving timestamp difference stored by the detecting sub-module 712 Whether the difference between the average transmission and reception time stamp difference is within a limited range;
  • the mutation value judging sub-module 71 3 is configured to determine whether the current transceiving time stamp difference value is a sudden value according to the detection result sent by the detecting sub-module 712.
  • the processing module 720 can further include:
  • the difference processing sub-module 721 is configured to calculate an average transmission and reception time stamp difference according to the determination result of the mutation value judgment sub-module 71 3, and update an average transmission/reception time stamp difference value stored by the detection sub-module 71 2 .
  • processing module 720 may further include:
  • a difference replacement submodule configured to determine, according to the mutation value, a determination result of the submodule 71 3, when the judgment result of the mutation value determination submodule 71 3 is that the current transmission and reception time stamp difference is a sudden value, The current sending and receiving time stamp difference value is replaced by the average sending and receiving time stamp difference value stored by the detecting submodule 712;
  • the average difference sub-module configured to: when the determination result of the mutation value judging sub-module 71 3 is that the current transceiving time stamp difference value is a sudden value, replace the current sending and receiving time stamp after the sub-module replacement according to the difference value And calculating, by the difference, the average sent/received timestamp difference, and updating the average sent/received timestamp difference stored by the detecting submodule 71 2; or, when the determination result of the abrupt value determining submodule 71 3 is the current sending and receiving timestamp difference When the value is not a mutation value, the average transmission and reception time stamp difference value is directly calculated, and the average transmission and reception time stamp difference value stored by the detection sub-module 712 is updated.
  • the service clock acquisition module 730 further includes:
  • the phase detector sub-module 731 is configured to receive a mutation value pre-processing time stamp from the processing module 720, and determine a frequency difference or a difference amplitude between the output clock signal and the receiving clock signal;
  • a filtering submodule 732 configured to perform smooth filtering on a frequency difference or a phase difference output by the phase detecting submodule 731;
  • the phase modulation sub-module 733 is configured to adjust a frequency or a phase of the output clock signal according to a frequency difference or a phase difference of the output of the filtering sub-module 732, and fix a frequency difference or a phase difference between the output clock signal and the receiving clock signal.
  • the above modules may be distributed in one device or distributed in multiple devices. The above modules can be combined into one module, or can be further split into multiple sub-modules.
  • the device provided by the embodiment of the invention smoothes the packet delay jitter by abrupt processing of the time stamp, reduces the damage of the packet delay jitter to the clock recovery, improves the clock recovery quality, and solves the clock synchronization problem.
  • the present invention can be implemented by hardware, or by software plus necessary general hardware platform.
  • the technical solution of the present invention may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several The instructions are for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.
  • modules in the apparatus in the embodiments may be distributed in the apparatus of the embodiment according to the description of the embodiments, or may be correspondingly changed in one or more apparatuses different from the embodiment.
  • the modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.

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Description

一种提高时钟稳定度的方法及设备
本申请要求于 2008年 9月 12 日 提交中 国专利局、 申请号为 200810211970. 0 、 发明名称为 "一种提高时钟稳定度的方法及设备" 中国专 利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信技术领域， 特别涉及一种提高时钟稳定度的方法 及设备。
背景技术
基于分组网的 CESoP ( C i rcui t Emula t ion Services over Packet , 电 路仿真业务） 中， 如何准确的恢复 TDM ( Time Divi s ion Mul t iplex , 时分复 用） 业务时钟是影响系统性能的一个关键。 例如， 在两个客户端之间使用专 用的租借线路， 通过运营商的电路仿真业务通道进行连接， 则客户端 TDM业务 的时钟频率必须在分组网的出口处精确地重新恢复。 长时间的频率不匹配将 导致分组网络出口处形成等待队列溢出或读空的情况， 产生滑动损伤。
自适应法是一种恢复时钟的常用方法， 接收端从分组携带的时间戳和分 组到达间隔中提取定时信息。 这种方法不需要额外的参考时钟， 非常适合在 分组网中使用。 自适应时钟恢复的流程如图 1所示。 图 1中业务适配模块的功 能是完成 TDM流和分组的适配。 发送端业务适配模块从 TDM设备获得时钟信号， 驱动计数器计数。 当收到一定数量的 TDM流数据时， 将数据封装分组发出。 同 时将分组发送时的计数器值， 即时间戳装入分组头。 接收端业务适配模块接 收分组， 将时间戳用于恢复发送端的业务时钟， 并利用该时钟将分组负载中 的 TDM数据以比特流的形式发出。
恢复时钟时不仅需要分组发送时的时间戳， 同时需要分组接收时的时间 戳， 这就必然引入分组网的分组延时特性。 自适应法的关键在于如何有效的 滤除 PDV ( Packet delay var iance , 分组延时抖动）对时钟恢复的损伤， 精 确恢复出发送端的时钟信号。 现有技术提供了一种减少分组延时抖动对时钟恢复的损伤的方法， 包括 以下步骤： 对接收到的数据包进行流量整形后输出写信号； 根据该写信号和 数字振荡器输出的读时钟， 求出先入先出緩冲器所緩存的数据量； 根据写信 号和求出的緩存数据量计算滤波参数； 根据该滤波参数求出恢复的读时钟。
在实现本发明的过程中， 发明人发现现有技术至少存在以下问题： 现有技术主要是通过滤波来减少分组延时抖动对时钟恢复的损伤， 而导 致接收端时间戳间隔变化的原因很多， 通过滤波方法很难适用于各种情况， 特别是当某一分组在网络中经历了很大的延时， 接收时间戳将产生突变， 这 会对时钟恢复带来严重损伤。
发明内容
本发明实施例提供一种提高时钟稳定度的方法及设备， 以提高时钟恢复 稳定度。
为达到上述目的， 本发明实施例一方面提供一种提高时钟稳定度的方法， 包括以下步骤：
当发送时间戳和接收时间戳的差值为突变值时， 对所述发送时间戳和接 收时间戳进行预处理；
根据所述预处理后的发送时间戳和接收时间戳获取业务时钟；
根据所述业务时钟发送时分复用数据。
本发明实施例另一方面提供一种提高时钟稳定度的设备， 包括： 判断单元， 用于判断发送时间戳和接收时间戳的差值是否为突变值； 接收时间戳；
业务时钟获取单元， 用于根据所述处理单元预处理后的发送时间戳和接 收时间戳获取业务时钟；
数据发送单元， 用于根据所述业务时钟获取单元获取的业务时钟发送时 分复用数据。
本发明实施例还提供一种提高时钟稳定度的装置， 所述提高时钟稳定度 的装置与数据接收装置、 数据发送装置相连， 所述数据发送装置用于根据所 述提高时钟稳定度的装置获取的业务时钟发送所述数据接收装置接收的时分 复用数据， 所述提高时钟稳定度的装置包括：
判断模块， 用于判断发送时间戳和接收时间戳的差值是否为突变值； 处理模块， 用于根据所述判断模块的判断结果预处理所述发送时间戳和 接收时间戳；
业务时钟获取模块， 用于根据所述处理模块预处理后的发送时间戳和接 收时间戳获取业务时钟。
与现有技术相比， 本发明实施例具有以下优点：
本发明实施例通过对时间戳的突变处理， 平滑了分组延时抖动， 减少了 分组延时抖动对时钟恢复的损伤， 改善了时钟恢复质量， 解决了时钟同步问 题。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例描述中所 需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发 明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前 提下， 还可以根据这些附图获得其他的附图。
图 1为自适应时钟恢复流程图；
图 2为本发明实施例一中一种提高时钟稳定度的方法流程图；
图 3为时间戳差值突变值和非突变值示意图；
图 4为本发明实施例二中一种提高时钟稳定度的方法流程图；
图 5为本发明实施例中突变值检测和修复的方法流程图；
图 6为本发明实施例中一种提高时钟稳定度的设备结构图；
图 7为本发明实施例中判断单元的结构图；
图 8为本发明实施例中业务时钟获取单元的结构图；
图 9为本发明实施例中一种提高时钟稳定度的装置结构图。
具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明的一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有 做出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例一提供了一种提高时钟稳定度的方法， 应用背景为采用自 适应法来恢复业务时钟， 如图 2所示， 该方法包括以下步骤：
步骤 s201, 判断发送时间戳 ST ( Sender Timestamp ) 和接收时间戳 RT ( Receiver Timestamp ) 的差值是否为突变值， 当该差值为突变值时， 对发 送时间戳和接收时间戳进行预处理。
其中， 判断发送时间戳 ST和接收时间戳 RT的差值是否为突变值的过程包 括： 比较当前收发时间戳差值与平均收发时间戳差值的相差幅度是否超出限 定范围， 如果是， 则检测随后 N个收发时间戳差值与平均收发时间戳差值的相 差幅度是否超出范围， N为一个变量， 根据对算法的需求 N可以灵活配置； 如 果随后 N个收发时间戳差值与平均收发时间戳差值的相差幅度没有保持超出 限定范围， 则为突变值。 如果当前收发时间戳差值与平均收发时间戳差值的 相差幅度没有超出限定范围， 则当前收发时间戳差值为非突变值； 或， 当前 收发时间戳差值与平均收发时间戳差值的相差幅度超出限定范围， 而在接下 来 N个收发时间戳与平均收发时间戳差值的相差幅度都保持超出限定范围， 则 当前收发时间戳差值为非突变值。
收发时间戳差值（RT-ST)的物理意义为对应分组的实际传输延时 Delay 和收发两端时钟偏差 off set之和：
ΔΤ = RT-ST = Delay + offset
传输延时 Delay和时钟偏差 off set中任何一个变化都会导致时间戳差值 的变化。 ΔΤ变化可能的原因可以包括下面的一种或几种：
1 ) 业务负载变化引起的排队延时变化；
2 ) CSMA/CD ( Carrier Sense Multiple Access/Collision Detect, 载 波监听多路访问 /冲突检测方法 ) 中多次重传产生的重传延时变化；
3)分组传输路径发生变化；
4)发送端时钟执行时间调整。 前三种情况可以导致分组传输延时 De lay变化， 最后一种情况可以导致收 发两端时钟偏差 off se t变化。 其中只有前两种情况会导致时间戳差值的突变。 时间戳差值的突变是指， 在所有时间戳差值中， 严重偏离大部分时间戳差值 所呈现出来的统计规律性的小部分时间戳差值。 如图 3所示， 左图中第 n个分 组的时间戳差值远离其它数值， 明显增大， 而周围数值基本保持不变， 所以 左图中第 n个分组的时间戳差值属于突变值。 右图中第 n个分组的时间戳差值 也呈现出数值增大， 但后续分组都呈现出数值增大的统计规律性， 所以右图 中第 n个分组的时间戳差值不属于突变值。
其中， 当该差值为突变值时， 对发送时间戳和接收时间戳进行预处理， 可以是： 当发送时间戳和接收时间戳的差值为突变值时， 将当前发送时间戳 和当前接收时间戳对应的当前收发时间戳差值， 替换为平均收发时间戳差值， 并根据替换后的当前收发时间戳差值计算新的平均收发时间戳差值。 预处理 后的发送时间戳和接收时间戳包括： 原有发送时间戳 ST、 原有接收时间戳 RT 和新的平均收发时间戳差值。
步骤 s 202 , 根据预处理后的发送时间戳和接收时间戳获取业务时钟。 锁 相计算突变值预处理后的发送时间戳、 接收时间戳和平均收发时间戳差值， 恢复出发送端的业务时钟。
步骤 s 203 , 根据所述业务时钟发送时分复用数据。
本发明实施例通过对时间戳的突变处理， 平滑了分组延时抖动， 减少了 分组延时抖动对时钟恢复的损伤， 改善了时钟恢复质量， 解决了时钟同步问 题。
本发明实施例二提供了一种提高时钟稳定度的方法， 应用背景为采用自 适应法来恢复业务时钟， 如图 4所示， 该方法包括以下步骤：
步骤 s401 , 接收分组数据， 记录当前接收时间戳， 并从分组数据中分离 出 TDM数据和发送时间戳。 按照发送时间戳由小到大的顺序分别存放 TDM数据、 发送时间戳和接收时间戳， TDM数据、 发送时间戳和接收戳保持——对应的关 系。 发送时间戳、 接收时间戳和 TDM数据分别对应存储在接收端的时间戳緩冲 区和数据緩冲区。 步骤 s 402 , 数据发送机制完成前一个数据分组发送的同时， 从数据緩冲 区读取当前分组的 TDM数据， 同时， 时间戳緩冲区将对应的发送时间戳和接收 时间戳发送到判断和处理单元。
步骤 s 403 , 检测和修复发送时间戳和接收时间戳差值的突变值。 判断发 送时间戳和接收时间戳的差值是否为突变值， 当为突变值时， 对发送时间戳 和接收时间戳进行预处理。 比较当前收发时间戳差值与平均收发时间戳差值 的相差幅度是否超出限定范围， 如果是， 则检测随后 N个时间戳差值与平均收 发时间戳差值的相差幅度是否保持超出限定范围； 如果在随后 N个时间戳差值 与平均收发时间戳差值的相差幅度没有保持超出限定范围， 则为突变值。 如 果当前收发时间戳差值与平均收发时间戳差值的相差幅度在限定范围内， 或， 当前收发时间戳差值与平均收发时间戳差值的相差幅度不在限定范围内， 而 在随后 N个时间戳差值与平均收发时间戳差值的相差幅度都保持超出限定范 围， 则当前收发时间戳差值为非突变值。 根据判断结果， 计算平均时间戳差 值。
步骤 s 404 , 根据预处理后的发送时间戳和接收时间戳获取业务时钟。 PLL
( Pha s e Locked Loop , 锁相环）接收突变值预处理后的时间戳， 包括发送时 间戳、 接收时间戳和平均收发时间戳差值， 根据接收到的突变值预处理后的 时间戳， 确认输出时钟信号与接收时钟信号的频差或相差幅度； 对输出时钟 信号与接收时钟信号的频差或相差进行平滑滤波， 滤去数据变化和其它不稳 定因素对整个模块的影响； 根据输出的频差或相差反相调节所述输出时钟信 号的频率或相位， 固定输出时钟信号和接收时钟信号频差或相差幅度， 恢复 出发送端的业务时钟。
步骤 s 405 , 数据发送机制接收 PLL恢复出的发送端的业务时钟， 根据该业 务时钟， 驱动数据发送机制推出 TDM比特流。
其中， 步骤 s 403中突变值检测和修复的方法如图 5所示， 包括以下步骤： 步骤 s 501 , 接收并检测第 n个分组时间戳对， 包括发送时间戳 ST和接收时 间戳 RT， 计算第 n个分组时间戳对的收发时间戳差值 ΔΤη。 步骤 s 502 , 判断第 η个分组时间戳对的收发时间戳差值 ΔΤη与平均收发时 间戳差值 ATaverage的相差幅度是否超出预定范围， 若是， 则执行步骤 s 503 ; 若否， 则执行步骤 s 507。
步骤 s 503 , 检测第 m=n+N个分组时间戳对， 计算第 m分组时间戳对的收发 时间戳差值 ATm。
步骤 s 504 , 判断第 m个时间戳对的收发时间戳差值 ATm与平均收发时间戳 差值 ATaverage相差幅度是否超出预定范围， 如果是， 则执行步骤 s 505 ; 如果 否， 则执行步骤 s 508。
步骤 s 505 , 检测第 m=m- 1个分组时间戳对。
步骤 s 506 , 判断 m是否大于 n , 是， 则执行步骤 s 504 , 计算第 m分组时间戳 对的收发时间戳差值 ATm; 否， 则执行步骤 s 507。
步骤 s 507 , 判定第 n个分组时间戳对的收发时间戳差值 ΔΤη为非突变值， 计算平均收发时间戳差值。
步骤 s 508 , 判定第 η个分组时间戳对的收发时间戳差值 ΔΤη为突变值， 且 将第 η个时间戳的收发时间戳差值 ΔΤη替换为平均收发时间戳差值。
本发明实施例二提供的一种提高时钟稳定度的方法， 通过分组检测突变 值， 对时间戳进行突变处理， 平滑了分组延时抖动， 减少了分组延时抖动对 时钟恢复的损伤， 改善了时钟恢复质量， 解决了时钟同步问题。 本发明实施例还提供了一种提高时钟稳定度的设备， 如图 6所示， 包括： 判断单元 61 0 , 用于分析来自緩冲区的时间戳， 判断发送时间戳和接收时 间戳的差值与平均收发时间戳差值的相差幅度是否超出限定范围。 如果超出， 则检测随后 Ν个收发时间戳差值与平均收发时间戳差值的相差幅度是否保持 超出限定范围， 如果随后 Ν个收发时间戳差值与平均收发时间戳差值的相差幅 度没有保持超出限定范围， 则为突变值。 如果当前收发时间戳差值与平均收 发时间戳差值的相差幅度没有超出限定范围， 或， 当前收发时间戳差值与平 均收发时间戳差值的相差幅度超出限定范围， 而随后 Ν个收发时间戳差值与平 均收发时间戳差值的相差幅度都保持超出限定范围， 则当前收发时间戳差值 为非突变值。
处理单元 620 , 用于根据判断单元 610的判断结果处理发送时间戳和接收 时间戳， 计算平均收发时间戳差值， 更新原有的平均收发时间戳差值。
业务时钟获取单元 630, 用于计算经过突变值预处理的发送时间戳、 接收 时间戳和平均收发时间戳差值， 恢复出发送端的业务时钟。 突变值预处理后 的发送时间戳和接收时间戳， 参与锁相计算， 恢复出发送端的业务时钟。 接 收突变值预处理的时间戳， 包括发送时间戳、 接收时间戳和平均收发时间戳 差值， 根据接收到的突变值预处理时间戳， 确定输出时钟信号与接收时钟信 号的频差或相差幅度； 对输出时钟信号与接收时钟信号的频差或相差进行平 滑滤波， 滤去数据变化和其它不稳定因素对整个模块的影响； 根据输出的频 差或相差反相调节所述输出时钟信号的频率或相位， 固定输出时钟信号和接 收时钟信号频差或相差幅度， 恢复出发送端的业务时钟。
数据发送单元 640 , 用于根据业务时钟获取单元 630恢复出的时钟信号发 送 TDM比特流。
其中， 判断单元 610结构如图 7所示， 还包括： 接收子单元 611 , 检测子单 元 612 , 判断子单元 613。
接收子单元 611 , 用于接收来自数据接收单元 650的时间戳对， 包括发送 时间戳和接收时间戳。
检测子单元 612 , 用于根据接收子单元 611接收的时间戳对和检测子单元 612存储的平均收发时间戳差值检测当前收发时间戳差值与平均收发时间戳 差值相差幅度是否在限定范围内， 将检测结果发送给判断子单元 613。 戳差值是否为突变值。
其中， 业务时钟获取单元 630结构如图 8所示， 包括： 鉴相子单元 631 , 滤 波子单元 632 , 调相子单元 633。 鉴相子单元 631 , 用于接收突变值预处理的时间戳， 包括发送时间戳、 接 收时间戳和平均收发时间戳差值， 根据接收到的突变值预处理的时间戳， 确 定输出时钟信号与接收时钟信号频差或相差幅度。
滤波子单元 632 , 用于对鉴相子单元 631输出时钟信号与接收时钟信号的 频差或相差进行平滑滤波， 滤去数据变化和其它不稳定因素对整个模块的影 响。
调相子单元 633 , 用于根据滤波子单元 632输出的频差或相差反相调节所 述输出时钟信号的频率或相位， 固定输出时钟信号和接收时钟信号频差或相 差幅度， 恢复出发送端的业务时钟。
本发明实施例提供的一种提高时钟稳定度的设备还包括： 数据接收单元 650 , 用于接收分组数据， 记录接收时间戳， 分离 TDM数据和发送时间戳， 并 将所述 TDM数据发送给所述数据发送单元 640 , 将所述发送时间戳和所述接收 时间戳发送给所述判断单元 610。 发送时间戳、 接收时间戳和 TDM数据分别对 应存储在时间戳緩冲区和数据緩冲区， 按照发送时间戳由小到大的顺序分别 存放数据和时间戳。 TDM数据和发送时间戳、接收时间戳保持——对应的关系。 排序机制可以有效减少分组乱序对时钟恢复的损伤。
本发明实施例还提供一种提高时钟稳定度的装置， 如图 9所示， 所述提高 时钟稳定度的装置与数据接收装置、 数据发送装置相连， 所述数据发送装置 用于根据所述提高时钟稳定度的装置获取的业务时钟发送所述数据接收装置 接收的时分复用数据， 所述提高时钟稳定度的装置包括：
判断模块 710 , 用于判断发送时间戳和接收时间戳的差值是否为突变值； 处理模块 720 , 用于根据所述判断模块 710的判断结果预处理所述发送时 间戳和接收时间戳；
业务时钟获取模块 730 , 用于根据所述处理模块 720预处理后的发送时间 戳和接收时间戳获取业务时钟。
其中， 判断模块 710进一步包括：
接收子模块 711 , 用于接收来自所述数据接收装置的所述发送时间戳和所 述接收时间戳； 检测子模块 712 , 用于根据所述接收子模块 71 1接收的所述发送时间戳和 所述接收时间戳和所述检测子模块 712存储的平均收发时间戳差值检测当前 收发时间戳差值与平均收发时间戳差值相差幅度是否在限定范围内；
突变值判断子模块 71 3 , 用于根据所述检测子模块 712发送的检测结果判 断所述当前收发时间戳差值是否为突变值。
上述处理模块 720可以进一步包括：
差值处理子模块 721 , 用于根据所述突变值判断子模块 71 3的判断结果计 算平均收发时间戳差值， 更新所述检测子模块 71 2存储的平均收发时间戳差 值。
或者， 上述处理模块 720可以进一步包括：
差值替换子模块， 用于根据所述突变值判断子模块 71 3的判断结果， 当所 述突变值判断子模块 71 3的判断结果为所述当前收发时间戳差值是突变值时， 将所述当前收发时间戳差值替换为所述检测子模块 712存储的平均收发时间 戳差值；
平均差值子模块， 用于当所述突变值判断子模块 71 3的判断结果为所述当 前收发时间戳差值是突变值时， 根据所述差值替换子模块替换后的当前收发 时间戳差值计算平均收发时间戳差值， 更新所述检测子模块 71 2存储的平均收 发时间戳差值； 或者， 当所述突变值判断子模块 71 3的判断结果为所述当前收 发时间戳差值不是突变值时， 直接计算平均收发时间戳差值， 更新所述检测 子模块 712存储的平均收发时间戳差值。
上述业务时钟获取模块 730进一步包括：
鉴相子模块 731 , 用于接收来自所述处理模块 720的突变值预处理时间戳， 确定输出时钟信号与接收时钟信号的频差或相差幅度；
滤波子模块 732 , 用于对所述鉴相子模块 731输出的频差或相差进行平滑 滤波；
调相子模块 733 , 用于根据所述滤波子模块 732输出的频差或相差反相调 节所述输出时钟信号的频率或相位， 固定输出时钟信号和接收时钟信号频差 或相差幅度。 上述模块可以分布于一个装置， 也可以分布于多个装置。 上述模块可以 合并为一个模块， 也可以进一步拆分成多个子模块。
本发明实施例提供的设备， 通过对时间戳的突变处理， 平滑了分组延时 抖动， 减少了分组延时抖动对时钟恢复的损伤， 改善了时钟恢复质量， 解决 了时钟同步问题。
通过以上的实施方式的描述， 本领域的技术人员可以清楚地了解到本发 明可以通过硬件实现， 也可以借助软件加必要的通用硬件平台的方式来实现。 基于这样的理解， 本发明的技术方案可以以软件产品的形式体现出来， 该软 件产品可以存储在一个非易失性存储介质（可以是 CD-ROM, U盘，移动硬盘等） 中， 包括若干指令用以使得一台计算机设备（可以是个人计算机， 服务器， 或者网络设备等）执行本发明各个实施例所述的方法。
本领域技术人员可以理解附图只是一个优选实施例的示意图， 附图中的 模块或流程并不一定是实施本发明所必须的。
本领域技术人员可以理解实施例中的装置中的模块可以按照实施例描述 进行分布于实施例的装置中， 也可以进行相应变化位于不同于本实施例的一 个或多个装置中。 上述实施例的模块可以合并为一个模块， 也可以进一步拆 分成多个子模块。
上述本发明实施例序号仅仅为了描述， 不代表实施例的优劣。
以上公开的仅为本发明的几个具体实施例， 但是， 本发明并非局限于此， 任何本领域的技术人员能思之的变化都应落入本发明的保护范围。

Claims

权 利 要 求 书
1、 一种提高时钟稳定度的方法， 其特征在于， 包括：
当发送时间戳和接收时间戳的差值为突变值时， 对所述发送时间戳和接 收时间戳进行预处理；
根据所述预处理后的发送时间戳和接收时间戳获取业务时钟；
根据所述业务时钟发送时分复用数据。
2、 如权利要求 1所述的方法， 其特征在于， 所述当发送时间戳和接收时 间戳的差值为突变值时的步骤之前， 还包括：
接收分组数据， 记录所述接收时间戳， 并从所述分组数据中分离所述时 分复用数据和所述发送时间戳。
3、 如权利要求 2所述的方法， 其特征在于， 所述分离所述时分复用数据 和所述发送时间戳包括：
按照所述发送时间戳由小到大的顺序分别存放所述时分复用数据、 所述 发送时间戳和所述接收时间戳， 所述时分复用数据、 所述发送时间戳和所述 接收时间戳保持——对应的关系。
4、 如权利要求 1所述的方法， 其特征在于， 判断发送时间戳和接收时间 戳的差值为突变值的步骤包括：
比较当前收发时间戳差值与平均收发时间戳差值的相差幅度是否超出限 定范围， 如果是， 则检测随后 N个收发时间戳差值与平均收发时间戳差值的 相差幅度是否超出限定范围；
如果所述随后 N个收发时间戳差值与平均收发时间戳的差值相差幅度没 有保持超出限定范围， 则所述发送时间戳和接收时间戳的差值为突变值。
5、 如权利要求 4所述的方法， 其特征在于， 所述对所述发送时间戳和接 收时间戳进行预处理包括：
将所述当前收发时间戳差值， 替换为所述平均收发时间戳差值。
6、 如权利要求 1所述的方法， 其特征在于， 所述根据所述预处理后的发 送时间戳和接收时间戳获取业务时钟包括：
根据所述突变值预处理后的发送时间戳和接收时间戳， 确定输出时钟信 号与接收时钟信号的频差或相差幅度；
对所述输出时钟信号与接收时钟信号的频差或相差进行平滑滤波； 根据所述平滑滤波后的频差或相差反相调节所述输出时钟信号的频率或 相位， 固定所述输出时钟信号和所述接收时钟信号频差或相差幅度， 恢复发 送端的业务时钟。
7、 一种提高时钟稳定度的设备， 其特征在于， 包括：
判断单元， 用于判断发送时间戳和接收时间戳的差值是否为突变值； 接收时间戳；
业务时钟获取单元， 用于根据所述处理单元预处理后的发送时间戳和接 收时间戳获取业务时钟。
8、 如权利要求 7所述的设备， 其特征在于， 所述判断单元包括： 接收子单元， 用于接收来自所述数据接收单元的所述发送时间戳和所述 接收时间戳；
检测子单元， 用于根据所述接收子单元接收的所述发送时间戳和所述接 收时间戳和所述检测子单元存储的平均收发时间戳差值检测当前收发时间戳 差值与平均收发时间戳差值相差幅度是否在限定范围内； 当前收发时间戳差值是否为突变值。
9、 如权利要求 8所述的设备， 其特征在于， 所述处理单元包括： 差值处理子单元， 用于根据所述突变值判断子单元的判断结果计算平均 收发时间戳差值， 更新所述检测子单元存储的平均收发时间戳差值。
10、 如权利要求 8所述的设备， 其特征在于， 所述处理单元包括： 差值替换子单元， 用于根据所述突变值判断子单元的判断结果， 当所述 述当前收发时间戳差值替换为所述检测子单元存储的平均收发时间戳差值； 收发时间戳差值是突变值时， 根据所述差值替换子单元替换后的当前收发时 间戳差值计算平均收发时间戳差值， 更新所述检测子单元存储的平均收发时 间戳差值； 或者， 当所述突变值判断子单元的判断结果为所述当前收发时间 戳差值不是突变值时， 直接计算平均收发时间戳差值， 更新所述检测子单元 存储的平均收发时间戳差值。
11、 如权利要求 7 所述的设备， 其特征在于， 所述业务时钟获取单元包 括：
鉴相子单元， 用于接收来自所述处理单元的突变值预处理时间戳， 确定 输出时钟信号与接收时钟信号的频差或相差幅度；
滤波子单元， 用于对所述鉴相子单元输出的频差或相差进行平滑滤波； 调相子单元， 用于根据所述滤波子单元输出的频差或相差反相调节所述 输出时钟信号的频率或相位， 固定输出时钟信号和接收时钟信号频差或相差 幅度。
12、 如权利要求 7至 11任一项所述的设备， 其特征在于， 所述设备还包 括：
数据接收单元， 用于接收分组数据， 记录接收时间戳， 分离时分复用数 据和发送时间戳， 并将所述时分复用数据发送给数据发送单元， 将所述发送 时间戳和所述接收时间戳发送给所述判断单元；
数据发送单元， 用于根据所述业务时钟获取单元获取的业务时钟， 发送 所述数据接收单元接收的时分复用数据。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101674174B (zh) * 2008-09-12 2013-06-05 华为技术有限公司 一种提高时钟稳定度的方法及设备
GB2488063B (en) * 2009-11-20 2015-08-26 Anue Systems Inc Method, system and computer program product for measuring a communication from a first device to a second device
CN102340365B (zh) * 2010-07-27 2014-06-11 中兴通讯股份有限公司 一种基于时戳的时钟恢复方法及装置
CN101951304B (zh) * 2010-08-31 2012-04-18 华为技术有限公司 微波传输装置
CN103283193B (zh) * 2011-01-04 2016-01-13 纳派泰克股份公司 用于接收和转发数据的装置和方法
CN102255683B (zh) * 2011-07-08 2014-10-15 电子科技大学 一种用于高速光时分复用系统的时钟恢复方法
EP2782272B1 (en) * 2011-11-17 2022-05-04 ZTE Corporation Method and apparatus for packet timing recovery
CN102946330B (zh) * 2012-09-29 2017-03-15 华为技术有限公司 网络丢包测量方法、装置和系统
CN104378192B (zh) * 2013-08-15 2017-08-04 加微通信技术（上海）有限公司 差分异常探测和补偿方法、装置及高精度时钟恢复系统
JP2016131287A (ja) * 2015-01-13 2016-07-21 三菱電機株式会社 通信システム、送信装置および受信装置
CN106603183B (zh) * 2015-10-15 2019-11-15 中兴通讯股份有限公司 一种时间戳过滤方法及装置
CN107241155A (zh) * 2016-03-28 2017-10-10 中兴通讯股份有限公司 一种自适应时钟恢复方法及装置
US10728130B2 (en) * 2016-04-21 2020-07-28 Cisco Technology, Inc. Distributed stateless inference of hop-wise delays and round-trip time for internet protocol traffic
KR101701389B1 (ko) 2016-07-22 2017-02-13 주식회사 링슨 야드 트랙터 충전 설비
KR101701390B1 (ko) 2016-08-30 2017-02-01 주식회사 링슨 전원 공급 효율을 개선할 수 있는 야드 트랙터 충전 설비
CN106357459B (zh) * 2016-11-02 2019-09-17 瑞斯康达科技发展股份有限公司 一种延迟抖动处理的方法及装置、时钟同步装置
CN112866135A (zh) * 2018-01-26 2021-05-28 华为技术有限公司 发送报文的方法、第一网络设备及计算机可读存储介质
CN111830892B (zh) * 2019-04-22 2022-09-23 新疆金风科技股份有限公司 风力发电机组统计时间校准方法和装置、存储介质
CN112821981B (zh) * 2021-01-19 2023-03-24 柳州达迪通信技术股份有限公司 基于光传送网的业务恢复时钟提取方法、系统及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1496072A (zh) * 2002-08-24 2004-05-12 ���ֿ˰뵼�����޹�˾ 自适应时钟恢复
CN1551556A (zh) * 2003-03-07 2004-12-01 卓联半导体有限公司 在分组网上的时钟同步
CN1581845A (zh) * 2003-08-01 2005-02-16 华为技术有限公司 对时分复接业务进行时钟恢复的装置及其方法
US20060291479A1 (en) * 2005-06-28 2006-12-28 Israel Sasson System and method for high precision clock recovery over packet networks
US7289538B1 (en) * 2001-08-14 2007-10-30 Atrica Israel Ltd. Clock reconstruction for time division multiplexed traffic transported over asynchronous ethernet networks

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2786964B1 (fr) * 1998-12-03 2001-01-05 Cit Alcatel Procede et systeme pour asservir une frequence via un reseau de transmission asynchrone et reseau radiotelephonique incluant ce systeme
US7191355B1 (en) * 2002-02-19 2007-03-13 Nortel Networks Limited Clock synchronization backup mechanism for circuit emulation service
US7020791B1 (en) * 2002-09-19 2006-03-28 Nortel Networks Limited Clock recovery using a double-exponential smoothing process
US7079554B2 (en) * 2002-10-16 2006-07-18 Terasync, Ltd. System and method for synchronizing between communication terminals of asynchronous packets networks
US7106823B2 (en) * 2002-11-15 2006-09-12 Broadcom Corporation System and method for accelerated clock synchronization of remotely distributed electronic devices
US7474624B2 (en) * 2003-05-29 2009-01-06 Motorola, Inc. Method and apparatus for reducing delay jitter
US7415044B2 (en) * 2003-08-22 2008-08-19 Telefonaktiebolaget Lm Ericsson (Publ) Remote synchronization in packet-switched networks
US8238376B2 (en) * 2005-04-13 2012-08-07 Sony Corporation Synchronized audio/video decoding for network devices
US20070104228A1 (en) * 2005-11-09 2007-05-10 Resolute Networks, Ltd. Asymmetric Differential Timing
GB2443867A (en) * 2006-03-21 2008-05-21 Zarlink Semiconductor Ltd Timing source with packet size controller providing a distribution of packet sizes
US7711009B2 (en) * 2006-09-29 2010-05-04 Agere Systems Inc. Methods and apparatus for timing synchronization in packet networks
CN101674174B (zh) * 2008-09-12 2013-06-05 华为技术有限公司 一种提高时钟稳定度的方法及设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7289538B1 (en) * 2001-08-14 2007-10-30 Atrica Israel Ltd. Clock reconstruction for time division multiplexed traffic transported over asynchronous ethernet networks
CN1496072A (zh) * 2002-08-24 2004-05-12 ���ֿ˰뵼�����޹�˾ 自适应时钟恢复
CN1551556A (zh) * 2003-03-07 2004-12-01 卓联半导体有限公司 在分组网上的时钟同步
CN1581845A (zh) * 2003-08-01 2005-02-16 华为技术有限公司 对时分复接业务进行时钟恢复的装置及其方法
US20060291479A1 (en) * 2005-06-28 2006-12-28 Israel Sasson System and method for high precision clock recovery over packet networks

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