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WO2009069616A1 - データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法 - Google Patents

データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法 Download PDF

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Publication number
WO2009069616A1
WO2009069616A1 PCT/JP2008/071382 JP2008071382W WO2009069616A1 WO 2009069616 A1 WO2009069616 A1 WO 2009069616A1 JP 2008071382 W JP2008071382 W JP 2008071382W WO 2009069616 A1 WO2009069616 A1 WO 2009069616A1
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WO
WIPO (PCT)
Prior art keywords
coding
data processing
check matrix
ldpc
code
Prior art date
Application number
PCT/JP2008/071382
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English (en)
French (fr)
Inventor
Takashi Yokokawa
Makiko Yamamoto
Satoshi Okada
Ryoji Ikegaya
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to TW098103711A priority Critical patent/TW201034392A/zh
Publication of WO2009069616A1 publication Critical patent/WO2009069616A1/ja

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
    • H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488—Multiresolution systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
  • Dc Digital Transmission (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

本発明は、エラーに対する耐性を向上させることができるデータ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法に関する。 LDPC符号化部２１は、例えば、符号長が64800ビットで、符号化率が2/3のLDPC符号による符号化を行う。LDPC符号の検査行列は、その検査行列の、符号長及び符号化率に応じた情報長に対応する情報行列の1の要素の位置を360列ごとに表す検査行列初期値テーブルによって定まる情報行列の1の要素を、列方向に360列ごとの周期で配置して構成される。検査行列初期値テーブルは、DVB-S.2の規格に規定されているものとは異なるものになっている。本発明は、LDPC符号化を行う符号化装置に適用できる。
PCT/JP2008/071382 2007-11-26 2008-11-26 データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法 WO2009069616A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW098103711A TW201034392A (en) 2008-03-18 2009-02-05 Data process device, data process method, coding device, coding method

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2007304690 2007-11-26
JP2007-304690 2007-11-26
JP2007304689 2007-11-26
JP2007-304689 2007-11-26
JP2008-070467 2008-03-18
JP2008070467 2008-03-18

Publications (1)

Publication Number Publication Date
WO2009069616A1 true WO2009069616A1 (ja) 2009-06-04

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PCT/JP2008/071312 WO2009069580A1 (ja) 2007-11-26 2008-11-25 データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法
PCT/JP2008/071382 WO2009069616A1 (ja) 2007-11-26 2008-11-26 データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法

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PCT/JP2008/071312 WO2009069580A1 (ja) 2007-11-26 2008-11-25 データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法

Country Status (18)

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US (2) US8402337B2 (ja)
EP (4) EP2214321B1 (ja)
JP (2) JP5273054B2 (ja)
KR (2) KR101481854B1 (ja)
CN (2) CN101911505B (ja)
AU (2) AU2008330816B2 (ja)
BR (2) BRPI0820163B1 (ja)
CO (1) CO6311122A2 (ja)
DK (2) DK2509270T3 (ja)
EA (2) EA021906B1 (ja)
ES (4) ES2636371T3 (ja)
MY (2) MY155083A (ja)
NZ (2) NZ585421A (ja)
PL (3) PL2509270T3 (ja)
PT (2) PT2509270T (ja)
TW (1) TW200939639A (ja)
WO (3) WO2009069513A1 (ja)
ZA (1) ZA201003529B (ja)

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