WO2009031392A1 - 貼り合わせウェーハの製造方法 - Google Patents
貼り合わせウェーハの製造方法 Download PDFInfo
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- WO2009031392A1 WO2009031392A1 PCT/JP2008/064505 JP2008064505W WO2009031392A1 WO 2009031392 A1 WO2009031392 A1 WO 2009031392A1 JP 2008064505 W JP2008064505 W JP 2008064505W WO 2009031392 A1 WO2009031392 A1 WO 2009031392A1
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- Prior art keywords
- wafer
- layer
- active layer
- oxygen ion
- bonding
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Definitions
- the present invention is intended to effectively prevent the deterioration of surface roughness and the generation of crystal defects particularly caused by the oxygen ion implanted layer in the method of manufacturing a bonded wafer.
- a bonded wafer As a general method of manufacturing a bonded wafer, another silicon wafer is bonded to one silicon wafer on which an oxide film (insulating film) is formed, and one side of this bonded silicon wafer is used.
- the SOI layer is formed by grinding and polishing (polishing method), or by implanting oxygen ions into the silicon I 18 and performing high-temperature annealing to bury the oxide film inside the silicon wafer. And forming the upper part of the oxide film as an SOI layer (S1M0X), implanting hydrogen ions, etc.
- a method of forming an SOI layer is known by forming a layer and then laminating it with a silicon wafer for a supporting substrate, and then peeling it off by the above ion implantation layer by heat treatment. That.
- the grinding and polishing method is inferior in the thickness uniformity of the active layer.
- the inventors firstly made a process combining oxygen ion implantation and grinding / polishing methods, that is,
- a method for producing a bonded wafer comprising directly bonding a wafer for an active layer with or without an insulating film to a wafer for a support layer and then thinning the wafer for the active layer,
- a method for producing a bonded wafer characterized in that the time-series coupling is as follows. Was developed and disclosed in Patent Document 1.
- Patent Document 1 it is possible to provide a directly bonded wafer having excellent thickness uniformity of the active layer and relatively few defects as evaluated by a transmission electron microscope (TEM).
- TEM transmission electron microscope
- Patent Document 1 Japanese Patent Application No. 2006—184237 Specification
- oxygen ion implantation is performed with an acceleration voltage of 150 keV and a dose of:
- the present invention advantageously solves the above-mentioned problems, and does not require a special furnace or the like, and does not cause a cost increase due to a decrease in yield. It is an object of the present invention to propose an advantageous manufacturing method.
- the present invention is based on the above findings.
- the gist configuration of the present invention is as follows.
- a method for producing a bonded wafer comprising: bonding an active layer wafer and a supporting layer wafer directly or not via an insulating film, and then reducing the thickness of the active layer wafer. There, (1) a step of implanting oxygen ions into the active layer wafer;
- the dose is 5 ⁇ 10 15 while the temperature of the active layer wafer is kept at 200 ° C. or lower.
- the accumulated residence time in the temperature region of 1000 ° C. or higher of the oxygen ion implanted layer is set to be within 1 h after the oxygen ion implanted step until the step of exposing the oxygen ion implanted layer. 1.
- FIG. 1 is a diagram showing a process flow of the present invention.
- FIG. 2 (a) is a cross-sectional TEM photograph of a wafer subjected to heat treatment after oxygen ion implantation according to the conventional conditions and (b) according to the present invention conditions.
- FIG. 3 A diagram showing the surface roughness of bonded wafers fabricated under various ion implantation conditions.
- a bonded wafer In order to fabricate a bonded wafer, two silicon wafers, an active layer wafer and a support layer wafer, are bonded together.
- an insulating film In the present invention, an insulating film ( Of course, the present invention can also be applied to the case of bonding directly without using such an insulating film.
- the type, concentration, oxygen concentration, etc. of the dough pan are not limited as long as the bonding wafer has a surface roughness suitable for bonding.
- wafers with no or few COPs are preferred.
- COP can be reduced by optimizing CZ pulling conditions to reduce COP, by applying high-temperature heat treatment at 1000 ° C or higher in a reducing atmosphere after wafer mirror finishing, and by using Si on the wafer by CVD. It is possible to apply a method such as a epitaxial growth method.
- the acceleration voltage at the time of oxygen ion implantation can be appropriately selected according to the thickness of the active layer of the final product, and is not particularly limited. Therefore, the acceleration voltage of a normal oxygen ion implanter may be about 100 to 300 keV.
- the dose at the time of oxygen ion implantation needs to be in the range of 5 ⁇ 10 15 to 5 ⁇ 10 16 atoms / m 2 . This is because if the dose during oxygen ion implantation is less than 5 X 10 15 atoms / m 2 , the Si amorphous layer containing oxygen atoms is not sufficiently formed, and the polishing stop cannot be performed accurately. Yes. On the other hand, if it exceeds 5 X 10 16 atoms / m 2 , the entire surface layer becomes amorphous and the surface active layer does not become a single crystal.
- the substrate temperature at the time of ion implantation needs to be 200 ° C. or lower. If the temperature exceeds 200 ° C, the amorphous layer will not be sufficiently formed. It is preferably room temperature (about 20 ° C) or more and 100 ° C or less. Although it can be carried out at room temperature or lower, it is necessary to add a function to the injector to forcibly cool the wafer.
- oxygen ion implantation may be divided into a plurality of divided implantations, and cleaning may be performed during that time.
- a heat treatment at a temperature of 1100 ° C. or lower after oxygen ion implantation and before bonding.
- oxygen implanted near the outermost surface during oxygen ion implantation is diffused outward by heat treatment to lower the oxygen concentration, and oxygen precipitation near the outermost surface during bonding strengthening heat treatment. This contributes to the suppression of objects, and as a result, the defect density can be further reduced.
- Ar, H 2 or a mixed atmosphere thereof is advantageously suitable.
- Figures 2 (a) and 2 (b) show a comparison of cross-sectional TEM photographs of wafers that have been heat-treated after implantation of oxygen ions according to the conventional conditions and the present invention conditions.
- the oxygen ion implantation conditions and heat treatment conditions are as follows.
- Oxygen ion implantation acceleration voltage 200 keV, dose: 2 X 10 17 atoms m 2 , substrate temperature: 450 ° C
- Oxygen ion implantation acceleration voltage 200 keV, dose: 2 X 10 16 atoms / cm 2
- Substrate temperature room temperature
- the wafer for active layer and the substrate for support layer: L 18 are bonded together.
- an insulating film may be used, or an insulating film may be used directly. You can also.
- the insulating film includes an oxide film (Si0 2 ) and a nitride film (Si 3 N 4 ) Etc. are suitable.
- As a film forming method heat treatment in an oxidizing atmosphere or a nitrogen atmosphere is performed.
- thermal oxidation in addition to oxygen gas, wet oxidation using water vapor can be used.
- the insulating film may be formed on the surface side substrate before oxygen ion implantation, or after the implantation.
- the insulating film can be formed on the active layer wafer, the support layer wafer, or both the active layer and support layer wafers.
- the bonding strength is not sufficient at a bonding temperature of 1000 ° C or less. If there is a risk of peeling depending on the conditions after grinding (polishing) (polishing speed), the bonding strength In order to increase the resistance, it is advantageous to subject the silicon surface before bonding to an activation treatment with plasma using oxygen'nitrogen ⁇ ⁇ ⁇ ⁇ 2 ⁇ Ar or a mixed atmosphere thereof.
- This heat treatment performed to increase the bonding strength is performed at a temperature of 1000 ° C. or higher in order to sufficiently increase the bonding strength, but the holding time is preferably within 1 h.
- the atmosphere is not particularly limited, an oxide film having a thickness of 150 nm or more is preferably provided as an oxidizing atmosphere in order to protect the wafer back surface in the next grinding step.
- the grinding of the wafer for the active layer of the bonded wafer is carried out by mechanical processing. In this grinding, a part of the active layer wafer is left on the surface side of the oxygen ion implanted layer.
- the thickness of part of the remaining active layer wafer is not limited.
- the remaining film Si thickness is preferably about 3 to 10 / m.
- the active layer wafer is further polished to expose the oxygen ion implanted layer.
- This polishing method is preferably performed while supplying an abrasive having an abrasive concentration of 1% by mass or less.
- a polishing liquid examples include an alkaline solution having an abrasive grain (for example, silica) concentration of less than mass%.
- an alkaline solution an inorganic alkaline solution (KOH, NaOH, etc.), an organic alkaline solution (eg, piperazine etheramine, etc. containing amine as a main component) or a mixed solution thereof is suitable.
- the abrasive concentration is 1% by mass or less, priority is given to a chemical polishing action that almost eliminates the mechanical polishing action by the abrasive grains. Then, a part of the active layer wafer (Si layer) is polished by the chemical polishing action by the alkaline solution. Since the alkaline solution has a high etching rate ratio of Si / (Si amorphous layer containing oxygen atoms), the Si layer, which is part of the active layer wafer, can be polished efficiently, but contains oxygen atoms. The Si amorphous layer is hardly polished. Therefore, even if the mechanical accuracy of the polishing apparatus is not sufficient, the oxygen ion implanted layer is hardly polished, and only the Si layer is polished. As a result, the oxygen ion implanted layer can be uniformly exposed.
- the terrace (outermost area of 1 to 3 mm where the two wafers are not bonded together) and the boundary of the bonded area become smooth, and particle generation is suppressed. Note that only the terrace portion may be polished before polishing.
- the accumulated residence time in the above temperature range is preferably within 1 h. I mean,
- the Si amorphous material containing oxygen atoms formed during oxygen ion implantation may recrystallize.
- the treatment time is not particularly limited as long as the treatment temperature during the heat treatment is 1000 ° C. or lower.
- Exposed oxygen ion implanted layer Si amorphous containing oxygen atoms, consisting of a part of recrystallized Si and Si0 2.
- a removal method an etching method, an oxidation + etching method, polishing, or the like can be applied.
- Oxygen ion implanted layer the oxygen dose for a complete Si0 2 layer, since the heat treatment is selected not name conditions sufficient, ⁇ the etching to remove the HF solution, Si to remove Si0 2 alkali solution or etching conditions such as performing the HF solution divided Si0 2 and produced by oxidizing a SC1 solution or ozone solution to oxidize Si alternately, are preferred.
- This method includes a step of forming an oxide film having a predetermined thickness on the exposed surface of the oxygen ion implanted layer, and a step of removing the oxide film.
- the oxidation treatment may be performed in an oxidizing atmosphere, but the treatment temperature is not particularly limited, but is preferably an oxidizing atmosphere of 600 to 1000 ° C.
- the amorphous oxygen ion implanted layer is to suppress the deterioration of the surface roughness due to the Si0 2 particles generated by the recrystallization is preferably fixture 600 ⁇ 900 ° C to be processed at low temperatures More preferred.
- the thickness of the oxide film is not particularly limited, but there is a crystal defect layer in the oxygen ion implanted layer. If present, the thickness is preferably about 100 to 500 nm under the oxygen ion implantation conditions of the present invention, which is preferably set to be equal to or greater than the thickness. If the thickness of the oxide film is less than 100 nm, the Si amorphous layer cannot be sufficiently removed under the oxygen ion implantation conditions of the present invention. On the other hand, if the thickness exceeds 500 nm, the in-plane uniformity of the oxide film is disrupted, resulting in an active layer film. Thickness uniformity deteriorates.
- cleaning with HF solution may be used, or etching with hydrogen gas, Ar gas, or gas containing HF may be used.
- etching with hydrogen gas, Ar gas, or gas containing HF may be used.
- the above oxidation treatment and removal treatment may be performed a plurality of times. As a result, it is possible to further reduce the thickness of the active layer while maintaining the flattened surface roughness.
- the bonded wafer surface after removal of the oxygen ion implanted layer is rough compared to mirror polishing, and thus needs to be flat.
- gas etching composed of gas “ion” radicals that can be heat-treated in a reducing atmosphere, polished, and etched by Si can be applied.
- Roughness is improved by slightly polishing the bonded surface.
- the polishing allowance is preferably about 10 to 500 nm. If it is less than 10 nm, the roughness cannot be improved sufficiently, while if it exceeds 500 nm, the film thickness uniformity of the active layer deteriorates. By this treatment, the surface roughness (RMS) can be reduced to 0.5 nm or less.
- the roughness of the bonded wafer surface is improved by heat treatment in an atmosphere of Ar, H 2 or a mixture thereof.
- the treatment temperature is preferably about 1000 ° C to 1300 ° C.
- the processing time needs to be longer as the temperature is lower, preferably about 1 to 2 hours at 1000 to 1200 ° C, about 10 to 30 minutes at 1200 to 1250 ° C, and about 1 to 5 minutes at 1250 or more. ,.
- High temperature above the above temperature and time "Long-time heat treatment, etching in reducing atmosphere Due to the action, the in-plane uniformity of the active layer may be deteriorated.
- the heat treatment from the bonding to the removal of the oxygen ion implanted layer is limited to 1 h or less in the temperature range of 1000 ° C or higher, so that a sufficient bonding strength is always obtained. Is not limited. Therefore, a planarization treatment at a temperature of 1 100 ° C. or higher where the bonding strength is improved after removing the oxygen ion implanted layer is more preferable.
- heat treatment at 1 100 ° C or higher is not necessarily required.
- a resistance heating type vertical furnace capable of processing a plurality of sheets at the same time or a lamp heating type RTA (rapid heating / cooling furnace) that processes each sheet is suitable.
- RTA is effective for processing above 1200 ° C.
- the surface roughness (RMS) can be reduced to 0.5 nm or less as in the case of the polishing method.
- the removal of the surface oxide film generated by this heat treatment may be performed by cleaning with HF liquid or by etching using hydrogen gas, Ar gas, or gas containing HF.
- silicon wafers having different crystal orientations are directly bonded (for example, bonding of 110 crystal and 100 crystal or bonding of 1 1 1 crystal and 100 crystal). It is also possible to make a combined woofer.
- Two silicon wafers with a diameter of 300 mm were prepared by slicing from a silicon ingot grown using the CZ method and boron as a dopant.
- the crystal orientation of one of the two silicon wafers was (100), and this was used as the active layer wafer.
- the crystal orientation of the other silicon wafer was (1 10), and this was used as a support layer wafer.
- the (100) wafer was treated in an oxidizing atmosphere at 1000 ° C for 3 hours to form an oxide film with a thickness of 150 nm.
- oxygen ions were implanted from the surface of the active layer wafer (100) wafer at an acceleration voltage of 200 keV.
- the substrate temperature was changed from room temperature to less than 200 ° C., and the dose was changed in the range of 1 ⁇ 10 15 to 1 ⁇ 10 17 atoms / m 2 .
- an oxygen ion implanted layer was formed at a depth of about 450 nm from the surface of the active layer wafer.
- both I-has were washed with HF + ozone to remove particles on the bonding surface, and then both wafers were bonded together.
- the heat treatment condition is 950 ° C for 1 hour in an oxidizing gas atmosphere.
- a 150 nm-thick oxide film was applied to form a back surface protective film during post-processing.
- the wafer for active layer of the bonded wafer was ground by a predetermined thickness from the surface using a grinding machine. That is, a grinding process was performed to leave only a part of the active layer wafer (film thickness approximately 5 ⁇ m) on the surface side of the oxygen ion implanted layer.
- an abrasive containing abrasive grains having an abrasive grain (silica) concentration of 1% by mass or less As an abrasive, an alkaline solution having an abrasive concentration of 1% by mass or less was used.
- This alkaline solution is an organic alkaline solution and contains an amine as a main component (for example, piperazine, ethylenediamine).
- the obtained oxygen ion implantation layer was uniformly formed in the surface of the bonded wafer, and as a result, it was confirmed that the oxygen ion implantation layer uniformly formed in the surface was exposed.
- the wafer was subjected to wet oxidation at a temperature of 950 ° C for 0.5 hours in an oxidizing atmosphere.
- oxide film having a predetermined thickness is formed on the exposed surface of the oxygen ion implanted layer, Si amorphous layer containing oxygen atoms becomes all oxide film (Si0 2).
- this oxide film was removed by HF etching (HF liquid composition: 10 ⁇ 1 ⁇ 2, temperature: 20 ° C.).
- HF liquid composition 10 ⁇ 1 ⁇ 2, temperature: 20 ° C.
- the bonded wafer was washed by the following treatment.
- the ozone concentration is 5 PP m
- an aqueous solution in which 0.06% by mass of citrate is mixed as an organic acid with respect to pure water, and then into an aqueous solution in which 0.05% by mass of hydrofluoric acid is added to an aqueous solution of dissolved ozone.
- the solution was soaked in an aqueous solution to which 0.6% by mass of citrate was added, and finally in a dissolved ozone solution at room temperature with an ozone concentration of 5 ppm.
- the treatment time was 5 minutes each, and the temperature was room temperature.
- heat treatment was performed at 1 100 ° C. for 2 hours in an argon gas atmosphere to complete the bonding wafer.
- the film thickness of the active layer thus obtained was 100 to 200 nm, and the variation of the film thickness distribution in the plane was within 10 to 20 o / o .
- a bonded wafer was produced under the same conditions as in Example 1 except that the (100) active layer wafer and the (110) support layer wafer were bonded without using an insulating film (oxide film).
- the film thickness of the active layer thus obtained was 250 to 350 nm, and the variation of the film thickness distribution in the plane was within 10 to 20 o / o .
- Example 2 the surface roughness of the bonded wafers obtained in Example 1 and Example 2 was investigated.
- the measurement was AFM and the evaluation field was 10 X 10 m.
- FIG. 3 also shows, for comparison, a substrate temperature: 450 ° C, a dose of the note input of oxygen ions was carried out at high temperature and high dose conditions according to 2 X 10 17 at O ms N conventional methods that m 2 The survey results are also shown.
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Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08792435.3A EP2187429B1 (en) | 2007-09-07 | 2008-08-06 | Bonding wafer manufacturing method |
US12/676,874 US8003494B2 (en) | 2007-09-07 | 2008-08-06 | Method for producing a bonded wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-232818 | 2007-09-07 | ||
JP2007232818A JP5499428B2 (ja) | 2007-09-07 | 2007-09-07 | 貼り合わせウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
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WO2009031392A1 true WO2009031392A1 (ja) | 2009-03-12 |
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ID=40428714
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PCT/JP2008/064505 WO2009031392A1 (ja) | 2007-09-07 | 2008-08-06 | 貼り合わせウェーハの製造方法 |
Country Status (6)
Country | Link |
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US (1) | US8003494B2 (ja) |
EP (1) | EP2187429B1 (ja) |
JP (1) | JP5499428B2 (ja) |
KR (1) | KR101071509B1 (ja) |
TW (1) | TW200931541A (ja) |
WO (1) | WO2009031392A1 (ja) |
Cited By (4)
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JP2014510418A (ja) * | 2011-04-08 | 2014-04-24 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウェーハを永久的に結合する方法 |
US10083933B2 (en) | 2011-01-25 | 2018-09-25 | Ev Group E. Thallner Gmbh | Method for permanent bonding of wafers |
CN108780776A (zh) * | 2015-11-20 | 2018-11-09 | 环球晶圆股份有限公司 | 使半导体表面平整的制造方法 |
US10825793B2 (en) | 2011-04-08 | 2020-11-03 | Ev Group E. Thallner Gmbh | Method for permanently bonding wafers |
Families Citing this family (4)
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JP2010135538A (ja) * | 2008-12-04 | 2010-06-17 | Sumco Corp | 貼り合わせウェーハの製造方法 |
KR20200128205A (ko) * | 2012-03-28 | 2020-11-11 | 가부시키가이샤 니콘 | 기판 접합 장치 및 기판 접합 방법 |
FR3028664B1 (fr) * | 2014-11-14 | 2016-11-25 | Soitec Silicon On Insulator | Procede de separation et de transfert de couches |
JP6473970B2 (ja) * | 2015-10-28 | 2019-02-27 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
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- 2008-08-06 EP EP08792435.3A patent/EP2187429B1/en active Active
- 2008-08-06 US US12/676,874 patent/US8003494B2/en active Active
- 2008-08-06 WO PCT/JP2008/064505 patent/WO2009031392A1/ja active Application Filing
- 2008-08-28 TW TW097132921A patent/TW200931541A/zh unknown
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10083933B2 (en) | 2011-01-25 | 2018-09-25 | Ev Group E. Thallner Gmbh | Method for permanent bonding of wafers |
JP2014510418A (ja) * | 2011-04-08 | 2014-04-24 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウェーハを永久的に結合する方法 |
US10825793B2 (en) | 2011-04-08 | 2020-11-03 | Ev Group E. Thallner Gmbh | Method for permanently bonding wafers |
CN108780776A (zh) * | 2015-11-20 | 2018-11-09 | 环球晶圆股份有限公司 | 使半导体表面平整的制造方法 |
CN108780776B (zh) * | 2015-11-20 | 2023-09-29 | 环球晶圆股份有限公司 | 使半导体表面平整的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2187429A4 (en) | 2011-03-02 |
TW200931541A (en) | 2009-07-16 |
US8003494B2 (en) | 2011-08-23 |
TWI363388B (ja) | 2012-05-01 |
KR20100040329A (ko) | 2010-04-19 |
JP5499428B2 (ja) | 2014-05-21 |
US20100248447A1 (en) | 2010-09-30 |
JP2009065039A (ja) | 2009-03-26 |
EP2187429B1 (en) | 2014-09-17 |
KR101071509B1 (ko) | 2011-10-10 |
EP2187429A1 (en) | 2010-05-19 |
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