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WO2008053556A1 - Dispositif d'affichage à plasma et son procédé de commande - Google Patents

Dispositif d'affichage à plasma et son procédé de commande Download PDF

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Publication number
WO2008053556A1
WO2008053556A1 PCT/JP2006/321952 JP2006321952W WO2008053556A1 WO 2008053556 A1 WO2008053556 A1 WO 2008053556A1 JP 2006321952 W JP2006321952 W JP 2006321952W WO 2008053556 A1 WO2008053556 A1 WO 2008053556A1
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WO
WIPO (PCT)
Prior art keywords
capacitive load
voltage
electrode
circuit
coil
Prior art date
Application number
PCT/JP2006/321952
Other languages
English (en)
Japanese (ja)
Inventor
Akira Otsuka
Tetsuya Sakamoto
Akihiro Takagi
Original Assignee
Hitachi Plasma Display Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Plasma Display Limited filed Critical Hitachi Plasma Display Limited
Priority to PCT/JP2006/321952 priority Critical patent/WO2008053556A1/fr
Publication of WO2008053556A1 publication Critical patent/WO2008053556A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating

Definitions

  • the present invention relates to a plasma display device and a driving method thereof.
  • a power recovery circuit that recovers charging / discharging power of a capacitive load serving as a display unit is provided.
  • the power consumption is reduced by collecting the charge / discharge power of the capacitive load related to the image display using the power recovery circuit (for example, see Patent Documents 1 and 2).
  • FIG. 9 is a diagram showing a driving circuit of a conventional plasma display device.
  • Figure 9 shows the sustain circuit in the drive circuit.
  • the sustain circuit is a circuit for generating the sustain discharge pulse shown in FIG. 10, which is applied to the capacitive load serving as the display means.
  • a sustain discharge is performed between the electrodes of the capacitive load selected according to the image to be displayed, and the image is displayed by emitting light.
  • FIG. 9 the force of the other electrode (second electrode) illustrating the configuration of the sustain circuit relating to one electrode (first electrode) of the two electrodes of the panel capacitance Cp is also shown. It is the same.
  • the panel capacitance Cp is a capacitive load that serves as a display means.
  • Transistors Ql, Q2, Q3, and Q4 are N-channel MOS field effect transistors (FETs).
  • the capacitor CI is connected between the interconnection point of the drain of the transistor Q1 and the source of the transistor Q2 and the ground (GND).
  • the source of transistor Q1 is connected to the anode of diode D1
  • the drain of transistor Q2 is connected to the force sword of diode D2.
  • the coil L1 is connected between the interconnection point of the power sword of the diode D1 and the anode of the diode D2, and the first electrode of the panel capacitance Cp.
  • the coil Ll, transistors Ql and Q2, diodes Dl and D2, and capacitor CI constitute a power recovery circuit.
  • the transistor Q3 has a drain connected to the voltage Vs and a source connected to the first electrode of the panel capacitance Cp.
  • the diode D3 is connected between the drain and source of the transistor Q3.
  • Transistor Q4 has a drain connected to the first electrode of panel capacitance Cp and a source connected to ground.
  • the diode D4 is connected between the drain and source of the transistor Q4.
  • a control signal SLU is supplied to the gate of the transistor Q1, and a control signal SLD is supplied to the gate of the transistor Q2. Further, the control signal SCU is supplied to the gate of the transistor Q3, and the control signal SCD is supplied to the gate of the transistor Q4.
  • the transistors Q1 to Q4 are on-off controlled as switching elements by these control signals SLU, SLD, SCU, and SCD.
  • FIG. 10 is a diagram showing a sustain discharge pulse generated by the sustain circuit shown in FIG.
  • SLU, SLD, SCU, and SCD are control signals supplied to the transistors Q1 to Q4.
  • the sustain voltage is a voltage applied to the first electrode of the panel capacitance Cp
  • the LC resonance current is a current flowing through the coil L1 in the sustain circuit.
  • control signal SLU when the control signal SLU is set to low level ("L"), the control signal SCU is set to "H”, the transistor Q1 is turned off, and the transistor Q3 is turned on, the panel capacitance Cp The first electrode is clamped at voltage Vs.
  • control signal SCU At time T23, set control signal SCU to "L” and turn off transistor Q3.
  • control signal SLD is set to "L”
  • control signal SCD is set to “H”
  • the transistor Q2 is turned off
  • the transistor Q4 is turned on.
  • the control signal SCD is set to “L” and the transistor Q4 is turned off.
  • the voltage rise gradient near the ultimate potential at the LC resonance becomes gentle, so a sustain discharge may occur during the voltage rise.
  • the discharge may vary depending on the discharge cell (panel capacity Cp: capacitive load serving as a display means) or the discharge may become unstable.
  • Patent Document 1 Japanese Patent Laid-Open No. 7-160219
  • Patent Document 2 Japanese Patent Laid-Open No. 2006-10750
  • An object of the present invention is to provide a plasma display device and a driving method thereof that can improve the efficiency of a power recovery circuit and reduce heat generation and radiation noise of a driving element.
  • a plasma display device of the present invention includes a plasma display panel that displays an image by applying a voltage to a capacitive load serving as a display means, and a drive circuit that applies a voltage to the capacitive load.
  • the drive circuit includes: a clamp circuit for clamping the electrode of the capacitive load to the first voltage or the second voltage; A coil circuit having one end connected to the electrode of the capacitive load, and a second end connected to the other end of the coil circuit.
  • a superimposed voltage is applied to the second electrode of the power recovery capacitor when charging and discharging the capacitive load by resonance between the power recovery capacitor to which the electrode 1 is connected and the capacitive load and the coil circuit. And a superimposed voltage circuit.
  • the plasma display device of the present invention includes a plasma display panel that displays an image by applying a voltage having different polarities to two electrodes of a capacitive load serving as a display means, and discharging according to the potential difference, and a voltage is applied to the capacitive load.
  • a driving circuit for applying the voltage wherein the driving circuit includes a clamp circuit for clamping the electrode of the capacitive load to the first voltage or the second voltage, and the capacitive load.
  • a coil circuit having one end connected to an electrode, and a superimposed voltage circuit that applies a superimposed voltage to the other end of the coil circuit when charging and discharging the capacitive load by resonance of the capacitive load and the coil circuit; It is characterized by providing.
  • the plasma display device driving method of the present invention includes a plasma display panel for displaying an image by applying a voltage to a capacitive load serving as a display means, a coil circuit having one end connected to the electrode of the capacitive load, and A driving method of a plasma display device, comprising: a power recovery capacitor having a first electrode connected to the other end of a coil circuit; and a driving circuit for applying a voltage to the capacitive load, wherein the capacitive load is And when the capacitive load is charged by resonance of the coil circuit, a first superimposed voltage is applied to the second electrode of the power recovery capacitor to raise the potential of the second electrode and When charging the load and discharging the capacitive load due to resonance between the capacitive load and the coil circuit, a second superimposed voltage is applied to the second electrode of the power recovery capacitor to apply the load. Lower the potential of the second electrode, characterized in that discharge the capacitive load.
  • the driving method of the plasma display device of the present invention comprises: a plasma display panel that displays an image by applying voltages of different polarities to two electrodes of a capacitive load serving as a display means, and discharging by the potential difference; and the capacitive load of the capacitive load
  • a driving method for a plasma display device comprising: a coil circuit having one end connected to an electrode; and a driving circuit for applying a voltage to the capacitive load, wherein the capacitive load and the coil circuit are caused to resonate.
  • a first superimposed voltage is applied to the other end of the coil circuit.
  • a second superimposed voltage is applied to the other end of the coil circuit! And discharging the capacitive load.
  • the present invention when a capacitive load is charged / discharged by resonance between the capacitive load and the coil circuit, the superimposed voltage is applied so as to cancel the change due to the loss in the circuit, thereby reaching the resonance frequency.
  • the potential can be appropriately controlled, and it is possible to reduce element heat generation and radiation noise.
  • FIG. 1 is a diagram showing a configuration example of a plasma display device in an embodiment of the present invention.
  • FIG. 2 is a diagram showing an example of a driving waveform of the plasma display device shown in FIG.
  • FIG. 3 is a circuit diagram showing a configuration example of a drive circuit in the first embodiment.
  • FIG. 4 is a diagram for explaining a driving method by the driving circuit shown in FIG. 3.
  • FIG. 5 is a circuit diagram showing a configuration example of a drive circuit according to a second embodiment.
  • FIG. 6 is a diagram for explaining a driving method by the driving circuit shown in FIG. 5.
  • FIG. 7 is a circuit diagram showing a configuration example of a drive circuit according to a third embodiment.
  • FIG. 8 is a circuit diagram showing another configuration example of the drive circuit according to the third embodiment.
  • FIG. 9 is a diagram showing a configuration of a conventional drive circuit.
  • FIG. 10 is a diagram showing a driving waveform by a conventional driving circuit.
  • FIG. 1 is a diagram showing a configuration example of a plasma display device according to an embodiment of the present invention.
  • the plasma display device in this embodiment is a plasma display panel 1
  • the X drive circuit 2 is a circuit that repeats sustain discharge, and includes a plurality of X electrodes (sustain electrodes) XI,
  • the Y drive circuit 3 is composed of a circuit that selects a row to be displayed by line-sequential scanning and a circuit that repeats a sustain discharge, and includes a plurality of Y electrodes (scan electrodes) Yl, ⁇ 2, ..., ⁇ Supply the specified voltage to Hereinafter, each of ⁇ electrode Yl, ⁇ 2,..., ⁇ or their generic name is called ⁇ electrode Yi, and i means a subscript.
  • the address drive circuit 4 has a circuit power for selecting a column to be displayed, and supplies a predetermined voltage to the plurality of address electrodes A 1, A 2,.
  • each of the address electrodes Al, A2,... Or their generic name is referred to as an address electrode Aj, where j is a subscript.
  • the control circuit 5 generates a control signal based on display data, a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and the like input from the outside of the apparatus.
  • the control circuit 5 supplies the generated control signal to the X drive circuit 2, the Y drive circuit 3, and the address drive circuit 4, and controls these drive circuits 2-4.
  • the Y electrode Yi and the X electrode Xi form a row extending in parallel in the horizontal direction, and the address electrode Aj forms a column extending in the vertical direction.
  • Y electrode Yi and X electrode Xi are alternately arranged in the vertical direction. That is, the Y electrode Yi and the X electrode Xi are arranged in parallel to each other, and the address electrode Aj is arranged in a direction substantially perpendicular to the Y electrode Yi and the X electrode Xi.
  • Y electrode Yi and address electrode Aj form a two-dimensional matrix of i rows and j columns.
  • the cell Cij is formed by the intersection of the Y electrode Yi and the address electrode Aj and the X electrode Xi adjacent thereto corresponding thereto.
  • This cell Cij corresponds to, for example, red, green, and blue subpixels, and one pixel is constituted by these three subpixels.
  • Panel 1 displays an image by lighting a plurality of pixels arranged two-dimensionally.
  • the line drive scanning circuit in the Y drive circuit 3 and the address drive circuit 4 determine which cells are lit, and the X drive circuit 2 and the Y drive circuit 3 repeat the sustain discharge to repeatedly discharge. As a result, the display operation on the plasma display device is performed.
  • FIG. 2 is a diagram showing an example of a driving waveform of the plasma display device shown in FIG.
  • the image is composed of a plurality of time-series frames f (subscripts indicate display order) such as frames fk 1, fk, fk + 1, etc. shown in FIG.
  • each frame f is divided into, for example, eight subframes sfl, sf2, sf3, sf4, sf5, sf6, sf7, and sf8.
  • the subframes sfl to sf8 are weighted so that the relative ratio of luminance is, for example, approximately 1: 2: 4: 8: 16: 32: 64: 128, and the number of times the subframes sf1 to sf8 are lit and maintained Is set.
  • the subframe period Tsf allocated to each of the subframes sfl to sf8 includes a reset period TR, an address period TA, and a sustain (sustain discharge) period TS.
  • the reset period TR the cell Cij is initialized.
  • positive obtuse waves (waveforms with a positive slope) Prl are simultaneously applied to the Y electrode Yi to form wall charges, followed by V and negative obtuse waves (with negative slopes). Waveform with) Apply Pr2 all at once to adjust the wall charge of cell Cij.
  • each cell Cij can be selected by the discharge between the address electrode Aj and the Y electrode Yi and the discharge between the X electrode XI and the Y electrode Yi.
  • the scan pulse Py is sequentially applied to the Y electrodes Yl, ⁇ 2, ⁇ 3,...
  • the address pulse Pa is applied to the address electrode Aj corresponding to the scan pulse Py. Discharge occurs between Y electrodes Yi. By this discharge, wall charges are formed on the X electrode XI and the Y electrode Yi, and it is possible to select light emission or non-light emission of a desired cell Cij.
  • sustain discharge is performed between the X electrode XI and the Y electrode Yi of the selected cell Cij to emit light.
  • the sustain discharge pulse Ps is applied alternately to the X electrode Xi and the Y electrode Yi. Each time the sustain discharge pulse Ps is applied, a discharge occurs in the cell in which wall charges are formed in the address period TA, and the cell emits light.
  • the sustain discharge pulse Ps is a pulse of OV and voltage Vs.
  • FIG. 3 is a circuit diagram showing a configuration example of the X drive circuit 2 and the Y drive circuit 3 in the first embodiment of the present invention.
  • FIG. 3 shows only the sustain circuit in one of the X drive circuit 2 and Y drive circuit 3, but the sustain circuit in the other drive circuit is configured similarly.
  • the sustain circuit generates the sustain discharge pulse Ps described above. This is a circuit (a circuit that repeats sustain discharge).
  • the panel capacitance Cp is a capacitance between the X electrode Xi and the Y electrode Yi, and corresponds to a capacitive load serving as a display means.
  • Transistors Ql, Q2, Q3, Q4, Q5, and Q6 are N-channel MOS field effect transistors, each of which functions as a switching element.
  • One electrode (first electrode) of the capacitor C1 as a power recovery capacitor is connected to an interconnection point between the source of the transistor Q5 and the drain of the transistor Q6.
  • the drain of transistor Q5 is connected to the first superimposed voltage
  • the source of transistor Q6 is connected to the second superimposed voltage. That is, the first superimposed voltage can be applied to the first electrode of the capacitor C1 via the transistor Q5, and the second superimposed voltage can be applied to the first electrode of the capacitor C1 via the transistor Q6.
  • the first superimposed voltage is a positive voltage (+ V) and the second superimposed voltage is a negative voltage ( ⁇ ⁇ ) with respect to the ground (GND).
  • the other electrode (second electrode) of capacitor C1 is connected to the interconnection point between the drain of transistor Q1 and the source of transistor Q2.
  • the source of transistor Q1 is connected to the anode of diode D1, and the drain of transistor Q2 is connected to the power sword of diode D2.
  • the coil L1 is connected between the interconnection point of the power sword of the diode D1 and the anode of the diode D2 and one electrode (first electrode) of the panel capacitance Cp.
  • These coil Ll, transistors Ql and Q2, and diodes Dl and D2 constitute a coil circuit.
  • the transistor Q3 has a drain connected to the voltage Vs and a source connected to the first electrode of the panel capacitance Cp.
  • Diode D3 is connected in parallel to transistor Q3. Specifically, diode D3 has a force sword connected to the drain of transistor Q3 and an anode connected to the source of transistor Q3.
  • the transistor Q4 has a drain connected to the first electrode of the panel capacitance Cp and a source connected to the ground.
  • Diode D4 is connected in parallel to transistor Q4. Specifically, diode D4 has a force sword connected to the drain of transistor Q4, and a diode connected to the source of transistor Q4.
  • the transistors Q3 and Q4 and the diodes D3 and D4 constitute a clamp circuit. Details Specifically, the transistor Q3 and the diode D3 constitute a high-side clamp circuit that clamps the first electrode of the panel capacitance Cp to the first voltage Vs that is the sustain discharge voltage. The transistor Q4 and the diode D4 A low-side clamp circuit is constructed that clamps the first electrode of the panel capacitance Cp to the ground as the second voltage.
  • the control signal SLU is supplied to the gate of the transistor Q1, and the control signal SLD is supplied to the gate of the transistor Q2. Further, the control signal SCU is supplied to the gate of the transistor Q3, and the control signal SCD is supplied to the gate of the transistor Q4. Further, the control signal SAU is supplied to the gate of the transistor Q5, and the control signal SAD is supplied to the gate of the transistor Q6.
  • the transistors Q1 to Q6 are ON / OFF controlled as switching elements by these control signals SLU, SLD, SCU, SCD, SAU, and SAD.
  • the first electrode of the capacitor C1 is connected to the ground, and the second electrode of the capacitor C1 is connected to the voltage (VsZ2). It is configured. As a result, the capacitor C1 is charged (initial charge) so that the potential difference S (VsZ2) between the electrodes of the capacitor C1 is obtained in the initial state. In addition, even during operation, charging can be performed so that the potential difference between the electrodes of the capacitor C1 becomes (VsZ2) as necessary.
  • FIG. 4 is a diagram for explaining a driving method by the driving circuit shown in FIG.
  • SLU, SLD, SCU, SCD, SAU, and SAD are control signals supplied to the transistors Q1 to Q6.
  • the sustain voltage is the voltage applied to the first electrode of the panel capacitance Cp
  • the LC resonance current is the current that flows through the sustain circuit due to LC resonance.
  • the sustain voltage the waveform in the conventional drive circuit is shown by a broken line for comparison and reference.
  • the capacitor C1 is charged in advance so that the potential difference between the electrodes becomes (VsZ2).
  • the transistor Q5 is on and the transistor Q6 is off, the first superimposed voltage (+ V) is applied to the first electrode of the capacitor C1.
  • the resonance reference potential changes by the amount of the first superimposed voltage (+ V a), and the LC resonance ultimate potential is To rise.
  • the first superimposed voltage (+ V a) is applied to the power recovery capacitor C1 as shown in FIG.
  • the sustain discharge voltage Vs can be reached by the LC resonance of the panel capacitance Cp and coil L1.
  • the voltage applied to the first electrode of the panel capacitance Cp can be clamped to the sustain discharge voltage Vs without increasing sharply.
  • the second superimposed voltage ( ⁇ Let ⁇ ) be ⁇ (1 -X / lOO) X (one VsZ2) ⁇ .
  • the second superimposed voltage ( ⁇ ⁇ ) is applied to the power recovery capacitor C 1 as shown in FIG. It can reach the ground by the panel capacitance C ⁇ and the LC resonance of the coil L1. Then, after reaching the ground, by turning on the transistor Q4, the voltage applied to the first electrode of the panel capacitance Cp can be clamped to the ground without changing abruptly.
  • control signal SCU is set to “H” and at the same time the control signals SLU and SAU are set to “L”. Any time after time T2 (time The control signals SLU and SAU may be set to “L” before T3.
  • control signal SCD is set to “H” and at the same time the control signals SLD and SAD are set to “L”. Any time when the control signal SCD force is “ ⁇ ” after time T5. It is also possible to set the control signals SLD and S AD to “L”!
  • the superimposed voltage is applied to the power recovery capacitor C1 to Even if there is a loss at, it is possible to control the ultimate potential at the LC resonance appropriately.
  • the panel capacitance Cp is charged by LC resonance, by applying the first superimposed voltage (+ V a) to the capacitor C1, the ultimate potential in the LC resonance is changed to the sustain discharge voltage Vs or The sustain discharge voltage can be raised to Vs.
  • the second superposed voltage one V j8 is applied to the capacitor C1, thereby reducing the ultimate potential at the LC resonance to ground or substantially ground. Can do.
  • the coil for LC resonance with the panel capacitance Cp has less loss as the inductance value is larger, and the recovery efficiency can be improved. However, the higher the inductance value of the coil, the slower the potential change.
  • the first coil for power supply that is required to change quickly, and the requirement for the change.
  • a second coil for low power recovery are provided.
  • the first coil for power supply and the second coil for power recovery have different inductance values, and the inductance value of the second coil is larger than the inductance value of the first coil.
  • the second embodiment is different from the first embodiment described above only in the configuration of the sustain circuits in the drive circuits 2 and 3, and the other configurations are the same as those in the first embodiment. Description is omitted.
  • FIG. 5 is a circuit diagram showing a configuration example of the X drive circuit 2 and the Y drive circuit 3 in the second embodiment.
  • FIG. 5 shows only the sustain circuit in one of the drive circuits 2 and 3, but the sustain circuit in the other drive circuit is configured similarly.
  • components having the same functions as those shown in FIG. 3 are given the same reference numerals.
  • the first electrode of capacitor CI as a power recovery capacitor is connected to the interconnection point of the source of transistor Q5 and the drain of transistor Q6.
  • the drain of the transistor Q5 is connected to the positive voltage (+ V a) that is the first superimposed voltage
  • the source of the transistor Q6 is connected to the negative voltage (one V j8) that is the second superimposed voltage.
  • the second electrode of capacitor C1 is connected to the interconnection point of the drain of transistor Q1 and the source of transistor Q2.
  • the source of the transistor Q1 is connected to the anode of the diode DI1.
  • the first coil LI1 for power supply is connected in series between the force sword of the diode DI1 and the first electrode of the panel capacitance Cp. That is, the diode DI1 is connected in series so that a current flows in the direction in which the current flows in the panel capacitance Cp in the first coil LI1, and a charging current for the panel capacitance Cp flows in the first coil LI1.
  • the drain of the transistor Q2 is connected to the force sword of the diode DOl.
  • the second coil LOl for power recovery is connected in series between the diode DO 1 and the first electrode of the panel capacitance Cp. That is, the diode DO 1 is connected in series so that the current flows in the direction in which the current flows from the panel capacitance Cp in the second coil LOl, and the discharge current from the panel capacitance Cp flows in the second coil LO1. .
  • a coil circuit is constituted by these coils LI1, L01, transistors Ql, Q2, and diodes DI1, DOl.
  • the inductance value of the second coil LOl is larger than the inductance value of the first coil LI 1! /.
  • the transistor Q3 has a drain connected to the voltage Vs and a source connected to the first electrode of the panel capacitance Cp.
  • the diode D3 is connected between the drain and source of the transistor Q3.
  • the transistor Q4 has a drain connected to the first electrode of the panel capacitance Cp and a source connected to the ground.
  • the diode D4 is connected between the drain and source of the transistor Q4.
  • control signals SLU, SLD, SCU, SCD, SAU, and SAD are supplied to the gates of the transistors Ql, Q2, Q3, Q4, Q5, and Q6, respectively.
  • the transistors Q1 to Q6 are ON / OFF controlled as switching elements by these control signals SLU, SLD, SCU, SCD, SAU, and SAD.
  • the first electrode of the capacitor C 1 is connected to the ground, and the second electrode of the capacitor C 1 is configured to be connected to the voltage (Vs / 2).
  • FIG. 6 is a diagram for explaining a driving method by the driving circuit shown in FIG.
  • SLU, SLD, SCU, SCD, SAU, and SAD are control signals supplied to the transistors Q1 to Q6.
  • the sustain voltage is the voltage applied to the first electrode of the panel capacitance Cp
  • the LC resonance current is the current that flows through the sustain circuit due to LC resonance.
  • the sustain voltage the waveform in the conventional drive circuit in the same configuration is shown by a broken line for comparison and reference.
  • the driving method in the second embodiment is the above-described first method. This is almost the same as the driving method in the first embodiment.
  • the resonance period related to the LC resonance of the node capacitance Cp and the second coil LOl is the panel. It is longer than the resonance period for the LC resonance of the capacitor Cp and the first coil LI1.
  • the panel capacitance Cp and the resonance period 1Z4 (period TD) of the second coil LOl are longer than the resonance period 1Z4 (period TU) of the panel capacitance Cp and the first coil LI1, and the sustain voltage is quickly It changes slowly, and changes slowly when descending.
  • the first superimposed voltage (+ V) and the second superimposed voltage ( ⁇ ⁇ ) are also different.
  • 8) may be set as appropriate according to the recovery efficiency.
  • the power recovery efficiency due to the LC resonance of the panel capacitance Cp and the first coil LI1 is Y%.
  • the first superimposed voltage (+ V a ) is ⁇ (1— YZlOO) X (VsZ2) ⁇ .
  • the same effects as those of the first embodiment described above can be obtained. Furthermore, by providing the first coil LI1 for power supply and the second coil LOl for power recovery, respectively, the circuit characteristics when the voltage rises and drops Z depends on the required resonance period, recovery efficiency, etc. Can be set independently, and the efficiency of the power recovery circuit can be improved.
  • the sustain discharge pulses Ps having different polarities are applied to the X electrode Xi and the Y electrode Yi at the same timing.
  • the potential difference between the sustain discharge pulse Ps applied to the X electrode Xi and the sustain discharge pulse Ps applied to the Y electrode Yi is used to discharge in the cell in which the wall charge is formed in the address period TA.
  • the sustain discharge pulse Ps is a voltage (VsZ2) and voltage (VsZ2) pulse.
  • FIG. 7 is a circuit diagram showing a configuration example of the X drive circuit 2 and the Y drive circuit 3 in the third embodiment.
  • FIG. 7 shows only the sustain circuit in one of the drive circuits 2 and 3, but the sustain circuit in the other drive circuit is configured similarly.
  • components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals.
  • the drain is connected to the voltage (+ V a,), and the source is connected to the anode of the diode D1.
  • Transistor Q2 has its drain connected to the power sword of diode D2 and its source connected to the voltage (one V j8,).
  • the voltage (+ V a,) is (VsZ2 + V a)
  • 8,) is ( ⁇ VsZ2 ⁇ V
  • 8) correspond to the first superimposed voltage and the second superimposed voltage in the first embodiment described above, respectively.
  • the coil LI is connected between the interconnection point of the power sword of the diode Dl and the anode of the diode D2, and the first electrode of the panel capacitance Cp.
  • the transistor Q3 has a drain connected to the voltage (Vs / 2) and a source connected to the first electrode of the panel capacitance Cp.
  • the diode D3 is connected between the drain and the source of the transistor Q3.
  • the transistor Q4 has a drain connected to the first electrode of the panel capacitance Cp and a source connected to the voltage (one Vs / 2).
  • the diode D4 is connected between the drain and source of the transistor Q4.
  • control signals SLU, SLD, SCU, and SCD are supplied to the gates of the transistors Ql, Q2, Q3, and Q4, respectively.
  • Transistors Q1-Q4 are on / off controlled as switching elements by these control signals SLU, SLD, SCU, SCD
  • FIG. 8 is a circuit diagram showing another configuration example of the X drive circuit 2 and the Y drive circuit 3 in the third embodiment, and supplies power similarly to the second embodiment shown in FIG.
  • the first coil LI 1 for power supply and the second coil LOl for power recovery are provided respectively. Even in this embodiment, the inductance value of the first coil LI 1 for power supply and the second coil LO 1 for power recovery are different from each other, and the inductance value of the second coil LOl is Greater than the inductance value of coil 1 LI1.
  • FIG. 8 also shows only the sustain circuit in one of the drive circuits 2 and 3, but the sustain circuit in the other drive circuit is configured similarly.
  • FIG. 8 components having the same functions as those shown in FIG. 5 are given the same reference numerals.
  • the drain is connected to the voltage (+ V a,), and the source is connected to the anode of the diode DI1.
  • the first coil LI1 for power supply is connected in series between the force sword of the diode DI1 and the first electrode of the panel capacitance Cp. That is, the diode DI1 is connected in series so that a current flows in the direction in which the current flows in the panel capacitance Cp in the first coil LI1, and a charging current for the panel capacitance Cp flows in the first coil LI1.
  • Transistor Q2 has a drain connected to the force sword of diode DOl and a source connected to voltage (
  • the second coil LOl for power recovery is connected in series between the anode of the diode DOl and the first electrode of the panel capacitance Cp. That is, the second coil A diode D Ol is connected in series so that current flows in the direction in which current flows from the panel capacitance Cp to LOl, and a discharge current from the panel capacitance Cp flows in the second coil LOl.
  • the voltage (+ V ⁇ ,) is (VsZ2 + V a), and the voltage (one V j8,) is (one VsZ2 ⁇ V j8). (+ ⁇ «) and ( ⁇ ⁇
  • 8) correspond to the first superimposed voltage and the second superimposed voltage in the second embodiment described above, respectively.
  • the transistor Q3 has a drain connected to the voltage (VsZ2) and a source connected to the first electrode of the panel capacitor.
  • the diode D3 is connected between the drain and source of the transistor Q3.
  • the transistor Q4 has a drain connected to the first electrode of the panel capacitance Cp and a source connected to a voltage (one VsZ2).
  • the diode D4 is connected between the drain and source of the transistor Q4.
  • Control signals SLU, SLD, SCU, and SCD are supplied to the gates of the transistors Ql, Q2, Q3, and Q4, respectively, as in the second embodiment.
  • Transistors Q1-Q4 are on / off controlled as switching elements by these control signals SLU, SLD, SCU, SCD
  • the first superimposed voltage applied when discharging the recovered power to charge the panel capacitance Cp is the voltage clamped by the clamp circuit,
  • the voltage that equalizes (or substantially equals) the potential reached at the LC resonance of the channel capacitance Cp and the coil LI (LI1) is not limited to this.
  • a voltage at which LC resonance is reached higher than the voltage clamped by the clamp circuit is applied as a first superimposed voltage, or the voltage at which LC resonance is reached is lower than the voltage clamped by the clamp circuit.
  • a so-called early clamp may be applied in which the clamping operation is performed before the 1Z4 period of the LC resonance has elapsed.
  • the first superimposed voltage is applied when the recovered power is discharged to charge the panel capacitance Cp
  • the second superimposed voltage is discharged when the panel capacitance Cp is discharged to recover the power. Only one of the forces applying the voltage may be performed. However, in that case, it is desirable to perform initial charging as appropriate during operation.
  • the power using an N-channel field effect transistor as a switching element is not limited to this. Any circuit capable of on-off control is possible. An element can be applied. For example, an IGBT may be used as the switching element.
  • the present invention by applying the superimposed voltage when charging and discharging the capacitive load by resonance between the capacitive load and the coil circuit, it is possible to appropriately control the ultimate potential at resonance, and The efficiency of the recovery circuit can be improved, and the heat generation and radiation noise of the drive element can be reduced compared to the conventional case.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention concerne un circuit de commande pour appliquer une tension à une charge capacitive d'un écran à plasma. Le circuit de commande comprend un circuit de verrouillage pour verrouiller l'électrode de la charge capacitive à une première tension ou une seconde tension, un circuit de bobine connecté au niveau d'une de ses extrémités à l'électrode de la charge capacitive, un condensateur de récupération de puissance connecté au niveau d'une de ses électrodes à l'autre extrémité du circuit de bobine, et un circuit de tension superposée pour appliquer une tension superposée à la seconde électrode du condensateur de récupération de puissance. Lorsque la charge capacitive est chargée ou déchargée par la résonance de la charge capacitive et du circuit de bobine, la tension superposée est appliquée à la seconde électrode du condensateur de récupération de puissance de manière à ce que le dernier potentiel dans la résonance puisse être commandé de manière adéquate afin de réduire la libération de chaleur et le bruit de rayonnement d'un élément.
PCT/JP2006/321952 2006-11-02 2006-11-02 Dispositif d'affichage à plasma et son procédé de commande WO2008053556A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/321952 WO2008053556A1 (fr) 2006-11-02 2006-11-02 Dispositif d'affichage à plasma et son procédé de commande

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PCT/JP2006/321952 WO2008053556A1 (fr) 2006-11-02 2006-11-02 Dispositif d'affichage à plasma et son procédé de commande

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1115426A (ja) * 1997-06-24 1999-01-22 Victor Co Of Japan Ltd 容量負荷駆動回路
JP2005003931A (ja) * 2003-06-12 2005-01-06 Hitachi Ltd 表示装置
JP2005077981A (ja) * 2003-09-03 2005-03-24 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動装置
JP2005221796A (ja) * 2004-02-06 2005-08-18 Hitachi Ltd プラズマディスプレイ装置およびプラズマディスプレイの駆動方法
JP2006058855A (ja) * 2004-08-18 2006-03-02 Samsung Sdi Co Ltd プラズマディスプレイパネルとその駆動方法
WO2006098030A1 (fr) * 2005-03-17 2006-09-21 Hitachi Plasma Patent Licensing Co., Ltd. Dispositif de charge/décharge, affichage, panneau d’affichage plasma et procédé de charge/décharge

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1115426A (ja) * 1997-06-24 1999-01-22 Victor Co Of Japan Ltd 容量負荷駆動回路
JP2005003931A (ja) * 2003-06-12 2005-01-06 Hitachi Ltd 表示装置
JP2005077981A (ja) * 2003-09-03 2005-03-24 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動装置
JP2005221796A (ja) * 2004-02-06 2005-08-18 Hitachi Ltd プラズマディスプレイ装置およびプラズマディスプレイの駆動方法
JP2006058855A (ja) * 2004-08-18 2006-03-02 Samsung Sdi Co Ltd プラズマディスプレイパネルとその駆動方法
WO2006098030A1 (fr) * 2005-03-17 2006-09-21 Hitachi Plasma Patent Licensing Co., Ltd. Dispositif de charge/décharge, affichage, panneau d’affichage plasma et procédé de charge/décharge

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