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WO2007080013A1 - Procede et appareil de traitement de substrats semiconducteurs en tranches collees - Google Patents

Procede et appareil de traitement de substrats semiconducteurs en tranches collees Download PDF

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Publication number
WO2007080013A1
WO2007080013A1 PCT/EP2006/068544 EP2006068544W WO2007080013A1 WO 2007080013 A1 WO2007080013 A1 WO 2007080013A1 EP 2006068544 W EP2006068544 W EP 2006068544W WO 2007080013 A1 WO2007080013 A1 WO 2007080013A1
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WO
WIPO (PCT)
Prior art keywords
wafer
furnace
substrates
wafers
temperature
Prior art date
Application number
PCT/EP2006/068544
Other languages
English (en)
Inventor
Rainer Krause
Gerd Pfeifer
Markus Schmidt
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO2007080013A1 publication Critical patent/WO2007080013A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates in general to a method and an apparatus for treating semiconductor substrates. More specifically, the invention relates to bonding wafer technology used for SOI wafer substrates. Still more specifically, the invention deals with an improved furnace for thermally treating such substrates.
  • SOI wafers are known in microelectronics and are used in special applications, including radiation hardened devices such as static random access memories (SRAMs) and more recently for high performance complementary metal oxide semiconductor (CMOS) and dynamic random access memory (DRAM) applications.
  • SOI wafers are usually manufactured by 1) implanted oxygen (SIMOX) in which oxygen is implanted into silicon and converted into a silicon dioxide buried layer, or 2) wafer bonding and etch-back (BESOI) in which two wafers are bonded with oxide surface layers and one wafer is thinned to leave a thin device layer.
  • SIMOX implanted oxygen
  • BESOI wafer bonding and etch-back
  • Smart-Cut ® process Another process for producing SOI substrates is the Smart-Cut ® process, which is described in detail in US-A-5, 374, 564.
  • This process is similar to the BESOI process, but instead of thinning by etching, it uses a hydrogen layer that is implanted prior to bonding, and the bulk silicon is fractured after bonding to leave a thin layer.
  • hydrogen implantation and annealing are used to fracture the bulk of the device wafer from the bonded wafers.
  • Chemical-mechanical polishing (CMP) is used to planarize and minimize non-uniformity of the as-cut SOI wafer.
  • wafers may be subjected to one or more heating or baking operations for a variety of reasons.
  • wafers may be subjected to such heating during thermal oxidation processes used to form a layer of silicon dioxide on the wafer.
  • problems are encountered with such heating or baking processes conducted with the wafer.
  • the wafers are loaded into a horizontal or vertical furnace and are baked by the furnace at a particular temperature for a specified baking time.
  • vertical furnaces have replaced horizontal furnaces because they present a number of advantages, including elimination of cantilever loading and insertion of quartz boats containing the increasingly massive semiconductor wafers, automated loading and unloading, and a smaller cleanroom footprint .
  • the actual temperature within each of the zones will vary from one zone to another within the furnace.
  • the temperature variation between the zones may result because heat from the bottom of the vertical furnace rises to the top, thereby causing the zones near the top of the furnace to be hotter than the zones towards the bottom of the furnace.
  • various other factors generally cause variations in temperature between the zones of the furnace, such as the gas flow within the furnace, for example .
  • the roughness specification limit for bonded wafer substrates used in the semiconductor industry is one of the most challenging points during the production of such substrates.
  • the limits are actually in the range of ⁇ 50 nm and are still decreasing.
  • the individual wafer is heated non-homogeneous when using vertical furnace technology. This has the effect of a high roughness area in the wafer range which is exposed to the heat longest.
  • the inhomogeneous wafer heating of the bonded layers cause certain mechanical stress which finally results in roughness increase of the area being first exposed to heat.
  • the observed roughness in the exposed area is several times higher than on the remaining surface.
  • Fig. 1 schematically shows the wafer flow in a vertical furnace and the related heat exposed roughness area
  • Fig. 2 schematically depicts the sequence of process steps in a state-of-the-art vertical furnace
  • Fig. 3 schematically shows the wafer flow of the method according to the invention
  • Fig. 4 is a temperature profile of a hot plate used in the method of the present invention.
  • Fig. 5 schematically depicts the sequence of process steps in a vertical furnace according to the present invention
  • Fig. 6 schematically shows temperature gradients based on the stack height and throughout the stack according to the invention
  • Fig. 7 schematically depicts the sequence of process steps in a state-of-the-art horizontal furnace
  • Fig. 8 schematically depicts the sequence of process steps in a horizontal furnace according to the present invention.
  • the present invention concerns a method and an apparatus for treating semiconductor substrates, meaning bulk as well as advanced substrates, like SOI-wafers and the like. Though the invention can be used with horizontal as well as vertical furnaces, it will in the following mainly be described in relation to vertical furnaces.
  • Fig. 1 schematically shows the flow of the wafers 14 in a vertical furnace 10 and the related heat exposed roughness area 14'.
  • the wafer move (cf. the vertical arrow in Fig. 1) thereby is from bottom up while the heat is applied using heat coils at higher up section in the furnace tube leading to an annealing step being "perpendicular" to the moving direction of the wafer 14.
  • Fig. 2 schematically depicts the sequence of process steps in a state-of-the-art vertical furnace. It shows a boat 12 with cold wafers 14 loaded outside the heating chamber 16 by a boat loading mechanism. To start the process, the boat 12 is raised into the heating chamber 16 that is at a certain temperature Tl, this temperature being the ramp start temperature. After loading, the furnace temperature will ramp and follow a predefined temperature profile. While loading, the wafers 14 will experience inhomogeneous temperature distribution over the wafer surface originating from the arrangement of the heating device surrounding the wafers 14 and the movement of the wafers into the heating chamber 16. This is mainly related to the hot air stream in the furnace tube as well as the gravity effect. The result is a gradient over the wafer surface and in-between the wafers 14.
  • the process has to be designed in a way that the first wafers loaded, i.e., the top slot in the boat, are seeing earlier peak temperature as compared to the bottom wafer, i.e., like the FIFO (first-in-first-out) principle, first pre-annealed wafer placed top and last pre-annealed wafer placed bottom in the stack.
  • FIFO first-in-first-out
  • the wafers 14 are pre-annealed before being applied to the original vertical furnace process step.
  • This pre-annealing can, e.g., be carried out by using a hot plate or a hot plate stack 18, a hot air chamber or the like, which applies homogeneous pre-heating across the wafers to prevent mechanical stress.
  • Fig. 3 schematically shows the wafer flow of the method according to the invention. Wafers 14 enter the final vertical furnace chamber at a higher temperature level, thereby reducing the mechanical stress on the wafer surfaces.
  • Fig. 4 depicts a temperature profile which could be applied using the hot plate or hot plate stack 18 according to the invention. Using such a temperature profile has the effect that the pre-annealed wafer is already on a fairly high temperature level before being applied to the original vertical furnace step. The pre-annealing prevents the stress on the wafers 14 which, in turn, secures homogeneous surface performance and reduced roughness across the entire wafer as compared to non pre-annelaed wafers.
  • Fig. 5 schematically depicts the sequence of process steps in a vertical furnace according to the present invention including pre-annealing. The cold wafers 14 are placed on a hot plate 18 and heated up homogeneously to a peak temperature of about 600 - 800 0 C.
  • This range is recommended to secure a high enough temperature level of the wafers 14 before entering the vertical furnace chamber to reduce the mechanical stress on the wafers significantly.
  • the best peak temperature is still to be detrmined on an empirical basis.
  • the wafers 14 are then loaded in the quartz boat 12 starting from top down. This means that the first pre-annealed wafers 14 enter the vertical furnace first.
  • the wafers 14 are now on a higher temperature level, which means that the mechanical stress is reduced and with this the higher surface roughness caused through splitting process as opposed to the state-of-the-art process (cf. Fig. 2).
  • Fig. 6 schematically shows temperature gradients based on the stack height and throughout the stack according to the invention.
  • Temperature profile 1 (Temp 1) is within the furnace tube while the beginning of the tube is marked by the grey bars 22.
  • Temperature profile 2 (Temp 2) shows the change across the stack from outside the furnace tube into the tube.
  • Temperature profile (Temp 3) shows the temperature change across the width of the furnace tube. The closed circles show the air stream between the wafers in the stack.
  • the final temperature profile for the pre-annealing must be determined empirically through appropriate experiments to secure that the furnace gradient is being compensated. This is to secure that all wafers 14 in the furnace boat 12 are on a sufficient temperature level (cf . temperature range given above) to reduce the mechanical stress on all wafers adequately.
  • the final temperature peak level has to be determined but should lie in the range shown in the temperature matrix above.
  • Fig. 8 schematically shows the state-of-the-art process.
  • the cold wafers 14 get loaded into the quartz boat 12 and then move into the heating chamber 16 of the horizontal furnace tube 20. This causes that the cold wafers 14 face high temperature and certain inhomogeneous conditions causing the high roughness spots.
  • Fig. 8 schematically depicts the process according to the invention.
  • the cold wafers 14 are placed on a hot plate 18 and heated up homogeneously to a peak temperature of about 600 - 800 0 C.
  • the wafers 14 are then loaded in the quartz boat 12 starting from the left side of the boat. This means that the first pre-annealed wafers enter the horizontal furnace 20 first.
  • the wafers are now on a higher temperature level, which means that the mechanical stress is reduced and with this the higher surface roughness caused through splitting process.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Procédé de traitement de substrats semiconducteurs, comprenant une étape de traitement thermique desdits substrats dans un four, lesdits substrats étant disposés en une pile de tranches. Les substrats sont pré-recuits avant d'être soumis à ladite étape de traitement thermique.
PCT/EP2006/068544 2006-01-09 2006-11-16 Procede et appareil de traitement de substrats semiconducteurs en tranches collees WO2007080013A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06100155 2006-01-09
EP06100155.8 2006-01-09

Publications (1)

Publication Number Publication Date
WO2007080013A1 true WO2007080013A1 (fr) 2007-07-19

Family

ID=37734967

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/068544 WO2007080013A1 (fr) 2006-01-09 2006-11-16 Procede et appareil de traitement de substrats semiconducteurs en tranches collees

Country Status (2)

Country Link
TW (1) TW200735265A (fr)
WO (1) WO2007080013A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1158581A1 (fr) * 1999-10-14 2001-11-28 Shin-Etsu Handotai Co., Ltd Procede de fabrication d'une tranche de soi, et tranche de soi
US6483081B1 (en) * 2000-11-27 2002-11-19 Novellus Systems, Inc. In-line cure furnace and method for using the same
WO2003005434A2 (fr) * 2001-07-04 2003-01-16 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite de surface d'une tranche semicondutrice
US20030203657A1 (en) * 2000-09-29 2003-10-30 Canon Kabushiki Kaisha SOI annealing method
FR2847714A1 (fr) * 2002-11-27 2004-05-28 Soitec Silicon On Insulator Procede et dispositif de recuit de tranche de semiconducteur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1158581A1 (fr) * 1999-10-14 2001-11-28 Shin-Etsu Handotai Co., Ltd Procede de fabrication d'une tranche de soi, et tranche de soi
US20030203657A1 (en) * 2000-09-29 2003-10-30 Canon Kabushiki Kaisha SOI annealing method
US6483081B1 (en) * 2000-11-27 2002-11-19 Novellus Systems, Inc. In-line cure furnace and method for using the same
WO2003005434A2 (fr) * 2001-07-04 2003-01-16 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite de surface d'une tranche semicondutrice
FR2847714A1 (fr) * 2002-11-27 2004-05-28 Soitec Silicon On Insulator Procede et dispositif de recuit de tranche de semiconducteur

Also Published As

Publication number Publication date
TW200735265A (en) 2007-09-16

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