WO2004112449A1 - 電子部品の製造方法および電子部品 - Google Patents
電子部品の製造方法および電子部品 Download PDFInfo
- Publication number
- WO2004112449A1 WO2004112449A1 PCT/JP2004/008298 JP2004008298W WO2004112449A1 WO 2004112449 A1 WO2004112449 A1 WO 2004112449A1 JP 2004008298 W JP2004008298 W JP 2004008298W WO 2004112449 A1 WO2004112449 A1 WO 2004112449A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring
- opening
- conductor
- power supply
- electronic component
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Definitions
- the present invention relates to a method for manufacturing an electronic component in which a wiring layer is sequentially laminated on a core material and an electronic component, and more particularly to a method for manufacturing an electronic component and an electronic component suitable for forming a conductor that makes interlayer connection in the wiring layer.
- 8A to 8D are process explanatory diagrams showing a conventional process of manufacturing a wiring layer of an electronic component.
- the wiring layer constituting the electronic component has a base material 1 made of an insulating material having a certain thickness, and a back surface of the base material 1 and the base material 1 formed inside the base material 1. And lower wiring 2.
- the copper layer 5 having the copper A dry film 6 serving as a protective film is attached to the front side of.
- the dry film 6 is exposed and developed as shown in FIG. 8B, and an opening 7 is formed in a region where the conductor 3 is formed.
- the copper foil exposed on the bottom surface of the opening 7 is removed by different etching to expose the substrate 1, and A blast treatment is performed on the surface of the base material 1 to expose the lower wiring 2 located below the base material 1.
- FIG. 8D shows a state in which the lower wiring 2 is exposed at the bottom of the opening 7 by the blast processing.
- the drilling of the base material 1 is performed by the blast processing.
- the present invention is not limited to this method, and another method may be used.
- FIGS. 9A and 9B are process explanatory diagrams showing a procedure for forming an opening using laser processing.
- FIG. 9A shows a state of the wiring layer before laser processing, and a laser processing machine (not shown) for processing the wiring layer is disposed above the wiring layer.
- FIG. 9B shows a state after the opening 7 is formed by laser processing.
- a YA G laser yttrium aluminum garnet laser
- a carbon dioxide gas laser is used for processing the base material 1 made of insulating resin. Is common.
- these different lasers may be mounted on the same positioning mechanism from the viewpoint of improving processing efficiency to perform continuous processing (copper foil 5 and base material 1). Instead of using the YAG laser, only the copper foil may be patterned by etching.
- the opening 7 from which the lower wiring 2 is exposed is formed on the surface of the wiring layer in this way, the opening 7 is filled with a metal material to form the conductor 3.
- FIGS. 10A, 10B, and 10C are process explanatory diagrams showing a procedure for forming a conductor portion in an opening.
- electroless plating is performed on the front side of the wiring layer where the opening 7 is formed in order to improve the adhesion to the base material 1.
- electroless plating layer 8 is formed.
- electrolytic plating is performed using the electroless plating layer 8 as an electrode, and an electrolytic plating layer 9 is deposited on the upper layer of the electroless plating layer 8 so as to fill the opening 7.
- FIG. 10B The state after the formation of the electrolytic plating layer 9 is shown in FIG. 10B.
- the copper foil 5, the electroless plating layer 8, and the electrolytic plating layer 9 are subjected to a subtractive method using a conductor part as shown in FIG. 10C. 3 and upper wiring 4 are formed.
- the adhesion between the base material 1 and the conductor portion 3 is improved by using an electroless plating layer (see, for example, Japanese Patent Application Laid-Open No. H11-333493).
- an electroless plating layer see, for example, Japanese Patent Application Laid-Open No. H11-333493.
- Another treatment is applied instead of the electroless plating layer (for example, see Japanese Patent Application Laid-Open No. 2001-217553).
- the electrolytic plating layer 9 is formed on the entire surface of one side of the wiring layer.
- the cross section of the wiring pattern becomes trapezoidal, resulting in a decrease in dimensional accuracy and a narrow width. There was a problem that the wiring pattern could not be formed.
- the present invention focuses on the above-mentioned conventional problems, and achieves simplification of the process by eliminating electroless plating, which is a pretreatment for electric plating, or other pretreatments equivalent thereto, thereby achieving electrical reliability. It is an object of the present invention to provide a method for manufacturing an electronic component and an electronic component capable of achieving improvement in performance.
- the present invention provides a method for forming a conductor portion without using an electroless plating layer as an electrode by using a copper foil formed in advance on a wiring layer as an electrode and growing the electroplating from the copper foil exposed from the end face of the opening. It is based on the finding that it can be formed.
- a method of manufacturing an electronic component according to the present invention is a method of manufacturing an electronic component in which a conductor connected to the lower wiring is exposed on an upper surface of an insulating member that covers the lower wiring. After the power supply film is formed on the surface, an opening is formed from the power supply film side with the lower wiring as the bottom, and the metal is attached from the opening to the edge of the power supply film using the power supply film as an electrode. The opening was filled with metal plating that adheres to the lower wiring, and this was used as a conductor.
- an opening may be formed, and a metal plating may be grown from the power supply film exposed from the opening.
- the present invention relates to a method for manufacturing an electronic component in which a conductor connected from the lower wiring is exposed on an upper surface of an insulating member covering the lower wiring.
- a conductor connected from the lower wiring is exposed on an upper surface of an insulating member covering the lower wiring.
- an opening having the lower wiring as a bottom is formed in the protective film and the power supply film in a region where the conductor is formed, and the power supply film is formed.
- the metal plating is grown from the power supply film exposed from the opening as an electrode, and after the metal plating reaches the lower wiring layer, the power supply film and the lower wiring layer are used as electrodes. The procedure was to fill the opening with metal plating that is in close contact with the lower wiring, and use this as a conductor.
- the insulating member is formed of a copper foil with an insulating resin, or a method in which an adhesive sheet and a metal foil corresponding to a copper foil are overlapped and formed by pressing. Good.
- the electronic component according to the present invention has a structure in which an upper wiring is formed on an upper surface of an insulating member that covers the lower wiring, and the lower wiring and the upper wiring are connected by a conductor penetrating the insulating member.
- the conductor portion that connects the lower wiring and the upper wiring is formed only by precipitation of metal by electroplating.
- the etching process is performed from above the insulating member on which the power supply film and the protective film are stacked.
- the insulating member is removed from the exposed insulating member by blasting or laser processing, and the lower wiring located below the insulating member is exposed to form an opening.
- the metal deposited by plating grows particularly at the edge of the power supply film in the opening due to the current density concentration effect. I do.
- the lower wiring acts as an electrode in addition to the end face of the power supply film. For this reason, the metal plating not only starts from the end face of the power supply film but also grows from the lower wiring. As the metal plating continues to grow from the end face of the power supply film and the lower wiring, the inside of the opening is filled with the metal plating to form a conductor.
- patterning may be performed by the subtractive method ⁇ the semi-additive method. By performing such a procedure, the electroless plating or other alternative treatment becomes unnecessary, and the conductor can be formed only by the electric plating.
- the deposition rate of the plating is high because the edge of the power supply portion is used, and after the plating is grown, the plating is performed by depositing the plating using the edge and the bottom of the opening as electrodes. The deposition rate can be improved.
- the lower layer wiring and the conductor portion located above the lower layer wiring are used for convenience of configuration, but the electronic component manufactured by the above process is not limited to this upper / lower relationship. It goes without saying that the conductor portion may be used as the lower side, and the lower layer wiring may be arranged above the conductor portion.
- FIG. 1 is a cross-sectional view of a main part showing a form immediately after a conductor part is formed on a wiring layer.
- 2A, 2B, 2C, and 2D are process explanatory diagrams showing a procedure for forming a conductor portion above a columnar conductor.
- 3A, 3B, 3C, 3D, and 3E are process explanatory diagrams showing a procedure for forming a conductor portion above a columnar conductor.
- FIGS. 4A, 4B, 4C, and 4D are process explanatory views showing a procedure for forming a conductor portion on a substrate having a wiring layer formed on the back surface and inside of the substrate.
- FIGS. 5A, 5B, 5C, 5D, and 5E are process explanatory views showing a procedure for forming a conductor portion on a base material having a wiring layer formed on the back surface and inside of the base material.
- 6A, 6B, 6C, and 6D are process explanatory diagrams showing another procedure for forming a conductor portion above a columnar conductor.
- 7A, 7B, 7C, 7D, and 7E are process explanatory diagrams showing another procedure for forming a conductor portion above a columnar conductor.
- 8A, 8B, 8C, and 8D are process explanatory views showing a conventional process of manufacturing a wiring layer of an electronic component.
- 9A and 9B are process explanatory views showing a procedure for forming an opening using laser processing of an electronic component.
- FIGS. 10A, 10B, and 10C are process explanatory diagrams showing a procedure for forming a conductor portion in an opening of an electronic component.
- the electronic component according to the present embodiment has a form in which wiring layers are sequentially laminated on both surfaces of a core material. The connection between the stacked wiring layers is performed to form a solid wiring structure.
- FIG. 1 is a cross-sectional view of a main part showing a form immediately after a conductor part is formed on a wiring layer.
- the wiring layer 10 constituting the electronic component according to the present embodiment includes a base material 12 made of an insulating member having a certain thickness, and an upper surface of the base material 12. It has a copper foil 14 formed uniformly and a columnar conductor 16 serving as a lower layer wiring formed inside the base material 12.
- An opening 18 penetrating the base material 12 and the copper foil 14 is formed above the columnar conductor 16, and a conductor 20 made of a metal material is formed inside the opening 18.
- the conductor portion 20 that electrically connects the copper foil 14 serving as the base of the upper layer wiring and the columnar conductor 16 is formed only by electric plating without performing pretreatment such as electroless plating. It is a thing. Therefore, in the wiring layer 10 manufactured by the manufacturing method according to the present embodiment, the electroless plating or the like Since the pre-processing step is unnecessary, the manufacturing process can be shortened. In addition, the elimination of the pretreatment step prevents the metal catalyst remaining on the copper foil 14 side, for example, for attaching metal to portions (insulator portions) other than the conductor in the electroless plating process. This can improve the reliability of electronic components.
- FIGS. 3A to 3E are process explanatory diagrams showing a procedure for forming a conductor portion above a columnar conductor.
- a dry film (protective film) 24 is provided on the upper surface of the copper foil 14 serving as the power supply film. to paste together. After laminating the dry film 24, photo-etching is performed on the dry film 24 as shown in FIG. 2B, so that the dry film 24 is formed in the region where the opening 18 is to be formed. Form corresponding holes.
- FIG. 2C shows a state after the copper foil 14 has been removed by etching.
- etching and blasting are used to remove the copper foil 14 and the base material 12 located above the columnar conductor 16, but the present invention is not limited to this.
- these members may be removed by performing laser irradiation using a laser processing machine in accordance with the copper foil 14 and the base material 1 "2 (for example, with respect to the copper foil 14 Is a YA G laser and a carbon dioxide laser is used for the substrate 12)-After the opening 18 is formed in the substrate 12 by the above-described process, Fig.
- electric plating is performed using the copper foil 14 as a power supply film (so-called electrode).
- the electric plating is performed while leaving the dry film 24 used in the etching and blasting process as it is.
- the conductor is more positively deposited using the recording end.
- the inner wall surface of the opening 18 is etched (or laser-processed) so that the end surface which becomes the edge of the copper foil 14 is exposed.
- a metal material 26 as a base of the conductor portion 20 is deposited from the end face of the copper foil 14, and the metal material 26 grows in the opening 18.
- the metal material 26 grows over time, the metal material 26 reaches the upper surface 28 of the columnar conductor 16. This state is shown in FIG. 3B. When the metal material 26 reaches the upper surface 28 of the columnar conductor 16 in this way, the copper foil 14 and the columnar conductor 16 are electrically connected, and the upper surface 28 of the columnar conductor 16 is deposited. The metal material 26 is also deposited on the upper surface 28 to form a conductor portion 20. This state is shown in Figure 3C.
- the dry film 24 is removed as shown in FIG. 3D, and then, as shown in FIG. 3E, the copper foil 14 is formed by the subtractive method ⁇ semi-additive method. Then, patterning is performed to form the upper wiring 30 from the copper foil 14. Further, it is necessary to make the height of the conductor portion 20 formed by the electric plating equal to the height of the upper layer wiring 30 or to make the surface of the conductor portion 20 flat. After the conductor portion 20 is formed, the upper surface thereof is polished so that the height of the conductor portion 20 is made equal to that of the upper layer wiring 30. Alternatively, when the conductor portion 20 is formed, a timer management or an electric The adjustment may be made by controlling the current or adding an additive to the plating solution.
- FIGS. 4A to 4D and FIGS. 5A to 5E are process explanatory diagrams showing a procedure for forming a conductor portion on a substrate having a wiring layer formed on the back surface and inside of the substrate.
- the electrolysis can be performed. Only by this, it is possible to form the conductor portion 20 exposed on the upper wiring 30 side.
- a dry film 24 is attached to the upper surface of the wiring layer 12 and then, as shown in FIGS. 4B to 4D, photo-etching of the dry film 24 and copper foil Etching of the substrate 14 and blasting of the substrate 12 are performed to form an opening 18 on the surface of the substrate 12.
- the copper foil 14 is used as a power supply film to form the opening.
- Gold in 1 8 The material 26 is deposited and grown. Then, as shown in FIG.
- the dry film 24 is removed as shown in FIG. 5D, and thereafter, the copper foil 14 is patterned as shown in FIG. 30 may be formed.
- the copper foil 14 serving as the base of the upper wiring 30 is used as a power supply film. If used, the conductor portion 20 can be formed only by the electric plating step without applying a pretreatment step such as electroless plating.
- the electrodeposition is performed with the dry film left on the surface of the copper foil, but the present invention is limited to this form. Without this, the present invention can be achieved without leaving a dry film on the surface of the copper foil.
- FIGS. 6A to 6D and FIGS. 7A to 7E are process explanatory views showing another procedure for forming a conductor portion above the columnar conductor.
- 2A to 2D and 3A to 3E members that are common to the method of forming a conductor portion will be described using the same reference numerals.
- a dry film (protective film) 24 is provided on the upper surface of the copper foil 14 serving as the power supply film. to paste together. After laminating the dry film 24, photo-etching is performed on the dry film 24 as shown in FIG. 6B, and the edge of the opening 18 is formed in a region where the opening 18 is to be formed. Is formed. After forming a hole corresponding to the edge of the opening 18 in the dry film 24 in this manner, the copper foil 14 exposed below the dry film 24 is etched. PT / JP2004 / 008298
- FIG. 6C shows a state after the copper foil 14 has been removed by etching.
- the base material 12 is subjected to a blast treatment as shown in FIG.
- the substrate 12 located is removed to expose the head of the columnar conductor 16.
- the openings 18 are formed in the base material 12 by the above-described process, as shown in FIG. 7A, the dry film 24 located on the upper layer of the copper foil 14 is removed, and the copper foil 1 is removed. Expose 4.
- the metal material 26 reaches the upper surface 28 of the columnar conductor 16 as shown in FIG. 7C.
- the metal material 26 reaches the upper surface 28 of the columnar conductor 16 in this way, the copper foil 14 and the columnar conductor 16 are electrically connected to each other, and the upper surface 28 of the columnar conductor 16 is also attached. It becomes an electrode for deposition, and the metal material 26 is also deposited on the upper surface 28 to form the conductor portion 20. This state is shown in FIG. 7D.
- the copper foil 14 is patterned by the subtractive method ⁇ the semi-additive method, and the upper layer wiring 30 is formed from the copper foil 14. do it.
- the lower layer wiring and the conductor located above the lower layer wiring are used.
- the present invention is not limited to this upper / lower relationship, and any wiring layer manufactured by the above process may be used.
- the electronic component using this is the conductor part (upper wiring side) It is needless to say that the lower layer wiring may be arranged on the lower side and the lower layer wiring may be arranged on the upper side of the conductor section.
- a method of manufacturing an electronic component in which a conductor connected from the lower wiring is exposed on an upper surface of an insulating member covering the lower wiring, wherein power is supplied to the upper surface of the insulating member.
- an opening is formed from the power supply film side with the lower layer wiring as a bottom, and a metal plating is grown from the opening to an edge of the power supply film using the power supply film as an electrode, Since the opening is filled with metal plating that is in close contact with the lower wiring and is used as the conductor, the electroless plating step (or another alternative processing step) conventionally performed can be eliminated.
- the manufacturing process can be simplified, and the residual metal catalyst can be solved, so that the electrical reliability can be improved.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2004800165668A CN1806476B (zh) | 2003-06-13 | 2004-06-08 | 电子部件的制造方法和电子部件 |
US10/559,334 US7371682B2 (en) | 2003-06-13 | 2004-06-08 | Production method for electronic component and electronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-168824 | 2003-06-13 | ||
JP2003168824A JP3674927B2 (ja) | 2003-06-13 | 2003-06-13 | 電子部品の製造方法および電子部品 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004112449A1 true WO2004112449A1 (ja) | 2004-12-23 |
Family
ID=33549344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/008298 WO2004112449A1 (ja) | 2003-06-13 | 2004-06-08 | 電子部品の製造方法および電子部品 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7371682B2 (ja) |
JP (1) | JP3674927B2 (ja) |
KR (1) | KR100772294B1 (ja) |
CN (1) | CN1806476B (ja) |
TW (1) | TWI303148B (ja) |
WO (1) | WO2004112449A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8314348B2 (en) * | 2008-03-03 | 2012-11-20 | Ibiden Co., Ltd. | Multilayer printed wiring board and method of manufacturing multilayer printed wiring board |
TWI492349B (zh) * | 2010-09-09 | 2015-07-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
CN114501801A (zh) * | 2020-10-28 | 2022-05-13 | 深南电路股份有限公司 | 一种线路板的加工方法及线路板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05335713A (ja) * | 1992-05-28 | 1993-12-17 | Fuji Kiko Denshi Kk | 片側閉塞微小スルホール付きプリント基板用積層板、およびそのプリント基板用積層板への導通メッキ方法 |
JPH10209644A (ja) * | 1997-01-16 | 1998-08-07 | Nippon Steel Chem Co Ltd | 多層配線板の製造方法 |
JPH1117340A (ja) * | 1997-06-27 | 1999-01-22 | Kokusai Electric Co Ltd | ブラインドスルーホールの形成方法 |
JP2003110211A (ja) * | 2001-09-28 | 2003-04-11 | Nitto Denko Corp | 回路基板およびその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0411165B1 (en) * | 1989-07-26 | 1997-04-02 | International Business Machines Corporation | Method of forming of an integrated circuit chip packaging structure |
CA2089791C (en) * | 1992-04-24 | 1998-11-24 | Michael J. Brady | Electronic devices having metallurgies containing copper-semiconductor compounds |
JPH11343593A (ja) | 1998-03-31 | 1999-12-14 | Mitsubishi Electric Corp | メッキ方法 |
JPH11307938A (ja) | 1998-04-18 | 1999-11-05 | Ibiden Co Ltd | コア基板、コア基板の製造方法及び多層プリント配線板 |
TW522536B (en) * | 1998-12-17 | 2003-03-01 | Wen-Chiang Lin | Bumpless flip chip assembly with strips-in-via and plating |
SG82590A1 (en) * | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips and via-fill |
TW408190B (en) | 1999-04-01 | 2000-10-11 | United Microelectronics Corp | Method of producing a metal conductive layer in the via hole of the inter-metal dielectrics of a semiconductor chip |
JP2001217553A (ja) | 2000-02-03 | 2001-08-10 | Nippon Zeon Co Ltd | 多層回路基板の製造方法 |
JP2002151623A (ja) | 2000-11-10 | 2002-05-24 | Shigetaka Ooto | ブラインドホ−ルがめつきによって穴埋めされた2メタルレイヤ−テ−プbga(tbga)の製造方法 |
JP2002223059A (ja) | 2001-01-24 | 2002-08-09 | Sharp Corp | 微細パターン形成方法 |
-
2003
- 2003-06-13 JP JP2003168824A patent/JP3674927B2/ja not_active Expired - Fee Related
-
2004
- 2004-06-08 WO PCT/JP2004/008298 patent/WO2004112449A1/ja active Application Filing
- 2004-06-08 CN CN2004800165668A patent/CN1806476B/zh not_active Expired - Fee Related
- 2004-06-08 US US10/559,334 patent/US7371682B2/en not_active Expired - Lifetime
- 2004-06-08 KR KR1020057023819A patent/KR100772294B1/ko not_active IP Right Cessation
- 2004-06-11 TW TW093116940A patent/TWI303148B/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05335713A (ja) * | 1992-05-28 | 1993-12-17 | Fuji Kiko Denshi Kk | 片側閉塞微小スルホール付きプリント基板用積層板、およびそのプリント基板用積層板への導通メッキ方法 |
JPH10209644A (ja) * | 1997-01-16 | 1998-08-07 | Nippon Steel Chem Co Ltd | 多層配線板の製造方法 |
JPH1117340A (ja) * | 1997-06-27 | 1999-01-22 | Kokusai Electric Co Ltd | ブラインドスルーホールの形成方法 |
JP2003110211A (ja) * | 2001-09-28 | 2003-04-11 | Nitto Denko Corp | 回路基板およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1806476A (zh) | 2006-07-19 |
CN1806476B (zh) | 2011-08-31 |
US7371682B2 (en) | 2008-05-13 |
US20060128143A1 (en) | 2006-06-15 |
KR20060018264A (ko) | 2006-02-28 |
TW200507723A (en) | 2005-02-16 |
KR100772294B1 (ko) | 2007-11-02 |
TWI303148B (en) | 2008-11-11 |
JP2005005559A (ja) | 2005-01-06 |
JP3674927B2 (ja) | 2005-07-27 |
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