WO2002103787A1 - Substrate for use in joining element - Google Patents
Substrate for use in joining element Download PDFInfo
- Publication number
- WO2002103787A1 WO2002103787A1 PCT/JP2002/005202 JP0205202W WO02103787A1 WO 2002103787 A1 WO2002103787 A1 WO 2002103787A1 JP 0205202 W JP0205202 W JP 0205202W WO 02103787 A1 WO02103787 A1 WO 02103787A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- layer
- solder
- metal
- gold
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 119
- 238000005304 joining Methods 0.000 title abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 106
- 239000010931 gold Substances 0.000 claims abstract description 82
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052737 gold Inorganic materials 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 230000008018 melting Effects 0.000 claims abstract description 20
- 238000002844 melting Methods 0.000 claims abstract description 20
- 238000005476 soldering Methods 0.000 claims abstract description 20
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 15
- 229910052709 silver Inorganic materials 0.000 claims abstract description 15
- 229910052802 copper Inorganic materials 0.000 claims abstract description 14
- 229910052745 lead Inorganic materials 0.000 claims abstract description 13
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 27
- 229910052718 tin Inorganic materials 0.000 claims description 23
- 239000000919 ceramic Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052738 indium Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 229910015363 Au—Sn Inorganic materials 0.000 abstract description 23
- 239000010410 layer Substances 0.000 description 123
- 230000004888 barrier function Effects 0.000 description 21
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical group [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000010953 base metal Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000010587 phase diagram Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910020935 Sn-Sb Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910008757 Sn—Sb Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910000905 alloy phase Inorganic materials 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000010938 white gold Substances 0.000 description 1
- 229910000832 white gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Definitions
- the present invention relates to a substrate for bonding elements and a method for manufacturing the same.
- the present invention relates to a substrate for bonding and fixing elements and a method for manufacturing the same.
- GaAs-based FETs Si-Ge-based HBTs, Si-based MO SFETs, and GaN-based lasers that operate in the high-frequency band have been developed.
- Ceramic substrates are used as substrates for mounting semiconductor elements such as semiconductors because of their low dielectric loss at high frequencies.
- aluminum nitride sintered substrates have attracted special attention because of their high thermal conductivity and thermal expansion coefficient close to that of semiconductor devices.
- the first and second base metal layers firmly bonded to the ceramic substrate are formed by metallization, and then the base metal layer is formed. It is common to form a gold electrode on top and solder the element to the gold electrode (see JP-A-7-94786, JP-A-10-242327 and JP-A-2000-288770). ).
- the solder used at this time is Au—Sn-based solder having a melting point of 280 in a composition containing about 80% by weight of gold (hereinafter referred to as “gold-rich Au—Sn-based solder”). Young's modulus 59. 2GPa (at 25 ° C)) is commonly used.
- soldering method using gold-rich Au-Sn-based solder is based on the fact that the mounting position of the element can be precisely controlled and automation is easy, so the solder supplied to the substrate in advance is used.
- the reflow method of melting and joining the components is suitably employed.
- a substrate in which a solder film is previously formed at a predetermined position on the substrate electrode layer is often used.
- a substrate in which a solder film is previously formed at a predetermined position on the substrate electrode layer is often used.
- a substrate in which a solder film is previously formed at a predetermined position on the substrate electrode layer is often used.
- Japanese Patent Application Publication No. 0-2887770 discloses that a multilayer electrode composed of a base layer, an i-plate layer, a ZA U-plate layer, and the like is formed on a ceramic substrate, and that “the lowermost layer is an Au thin film,
- a substrate in which a wiping prevention metal layer is laminated thereon, and a multilayer solder having an alternate layer of an Au layer and a Sn layer is laminated on the diffusion prevention metal layer, and the substrate has an AU electrode. It is shown that a semiconductor element can be joined with a sufficient joining strength.
- the multilayer solder has a Au / Sn content of 70/30 to 7 so that the total weight ratio of Au to Sn becomes the same as the composition of the gold-rich Au—Sn solder when molten. It is described that a laminate of an Au layer and a Sn layer at a weight ratio of 6/24 is suitable. Further, the diffusion preventing metal layer prevents the diffusion of voids and impurities caused by the plating solution mixed at the time of plating, such as an Au plating layer, and prevents the diffusion on the layer.
- the solder has a low melting point and is soft, such as Au—Sn alloy, in which the tin content exceeds 80% by weight and the melting point is less than 280 ° C. It can be realized by using a solder made of a low melting point alloy (hereinafter, also referred to as "tin-rich Au-Sn-based solder"). However, when a tin-rich Au-Sn-based solder layer was actually formed on the gold electrode layer formed on the substrate and the soldering of the element was performed, the melting point of the solder increased and the solder was soldered. It has been clarified that the melting characteristics of the alloy deteriorate.
- the present inventor has reported that the diffusion of gold as described above (in other words, the corrosion of gold by a tin-rich Au—Sn solder) is a diffusion preventing metal as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2000-288770. It is thought that this can be prevented by providing a metal barrier layer (hereinafter, also referred to as a metal barrier layer).
- a metal barrier layer made of Pt with a thickness of 2 m is provided on the gold electrode layer, and tin is We formed a rich Au-Sn solder film layer and soldered a device with gold electrodes.
- An object of the present invention is to provide a substrate for element bonding, which has a gold electrode layer on its surface and can bond solder with high bonding strength.
- Another object of the present invention is to provide an element having a gold electrode layer on its surface, which can be soldered at a low temperature by using a soft hang having a low melting point such as tin-rich Au-Sn solder.
- An object of the present invention is to provide a bonding substrate.
- Still another object of the present invention is to provide a method for manufacturing a device bonding substrate having a gold electrode layer on its surface, which can bond solder with high bonding strength.
- the present inventor has made intensive studies to solve the above-mentioned problems.
- a substrate having a metal electrode layer formed of a specific metal on the gold electrode layer of a substrate having a gold electrode layer formed on the surface was used, and the element was formed using tin-rich Au-Sn solder using the substrate.
- Solder We found that soldering can be performed at low temperatures and that the bonding strength at that time is high. As a result of further study based on the findings, it was found that such an effect is not limited to the use of tin-rich Au-Sn-based solder, and that the In-based alloy having a gold content of less than 20% by weight was used.
- the present inventors have found that the expression occurs even when solder is used, and have completed the present invention.
- the first invention of the present application provides at least one metal selected from the group consisting of Ag, Cu, Ni, and Pb on a gold electrode layer of a substrate having a surface formed with a gold electrode layer.
- An element bonding substrate characterized in that it has a laminated structure in which metal layers made of are laminated.
- the element bonding substrate according to the present invention includes a solder layer made of a metal containing Sn or In as a main component and having a gold content of less than 20% by weight, such as a tin-rich Au—Sn-based solder. It has the characteristic that the element can be bonded with high bonding strength by using.
- a substrate having a gold electrode layer formed on the surface a ceramic substrate mainly composed of aluminum nitride, a first underlayer mainly composed of Ti, Pt
- a metallized substrate in which a second underlayer mainly composed of and a gold electrode layer are laminated in this order not only the high-frequency dielectric loss when the elements are bonded and used, but also However, it has the feature that the function to radiate the heat generated at that time is high.
- a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb Sn or In is contained as a main component and gold is contained.
- the element bonding substrate having a laminated structure in which a solder layer made of a metal having less than 20% by weight is further laminated can be suitably used for reflow soldering. Further, the metal forming the solder layer contains Sn or In as a main component, the gold content is less than 20% by weight, the Young's modulus at 25 is less than 5 OGPa, In addition, the element bonding substrate having a melting point of less than 280 ° C. has a feature that the bonding surface is hardly broken even when the elements are bonded and used for a long time.
- the second invention of the present application is directed to a substrate having a gold electrode layer bonded to a surface thereof, on the gold electrode layer, at least one metal selected from the group consisting of Ag, Cu, Ni and Pb.
- a method for manufacturing a device bonding substrate comprising forming a metal layer made of a metal.
- Sn or In as a main component is formed on a formed metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni, and Pb.
- a solder layer made of a metal having a gold content of less than 20% by weight a substrate for element bonding which can be suitably used for the reflow soldering can also be manufactured.
- an element having an electrode is mounted on the solder layer of the element bonding substrate, which is preferably used for the reflow soldering, such that the electrode is in contact with the solder layer.
- This is a method for manufacturing an element bonding substrate, which is characterized by performing reflow soldering later. According to the above manufacturing method, the element can be accurately and efficiently soldered at a low temperature of, for example, less than 280 ° C.
- the fourth invention of the present application is an element bonding substrate manufactured by the above method.
- the element bonding substrate of the fourth invention of the present application can be used stably for a long period of time.
- FIG. 1 is a phase diagram of an Au—Sn alloy.
- FIG. 2 is a typical cross-sectional view of the element bonding substrate of the present invention.
- the substrate for element bonding is a substrate having a gold electrode layer formed on a surface thereof. It has a laminated structure in which a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb is laminated on the layer. It refers to electronic components and semiconductor elements such as resistors and capacitors having terminals that can be directly connected to wiring.
- the “substrate having a gold electrode layer formed on its surface” used for the element bonding substrate of the present invention is not particularly limited as long as it is a substrate on which a layer made of gold that functions as an electrode is formed on part or all of its surface. Not done. From the viewpoint of low dielectric loss at high frequencies when semiconductor devices are bonded and used, metallized substrates with metal electrodes formed by metallization on ceramic substrates of aluminum nitride, alumina, SiC, Si, etc. It is preferred to use In these metallized substrates, as described above, the gold electrode layer is generally formed directly or indirectly on a base metal layer firmly bonded to a ceramic substrate.
- an electrode pattern made of a refractory metal base such as tungsten or molybdenum is printed on an alumina green sheet, and the pattern is simultaneously sintered with the green sheet. Then, if necessary, a nickel layer is formed as a refractory metal layer. It is preferable to use a metal electrode formed thereon and further forming a gold electrode thereon.
- a sintering aid is added to aluminum nitride powder, and after forming, the surface of the sintered substrate is basically formed with an electrode pattern by a sputtering method or the like.
- a metal layer (first underlayer) mainly composed of titanium having the same shape After forming a metal layer (first underlayer) mainly composed of titanium having the same shape, a second underlayer mainly composed of platinum is similarly formed on the first underlayer by a sputtering method or the like.
- a metallized substrate obtained by forming a gold electrode layer thereon by a sputtering method or the like can be suitably used.
- the aluminum nitride-based metallized substrate obtained as described above is used from the viewpoint of good heat radiation characteristics for radiating heat generated when the elements are bonded and used. Is particularly preferred.
- a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb needs to be formed on the gold electrode layer.
- a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb needs to be formed on the gold electrode layer.
- a tin-rich Au—Sn-based When soldering is performed by forming a layer of soft solder having a low melting point such as solder, it becomes possible to perform soldering with high bonding strength at low temperatures.
- the metal layer is considered to have the same function as the above-mentioned metal barrier layer (therefore, the metal layer is also simply referred to as a barrier layer hereinafter).
- platinum is the most common metal for a metal barrier layer.
- the thickness of the barrier layer is not particularly limited, but is preferably 0.2 to 5 m, particularly preferably 1 to 3 m from the viewpoint of cost performance.
- the thickness of the layer is less than 0.2 zm, the effect is low, and when the thickness is 5 m or more, the effect is almost the same as when the thickness is 1 to 3 m.
- the metal layer is not particularly limited as long as it is made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb, and is made of a single metal species.
- the alloy may be an alloy composed of a plurality of metal species, an intermetallic compound or a solid solution, but is most preferably composed of Ag from the viewpoint of the effect.
- the barrier layer does not need to cover the entire surface of the gold electrode layer, but it is preferable that at least a portion of the gold electrode layer where elements are joined or a portion that comes into contact with solder is covered with at least a barrier layer.
- the method for forming the barrier layer on the gold electrode layer is not particularly limited, and can be suitably performed by, for example, a sputtering method, an ion plating method, an evaporation method, a CVD method, or a plating method.
- solder can be supplied at the time of soldering and bonded to the element, but the element can be accurately placed at a predetermined position.
- solder for the solder layer to be formed on the solder layer is not particularly limited, but the effect of the barrier layer is particularly high because the solder itself is relatively soft and can be soldered at a low temperature.
- solder consisting of a metal containing, Sn or In as the main component and a gold content of less than 20% by weight, especially less than 10% by weight. Is preferred.
- solders include the above-mentioned tin-rich Au—Sn solder, Sn 100% solder, Sn—Ag solder, Sn—Pb solder, Sn—Bi solder, Sn—Sb solder, Sn— In solder, ⁇ 100% solder, In—Au solder (but less than 20% by weight of gold), In—Ag solder, In—Bi solder, In—Sb solder, I Examples include n—Zn solders and solders arbitrarily combining these solders.
- Au—Sn-based solder can be particularly preferably used because the bonding strength in the die shear test after bonding to the element is the highest.
- the above-described element is bonded to a solder made of a metal containing Sn or In as a main component and containing less than 20% by weight of gold as described above.
- a solder made of metal with a melting point of less than 280 ° C, especially 235 ° C or less and a Young's modulus of less than 5 OGPa (at 25 ⁇ ), from the viewpoint that it is unlikely that the joint will be destroyed due to temperature changes during use. Is most preferred.
- the solder layer in the soldered substrate of the present invention may be composed of a single layer composed of a single-component metal, and a composition that satisfies the above-described conditions when each layer is melted and mixed. It may be composed of a laminate of a plurality of layers made of metals having different compositions so that The thickness of the entire solder layer is preferably 1 to: L 0 m, and particularly preferably 2 to 6 m. If the thickness of the layer is less than 1 m, sufficient bonding strength tends not to be obtained because the absolute amount of solder is small.On the other hand, if the thickness exceeds 1, the amount of solder is too large and hangs after bonding.
- the method of forming a layer made of solder as described above on the barrier layer is not particularly limited, and can be suitably performed by, for example, a sputtering method, an ion plating method, an evaporation method, a CVD method, or a plating method.
- the method of joining a device such as a semiconductor device to the device joining substrate of the present invention is not particularly limited, and a known soldering method can be employed without any limitation.
- An element having an electrode on the solder layer of the element bonding substrate of the present invention, which is a substrate with solder, is placed so that the electrode contacts the solder layer. After that, it is preferable to perform reflow soldering.
- reflow soldering means that solder is supplied to predetermined lands on the board, component electrodes, or both in advance, and after the components are fixed to the predetermined positions on the board, In this method, the solder is melted (flown) to join the component and the board.
- the method of reflowing the solder is not particularly limited, and a method using a reflow conveyor, a method using a hot plate, a vapor reflow method, or the like can be employed.
- the heating temperature and the heating time may be appropriately determined according to the type of solder used. However, when the element bonding substrate of the present invention is used, the characteristics of the used hang are not impaired. When a rich Au—Sn solder is used, good soldering can be performed at a low temperature of less than 280 ° C.
- the element to be soldered is not particularly limited as long as it has an electrode made of a metal that can be joined by solder.
- the above-mentioned electrodes are often made of gold.
- gold atoms of the gold electrode diffuse into the solder.However, as shown in an example described later, when an element having a gold electrode is soldered. Since high bonding strength is obtained, the diffusion that occurs at this time does not seem to have a significant effect on bonding strength.
- the electrode surface of the element in contact with the solder must have at least i kinds of electrodes selected from the group consisting of Ag, Cu, Ni and Pb. It is preferable to coat with metal, especially Ag.
- FIG. 2 is a cross-sectional view of a typical element bonding substrate 100 of the present invention, in which a first lower layer mainly composed of Ti is formed on an aluminum nitride sintered substrate 201.
- a barrier layer 300 made of a metal such as silver and a solder layer 400 made of a Sn-based or In-based metal having a gold content of less than 20% by weight are laminated on the 200 gold electrode layer. It has a structure.
- a titanium nitride substrate with a thickness of 0.06 zm 50.8 mmX 50.8 mmX0.3 mmt, manufactured by Tokuyama Corporation) was sputtered on a surface of the substrate using a sputtering apparatus.
- a barrier layer consisting of a 2 m-thick Ag film was formed on the gold electrode layer using a vacuum evaporation apparatus, and then a gold content of 10% was obtained by a simultaneous evaporation method using Au and Sn as targets.
- a device bonding substrate was prepared in the same manner as in Example 1, except that a bonding temperature was set to 210 ° C.
- Ten element bonding substrates were prepared in the same manner, and the bonding strength was measured in the same manner as in Example 1. The average bonding strength was 2.5 kgf / mm2, and the peeling mode was within 100% solder.
- Example 1 a device bonding substrate and a device bonding substrate were prepared in the same manner as in Example 1 except that the material of the pal layer was changed from Ag to the metal shown in Table 1. The joining strength was measured in the same manner. Table 1 also shows the results.
- Example 1 a device bonding substrate and a device bonding substrate were prepared in the same manner as in Example 1 except that the thicknesses of the anode and solder layers were changed to the film thicknesses shown in Table 1. To measure the bonding strength. Table 1 also shows the results.
- a device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the thickness of the barrier layer was changed to the thickness shown in Table 1 in Example 1, and bonding was performed in the same manner as in Example 1. The strength was measured. Table 1 also shows the results.
- a device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the NOR layer was not provided, and the bonding strength was measured. Table 1 also shows the results. As shown in Table 1, when the barrier layer was not provided, the average joint strength was 0.8 kgf Zmm 2 .
- a device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the material of the barrier layer was changed from Ag to Pt, and the bonding strength was measured. Table 1 also shows the results. As shown in Table 1, even when the metal layer was provided, when the material was not the metal specified in the present invention, the average bonding strength was only 1.4 kgf Zmm 2 .
- AulO—Sn: 11-Sn alloy with gold content of 10% by weight As described above, by using the element bonding substrate of the present invention, tin is formed on the gold electrode of the substrate having the gold electrode formed on the surface.
- the semiconductor element can be soldered at a low temperature and with high bonding strength by using a soft solder having a low melting point, such as that of the Au-Sn series solder.
- the element bonding substrate of the present invention thus bonded can be stably used for a long period of time because the bonding portion is not easily broken even when the temperature difference during use is large.
- a substrate using a ceramic substrate mainly composed of aluminum nitride with a gold electrode formed on the surface as the substrate has such characteristics, and in addition to having a low dielectric loss of high frequency, it is generated during use. It is a very good device bonding board that combines the features of good heat dissipation characteristics to dissipate heat.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
A substrate for use in joining an element which comprises a base substrate of aluminum nitride or the like, a gold electrode layer formed on the surface thereof, a metal layer comprising at least one metal selected from the group consisting of Ag, Cu, Ni and Pb formed on the gold electrode layer and, formed thereon, a layer comprising a soft solder having a low melting point such as an Au-Sn type solder having a gold content of 20 wt % or less. An element having an electrode is joined by placing the element in such a manner that the electrode is contacted with the solder layer of the above substrate and then soldering by reflow at a low temperature. The above substrate allows an element to be joined to the substrate with enhanced joining strength.
Description
明 細 素子接合用基板およびその製造方法 技術分野 TECHNICAL FIELD The present invention relates to a substrate for bonding elements and a method for manufacturing the same.
本発明は、 素子を接合、 固定するための基板およびその製造方法に関するもの である。 The present invention relates to a substrate for bonding and fixing elements and a method for manufacturing the same.
背景技術 Background art
近年、 携帯電話や光通信などの普及に伴い高周波帯域で作動する高出力 ·高消 費電力の GaAs系 FET、 S i— Ge系 HBT、 S i系 MO S F E Tあるいは G a N系レーザ一ダイォ一ドなどの半導体素子の実装用基板として、 セラミック ス基板が高周波の誘電損失が少ないため使用されている。 このセラミックス基板 の中でも窒化アルミニウム焼結体基板は、 熱伝導率が高く熱膨張係数が半導体素 子に近いことから特に注目されている。 In recent years, with the spread of mobile phones and optical communications, high output and high power GaAs-based FETs, Si-Ge-based HBTs, Si-based MO SFETs, and GaN-based lasers that operate in the high-frequency band have been developed. Ceramic substrates are used as substrates for mounting semiconductor elements such as semiconductors because of their low dielectric loss at high frequencies. Among these ceramic substrates, aluminum nitride sintered substrates have attracted special attention because of their high thermal conductivity and thermal expansion coefficient close to that of semiconductor devices.
通常、 窒化アルミニウム焼結体等のセラミックス基板上に素子を接合する場合 には、 メタライゼーシヨンによりセラミックス基板に強固に接合した第一および 第二下地金属層を形成した後、 該下地金属層上に金電極を形成し、 該金電極に素 子をハンダ付けするのが一般的である （特開平 7— 94786号公報、 特開平 1 0-242327号公報および特開 2000— 288770号公報参照） 。 そし て、 そのときに用いるハンダとしては、 金の含有量が約 80重量％の組成におけ る融点が 280 である Au— Sn系ハンダ （以下、 「金リッチ Au— S n系ハ ンダ」 ともいう。 ヤング率 59. 2GP a (25°Cにおいて） ） が一般に使用さ れている。 また、 上記の金リッチ Au— Sn系ハンダを用いた八ンダ付け方法と しては、 素子の搭載位置を精密に制御でき、 自動化も容易であることから、 あら かじめ基板に供給されたハンダを溶かして接合するリフロー法が好適に採用され ている。 Normally, when an element is bonded on a ceramic substrate such as an aluminum nitride sintered body, the first and second base metal layers firmly bonded to the ceramic substrate are formed by metallization, and then the base metal layer is formed. It is common to form a gold electrode on top and solder the element to the gold electrode (see JP-A-7-94786, JP-A-10-242327 and JP-A-2000-288770). ). The solder used at this time is Au—Sn-based solder having a melting point of 280 in a composition containing about 80% by weight of gold (hereinafter referred to as “gold-rich Au—Sn-based solder”). Young's modulus 59. 2GPa (at 25 ° C)) is commonly used. In addition, the soldering method using gold-rich Au-Sn-based solder is based on the fact that the mounting position of the element can be precisely controlled and automation is easy, so the solder supplied to the substrate in advance is used. The reflow method of melting and joining the components is suitably employed.
そのため、 素子を接合する基板としては、 基板電極層上の所定の位置にハンダ 膜をあらかじめ形成したものが使用されることも多い。 例えば、 上記特開 200
0 - 2 8 8 7 7 0号公報には、 セラミックス基板上に下地層 iメツキ層 ZA Uメツキ層等からなる多層電極を形成し、 該電極上に 「最下層が Au薄膜であり、 Au薄膜上に拭散防止金属層が積層され、 該拡散防止金属層上に Au層と S n層 の交互層を有する多層ハンダ」 を積層した基板が開示されており、 該基板には A U電極を有する半導体素子を十分な接合強度で接合できることが示されている。 該公報では、 上記多層ハンダとしては、 全体の Auと S nの重量比が溶融時に金 リッチ Au— S n系ハンダの組成と同じになるように Au/S nで 7 0 / 3 0〜 7 6 / 2 4となるような重量比で Au層と S n層が積層されたものが好適である と説明されている。 さらに、 上記拡散防止金属層は、 A uメツキ層等のメツキ時 に混入したメツキ液に起因するボイドゃ不純物の拡散を防止すると共に該層上のTherefore, as a substrate for bonding the elements, a substrate in which a solder film is previously formed at a predetermined position on the substrate electrode layer is often used. For example, see Japanese Patent Application Publication No. 0-2887770 discloses that a multilayer electrode composed of a base layer, an i-plate layer, a ZA U-plate layer, and the like is formed on a ceramic substrate, and that “the lowermost layer is an Au thin film, There is disclosed a substrate in which a wiping prevention metal layer is laminated thereon, and a multilayer solder having an alternate layer of an Au layer and a Sn layer is laminated on the diffusion prevention metal layer, and the substrate has an AU electrode. It is shown that a semiconductor element can be joined with a sufficient joining strength. According to the publication, the multilayer solder has a Au / Sn content of 70/30 to 7 so that the total weight ratio of Au to Sn becomes the same as the composition of the gold-rich Au—Sn solder when molten. It is described that a laminate of an Au layer and a Sn layer at a weight ratio of 6/24 is suitable. Further, the diffusion preventing metal layer prevents the diffusion of voids and impurities caused by the plating solution mixed at the time of plating, such as an Au plating layer, and prevents the diffusion on the layer.
Au S n多層ハンダが下地の Auメツキ層を溶食することを防ぐものであり、 該 層を構成する金属としては白金族元素、 特に P tが好適であると説明されている。 ところで近年、 半導体素子においては、 記録密度ゃデ一夕の電送距離を向上さ せるために高出力化が計られ、 使用時に素子から発生する熱量も増大している。 このような発熱量の増大は、 使用時の温度変化の増大を意味し、 基板と素子の熱 膨張係数差に起因する応力により接合部の破壊が惹起されるという問題が起る。 このような問題を解決するための方法として、 （1 ) より低融点のハンダを用い て低温接合を行い、 ハンダ付け後に室温まで冷却したときに素子と基板との接合 部位に残留する応力をできるだけ小さくする方法、 および （2 ) 使角時の温度変 化に起因して接合部位に発生する応力を緩和する能力を有する柔らかいハンダ (ソフトハンダ） を使用する方法等が提案されている。 It is intended to prevent the AuSn multilayer solder from eroding the underlying Au plating layer, and it is described that a platinum group element, particularly Pt, is suitable as a metal forming the layer. By the way, in recent years, the output of semiconductor devices has been increased in order to improve the transmission distance of the recording density / delay, and the amount of heat generated from the devices during use has been increasing. Such an increase in the amount of generated heat means an increase in temperature change during use, and there is a problem that a joint caused by the difference in thermal expansion coefficient between the substrate and the element causes breakage of the joint. In order to solve such problems, (1) low-temperature bonding using solder with a lower melting point is performed, and after cooling to room temperature after soldering, the stress remaining at the bonding site between the element and the substrate is minimized. A method of reducing the size and (2) a method of using a soft solder (soft solder) having an ability to relieve a stress generated at a joint portion due to a change in temperature during use have been proposed.
上記 （1 ) および （2 ) の方法は、 低融点でかつ柔らかいハンダ、 例えば A u — S n系合金において錫の含有量が 8 0重量％を超えかつその融点が 2 8 0 °C未 満という低融点の合金からなるハンダ （以下、 「錫リッチ A u— S n系ハンダ」 ともいう。 ） を使用することにより実現できると考えられる。 しかし、 実際に基 板上に形成された金電極層上に錫リッチ A u— S n系ハンダからなる層を形成し て素子のハンダ付けを行つてみたところ、 ハンダの融点が上昇したりハンダの溶 融特性が悪化したりすることが明らかとなつた。 このような現象が起つた原因は、
図 1に示す A u— S n合金状態図 （出典： 「金属臨時増刊号 実用二元合金状態 図集」 、 株式会社ァグネ、 平成 4年 10月 10日発行、 第 92頁） から理解でき るように、 錫リッチ A u— S n系ハンダ層の製膜中あるいは製膜後の保存中に金 電極層中の金原子が該八ンダ層中に拡散し、 融点の高い組成に変化すると共に金 電極とハンダの界面近傍で、 113112ゃ八113114とぃった脆弱な性質を示す 金属間化合物が形成したためであると考えられる。 In the above methods (1) and (2), the solder has a low melting point and is soft, such as Au—Sn alloy, in which the tin content exceeds 80% by weight and the melting point is less than 280 ° C. It can be realized by using a solder made of a low melting point alloy (hereinafter, also referred to as "tin-rich Au-Sn-based solder"). However, when a tin-rich Au-Sn-based solder layer was actually formed on the gold electrode layer formed on the substrate and the soldering of the element was performed, the melting point of the solder increased and the solder was soldered. It has been clarified that the melting characteristics of the alloy deteriorate. The cause of this phenomenon is that It can be understood from the Au-Sn alloy phase diagram shown in Fig. 1 (Source: "Metal Extra Number, Practical Binary Alloy State Diagrams", Agne Inc., published October 10, 1992, p. 92). As described above, during the formation of the tin-rich Au—Sn-based solder layer or during storage after the formation, the gold atoms in the gold electrode layer diffuse into the metal layer and change to a composition having a high melting point. near the interface of the gold electrode and the solder is thought to be due to the intermetallic compound showing a fragile nature was 11311 2 Ya eight 11311 4 and I'was formed.
本発明者は、 上記したような金の拡散 （換言すれば錫リッチ Au— Sn系ハン ダによる金の溶食） は前記の特開 2000-288770号公報に開示されてい るような拡散防止金属層 （以下、 金属バリヤ層ともいう。 ） を設けることにより 防止することができるのではないかと考え、 金電極層上に厚さ 2 mの P tから なる金属バリヤ層を設け、 その上に錫リッチ Au— Sn系ハンダ膜層を形成し、 金電極を有する素子のハンダ付けを行ってみた。 その結果、 融点上昇は改善され、 ハンダの溶融特性も向上することが確認されたものの、 接合強度が低いという問 題があることが判明した。 すなわち、 接合強度をダイシェアテスタにより測定し たところ、 金属バリア層とハンダ層との間で剥離が起ってしまい、 ダイシェア強 度の平均も 1. 4kg f Zmm2と低いことが判明した。 The present inventor has reported that the diffusion of gold as described above (in other words, the corrosion of gold by a tin-rich Au—Sn solder) is a diffusion preventing metal as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2000-288770. It is thought that this can be prevented by providing a metal barrier layer (hereinafter, also referred to as a metal barrier layer). A metal barrier layer made of Pt with a thickness of 2 m is provided on the gold electrode layer, and tin is We formed a rich Au-Sn solder film layer and soldered a device with gold electrodes. As a result, it was confirmed that the melting point rise was improved and the melting characteristics of the solder were also improved, but it was found that there was a problem that the joining strength was low. That is, where the bonding strength was measured by a die shear tester, causes standing peeling between the metal barrier layer and the solder layer, that the average die shear strength of as low as 1. 4kg f Zmm 2 was found.
発明の開示 Disclosure of the invention
本発明の目的は、 ハンダを高接合強度で接合可能な、 金電極層を表面に有する 素子接合'用基板を提供することである。 An object of the present invention is to provide a substrate for element bonding, which has a gold electrode layer on its surface and can bond solder with high bonding strength.
また、 本発明の他の目的は、 錫リッチ Au— Sn系ハンダのような低融点で柔 らかいハングを用いて、 低温での素子のハンダ付けが可能な、 金電極層を表面に 有する素子接合用基板を提供することである。 Another object of the present invention is to provide an element having a gold electrode layer on its surface, which can be soldered at a low temperature by using a soft hang having a low melting point such as tin-rich Au-Sn solder. An object of the present invention is to provide a bonding substrate.
さらに、 本発明の他の目的は、 ハンダを高接合強度で接合可能な、 金電極層を 表面に有する素子接合用基板の製造方法を提供することである。 Still another object of the present invention is to provide a method for manufacturing a device bonding substrate having a gold electrode layer on its surface, which can bond solder with high bonding strength.
本発明の他の目的は、 以下の説明から明らかになるであろう。 Other objects of the present invention will become clear from the following description.
本発明者は上記課題を解決すべく鋭意検討を行った。 その結果、 表面に金電極 層が形成されてなる基板の該金電極層上に特定の金属からなる金属パリア層を設 けた基板とし、 該基板を用いて錫リッチ Au— Sn系ハンダにより素子のハンダ
付けを行ったところ、 低温でハンダ付けを行うことができ、 しかもそのときの接 合強度は高いという知見を得た。 そして、 該知見に基づきさらに検討を行った結 果、 このような効果は錫リッチ Au— S n系ハンダを用いたときに限らず、 金の 含有量が 2 0重量％未満である I n系ハンダを用いた場合にも発現することを見 出し、 本発明を完成するに至った。 The present inventor has made intensive studies to solve the above-mentioned problems. As a result, a substrate having a metal electrode layer formed of a specific metal on the gold electrode layer of a substrate having a gold electrode layer formed on the surface was used, and the element was formed using tin-rich Au-Sn solder using the substrate. Solder We found that soldering can be performed at low temperatures and that the bonding strength at that time is high. As a result of further study based on the findings, it was found that such an effect is not limited to the use of tin-rich Au-Sn-based solder, and that the In-based alloy having a gold content of less than 20% by weight was used. The present inventors have found that the expression occurs even when solder is used, and have completed the present invention.
すなわち、 本願第一発明は、 表面に金電極層が形成されてなる基板の該金電極 層上に A g、 C u、 N iおよび P bよりなる群から選ばれた少なくとも 1種の金 属からなる金属層が積層された積層構造を有することを特徴とする素子接合用基 板である。 That is, the first invention of the present application provides at least one metal selected from the group consisting of Ag, Cu, Ni, and Pb on a gold electrode layer of a substrate having a surface formed with a gold electrode layer. An element bonding substrate characterized in that it has a laminated structure in which metal layers made of are laminated.
本発明の素子接合用基板は、 錫リッチ A u— S n系ハンダ等の S nまたは I n を主成分として含有しかつ金の含有量が 2 0重量％未満である金属からなるハン ダ層を用いて、 素子を高接合強度で接合できるという特徴を有する。 上記本発明 の素子接合用基板の中でも、 表面に金電極層が形成されてなる基板として、 窒化 アルミニウムを主成分とするセラミックス基板上に、 T iを主成分とする第一下 地層、 P tを主成分とする第二下地層、 および金からなる電極層がこの順番で積 層されたメタライズ基板を用いたものは、 素子を接合して使用したときの高周波 の誘電損失が少ないばかりでなく、 そのときに発生する熱を放熱する機能が高い という特徴を有する。 The element bonding substrate according to the present invention includes a solder layer made of a metal containing Sn or In as a main component and having a gold content of less than 20% by weight, such as a tin-rich Au—Sn-based solder. It has the characteristic that the element can be bonded with high bonding strength by using. Among the above-mentioned element bonding substrates of the present invention, as a substrate having a gold electrode layer formed on the surface, a ceramic substrate mainly composed of aluminum nitride, a first underlayer mainly composed of Ti, Pt In the case of using a metallized substrate in which a second underlayer mainly composed of and a gold electrode layer are laminated in this order, not only the high-frequency dielectric loss when the elements are bonded and used, but also However, it has the feature that the function to radiate the heat generated at that time is high.
また、 前記 A g、 C u、 N iおよび P bよりなる群から選ばれた少なくとも 1 種の金属からなる金属層上に、 S nまたは I nを主成分として含有しかつ金の含 有量が 2 0重量％未満である金属からなるハンダ層がさらに積層された積層構造 を有する素子接合用基板は、 リフローハンダ付けに好適に使用できる。 さらに、 ハンダ層を形成する金属が、 S nまたは I nを主成分として含有し、 金の含有量 が 2 0重量％未満であり、 2 5 におけるヤング率が 5 O GP a未満であり、 さ らに融点が 2 8 0 °C未満である素子接合用基板は、 素子を接合して長期間使用し ても接合面が破壊され難いという特徴を有する。 Further, on a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb, Sn or In is contained as a main component and gold is contained. The element bonding substrate having a laminated structure in which a solder layer made of a metal having less than 20% by weight is further laminated can be suitably used for reflow soldering. Further, the metal forming the solder layer contains Sn or In as a main component, the gold content is less than 20% by weight, the Young's modulus at 25 is less than 5 OGPa, In addition, the element bonding substrate having a melting point of less than 280 ° C. has a feature that the bonding surface is hardly broken even when the elements are bonded and used for a long time.
また、 本願第二発明は、 表面に金電極層が接合されてなる基板の該金電極層上 に A g、 C u、 N iおよび P bよりなる群から選ばれた少なくとも 1種の金属か
らなる金属層を形成することを特徴とする素子接合用基板の製造方法である。 こ の製造方法においては、 形成された A g、 C u、 N iおよび P bよりなる群から 選ばれた少なくとも 1種の金属からなる金属層上に、 S nまたは I nを主成分と して含有しかつ金の含有量が 2 0重量％未満である金属からなるハンダ層を形成 することにより、 上記リフローハンダ付けに好適に使用できる素子接合用基板を 製造することもできる。 Further, the second invention of the present application is directed to a substrate having a gold electrode layer bonded to a surface thereof, on the gold electrode layer, at least one metal selected from the group consisting of Ag, Cu, Ni and Pb. A method for manufacturing a device bonding substrate, comprising forming a metal layer made of a metal. In this manufacturing method, Sn or In as a main component is formed on a formed metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni, and Pb. By forming a solder layer made of a metal having a gold content of less than 20% by weight, a substrate for element bonding which can be suitably used for the reflow soldering can also be manufactured.
また、 本願第三発明は、 前記したリフローハンダ付け〖こ好適に使用できる素子 接合用基板のハンダ層上に電極を有する素子を当該電極が前記ノヽンダ層に接蝕す るように載置した後にリフローハンダ付けすることを特徴とする素子接合基板の 製造方法である。 上記の製法によれば、 例えば 2 8 0 °C未満という低温で素子を 精度よく効率的にハンダ付けすることができる。 Further, in the third invention of the present application, an element having an electrode is mounted on the solder layer of the element bonding substrate, which is preferably used for the reflow soldering, such that the electrode is in contact with the solder layer. This is a method for manufacturing an element bonding substrate, which is characterized by performing reflow soldering later. According to the above manufacturing method, the element can be accurately and efficiently soldered at a low temperature of, for example, less than 280 ° C.
さらに本願第四発明は、 上記方法で製造された素子接合基板である。 本出願の 第四発明の素子接合基板は、 長期間安定に使用することができる。 The fourth invention of the present application is an element bonding substrate manufactured by the above method. The element bonding substrate of the fourth invention of the present application can be used stably for a long period of time.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
図 1は、 Au— S n合金状態図である。 FIG. 1 is a phase diagram of an Au—Sn alloy.
図 2は、 本発明の素子接合用基板の代表的な断面図である。 FIG. 2 is a typical cross-sectional view of the element bonding substrate of the present invention.
図中の各記号は次の意味を有する。 Each symbol in the figure has the following meaning.
1 0 0 :素子接合用基板 1 0 0: Element bonding substrate
2 0 0 :表面に金電極層が形成されてなる基板 200: Substrate with gold electrode layer formed on the surface
2 0 1 :窒化アルミニウム焼結体基板 201: Aluminum nitride sintered body substrate
2 0 2 ： T iを主成分とする第一下地層 20 2: First underlayer mainly composed of Ti
2 0 3 ： P tを主成分とする第二下地層 203: Second underlayer containing Pt as a main component
2 0 4 :金電極層 204: Gold electrode layer
3 0 0 :バリヤ層 3 0 0: Barrier layer
4 0 0 : S nまたは I nを主成分として含有しかつ金の含有量が 2 0重量％未満 である金属からなる八ンダ層 400: an metal layer containing Sn or In as a main component and a gold content of less than 20% by weight.
発明の好ましい実施の形態 Preferred embodiments of the invention
本発明の素子接合用基板は、 表面に金電極層が形成されてなる基板の該金電極
層上に A g、 C u、 N iおよび P bよりなる群から選ばれた少なくとも 1種の金 属からなる金属層が積層された積層構造を有する ここで、 素子とは他の電気的 な配線に直接接続できる端子を有する抵抗やキャパシ夕等の電子部品および半導 体素子を意味する。 The substrate for element bonding according to the present invention is a substrate having a gold electrode layer formed on a surface thereof. It has a laminated structure in which a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb is laminated on the layer. It refers to electronic components and semiconductor elements such as resistors and capacitors having terminals that can be directly connected to wiring.
本発明の素子接合用基板に用いる 「表面に金電極層が形成されてなる基板」 は、 その表面の一部または全面に電極として機能する金からなる層が形成された基板 であれば特に限定されない。 半導体素子を接合して使用したときの高周波の誘電 損失が少ないという観点から、 窒化アルミニウム、 アルミナ、 S i C、 S i等の セラミックス基板上にメタライゼーシヨンにより金電極を形成したメタライズ基 板を用いるのが好適である。 なお、 これらメタライズ基板においては、 前記した ように金電極層は、 セラミックス基板に強固に接合した下地金属層上に直接また は間接的に形成されるのが一般的であり、 例えばアルミナ基板においてはアルミ ナグリーンシート上にタングステンまたはモリブデン等の高融点金属べ一ストか らなる電極パターンを印刷し、 該パターンをグリーンシートと同時焼結した後に、 必要に応じて高融点金属層状にニッケル層を形成し、 さらにその上に金電極を形 成したものが好適に使用できる。 また、 窒化アルミニウムを主成分とするセラミ ックス基板においては、 窒化アルミニウム粉末に焼結助剤を添加して成形した後 に焼結した基板の表面にスパッ夕リング法等により基本的に電極パターンと同一 形状のチタンを主成分とする金属層 （第一下地層） を形成した後に該第ー下地層 上に同じくスパッ夕リング法等により白金を主成分とする第二下地層を形成し、 さらにその上にスパッタリング法等により金電極層を形成して得たメタライズ基 板が好適に使用できる。 本発明の素子接合用基板においては、 素子を接合して使 用したときに発生する熱を放熱する放熱特性が良好であるという観点から、 上記 の様にして得られる窒化アルミニウム系メタライズ基板を用いるのが特に好適で ある。 The “substrate having a gold electrode layer formed on its surface” used for the element bonding substrate of the present invention is not particularly limited as long as it is a substrate on which a layer made of gold that functions as an electrode is formed on part or all of its surface. Not done. From the viewpoint of low dielectric loss at high frequencies when semiconductor devices are bonded and used, metallized substrates with metal electrodes formed by metallization on ceramic substrates of aluminum nitride, alumina, SiC, Si, etc. It is preferred to use In these metallized substrates, as described above, the gold electrode layer is generally formed directly or indirectly on a base metal layer firmly bonded to a ceramic substrate. For example, in an alumina substrate, An electrode pattern made of a refractory metal base such as tungsten or molybdenum is printed on an alumina green sheet, and the pattern is simultaneously sintered with the green sheet. Then, if necessary, a nickel layer is formed as a refractory metal layer. It is preferable to use a metal electrode formed thereon and further forming a gold electrode thereon. In the case of a ceramic substrate containing aluminum nitride as a main component, a sintering aid is added to aluminum nitride powder, and after forming, the surface of the sintered substrate is basically formed with an electrode pattern by a sputtering method or the like. After forming a metal layer (first underlayer) mainly composed of titanium having the same shape, a second underlayer mainly composed of platinum is similarly formed on the first underlayer by a sputtering method or the like. A metallized substrate obtained by forming a gold electrode layer thereon by a sputtering method or the like can be suitably used. In the element bonding substrate of the present invention, the aluminum nitride-based metallized substrate obtained as described above is used from the viewpoint of good heat radiation characteristics for radiating heat generated when the elements are bonded and used. Is particularly preferred.
本発明の素子接合用基板は、 上記金電極層上に A g、 C u、 N iおよび P bよ りなる群から選ばれた少なくとも 1種の金属からなる金属層が形成される必要が ある。 このような金属層を形成することにより、 該層上に錫リッチ Au— S n系
ハンダ等の低融点で柔らかいハンダの層を形成して八ンダ付けを行った場合に、 低温で高接合強度のハンダ付けを行うことが可能となる。 該金属層は、 前記した 金属バリヤ層と同様の作用をするものと考えられる （従って、 以下該金属層を単 にバリヤ層ともいう。 ） が、 金属バリヤ層用の金属として最も一般的な白金を用 いた場合には、 用いるハンダ金属の種類との関係で高強度の接合を行うことがで きない。 該バリヤ層の厚さは特に限定されないが、 コストパフォーマンスの観点 ら、 0 . 2〜5 m、 特に 1〜3 mであるのが好適である。 該層の厚さが 0. 2 zm未満だと効果が低く、 また 5 m以上としてもその効果は 1 ~ 3 mのと きとほとんど変わらない。 In the element bonding substrate of the present invention, a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb needs to be formed on the gold electrode layer. . By forming such a metal layer, a tin-rich Au—Sn-based When soldering is performed by forming a layer of soft solder having a low melting point such as solder, it becomes possible to perform soldering with high bonding strength at low temperatures. The metal layer is considered to have the same function as the above-mentioned metal barrier layer (therefore, the metal layer is also simply referred to as a barrier layer hereinafter). However, platinum is the most common metal for a metal barrier layer. In the case of using solder, it is not possible to perform high-strength bonding due to the type of solder metal used. The thickness of the barrier layer is not particularly limited, but is preferably 0.2 to 5 m, particularly preferably 1 to 3 m from the viewpoint of cost performance. When the thickness of the layer is less than 0.2 zm, the effect is low, and when the thickness is 5 m or more, the effect is almost the same as when the thickness is 1 to 3 m.
上記金属層 ひ リャ層） は、 A g、 C u、 N iおよび P bよりなる群から選ば れた少なくとも 1種の金属からなるものであれば特に限定されず、 単一の金属種 から成るものであってもよく、 また、 複数の金属種から成る合金あるいは金属間 化合物または固溶体であつてもよいが、 効果の観点からは A gからなるのが最も 好適である。 なお、 バリヤ層は、 金電極層の全面を覆う必要はないが、 金電極層 の素子が接合される部分またはハンダと接触する部分は少なくともバリヤ層で覆 われているのが好適である。 前記金電極層上にバリヤ層を形成する方法は特に限 定されず、 例えば、 スパッタリング法、 イオンプレ一ティング法、 蒸着法、 CV D法、 メツキ法により好適に行うことができる。 The metal layer is not particularly limited as long as it is made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb, and is made of a single metal species. The alloy may be an alloy composed of a plurality of metal species, an intermetallic compound or a solid solution, but is most preferably composed of Ag from the viewpoint of the effect. The barrier layer does not need to cover the entire surface of the gold electrode layer, but it is preferable that at least a portion of the gold electrode layer where elements are joined or a portion that comes into contact with solder is covered with at least a barrier layer. The method for forming the barrier layer on the gold electrode layer is not particularly limited, and can be suitably performed by, for example, a sputtering method, an ion plating method, an evaporation method, a CVD method, or a plating method.
本発明の素子接合用基板は、 金電極層上に前記バリヤ層を形成した状態で、 ハ ンダ付け時にハンダを供給して素子と接合することもできるが、 所定の位置に精 度良く素子を接合するために、 バリヤ層上、 好ましくは素子の接合予定部位のみ にハンダの層を形成しておくのが好適である。 このような態様の基板 （以下、 単 にハンダ付き基板ともいう。 ） とすることにより、 素子の搭載位置を精密に制御 でき、 自動ィヒも容易であるリフ口一ハンダ付けを容易に行うことが可能となる。 このとき、 ノ、リャ層上に形成するハンダ層用のハンダは特に限定されるものでは ないが、 前記バリヤ層の効果が特に高く、 それ自体が比較的柔らかく低温でのハ ンダ付けができることから、 S nまたは I nを主成分として含有しかつ金の含有 量が 2 0重量％未満、 特に 1 0重量％未満である金属から成るハンダを用いるの
が好適である。 このようなハンダを具体的に例示すれば、 前記した錫リッチ Au — Sn系ハンダ、 Sn 100%ハンダ、 Sn— Agハンダ、 Sn— Pbハンダ、 Sn— B iハンダ、 Sn— Sbハンダ、 Sn— I nハンダ、 Ι η100%ハンダ、 I n— Auハンダ （ただし金の含有量が 20重量％未満のもの） 、 I n— Agハ ンダ、 I n— B iハンダ、 I n— Sbハンダ、 I n— Z nハンダおよびこれらを 任意に組合せたハンダ等が例示される。 In the element bonding substrate of the present invention, while the barrier layer is formed on the gold electrode layer, solder can be supplied at the time of soldering and bonded to the element, but the element can be accurately placed at a predetermined position. For bonding, it is preferable to form a solder layer on the barrier layer, preferably only at the portion where the device is to be bonded. By using a substrate of such an embodiment (hereinafter, also simply referred to as a substrate with solder), it is possible to precisely control the mounting position of the element and to easily perform the soldering of the riff opening, which is easy to perform automatically. Becomes possible. At this time, the solder for the solder layer to be formed on the solder layer is not particularly limited, but the effect of the barrier layer is particularly high because the solder itself is relatively soft and can be soldered at a low temperature. The use of solder consisting of a metal containing, Sn or In as the main component and a gold content of less than 20% by weight, especially less than 10% by weight. Is preferred. Specific examples of such solders include the above-mentioned tin-rich Au—Sn solder, Sn 100% solder, Sn—Ag solder, Sn—Pb solder, Sn—Bi solder, Sn—Sb solder, Sn— In solder, Ιη 100% solder, In—Au solder (but less than 20% by weight of gold), In—Ag solder, In—Bi solder, In—Sb solder, I Examples include n—Zn solders and solders arbitrarily combining these solders.
これらの中でも、 素子と接合した後のダイシェア試験の接合強度が最も高いと いう理由から、 Au— Sn系ハンダが特に好適に使用できる。 また、 本発明にお いては、 上記したような Snまたは I nを主成分として含有しかつ金の含有量が 20重量％未満である金属から成るハンダの中でも、 前記したような素子を接合 して使用したときの温度変化による接合部位の破壊が起り難いという観点から、 融点 280°C未満、 特に 235 °C以下でかつヤング率が 5 OGPa未満 （25 ■ において） の金属からなるハンダを用いるのが最も好適である。 Among these, Au—Sn-based solder can be particularly preferably used because the bonding strength in the die shear test after bonding to the element is the highest. Further, in the present invention, the above-described element is bonded to a solder made of a metal containing Sn or In as a main component and containing less than 20% by weight of gold as described above. Use a solder made of metal with a melting point of less than 280 ° C, especially 235 ° C or less and a Young's modulus of less than 5 OGPa (at 25 ■), from the viewpoint that it is unlikely that the joint will be destroyed due to temperature changes during use. Is most preferred.
本発明のハンダ付き基板における上記ハンダ層は、 単一組成の金属からなる 1 層から成っていてもよく、 また、 各層が溶融して混合したときに前記したような 条件を満足するような組成となるように、 異なる組成の金属からなる複数の層の 積層体から成っていてもよい。 該ハンダ層全体の厚さは、 1〜： L 0 m、 特に 2 〜 6 mとするのが好適である。 該層の厚さが 1 m未満ではハンダの絶対量が 少ないために十分な接合強度が得られない傾向があり、 逆に 1 を超える厚 さとしたときはハンダ量が多すぎるために接合後にハングが素子の側面や上面 (半導体素子においては発光面ともなる） を遮る不具合が生じたりすることがあ る。 前記バリヤ層上に上記のようなハンダからなる層を形成する方法は特に限定 されず、 例えば、 スパッタリング法、 イオンプレーティング法、 蒸着法、 CVD 法、 メツキ法により好適に行うことができる。 The solder layer in the soldered substrate of the present invention may be composed of a single layer composed of a single-component metal, and a composition that satisfies the above-described conditions when each layer is melted and mixed. It may be composed of a laminate of a plurality of layers made of metals having different compositions so that The thickness of the entire solder layer is preferably 1 to: L 0 m, and particularly preferably 2 to 6 m. If the thickness of the layer is less than 1 m, sufficient bonding strength tends not to be obtained because the absolute amount of solder is small.On the other hand, if the thickness exceeds 1, the amount of solder is too large and hangs after bonding. This may cause a problem that the side and top surfaces of the device (which also serve as a light emitting surface in a semiconductor device) are blocked. The method of forming a layer made of solder as described above on the barrier layer is not particularly limited, and can be suitably performed by, for example, a sputtering method, an ion plating method, an evaporation method, a CVD method, or a plating method.
本発明の素子接合用基板に半導体素子等の素子を接合する方法は特に限定され ず、 公知のハンダ付け法が限定なく採用できるが、 精度よい接合を効率的に行う ことができるという理由より、 ハンダ付き基板である本発明の素子接合用基板の ハンダ層上に電極を有する素子を当該電極が前記ハンダ層に接触するように載置
した後にリフローハンダ付けするのが好適である。 なお、 リフローハンダ付け (リフローソルダリング） とは、 基板の所定のランド上、 または部品電極、 ある いはその両方にあらかじめハンダを供給しておき、 部品を基板上の所定の位置に 固定した後に、 ハンダを溶かし （フローさせ） て、 部品と基板との接合を行う方 法である。 上記方法において、 ハンダをリフローさせる方法は特に限定されずリ フローコンペャを利用する方法、 熱板を用いる方法、 ベーパーリフロー法等が採 用できる。 また、 加熱温度や加熱時間は用いるハンダの種類に応じて適宜決定す ればよいが、 本発明の素子接合用基板を用いた場合には、 用いたハングの特性が 損われないので、 例えば錫リッチ A u— S n系ハンダを用いた場合には、 2 8 0 °C未満の低温で良好な八ンダ付けを行うことが可能である。 The method of joining a device such as a semiconductor device to the device joining substrate of the present invention is not particularly limited, and a known soldering method can be employed without any limitation. However, since accurate joining can be efficiently performed, An element having an electrode on the solder layer of the element bonding substrate of the present invention, which is a substrate with solder, is placed so that the electrode contacts the solder layer. After that, it is preferable to perform reflow soldering. In addition, reflow soldering (reflow soldering) means that solder is supplied to predetermined lands on the board, component electrodes, or both in advance, and after the components are fixed to the predetermined positions on the board, In this method, the solder is melted (flown) to join the component and the board. In the above method, the method of reflowing the solder is not particularly limited, and a method using a reflow conveyor, a method using a hot plate, a vapor reflow method, or the like can be employed. The heating temperature and the heating time may be appropriately determined according to the type of solder used. However, when the element bonding substrate of the present invention is used, the characteristics of the used hang are not impaired. When a rich Au—Sn solder is used, good soldering can be performed at a low temperature of less than 280 ° C.
なお、 ハンダ付けする素子は、 ハンダにより接合可能な金属から成る電極を有 するものであれば特に限定されない。 一般的な半導体素子においては、 上記電極 は金で構成されているものが多い。 このような金電極を有する素子をハンダ付け する際には、 金電極の金原子がハンダに拡散すると考えられるが、 後述する実施 例に示されるように、 金電極を有する素子をハンダ付けした場合にも高い接合強 度が得られることから、 このときに起る拡散は接合強度に重大な影響をおよぼさ ないと思われる。 しかしながら、 このような金原子の拡散をより良好に防止する ためには、 ハンダと接触する素子の電極表面を A g、 C u、 N iおよび P bより なる群から選ばれた少なくとも i種の金属、 特に A gで被覆しておくことが好適 である。 The element to be soldered is not particularly limited as long as it has an electrode made of a metal that can be joined by solder. In general semiconductor elements, the above-mentioned electrodes are often made of gold. When soldering an element having such a gold electrode, it is considered that gold atoms of the gold electrode diffuse into the solder.However, as shown in an example described later, when an element having a gold electrode is soldered. Since high bonding strength is obtained, the diffusion that occurs at this time does not seem to have a significant effect on bonding strength. However, in order to better prevent such diffusion of gold atoms, the electrode surface of the element in contact with the solder must have at least i kinds of electrodes selected from the group consisting of Ag, Cu, Ni and Pb. It is preferable to coat with metal, especially Ag.
実施例 Example
以下、 実施例および比較例を挙げて本発明をさらに詳しく説明するが、 本発明 はこれらの実施例に限定されるものではない。 Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples, but the present invention is not limited to these Examples.
実施例 1 Example 1
図 2に示すような構造の素子接合用基板を、 以下の様にして作製した。 なお、 図 2は、 本発明の代表的な素子接合用基板 1 0 0の断面図であり、 窒化アルミ二 ゥム焼結体基板 2 0 1上に、 T iを主成分とする第一下地層 2 0 2、 白金を主成 分とする第二下地層 2 0 3、 および金電極層 2 0 4がこの j頃番で積層された基板
200の金電極層上に、 銀等の金属から成るバリヤ層 300および Sn系あるい は I n系であってかつ金の含有量が 20重量％未満である金属からなるハンダ層 400が積層された構造を有する。 An element bonding substrate having a structure as shown in FIG. 2 was produced as follows. FIG. 2 is a cross-sectional view of a typical element bonding substrate 100 of the present invention, in which a first lower layer mainly composed of Ti is formed on an aluminum nitride sintered substrate 201. A substrate on which a ground layer 202, a second underlayer 203 mainly composed of platinum, and a gold electrode layer 204 are stacked in the order of j. A barrier layer 300 made of a metal such as silver and a solder layer 400 made of a Sn-based or In-based metal having a gold content of less than 20% by weight are laminated on the 200 gold electrode layer. It has a structure.
まず、 窒ィ匕アルミニウム焼結体基板 （50. 8mmX 50. 8mmX0. 3m mt (株） トクャマ製） 'の表面にスパッタリング装置を用いてスパッタリング法 により厚さ 0. 06 zmの Tiを主成分とする第一下地層、 厚さ 0. の白 金を主成分とする第二下地層および厚さ 0. 6 の金電極層を順次形成した。 次いで、 真空蒸着装置を用いて上記金電極層上に、 厚さ 2 mの Ag膜からなる バリヤ層を形成し、 引続きターゲットとして Auおよび Snを用いた同時蒸着法 により、 金含有量が 10重量％の Au— S n合金 （融点 217 およびヤング率 45. 0 GP a (25 °Cにおいて） ） から成る厚さ 5 mのハンダ層を形成し、 本発明の素子接合用基板を作製した。 次に、 このようにして作製した素子接合用 基板のハンダ層上に Au電極を有する半導体素子を載置し、 ダイポンダー装置を 用いて 250°Cで 30秒接合し、 素子接合基板を作製した。 First, a titanium nitride substrate with a thickness of 0.06 zm (50.8 mmX 50.8 mmX0.3 mmt, manufactured by Tokuyama Corporation) was sputtered on a surface of the substrate using a sputtering apparatus. A first underlayer to be formed, a second underlayer mainly composed of white gold having a thickness of 0.6, and a gold electrode layer having a thickness of 0.6 were sequentially formed. Next, a barrier layer consisting of a 2 m-thick Ag film was formed on the gold electrode layer using a vacuum evaporation apparatus, and then a gold content of 10% was obtained by a simultaneous evaporation method using Au and Sn as targets. % Of Au—Sn alloy (melting point: 217 and Young's modulus: 45.0 GPa (at 25 ° C.)), a 5 m-thick solder layer was formed, and a device bonding substrate of the present invention was produced. Next, a semiconductor element having an Au electrode was mounted on the solder layer of the element bonding substrate manufactured in this manner, and bonded at 250 ° C. for 30 seconds using a diponder apparatus, thereby manufacturing an element bonding substrate.
同様にして 10個の素子接合基板を作製し、 ダイシェアテス夕 （IMADA社 製） により接合強度を測定したところ、 平均接合強度は 2. Skg fZmm2で あり、 剥離モードは全数ハンダ内であった （各層間での剥離ではなく、 ハンダ層 が破壊されて剥離していた。 ） 。 In the same way, ten element bonding substrates were fabricated, and the bonding strength was measured using a die shear tester (manufactured by IMADA). The average bonding strength was 2. Skg fZmm 2 , and the peeling mode was within 100% of the solder ( Instead of peeling between the layers, the solder layer was broken and peeled off.)
実施例 2 . Example 2.
ターゲットとして I n (融点 156で、 ヤング率 12. 7GP a (25。Cにお いて） ） を用いた蒸着法により厚さ 5 mのハンダ層を形成したこと以外は実施 例 1と同様にして、 素子接合用基板を作製し、 接合温度を 210°Cとする他は実 施例 1と同様にして素子接合基板を作製した。 同様にして 10個の素子接合基板 を作製し、 実施例 1と同様にして接合強度を測定したところ、 平均接合強度は 2. 5 kg f /mm2であり、 剥離モードは全数ハンダ内であった。 Except that a 5 m-thick solder layer was formed by vapor deposition using In (melting point: 156, Young's modulus: 12.7 GPa (at 25.C)) as a target, Then, a device bonding substrate was prepared in the same manner as in Example 1, except that a bonding temperature was set to 210 ° C. Ten element bonding substrates were prepared in the same manner, and the bonding strength was measured in the same manner as in Example 1. The average bonding strength was 2.5 kgf / mm2, and the peeling mode was within 100% solder. Was.
実施例 3 Example 3
実施例 1において、 パリャ層の材質を A gから表 1に示す金属に変えた他は実 施例 1と同様にして、 素子接合用基板および素子接合基板を作製し、 実施例 1と
同様にして接合強度を測定した。 その結果を併せて表 1に示した。 In Example 1, a device bonding substrate and a device bonding substrate were prepared in the same manner as in Example 1 except that the material of the pal layer was changed from Ag to the metal shown in Table 1. The joining strength was measured in the same manner. Table 1 also shows the results.
実施例 4 Example 4
実施例 1において、 ノ、ンダ層の Ei¥を表 1に示す膜厚に変えた他は実施例 1と 同様にして、 素子接合用基板および素子接合基板を作製し、 実施例 1と同様にし て接合強度を測定した。 その結果を併せて表 1に示した。 In Example 1, a device bonding substrate and a device bonding substrate were prepared in the same manner as in Example 1 except that the thicknesses of the anode and solder layers were changed to the film thicknesses shown in Table 1. To measure the bonding strength. Table 1 also shows the results.
実施例 5 Example 5
実施例 1において、 バリヤ層の膜厚を表 1に示す膜厚に変えた他は実施例 1と 同様にして、 素子接合用基板および素子接合基板を作製し、 実施例 1と同様にし て接合強度を測定した。 その結果を併せて表 1に示した。 A device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the thickness of the barrier layer was changed to the thickness shown in Table 1 in Example 1, and bonding was performed in the same manner as in Example 1. The strength was measured. Table 1 also shows the results.
比較例 1 Comparative Example 1
実施例 1において、 ノ リャ層を設けなかった他は実施例 1と同様にして、 素子 接合用基板および素子接合基板を作製し、 接合強度を測定した。 その結果を併せ て表 1に示した。 表 1に示されるように、 バリヤ層を設けない場合には、 平均接 合強度は 0. 8 k g f Zmm2であった。 A device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the NOR layer was not provided, and the bonding strength was measured. Table 1 also shows the results. As shown in Table 1, when the barrier layer was not provided, the average joint strength was 0.8 kgf Zmm 2 .
比較例 2 Comparative Example 2
実施例 1において、 バリヤ層の材質を A gから P tに変えた他は実施例 1と同 様にして、 素子接合用基板および素子接合基板を作製し、 接合強度を測定した。 その結果を併せて表 1に示した。 表 1に示されるように、 ノ Jャ層を設けても、 その材質が本発明で特定する金属でない場合には、 平均接合強度は 1 . 4 k g f Zmm2でしかなかった。
A device bonding substrate and a device bonding substrate were produced in the same manner as in Example 1 except that the material of the barrier layer was changed from Ag to Pt, and the bonding strength was measured. Table 1 also shows the results. As shown in Table 1, even when the metal layer was provided, when the material was not the metal specified in the present invention, the average bonding strength was only 1.4 kgf Zmm 2 .
表 1 table 1
AulO— Sn：金含有量が 1 0重量％の 11— S n合金 以上のとおり、 本発明の素子接合用基板を用いることにより、 表面に金電極が 形成された基板の金電極上に、 錫リツチ A u— S n系ハンダのような融点が低く 柔らかいハンダを用いて半導体素子を低温で高接合強度にハンダ付けすることが 可能となる。 そして、 このようにして接合された本発明の素子接合基板は、 使用 時における温度差が大きくなつても接合部位が破壊され難く長期間安定して使用 することが可能である。 特に基板として表面に金電極が形成された窒化アルミ二 ゥムを主成分とするセラミックス基板を用いたものは、 このような特長に加えて 高周波の誘電損失が少ないばかりでなく、 使用時に発生する熱を放熱する放熱特 性が良好であるという特長を併せ持つ非常に優れた素子接合基板である。
AulO—Sn: 11-Sn alloy with gold content of 10% by weight As described above, by using the element bonding substrate of the present invention, tin is formed on the gold electrode of the substrate having the gold electrode formed on the surface. The semiconductor element can be soldered at a low temperature and with high bonding strength by using a soft solder having a low melting point, such as that of the Au-Sn series solder. The element bonding substrate of the present invention thus bonded can be stably used for a long period of time because the bonding portion is not easily broken even when the temperature difference during use is large. In particular, a substrate using a ceramic substrate mainly composed of aluminum nitride with a gold electrode formed on the surface as the substrate has such characteristics, and in addition to having a low dielectric loss of high frequency, it is generated during use. It is a very good device bonding board that combines the features of good heat dissipation characteristics to dissipate heat.
Claims
1. 表面に金電極層が形成されてなる基板の該金電極層上に Ag、 Cu、 N iお よび Pbよりなる群から選ばれた少なくとも 1種の金属からなる金属層が積層さ れた積層構造を有することを特徴とする素子接合用基板。 1. A metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb is laminated on the gold electrode layer of a substrate having a gold electrode layer formed on the surface An element bonding substrate having a laminated structure.
2. 表面に金電極層が形成されてなる基板が、 窒化アルミニウムを主成分とする セラミックス基板上に、 T iを主成分とする第一下地層、 P tを主成分とする第 二下地層、 および金からなる電極層がこの順番で積層されたメタライズ基板であ る請求の範囲 1項に記載の素子接合用基板。 2. A substrate with a gold electrode layer formed on its surface is formed on a ceramic substrate containing aluminum nitride as the main component, a first underlayer containing Ti as the main component, and a second base layer containing Pt as the main component. 2. The element bonding substrate according to claim 1, wherein the substrate is a metallized substrate in which electrode layers made of gold and gold are laminated in this order.
3. Ag、 Cu、 N iおよび Pbよりなる群から選ばれた少なくとも 1種の金属 からなる金属層の厚みが、 0. 2〜 5 mである請求の範囲 1項に記載の素子接 合用基板。 3. The element bonding substrate according to claim 1, wherein the thickness of the metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni, and Pb is 0.2 to 5 m. .
4. Ag、 Cu、 N iおよび Pbよりなる群から選ばれた少なくとも 1種の金属 からなる金属層上に、 S nまたは I nを主成分として含有しかつ金の含有量が 2 0重量％未満である金属からなるハンダ層がさらに積層された積層構造を有する 請求の範囲 1項または 2項に記載の素子接合用基板。 4. On a metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb, containing Sn or In as a main component and a gold content of 20% by weight. 3. The element bonding substrate according to claim 1, wherein the substrate has a laminated structure in which a solder layer made of a metal having a thickness of less than or equal to is further laminated.
5. ハンダ層を形成する Snまたは I nを主成分として含有しかつ金の含有量が 20重量％未満である金属が、 25 °Cにおけるヤング率が 5 OGP a未満であり そして融点が 280 未満の金属である請求の範囲 4項に記載の素子接合用基板。 5. A metal that contains Sn or In as the main component and forms a solder layer and has a gold content of less than 20% by weight has a Young's modulus at 25 ° C of less than 5 OGPa and a melting point of less than 280. 5. The element bonding substrate according to claim 4, wherein the substrate is a metal.
6. 表面に金電極層が接合されてなる基板の該金電極層上に、 Ag、 Cu、 Ni および P よりなる群から選ばれた少なくとも 1種の金属からなる金属層を形成 することを特徴とする、 請求の範囲 1項または 2項に記載の素子接合用基板を製 造する方法。
6. A metal layer comprising at least one metal selected from the group consisting of Ag, Cu, Ni and P is formed on the gold electrode layer of the substrate having the surface bonded with the gold electrode layer. 3. A method for manufacturing the element bonding substrate according to claim 1 or 2.
7. 形成された A g、 C u、 N iおよび P bよりなる群から選ばれた少なくとも 1種の金属からなる金属層上に、 次いで S nまたは I nを主成分として含有しか つ金の含有量が 2 0重量％未満である金属からなるハンダ層を形成する請求の範 囲 6項に記載の方法。 7. On the formed metal layer made of at least one metal selected from the group consisting of Ag, Cu, Ni and Pb, The method according to claim 6, wherein a solder layer made of a metal having a content of less than 20% by weight is formed.
8. 請求の範囲 4項または 5項に記載の素子接合用基板のハンダ層上に、 電極を 有する素子を、 当該電極が前記八ンダ層に接触するように載置し、 次いでリフロ ーハンダ付けすることを特徴とする素子接合基板の製造方法。 8. An element having an electrode is placed on the solder layer of the element bonding substrate according to claim 4 or 5 such that the electrode contacts the solder layer, and then reflow soldering is performed. A method for manufacturing an element bonding substrate, comprising:
9. 請求の範囲 8項に記載の方法で製造された素子接合基板。
9. An element bonding substrate manufactured by the method according to claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-7012335A KR20040014475A (en) | 2001-06-14 | 2002-05-29 | Substrate for use in joining element |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001180365A JP2002373960A (en) | 2001-06-14 | 2001-06-14 | Element bonding substrate and method of manufacturing the same |
| JP2001-180365 | 2001-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2002103787A1 true WO2002103787A1 (en) | 2002-12-27 |
Family
ID=19020798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2002/005202 WO2002103787A1 (en) | 2001-06-14 | 2002-05-29 | Substrate for use in joining element |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2002373960A (en) |
| KR (1) | KR20040014475A (en) |
| CN (1) | CN1316605C (en) |
| TW (1) | TW548805B (en) |
| WO (1) | WO2002103787A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102560371A (en) * | 2011-12-31 | 2012-07-11 | 广东风华高新科技股份有限公司 | Gold-stannum alloy film preparation technology |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459794B2 (en) | 2003-08-26 | 2008-12-02 | Tokuyama Corporation | Substrate for device bonding, device bonded substrate, and method for producing same |
| KR100781859B1 (en) * | 2003-09-22 | 2007-12-03 | 가부시끼가이샤 도시바 | Method of manufacturing semiconductor laser device |
| US7626264B2 (en) | 2004-03-24 | 2009-12-01 | Tokuyama Corporation | Substrate for device bonding and method for manufacturing same |
| JP4644007B2 (en) * | 2004-03-24 | 2011-03-02 | 株式会社トクヤマ | Device bonding substrate and manufacturing method thereof |
| EP2099068A4 (en) * | 2006-12-28 | 2011-01-26 | Tokuyama Corp | Process for producing metallized aluminum nitride substrate |
| JP2010103206A (en) * | 2008-10-22 | 2010-05-06 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
| JP2011223035A (en) * | 2011-07-25 | 2011-11-04 | Toshiba Corp | Semiconductor device |
| JP6067982B2 (en) * | 2012-03-19 | 2017-01-25 | スタンレー電気株式会社 | Manufacturing method of semiconductor device |
| KR101924682B1 (en) * | 2012-11-30 | 2018-12-03 | 센주긴조쿠고교 가부시키가이샤 | Layered solder material for bonding dissimilar electrodes, and method for bonding dissimilar electrodes to electronic components |
| JP6221690B2 (en) * | 2013-11-29 | 2017-11-01 | 日立金属株式会社 | Base material with brazing material and method for producing base material with brazing material |
| CN107256830A (en) * | 2017-06-01 | 2017-10-17 | 合肥邦诺科技有限公司 | A kind of method that utilization screen printing technique prepares thick-film type aluminium nitride copper-clad base plate |
| CN107256829A (en) * | 2017-06-01 | 2017-10-17 | 合肥邦诺科技有限公司 | A kind of method that utilization thin film technique prepares aluminium nitride copper-clad base plate |
| WO2021134239A1 (en) * | 2019-12-30 | 2021-07-08 | 重庆康佳光电技术研究院有限公司 | Light emitting device and manufacturing method therefor, and display apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11307692A (en) * | 1998-04-23 | 1999-11-05 | Kyocera Corp | Semiconductor element support member and semiconductor element storage package using the same |
| JP2001127375A (en) * | 1999-10-29 | 2001-05-11 | Kyocera Corp | Submount for mounting optical semiconductor elements |
-
2001
- 2001-06-14 JP JP2001180365A patent/JP2002373960A/en active Pending
-
2002
- 2002-05-29 WO PCT/JP2002/005202 patent/WO2002103787A1/en active Application Filing
- 2002-05-29 KR KR10-2003-7012335A patent/KR20040014475A/en not_active Ceased
- 2002-05-29 TW TW091111482A patent/TW548805B/en not_active IP Right Cessation
- 2002-05-29 CN CNB028083644A patent/CN1316605C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11307692A (en) * | 1998-04-23 | 1999-11-05 | Kyocera Corp | Semiconductor element support member and semiconductor element storage package using the same |
| JP2001127375A (en) * | 1999-10-29 | 2001-05-11 | Kyocera Corp | Submount for mounting optical semiconductor elements |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102560371A (en) * | 2011-12-31 | 2012-07-11 | 广东风华高新科技股份有限公司 | Gold-stannum alloy film preparation technology |
Also Published As
| Publication number | Publication date |
|---|---|
| TW548805B (en) | 2003-08-21 |
| CN1316605C (en) | 2007-05-16 |
| KR20040014475A (en) | 2004-02-14 |
| CN1509499A (en) | 2004-06-30 |
| JP2002373960A (en) | 2002-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0798779B1 (en) | Ceramic circuit board | |
| EP1909321B1 (en) | Metal-ceramic composite substrate and method for manufacturing same | |
| JP2984068B2 (en) | Method for manufacturing semiconductor device | |
| WO2002103787A1 (en) | Substrate for use in joining element | |
| JP2023506558A (en) | Methods of producing metal-ceramic substrates and metal-ceramic substrates produced by such methods | |
| JP2003197826A (en) | Ceramic circuit board and semiconductor module using the same | |
| US7626264B2 (en) | Substrate for device bonding and method for manufacturing same | |
| JPH06296084A (en) | Thermal conductor of high conductivity, wiring board provided therewith and manufacture thereof | |
| JP2000340912A (en) | Ceramic circuit board | |
| JPH08102570A (en) | Ceramic circuit board | |
| JP2001308438A (en) | Sub-mounting material | |
| JP2017168635A (en) | Substrate for power module and manufacturing method of power module | |
| US20050089700A1 (en) | Solder film manufacturing method, heat sink furnished with solder film, and semiconductor-device-and-heat-sink junction | |
| JP2003192462A (en) | Silicon nitride circuit board and method of producing the same | |
| EP0660404A2 (en) | Element joining pad for semiconductor device mounting board | |
| JP4644007B2 (en) | Device bonding substrate and manufacturing method thereof | |
| JP5560441B2 (en) | Electric circuit board manufacturing method and electric circuit applied product | |
| JP2006100625A (en) | Substrate with solder layer | |
| JPH02208033A (en) | Ceramics plate for printed circuit board | |
| JP2007081412A (en) | Substrate for submount material | |
| JP2515051Y2 (en) | Package for storing semiconductor devices | |
| JP2000349098A (en) | Joint of ceramic substrate and semiconductor element and method of manufacturing the same | |
| JPH02208032A (en) | Metallic plate for circuit substrate | |
| JP2002252317A (en) | Heat sink and module structure using it | |
| JPH0632687A (en) | Aluminum nitride sintered compact substrate having metallized film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN KR US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| WWE | Wipo information: entry into national phase |
Ref document number: 1020037012335 Country of ref document: KR |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 028083644 Country of ref document: CN |
|
| 122 | Ep: pct application non-entry in european phase |