WO2000002317A9

WO2000002317A9 - Method and apparatus for adjusting phase offset in a phase locked loop

Info

Publication number: WO2000002317A9
Application number: PCT/US1999/014904
Authority: WO
Inventors: Woogeun Rhee; Akbar Ali
Original assignee: Conexant Systems Inc
Priority date: 1998-07-01
Filing date: 1999-06-30
Publication date: 2000-05-18
Also published as: WO2000002317A1

Abstract

A charge pump (414) suitable for tuning the phase of offsets in phase locked loops (400) and delay locked loops is disclosed. The charge pump (414) includes a variable positive source (513), a variable negative source (529), a first switch (510) for controllably coupling the positive source to the output of the charge pump and a second switch (512) for controllably coupling the variable negative source to the output of the charge pump. The variable positive and negative sources can include a primary current source (514, 530) and at least one incremental current source (516, 532).

Description

METHOD AND APPARATUS FOR ADJUSTING PHASE OFFSET IN A PHASE LOCKED LOOP

Background of the Invention Field of the Invention

The invention relates generally to phase locked loops and delay locked loops. Embodiments of the invention relate to charge pumps which can be used in phase locked loops and delay locked loops. Description of the Related Art

Phase locked loops, and similarly, delayed locked loops, are routinely used for data communications, frequency synthesis, clock generation and clock recovery, to name a few applications. The two types of locked loops are often implemented in integrated circuits and commonly are realized using charge pump techniques. The primary difference between phase locked loops and delay locked loops is that phase locked loops employ a voltage controlled oscillator while delay locked loops employ a voltage controlled delay line.

Figure 1 shows a block diagram of a typical charge pump based phase locked loop generally identified as

100. The phase locked loop 100 includes a phase detector 112, a charge pump 114, a loop filter 116 and a voltage controlled oscillator 1 18. A phase locked loop can operate to align two signals in both frequency and phase. When the phase locked loop is used to synthesize frequencies, a divider is typically interposed between the voltage controlled oscillator 118 and the input of the phase detector 112. For simplicity, the divider has been omitted.

The phase detector 12 receives two inputs at the inputs IN1 and IN2 at terminals 120 and 122, respectively. The phase detector 12 generates an output pulse on its UP output 124 when input signal f_ref leads input signal f _out and generates an output pulse on its DOWN output 126 when input signal f_ref lags input signal f_out. Figure 2 shows a block diagram of a typical phase detector 112 which can be used in a phase locked loop or in a delay locked loop. The phase detector 112 comprises a D flip-flop 210, a second D flip-flop 212, an AND gate 214 and a delay block 216. The D flip-flops 210 and 212 are rising edge trigger flip-flops having their D input terminals connected to a logic one voltage level. As a result, at every rising edge on their clock terminals, the D flip-flops generate a logic one output signal at their Q output terminals 220 and 222. An AND gate 214 resets D flip-flops 210 and 212 when the voltages on the Q output terminals 220 and 222 are both at a logic level one.

Figure 3 is a timing diagram of various signals within the phase detector 112 while in operation. In the example depicted in Figure 3, the input signal f_rβf, illustrated by a waveform 310, leads the signal f_out, illustrated by a waveform 312. The signal on the Q output terminal 220 rises to a logic level one at time t, when the input signal f_ref has a rising edge. The voltage at the UP output terminal 124 also rises to a logic one as illustrated by the waveform 314. The voltage on the Q output terminal 222 and the DOWN output terminal 126 rises to a logic one at time t₂, which resets the D flip-flops 210 and 212 after the delay introduced by the delay block 216. The voltage at UP output terminal 124 then falls to a logic zero from the rising edge of the signal f_out. Thus, an output pulse with a width equal to the phase difference between the f_re, and f_ou, signals is transmitted on the UP output terminal 124 as illustrated by the waveform 314. A minimum pulse width is transmitted on the DOWN output terminal 126 as illustrated by the waveform 316. -2-

As depicted in Figure 1, charge pump 114 receives the UP and DOWN signals from the phase detector 112 at the terminals 128 and 130, respectively. The charge pump 114 controls the voltage V_out at an output terminal 132 by adding charge to the output terminal 132, as long as it detects a pulse on the terminal 128, and removing charge from the output terminal 132, as long as it detects a pulse on the terminal 130. To add and remove charge from the output terminal 132, a conventional charge pump provides both a charging current source 140 and a discharging circuit source

142. Thus, the voltage V_out at the output terminal 132 increases when f_ref leads signal f_out in phase and decreases when the signal f_ref lags the signal f_out.

The loop filter 116 is coupled at its input terminal 134 to the output terminal 132 of the charge pump 114.

The loop filter 116 stabilizes the loop. The voltage-controlled oscillator 118 generates an oscillating output signal f_ou, at the terminal 136 with a frequency proportional to the voltage at the input terminal 138. Thus, when the signal f_re, leads the signal f_out, the voltage V_out increases as described above, which in turn causes the voltage controlled oscillator 118 to increase the frequency of signal f_out. Conversely, when the signal f_ιef lags the signal f_DUt, the voltage V_ou, decreases, which causes the voltage controlled oscillator 118 to decrease the frequency of f_out. The feedback circuit of Figure 1 thus constantly attempts to align f_out with f_ref in frequency and phase. When the loop is substantially stabilized, the signals f_fef and f_out are aligned in frequency and phase and the phase locked loop 100 is said to be in the "locked" condition.

A delay locked loop operates in a similar manner to a phase locked loop except that the voltage controlled oscillator 118 is replaced with a voltage controlled delay line. The voltage controlled delay line receives the signal f_ref and generates a signal f_out. The loop adjusts the delay in the voltage controlled delay line until the signals f,_ef and f_out are aligned in phase, which is the stabilized or locked condition.

Conventional phase locked loops using charge pumps, and particularly when the arrangement is used as a frequency synthesizer, can suffer from the reference spur requirement, which makes it difficult to design wide-band width frequency synthesizers. The reference spur is generated by non-ideal behavior of the phase locked loop, including the mismatch of the phase detector and the charge pump. One previous attempt to address this problem has been to use a notch filter in the loop filter. However, this approach degrades the phase margin significantly and can result in a problem with stability and increased power consumption.

Unequal charge pump current sources contribute to the reference spur problem. As mentioned above, charge pumps typically use a charging current source to charge the output terminal 132 and a discharging current source to discharge the output terminal 132. The charging current source and the discharging current source are extremely difficult to match exactly because of physical limitations. Thus, when a minimum pulse is forced on each input terminal 124 and 126 of the charge pump 112 in the locked condition, charge will be added or removed from output terminal 132 because the charging and discharging currents are not equal. This results in a change in the charge at the output terminal 132 causing a change in the voltage V_αut, which in turn causes the phase locked loop 100 to change the phase of the signal f_ou„ thereby introducing a static phase error. Another problem with conventional phase locked loops utilizing charge pumps is the so-called "dead zone." A dead zone can result from the inability of phase detectors to output short duration pulses. Short duration pulses result from small phase differences between f_ref and f_out depicted in Figure 1. This limitation results in part due to the rise and fall times of the devices used to implement the phase detector. In the dead zone region, no pulse is output by the phase detector even though a small phase difference may exist between the two inputs. Thus, no current is output by the charge pump. This dead zone can result in non-linearity in the operation of the conventional phase detector and can result in jitter around the dead zone region.

Summary of the Invention There is a need in the industry to have an apparatus and method for enhancing the performance of phase locked loops and delay locked loops by tuning the phase offset of the loop.

One embodiment of the invention is in the form of a phase locked loop employing an improved charge pump having at least one variable source. The phase locked loop includes a controlled oscillator having a frequency output controlled by an input signal, a phase detector coupled to receive the output of the controlled oscillator and to receive a reference frequency. The phase detector is configured to output a signal proportional to the difference in phase between its two inputs. A charge pump is coupled to receive the output of the phase detector and to produce an output in response thereto. The charge pump includes at least one variable source and is capable of receiving a control signal wherein the variable source can be varied according to the control signal. The output of the charge pump is provided to the input of the controlled oscillator.

In another aspect of the invention, the charge pump includes a variable positive source, a variable negative source, a first switch for controllably coupling the variable positive source to the output of the charge pump and a second switch for controllably coupling the variable negative source to the output of the charge pump. In addition, both the variable positive source and the variable negative source can further include a primary current source and at least one incremental current source.

In another aspect of the invention, a delay locked loop includes a variable delay line configured to receive a reference signal and having a delayed output controlled by an input signal received at an input. A phase detector is coupled to receive the delayed output of the variable delay line and the reference signal. The phase detector is configured to output a phase error signal proportional to the difference in phase between the two inputs of the phase detector. A charge pump is coupled to receive the phase error signal and to generate a charge output. The charge pump includes at least one variable source which is configured to receive a control signal. The at least one variable current source is varied according to the control signal and the charge output of the charge pump is provided to the input of the controlled oscillator.

A further aspect of the invention includes a charge pump suitable for use in a locked loop having a phase detector and a controlled oscillator or a controlled delay line, both having an output controlled by an input signal. The charge pump includes a variable positive source and a first switch coupled to the variable positive source and configured to receive a control signal for controllably coupling the variable positive source to an output of the charge pump. The charge pump also includes a negative source and a second switch coupled to the negative source and configured to receive a control signal for controllably coupling said negative source to the output of said charge pump. In another aspect of the invention, the variable positive source further includes a primary source and at least one incremental source, wherein the application of the at least one incremental source is controlled by the control signal.

Brief Description of the Drawings The features, objectives and advantages of the invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, wherein: Figure 1 is a block diagram of a phase locked loop. Figure 2 is a block diagram of a phase detector.

Figure 3 is a timing diagram of selected signals within the phase detector of Figure 2. Figure 4 is a block diagram of a phase locked loop in accordance with the present invention. Figure 5 is a circuit diagram of an embodiment of a charge pump according to the present invention. Figure 6 is a timing diagram of various signals within the phase locked loop of Figure 4. Figure 7 is a block diagram of a delay locked loop in accordance with the present invention.

Detailed Description of the Preferred Embodiment

The invention is described in terms of exemplary embodiments with particular focus upon phase locked loops for synthesizing frequencies. However, it will be clear to those skilled in the art reading this description that the invention can be utilized in various systems including, for example, delay locked loops. Figure 4 is a block diagram of a phase locked loop 400 particularly suited for use as a frequency synthesizer.

The phase locked loop 400 can be implemented as an integrated circuit using known CMOS fabrication methods or other suitable semiconductor chip technology. A reference frequency (f_ref) is provided to an input of the phase detector

412, which may be a phase/frequency detector. The reference frequency can be provided, for example, by an oscillator such as a crystal oscillator (not shown). The two outputs of the phase detector, up (UP) and down (DW), are provided to the charge pump 414. The charge pump 414 also receives control signal on a control line 422. The charge pump adds or subtracts charge from the loop filter 416. The output of the loop filter is provided to the input of the controlled oscillator 418 which may be in the form of a voltage controlled oscillator. The output of the controlled oscillator 418 is used as the output of the phase locked loop 400 and as the input to a divider 420. The divided output

(f_diy) of the divider 420 is then provided as the second input to the phase detector 412. The phase detector 412, loop filter 416, voltage controlled oscillator 418 and divider 420 operate in the manner described above and may be of any suitable type known to those of ordinary skill. For example, the controlled oscillator may be voltage or current controlled, the loop filter may be passive or active and the phase detector can be a phase/frequency detector.

Figure 5 is a circuit diagram of the embodiment of the charge pump 414 shown in Figure 4. The terminals labeled UP and DW control the application of the current sources of the charge pump which add to the voltage at the output 511 labeled V_out and subtract from that voltage, respectively. Signal UP controls the first switch 510 and signal DW controls the second switch 512. Each of the switches 510, 512 apply and remove charge based upon the signal present on the control line.

A variable positive current source 513 is coupled at its output to the input side of the switch 510. A primary current source 514 is coupled to the output of the variable positive current source 513. Three incremental positive current sources 516, 518 and 520 are switchably coupled to the output of the variable positive current source 513 via the switches 522, 524 and 526, respectively. The control line 422 controls the operation of the switches 522, 524 and 526. The control can be accomplished, for example, using appropriate control logic (not shown) and a three bit control word.

The variable negative current source 529 is coupled at its output to the input terminal of the switch 512. The variable negative current source 529 includes a primary current source 530. In addition, the incremental current sources 532, 534 and 536 are switchably connected to the output of the variable negative current source 529 via the switches 538, 540 and 542, respectively. The control line 422 is coupled to each of the switches 538, 540 and 542 and controls their state. Of course, varying numbers of incremental current sources as well as subtractive current sources can be utilized depending upon the particular design requirements of the system in which the charge pump is to be used. For example, the primary current sources 514 and 530 may be 1 milliamp sources with each of the incremental current sources providing 0.1 milliamps of current. Of course, other techniques to vary or program the output of the current sources 513, 529 can be used instead of the incremental sources shown in Figure 5. For example, the output of the current sources 513, 529 could be varied by varying their power input or through the use of varying resistance. Figure 6 is a timing diagram showing selected signals present in the phase locked loop of Figure 4 wherein the current sources 514 and 530 are approximately equal. As shown in Section (a) of Figure 6, when the signals f_ref and f_diϊ are in phase, the output from the current source 513 is equal to the output from the current source 529 with the effective output V_out being 0 (see Figures 4 and 5). Therefore, the control line 422 is set such that none of the incremental current sources 516, 518, 520, 538, 540 and 542 are being used. When signal f_diϊ leads signal f_ref the output from the current source 513 is again effectively canceled by the output from the current source 529 with the current source 529 also generating additional output to compensate for the lead of signal f_drv.

However, when a phase offset is desired, the amount of current output by the source 513 can be increased, for example, by having the control line 422 turn on switch 522, thereby adding the output of the incremental current source 516 to the output of the current source 514, thereby increasing the output of current source 513. Therefore, when the phase locked loop shown in Figure 4 is locked, because the current output of the source 513 is mismatched to the output of the source 529, a phase offset between the signals f_ref and f_div occurs, with the offset being proportional to the amount of the mismatch. The amount of the mismatch can be controlled or set by the selecting of the supplemental current sources. In the example shown in Section (b) of Figure 6, the output of the current source 513 is set to be greater than the output of the current source 529. That results in signal f_diϊ having a phase offset which causes it to lead signal f_ref. The charge pump 414 with its digitally programmable current mismatch allows a circuit designer or user of a phase locked loop to fine-tune the phase offset by controlling the current mismatch of the charge pump. As noted previously, this is also applicable to delay locked loops. Referring now to Figure 7, a delay locked loop employing the principals of the present invention will be described. Figure 7 is a block diagram of a delay locked loop 700. The delay locked loop 700 can be implemented as an integrated circuit using known CMOS fabrication methods or other suitable semiconductor chip technology. A reference frequency (f_ref) is provided to an input of the phase detector 412. The reference frequency can be provided, for example, by an oscillator such as a crystal oscillator (not shown). The two outputs of the phase detector, up (UP) and down (DW), are provided to the charge pump 414. The charge pump 414 also receives a control signal on a control line 422 as was described in detail above. The charge pump adds or subtracts charge from the loop filter 416. The output of the loop filter 416 is provided as the input or control signal of the variable delay element 710 which may be in the form of a voltage controlled delay line. The variable delay element 710 also receives reference frequency (f_ref) as a reference signal. The output of the variable delay element 710, is used as the output of the delay locked loop 700. The delayed output (f_out) of the variable delay element 710 is then provided as the second input to the phase detector 412. The phase detector 412, loop filter 416, and variable delay element 710 operate in the manner described above and may be of any suitable type known to those of ordinary skill.

The delay locked loop depicted in Figure 7 can be utilized, for example, to synchronize a high speed digital memory. Aspects of the current invention can be utilized to fine tune clock skew in the pico second range. For example, if the minimum turn-on-time of the phase detector is 1 nanosecond, digitally programming or adjusting the mismatch of the charge pump, such as charge pump 414, to 10% adjusts the skew by 100 pico seconds. In that manner, the skew can be controlled or substantially eliminated.

The invention has been shown and described with respect to particular embodiments. However, various changes may be made therein without departing from the spirit and scope of the invention. For example, fewer or more incremental current sources can be employed in the charge pump of the present invention. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning range of equivalency of the claims are to be embraced within their scope.

Claims

WHAT IS CLAIMED IS:

1. A phase locked loop comprising: a controlled oscillator having a frequency output controlled by an input signal; a phase detector coupled to receive as inputs the output of said controlled oscillator and a reference frequency, said phase detector responsive to said inputs to output a signal representative of the difference in phase between the two inputs; and a charge pump coupled to receive as inputs the output of said phase detector and a control signal, said charge pump responsive to said control signal and said output of said phase detector to vary the output of the charge pump, the output of the charge pump providing said input of said controlled oscillator.

2. The phase locked loop of Claim 1, said charge pump having a variable power source, said variable power source responsive to said control signal to provide a power level in said charge pump selected by said control signal.

3. The phase locked loop of Claim 2, wherein said variable power source is a current source.

4. The phase locked loop of Claim 1, further comprising a frequency divider coupled between the output of said controlled oscillator and the input of said phase detector, said divider providing a frequency divided output of the controlled oscillator to the input of said phase detector.

5. The frequency synthesizer of Claim 4, further comprising a loop filter coupled to receive the output of said charge pump and to generate an output signal contribute to control of said controlled oscillator.

6. The phase locked loop of Claim 1, wherein said controlled oscillator is a voltage controlled oscillator.

7. The phase locked loop of Claim 4, wherein said frequency divider is a fractional-N divider.

8. The phase locked loop of Claim 1, wherein said charge pump further comprises a variable positive source, a variable negative source, a first switch for controllably coupling said variable positive source to the output of said charge pump, and a second switch for controllably coupling said variable negative source to the output of said charge pump.

9. The phase locked loop of Claim 8, wherein said variable positive source and said variable negative source are current sources.

10. The phased locked loop of Claim 6, wherein the output of said phase detector comprises at least two signals with a first signal coupled to said first switch and a second signal coupled to said second switch.

11. The phase locked loop of Claim 8, wherein said variable positive source comprises a primary current source and at least one incremental current source.

12. The phase locked loop of Claim 8, wherein said variable negative current source further comprises a primary current source and at least one incremental current source, wherein the application of said at least one incremental current source is controlled by said control signal.

13. A delay locked loop, comprising: a variable delay configured to receive a reference signal and an input signal, said variable delay having a delayed output controlled by an input signal received at an input; a phase detector coupled to receive the delayed output of said variable delay and the reference signal and to output a phase error signal proportional to the difference in phase between the output of the variable delay and the reference signal; and a charge pump coupled to receive the phase error signal and generate a charge output, said charge pump having at least one variable source and configured to receive a control signal, wherein said at least one variable source is varied according to the control signal and the charge output of said charge pump is provided to the input of said controlled oscillator.

14. The delay locked loop of Claim 13, further comprising a loop filter coupled to receive the output of said charge pump and to generate an output signal to control said variable delay line.

15. The delay locked loop of Claim 13, wherein said charge pump further comprises a variable positive source, a variable negative source, a first switch for controllably coupling said variable positive source to the output of said charge pump, and a second switch for controllably coupling said variable negative source to the output of said charge pump.

16. The delay locked loop of Claim 15, wherein the output of said phase detector comprises a two part signal with a first part coupled to said first switch and a second part coupled to said second switch.

17. The delay locked loop of Claim 15, wherein said variable positive source further comprises a primary current source and at least one incremental current source, wherein the application of said at least one incremental current source is controlled by said control signal.

18. The delay locked loop of Claim 15, wherein said variable negative source further comprises a primary current source and at least one incremental current source, wherein the application of said at least one incremental current source is controlled by said control signal.

19. A charge pump suitable for use in a locked loop having a controlled oscillator, or a controlled delay line, having an output controlled by an input signal and a phase detector, the charge pump comprising: a variable positive source; a first switch coupled to said variable positive source and configured to receive an input signal for controllably coupling said variable positive source to an output of said charge pump; a negative source; and a second switch coupled to said negative source and configured to receive the input signal for controllably coupling said negative source to the output of said charge pump.

20. The charge pump of Claim 19, wherein said variable positive source further comprises a primary source and at least one incremental source, wherein the application of said at least one incremental source is controlled by a control signal.

21. The charge pump of Claim 20, wherein said primary source and said incremental source are current sources.

22. The charge pump of Claim 19, wherein said negative source is variable and further comprises a primary source and at least one incremental source, wherein the application of said at least one incremental source is controlled by a control signal.

23. The charge pump of Claim 17, wherein said primary source and said incremental source are current sources.