Moon et al., 2000 - Google Patents
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performanceMoon et al., 2000
View PDF- Document ID
- 8863376739487180624
- Author
- Moon Y
- Choi J
- Lee K
- Jeong D
- Kim M
- Publication year
- Publication venue
- IEEE Journal of Solid-State Circuits
External Links
Snippet
This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled …
- 238000000034 method 0 abstract description 12
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Moon et al. | An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance | |
Kim et al. | A low-power small-area/spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator | |
Chang et al. | A wide-range delay-locked loop with a fixed latency of one clock cycle | |
US20120177162A1 (en) | Symmetric Phase Detector | |
US10938394B2 (en) | Phase-locked loop circuit | |
Yang | Delay-locked loops-an overview | |
KR101252048B1 (en) | A Frequency-Phase-Locked Loop with a Self-Noise Suppressing Voltage Controlled Oscillator | |
Chang et al. | A 0.7-2-GHz self-calibrated multiphase delay-locked loop | |
US7750695B2 (en) | Phase-locked loop circuitry using charge pumps with current mirror circuitry | |
Larsson | A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction | |
Cai et al. | A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter | |
Tan et al. | A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector | |
Cheng et al. | A difference detector PFD for low jitter PLL | |
Tak et al. | A low-reference spur MDLL-based clock multiplier and derivation of discrete-time noise transfer function for phase noise analysis | |
Dutta et al. | Exploring the landscape of phase-locked loop architectures: A comprehensive review | |
Bae et al. | A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme | |
US7283602B2 (en) | Half-rate clock and data recovery circuit | |
JP2012034212A (en) | Phase-locked loop circuit | |
US7545193B2 (en) | Voltage-controlled delay circuit using second-order phase interpolation | |
KR100769690B1 (en) | Interface device using clock generator based on frequency voltage converter and clock generator based on frequency voltage converter | |
Chong et al. | A PLL with a VCO of improved PVT tolerance | |
Tan et al. | Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance | |
Moazedi et al. | A low-power multiphase-delay-locked loop with a self-biased charge pump and wide-range linear delay element | |
Moon et al. | A 62.5-250 mhz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells | |
KR102418077B1 (en) | Injection-locked PLL architecture using sub-sampling-based frequency tracking loop and delay locked loop |