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US3893067A - Traffic signal control system - Google Patents

Traffic signal control system Download PDF

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Publication number
US3893067A
US3893067A US341848A US34184873A US3893067A US 3893067 A US3893067 A US 3893067A US 341848 A US341848 A US 341848A US 34184873 A US34184873 A US 34184873A US 3893067 A US3893067 A US 3893067A
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United States
Prior art keywords
computer
signals
phase
traffic
fail
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Expired - Lifetime
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US341848A
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English (en)
Inventor
Hiroo Watanabe
Minoru Nagao
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Omron Corp
Original Assignee
Omron Tateisi Electronics Co
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Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/07—Controlling traffic signals
    • G08G1/081—Plural intersections under common control

Definitions

  • ABSTRACT Fail-safe apparatus for controlling traffic signals upon failure of an electronic computer.
  • the computer normally controls traffic signals at a multiplicity of intersections.
  • the computer and the fail-safe apparatus count the indication times of the traffic signals in synchronism.
  • the indications of the traffic signals are controlled, upon failure of the computer, in accordance with signals generated corresponding to each countout of the indication times by the fail-safe apparatus.
  • the invention relates to a traffic signal control system, and particularly relates to a centralized traffic signal control system for controlling traffic signals at a multiplicity of intersections from a central control station.
  • a centralized traffic signal control wherein traffic signals over a wide territory are centralizedly controlled at a central control station is well known.
  • a central processing unit and an electronic computer to which traffic informations at certain locations in the territory are supplied, are provided at the central control station.
  • vehicle detectors At the locations where traffic signals are installed, supersonic inductance or earth magnetism vehicle detectors for collecting traffic informations are profided.
  • vehicle detectors are well known in which information of vehicle movements obtained by such vehicle detectors are supplied to the electronic computer.
  • the computer computes traffic volumes, time occupancy and speed of vehicles according to the vehicle detection signals.
  • the computer computes traffic patterns to suit the conditions of vehicular traffic flows, and makes decision ot timings of traffic signals, such as times or respective phases of traffic signals. Such times of phases of traffic signals are counted by the computer. Each time the computer counts out the respective computed values, a signal for advancing the phase of traffic signals is transmitted to the traffic signals. The indication of the traffic signals is switched over in accordance with the signal transmitted from the central control station.
  • a fail-safe apparatus which continues, upon failure of the computer, systematic control ofthe traffic signals according to the traffic control pattern based on a pre-set program therein, is provided at the central control station.
  • This fail-safe apparatus counts indication times of traffic signals and transmits signals for advancing phases of traffic signals.
  • each traffic signal is switched according to the signals for advancing phases from the fail-safe device, instead of the signals from the computer.
  • one traftic control pattern may be pre-set, or two or three traffic control patterns, which are selected according to the time of day, may be pre-set.
  • the failsafe apparatus counts the indication times independent of the computer during the normal operation of the computer.
  • the phase advancing signals generated from the failsafe apparatus are not supplied to the traffic signals during the normal operation of the computer.
  • the phase advance signals generated by the fail-safe apparatus are supplied to the traffic signals.
  • the count of the indication times by the fail-safe apparatus is performed independent of the count by the computer, it takes a certain time for transfering the control of the traffic signals by the computer to the control by the fail-safe apparatus. Namely, if the computer fails within a short time after right-of-way ofa certain main street has been given and the count of time by the fail-safe apparatus is, at that time, approaching to a value to finish the right-of-way of the main street, then the right-of-way of the main street given by the computer will be finished within a very short time by the phase advance signal from the fail-safe apparatus.
  • each traffic signal was disconnected from the central control station at the time of failure of the computer, and controlled independently by corresponding local controller installed at corresponding intersection for a certain time and the control by the respective fail-safe apparatus was commenced at the time when the phase or indication of the fail-safe apparatus coincides with that of the local controller.
  • the object of the present invention is to provide a traffic signal control system which can smoothly control traffic flows over a wide territory by immediately transfering the control of traffic signals by electronic computer to the control by fail-safe apparatus upon failure of computer.
  • a fail-safe apparatus is provided at the central control station or at other suitable location.
  • indication times of traffic signals such as times of phases are preset.
  • the fail-safe apparatus counts the times of the indication of traffic signals in synchronism with the time count of the computer.
  • the fail-safe apparatus is so constituted to commence the count of each time in accordance with the phase advance pulses generated by the computer, and also to commence the count of each time in accordance with signals transmitted from the respective traffic signals, as will be described later with respect to an embodiment of the invention.
  • the count of times by the fail-safe apparatus according to the invention is not performed independent of the count of time by the computer.
  • the indication of the traffic signals is switched in accordance with the countout of the respective indication times by the computer, and when the computer fails, the indication of the traffic signals is switched in accordance with countout of the respective indication times by the failsafe apparatus.
  • FIG. 1 is a block diagram illustrating an embodiment of the invention
  • FIG. 2 is a block diagram illustrating more particular constitution of fail-safe apparatus in FIG. l,
  • FIG. 3 is an explanatory drawing showing synchronous time counting operation of computer and the failsafe apparatus
  • FIG. 4 is an explanatory drawing showing the manner of control before and after failure of the computer, and,
  • FIG. is an explanatoly drawing showing the mutual relationship of phase advance signals for adjacent traffic signals.
  • a computer is shown as a block 100
  • a fail-safe apparatus is shown as a block 200.
  • the phase advance signal SC generated by the computer 100 is supplied respectively to one input terminal of gate circuits 300, 301 and 302.
  • Signal S1 is respectively sup plied to another input terminal of the gate circuits 300, and 302.
  • the phase advance signal SC supplied to the input terminals of the gate circuits 300, 301 and 302 appears at the output terminals thereof according to presence of the signal S1.
  • the output signals of the gate circuits 300, 301 and 302 are supplied to OR gates 400, 401 and 402.
  • the signal S1 is present when the computer 100 is normally operating, and is not present when the computer 100 fails.
  • the phase advance signal SF generated by the failsafe apparatus 200 is respectively supplied to one input terminal of INHIBIT gates 500, S01 and 502.
  • the signal S1 is supplied to respective other input terminal of the INHIBIT gates S00, S01 and 502.
  • the signal SF generated by the fail-safe apparatus 200 appears at the output terminals of the gates 500, 501 and 502 when the signal S1 is absent.
  • the output signals of the gate circuits 500, 501 and 502 are supplied to respective other input terminal of the OR gates 400, 401 and 402.
  • the output signals of the OR gates 400, 401 and 402 are transmitted to corresponding traffic signals 600, 60l and 602 through transmission lines 700, 701 and 702.
  • the indications of the traffic signals are switched, when the computer 100 is operating normally, in accordance with the phase advance signal SC generated by the computer 100, and are switched, when the computer 100 is in failure, in accordance with the phase advance signal SF generated by the fail-safe apparatus 200.
  • the fail-safe apparatus 200 is connected to the computer 100 through a control line CL and a bus line BL.
  • control parameters computed by the computer 100 are supplied to the failsafe apparatus 200.
  • FIG. 2 shows the fail-safe apparatus 200.
  • Registers 1, 2, 3, 4, 5 and 6 are provided in the fail-safe apparatus 200 for setting the respective time of phase of the traffic signals 600.
  • the fail-safe apparatus may include additional registers and similar circuitry as described below for control of traffic signals 601, 602.
  • the data to be stored in the registers 1, 2, 3, 4, S and 6 are emit ted at a first bus line BL] from the computer 100.
  • the computer 100, in FIG. 1, is connected respectively to one input terminal of AND gates 21, 22, 23, 24, 25 and 26 through a bus line BL], and also is connected respectively to another input terminal of the AND gates 21 through 26 through a first control line CLl.
  • the output terminals of the AND gates 21 through 26 are respectively connected to the input terminals of the registers 1 through 6.
  • the data signals from the computer 100 are conveyed on the bus line BL] and appear at the output terminals of the AND gates 21 through 26 when a signal is supplied to a respective input terminal thereof from the computer through the control line CLl.
  • the output terminals of the AND gates 21 through 26 are respectively connected to the input terminals of the registers l, 2, 3, 4, 5 and 6. Therefore, respective value of phase times computed by the computer 100 is stored in the registers 1, 2, 3, 4, 5 and 6 every unit time, for example, five minutes.
  • the value of the time of a first phase is stored in the register 1
  • the value of the time ofa sec ond phase is stored in the register 2
  • in sequence the value of the time of a sixth phase is stored in the register 6.
  • a counter 7 is provided for counting the respective time of phases.
  • the counter 7 advances in accordance with clock pulses generated by a clock pulse generator 8, and is reset each time when a counter 9 advances.
  • the clock pulses generated by the generator 8 are supplied to the input terminal ofa frequency divider 10.
  • a decoder 11 is provided for controlling the divider 10, and the divider 10 generates at its output terminal pulse signals by dividing the frequency of the clock pulses by the value instructed by the decoder 11.
  • the decoder 11 is controlled by the computer 100 through a bus line BL2.
  • the pulse signals appearing at the output terminal of the divider 10 are called "per-cent pulses.
  • the output terminal of the divider 10 is connected to both input terminals of gate circuits 12 and 13. Both the output terminals of the gate circuits [2 and 13 are connected to input terminal of OR gate 14, and the output terminal of the OR gate 14 is connected to the input terminal of the counter 7.
  • the signal S1 is supplied to the other terminals of the gate circuits 12, 13.
  • the set output terminal of a flipflop 15 is connected to the remaining input terminal of the gate circuit 13.
  • the counter 7 advances stepwise in accordance with the per-cent pulses with the flip-flop 15 being set.
  • the counter 7 advances in accordance with the per-cent pulses regardless of the state of the flip-flop 15.
  • the flip-flop 15 is set by the signal SC transmitted from the computer 100.
  • the signal SC is also supplied to the input terminal of OR gate 16.
  • the output terminal of the OR gate 16 is connected to the reset terminal of the counter 7 and also to the counter 9.
  • the output terminal of the counter 9 is connected respectively to one input terminal of AND gates 31, 32, 33, 34, 35 and 36.
  • the respective other terminal of the AND gates 31, 32. 33, 34, 35 and 36 are connected to respective output terminals of the registers l, 2, 3, 4, 5 and 6.
  • the data signals stored in the registers 1, 2, 3, 4, 5 and 6 appear at the output terminals of the AND gates 31, 32, 33, 34, 35 and 36, respectively, in accordance with the supply of output signal from the counter 9 to the respective one input terminal of the AND gates 31 through 36.
  • the output terminals of the AND gates 31 through 36 are connected to one input terminal of a co incidence circuit 17.
  • the output terminal of the counter 7 is connected to the other input terminal of the coincidence counter 17.
  • a signal 82 appears at the output terminal of the coincidence circuit 17 upon coincidence of the count value of the counter 7 with the data signal from the AND circuits 31, 32, 33, 34, 35 and 36.
  • the output terminal of the coincidence circuit 17 is connected to the input terminal of a gate circuit 500 as well as to the reset input terminal of the flip-flop circuit 15.
  • the counter 9 advances stepwise in accordance with the output of the OR gate 16, and the output of the counter 9 in each stage opens a corresponding one of the AND gates 31 through 36 in sequence.
  • the time value stored in each register 1 through 6 is supplied to the coincidence circuit 17 respectively in accordance with corresponding output of the counter 9 through the AND gates 31 to 36.
  • times of each phase computed by the computer are set in the registers I through 6 respectively, and the times of each phase are counted successively in the computer 100.
  • the computer 100 generates the signal SC when it counts out the time of a respective phase. Since the counter 7 is reset by the signal SC, the signal S2 at the output terminal of the coincidence circuit 17 appears simultaneously with the signal SC generated by the computer 100.
  • the counter 9 is advanced by the advance signal SC, and the count of time of the time counter 7 and the count of time of the computer 100 are commenced simultaneously, and accordingly, it will be understood that the time when the signal SC is generated by the computer 100 and the time when the output signal of the coincidence circuit 17 appears are in coincidence in every phase. Therefore, even if the computer I00 fails at a time t as shown in FIG. 4, since the phase of the counter 9 provided in the fail-safe apparatus 200 is same to that of the traffic signal, and the value of time count of the counter 9 in that phase is equal to that of the computer [00, the control of the traffic signals 600, 60], 602 can be switched from the control by the computer 100 to the control by the failsafe apparatus without any troubles.
  • the signal SC from the computer 100 is transmitted to the traffic signals at adjacent intersections with an offset value ()FV suited to the traffic flow.
  • the mutual relationship between phase advance signals transmitted to those adjacent intersections are shown in FIG. 5.
  • phase advance signal SCO has been 5 transmitted to the traffic signal 500 shown in FIG. I.
  • phase advance signal SCI is transmitted to the ad jacent traffic signal 50] with offset value OFVI in that phase.
  • the phase advance signal 5C2 is transmitted to the adjacent traffic signal 502 with offset value OFVZ in that phase. In this manner, the traffic signals are systematically controlled.
  • a third bus line BL3 is provided for the purpose of adjusting the phase of the counter 9, at a desired time, in coincidence with the phase of traffic signals instructed by the computer I00.
  • the setting of the signal of data to the registers 1 through 6 is performed by the computer 100, however, it may be so constituted that the setting of signals of data to the registers 1 through 6 is performed manually.
  • the values of data to be set in the registers 1 through 6 are not necessary in coincidence with the phase times computed by the computor 100. The only one condition necessary is that the sum of the data to be set in the registers 1 through 6 are equal with respect to the respective intersections to be systematically controlled.
  • a traffic signal control system for controlling traffic signals at a multiplicity of intersections comprising,
  • a computer for counting first phase time of traffic signals and generating first signals for advancing phases of the traffic signals upon each eountout of the first phase times
  • a fail-safe apparatus in which second phase times of the traffic signals are set, and to which said first phase advance signals generated by said computer are supplied,
  • said fail-safe apparatus commencing the count of the second phase times in accordance with said first phase advance signals from said computer when said computer is normally operating, and for generating second signals for advancing the phases of said traffic signals upon attaining a count of said set second phase times, and
  • logic switch means for transmitting said first phase advance signals from said computer when said computer is normally operating, and for transmitting said second phase advance signals from said fail-safe apparatus when said computer fails.
  • said fail-safe apparatus includes means responsive to said computer for setting the second phase times in said fail-safe apparatus by said computer.
  • a traffic signal control system according to claim I, wherein said fail-safe apparatus includes means for manually setting said second phase times in said failsafe apparatus.
  • said fail-safe apparatus includes:
  • first means in which the second phase times are set and providing an output value indicative thereof.
  • third means for generating second phase advance signals upon coincidence of the count value of said second means with said output value of said first means.
  • a traffic signal control system further including means for interrupting the supply of said clock pulses to said second means for a time period between the second generation of the phase advance signal by the third means and the generation of a first phase advance signal by said computer.
  • a traffic signal control system wherein said first means includes a plurality of registers, each of said registers storing a value corresponding to a different phase time, said third means comparing the value of each of said registers with the count value of said second means for generating second phase advance signals upon coincidence thereof.
  • a traffic signal control system further comprising means for sequentially supplying the output of each of said registers to said third means.
  • a trat'fic signal control system includes a counter for enabling a gating means at the output of each of said registers in a predetermined sequence.
  • a traffic signal control system wherein said registers store a signal value therein supplied by said computer

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Traffic Control Systems (AREA)
  • Feedback Control In General (AREA)
  • Safety Devices In Control Systems (AREA)
US341848A 1972-03-16 1973-03-16 Traffic signal control system Expired - Lifetime US3893067A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47026848A JPS5225077B2 (fr) 1972-03-16 1972-03-16

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US3893067A true US3893067A (en) 1975-07-01

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US341848A Expired - Lifetime US3893067A (en) 1972-03-16 1973-03-16 Traffic signal control system

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US (1) US3893067A (fr)
JP (1) JPS5225077B2 (fr)
BE (1) BE796882A (fr)
CA (1) CA1013048A (fr)
FR (1) FR2176127B1 (fr)
GB (1) GB1386716A (fr)
HK (1) HK34876A (fr)
IT (1) IT980605B (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402260A1 (fr) * 1977-09-02 1979-03-30 Siemens Ag Installation de signalisation de carrefour routier
US4356485A (en) * 1979-12-21 1982-10-26 Siemens Aktiengesellschaft Device for the signal-technical secure control and monitoring of electrical loads
US4481515A (en) * 1982-04-01 1984-11-06 Philmont Electronics, Inc. Coordinator for traffic signal controller
US4539993A (en) * 1982-11-18 1985-09-10 Medtronic, Inc. Fail-safe muscle stimulator device
US5208584A (en) * 1991-09-03 1993-05-04 Jonathan Kaye Traffic light and back-up traffic controller
US20050087955A1 (en) * 2003-09-02 2005-04-28 Charles Kellogg Trailer hitching aid
CN111815969A (zh) * 2020-06-18 2020-10-23 广东振业优控科技股份有限公司 基于对称相位非均衡交通流交叉口设置自由变向区的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399815A (en) * 1977-02-14 1978-08-31 Hokushin Electric Works Device for separating malfunctioned transmitter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3254324A (en) * 1961-01-13 1966-05-31 Casciato Leonard Traffic signal systems
US3255432A (en) * 1962-09-26 1966-06-07 Rad O Lite Inc Traffic light control systems
US3302170A (en) * 1964-04-28 1967-01-31 Ibm Traffic light control buffer
US3328791A (en) * 1961-01-13 1967-06-27 Peat Marwick Mitchell & Co Traffic monitoring systems
US3363185A (en) * 1965-05-04 1968-01-09 Sperry Rand Corp Auxiliary reference signal generating means for controlling vehicular traffic flow or other moving elements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3254324A (en) * 1961-01-13 1966-05-31 Casciato Leonard Traffic signal systems
US3328791A (en) * 1961-01-13 1967-06-27 Peat Marwick Mitchell & Co Traffic monitoring systems
US3255432A (en) * 1962-09-26 1966-06-07 Rad O Lite Inc Traffic light control systems
US3302170A (en) * 1964-04-28 1967-01-31 Ibm Traffic light control buffer
US3363185A (en) * 1965-05-04 1968-01-09 Sperry Rand Corp Auxiliary reference signal generating means for controlling vehicular traffic flow or other moving elements

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402260A1 (fr) * 1977-09-02 1979-03-30 Siemens Ag Installation de signalisation de carrefour routier
US4356485A (en) * 1979-12-21 1982-10-26 Siemens Aktiengesellschaft Device for the signal-technical secure control and monitoring of electrical loads
US4481515A (en) * 1982-04-01 1984-11-06 Philmont Electronics, Inc. Coordinator for traffic signal controller
US4539993A (en) * 1982-11-18 1985-09-10 Medtronic, Inc. Fail-safe muscle stimulator device
US5208584A (en) * 1991-09-03 1993-05-04 Jonathan Kaye Traffic light and back-up traffic controller
US20050087955A1 (en) * 2003-09-02 2005-04-28 Charles Kellogg Trailer hitching aid
CN111815969A (zh) * 2020-06-18 2020-10-23 广东振业优控科技股份有限公司 基于对称相位非均衡交通流交叉口设置自由变向区的方法
CN111815969B (zh) * 2020-06-18 2022-03-15 广东振业优控科技股份有限公司 基于对称相位非均衡交通流交叉口设置自由变向区的方法

Also Published As

Publication number Publication date
DE2312954A1 (de) 1973-09-20
FR2176127A1 (fr) 1973-10-26
IT980605B (it) 1974-10-10
JPS4895199A (fr) 1973-12-06
BE796882A (fr) 1973-09-17
HK34876A (en) 1976-06-18
JPS5225077B2 (fr) 1977-07-05
CA1013048A (en) 1977-06-28
DE2312954B2 (de) 1975-06-19
FR2176127B1 (fr) 1977-02-11
GB1386716A (en) 1975-03-12
AU5341173A (en) 1974-09-19

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