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US20020110637A1 - Conductive pattern producing method and its applications - Google Patents

Conductive pattern producing method and its applications Download PDF

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Publication number
US20020110637A1
US20020110637A1 US09/995,866 US99586601A US2002110637A1 US 20020110637 A1 US20020110637 A1 US 20020110637A1 US 99586601 A US99586601 A US 99586601A US 2002110637 A1 US2002110637 A1 US 2002110637A1
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Prior art keywords
pattern
substrate
chip
conductive film
conductive pattern
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US09/995,866
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Akira Mase
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Priority to US09/995,866 priority Critical patent/US20020110637A1/en
Publication of US20020110637A1 publication Critical patent/US20020110637A1/en
Priority to US11/048,767 priority patent/US7288437B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H05K2201/0326—Inorganic, non-metallic conductor, e.g. indium-tin oxide [ITO]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49137—Different components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • This invention relates to a conductive pattern producing method, and more particularly, relates to an improvement for conductive pattern producing method which makes the pattern thus produced by the method more credible.
  • the interest of operators to manufacture liquid crystal devices which comprises a pair of glass substrates and electrode pattern including addressing lines and signal lines for producing a matrix arragement, is directed to how to form a pattern on the substrates without deffect and with a high reliability of the pattern.
  • the device generally includes an IC chip for driving the liquid crystal device.
  • the facilitataion and credibility of the connection between the IC chip and the pattern is alway in question. Particularly, in the case that a pattern is formed on a glass substrate, there likely occur fissures in the pattern which cause disconnection of circuitry.
  • patterns are manufactured with double-layered film.
  • FIGS. 1 (A) to 1 (D) are cross sectional views showing a method of manufacturing a conductive pattern in accordance with the present invention.
  • FIGS. 2 (A) and 2 (B) are a plan view and cross sectional partial view showing a pattern fromed in accordance with the present invention.
  • FIGS. 3 (A) and 3 (B) are cross sectional partial views showing contact portions between IC chips and conductive patterns in accordance with the present invention.
  • FIGS. 4 (A) and 4 (B) are graphical diagrams of temperature curves which are used in methods in accordance with the present invention.
  • FIGS. 5 (A) to 5 (C) are cross sectional views showing a method in accordance with the present invention.
  • FIG. 6 is a cross sectional view showing the contact portion between an IC chip and the conductive pattern produced by the method as illustrated in FIGS. 5 (A) to 5 (C).
  • FIGS. 1 (A) to 1 (D) a method of forming a conductive pattern on a substrate for mounting thereon an IC chip in accordance with the present invention.
  • a conductive pattern is formed by offset screen printing with a conductive paste (FIG. 1(A)).
  • the conductive paste for the pattern is prepared by mixing, with an oil emulsion, “cover silver paste” (Prod No. 61900234) distributed by Detmeron, a manufacture of FRG.
  • the thickness of the pattern is 10 microns.
  • the substrate is baked in a nitrogen atmosphere in accordance with a temperature curve shown in FIG.
  • FIGS. 2 (A) and 2 (B) are plan view and a cross sectional view showing the whole pattern on the substrate formed as explaned above.
  • a transparent adhesive of epoxy resin mixed with Ni particles having 15 microns in average diameter is applied to the surface of the substrate which is to face the bottom surface and the electrode pads of an IC.
  • the Ni particles are added into at 50 mg per each 5 g of the adhesive.
  • the IC chip is mounted on the substrate with its aluminium pads contacting corresponding pads of the thick portion of the pattern, and the epoxy resin is hardened at 180° C. while pressing the IC against the substrate for 20 munites with a force of 3 Kg using a jig.
  • the alignment of the pads of the IC chip with the pattern on the substrate is checked by viewing the both from the bottom of the substrate through the transparent resin.
  • a resin which can be cured by a UV light may be also used as the adhesive.
  • the resin is irradiated with a UV light through the transparent substrate.
  • FIG. 3(A) is a partial cross section view showing the contact of the IC chip 5 with the substrate 1 after the hardening of the epoxy adhesive.
  • the distance between the Al pad 8 and the top of the thick portion 3 is designed 3 microns in which the Ni particles are caught and make the resistance of the contact low.
  • Other particles contained in the epoxy resin are situated between the IC chip and the substrate with 30 microns in distance, and do not damage the IC chip and the pattern 2 on the substrate 1 .
  • the area of the thick portion is preferably smaller than that of the corresponding pad of the pattern.
  • FIG. 3(B) is a cross sectional view showing the electrical connection between the IC chip and the pattern in accordance with this embodiment.
  • FIGS. 5 (A) to 5 (C) a third embodiment of the invention is illustrated.
  • a glass substrate 1 is coated by printing with a conductive paste consisting of Cu particles dispersed in a phenol resin, in order to form a prescribed pattern 11 comprising electrode lines for making contact with counterpart pads of the IC chip.
  • the average diameter of the Cu particle is 5-10 microns.
  • This conductive paste coating is then baked at 60° C. for 10 munites and becomes thin by shrinking.
  • the baked layer 11 might have a fissure 12 .
  • Another layer 13 of the Cu conductive paste is super-imposed over the layer 11 by printing on the baked Cu layer as shown in FIG. 5(B).
  • the overlying Cu layer is also baked at 60° C. for 10 munites.
  • the fissure 12 has to be mended by this overlying pattern.
  • the dispersion of the double-layered pattern in thickness is about 30 microns.
  • the double-layered pattern is then pressed to produce an even top surface 14 .
  • the thickness of the double-layered pattern becomes about 20 microns after pressing.
  • On the pattern is mounted an IC chip whose electrode pads to be made contact with the patterns are given Au bumps by plating and the IC chip is pressed against the substrate with an adhesive resin securing the IC chip in place.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Liquid Crystal (AREA)

Abstract

An improved method of forming an electrode pattern on a substrate is described. The substrate is coated with a first conductive film and subjected to baking. On the first conductive film is then overlied a second conductive film which mends possible fissures of the first conductive film which, besides, would produce open circuits in the pattern.

Description

    BACKGROUND OF THE INVENTION
  • This invention relates to a conductive pattern producing method, and more particularly, relates to an improvement for conductive pattern producing method which makes the pattern thus produced by the method more credible. [0001]
  • Heretofore, the interest of operators to manufacture liquid crystal devices which comprises a pair of glass substrates and electrode pattern including addressing lines and signal lines for producing a matrix arragement, is directed to how to form a pattern on the substrates without deffect and with a high reliability of the pattern. Also the device generally includes an IC chip for driving the liquid crystal device. The facilitataion and credibility of the connection between the IC chip and the pattern is alway in question. Particularly, in the case that a pattern is formed on a glass substrate, there likely occur fissures in the pattern which cause disconnection of circuitry. [0002]
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the invention to provide a method for producing a credible pattern. [0003]
  • In order to accomplish the object of the invention, patterns are manufactured with double-layered film.[0004]
    • BRIEF DESCRIPTION OF THE INVENTION
  • FIGS. [0005] 1(A) to 1(D) are cross sectional views showing a method of manufacturing a conductive pattern in accordance with the present invention.
  • FIGS. [0006] 2(A) and 2(B) are a plan view and cross sectional partial view showing a pattern fromed in accordance with the present invention.
  • FIGS. [0007] 3(A) and 3(B) are cross sectional partial views showing contact portions between IC chips and conductive patterns in accordance with the present invention.
  • FIGS. [0008] 4(A) and 4(B) are graphical diagrams of temperature curves which are used in methods in accordance with the present invention.
  • FIGS. [0009] 5(A) to 5(C) are cross sectional views showing a method in accordance with the present invention.
  • FIG. 6 is a cross sectional view showing the contact portion between an IC chip and the conductive pattern produced by the method as illustrated in FIGS. [0010] 5(A) to 5(C).
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIGS. [0011] 1(A) to 1(D), a method of forming a conductive pattern on a substrate for mounting thereon an IC chip in accordance with the present invention. On a glass substrate for liquid crystal device, only a portion of which is illustrated in the figures, a conductive pattern is formed by offset screen printing with a conductive paste (FIG. 1(A)). The conductive paste for the pattern is prepared by mixing, with an oil emulsion, “cover silver paste” (Prod No. 61900234) distributed by Detmeron, a manufacture of FRG. The thickness of the pattern is 10 microns. Then, the substrate is baked in a nitrogen atmosphere in accordance with a temperature curve shown in FIG. 4(A), so that formed are a contact region 2 a and a sintered region largely consisting of silver (FIG. 1(B)). Also, on a portion of the pattern, another pattern to make a thick portion is formed in the same manner by printing and baking (FIGS. 1(C) and 1(D)). The thickness of the thick portion is 30 microns after baking. Instead of printing, the pattern can be formed of ITO by sputtering with a good contact and a good conductivity. FIGS. 2(A) and 2(B) are plan view and a cross sectional view showing the whole pattern on the substrate formed as explaned above.
  • After the formation of the pattern, a transparent adhesive of epoxy resin mixed with Ni particles having 15 microns in average diameter is applied to the surface of the substrate which is to face the bottom surface and the electrode pads of an IC. The Ni particles are added into at 50 mg per each 5 g of the adhesive. Then, the IC chip is mounted on the substrate with its aluminium pads contacting corresponding pads of the thick portion of the pattern, and the epoxy resin is hardened at 180° C. while pressing the IC against the substrate for 20 munites with a force of 3 Kg using a jig. During the mounting of the IC chip, the alignment of the pads of the IC chip with the pattern on the substrate is checked by viewing the both from the bottom of the substrate through the transparent resin. [0012]
  • A resin which can be cured by a UV light may be also used as the adhesive. In this alternative, the resin is irradiated with a UV light through the transparent substrate. [0013]
  • FIG. 3(A) is a partial cross section view showing the contact of the [0014] IC chip 5 with the substrate 1 after the hardening of the epoxy adhesive. The distance between the Al pad 8 and the top of the thick portion 3 is designed 3 microns in which the Ni particles are caught and make the resistance of the contact low. Other particles contained in the epoxy resin are situated between the IC chip and the substrate with 30 microns in distance, and do not damage the IC chip and the pattern 2 on the substrate 1. The area of the thick portion is preferably smaller than that of the corresponding pad of the pattern.
  • Next, a second embodiment of the invention is described. After the formation of the pattern by printing and baking in the same manner as the [0015] pattern 2 of the preceding embodiment, a thick portion 3 is formed by coating the prescribed portion with DAP1 N (No.61901143), a conductive adhesive distributed by Detmeron. Then, the IC chip is mounted on the substrate with its aluminium pads contacting corresponding lands of the thick portion of the pattern and pressed against the substrate with a jig, and the substrate is baked in accordance with the temperature curve shown in FIG. 4(B). FIG. 3(B) is a cross sectional view showing the electrical connection between the IC chip and the pattern in accordance with this embodiment. By this embodiment, the method of the present invention brings the advantage that a few number of processing steps are required for mounting an IC chip and making necessary contact with the IC chip.
  • Referring to FIGS. [0016] 5(A) to 5(C), a third embodiment of the invention is illustrated. In FIG. 5(A), a glass substrate 1 is coated by printing with a conductive paste consisting of Cu particles dispersed in a phenol resin, in order to form a prescribed pattern 11 inclusing electrode lines for making contact with counterpart pads of the IC chip. The average diameter of the Cu particle is 5-10 microns. This conductive paste coating is then baked at 60° C. for 10 munites and becomes thin by shrinking. The baked layer 11 might have a fissure 12.
  • Then, another [0017] layer 13 of the Cu conductive paste is super-imposed over the layer 11 by printing on the baked Cu layer as shown in FIG. 5(B). The overlying Cu layer is also baked at 60° C. for 10 munites. The fissure 12 has to be mended by this overlying pattern. The dispersion of the double-layered pattern in thickness is about 30 microns. The double-layered pattern is then pressed to produce an even top surface 14. The thickness of the double-layered pattern becomes about 20 microns after pressing. On the pattern is mounted an IC chip whose electrode pads to be made contact with the patterns are given Au bumps by plating and the IC chip is pressed against the substrate with an adhesive resin securing the IC chip in place.
  • While a description has been made for several embodiments, the present invention should be limited only by the appended claims and should not be limited by the particualr examles. [0018]

Claims (1)

1. A method for producing an electrode pattern on a substrate comprising:
coating said substrate with a first conductive film in the form of an electrode pattern for circuitry; and
coating said substrate with a second conductive film overlying said first conductive film, said second conductive film being designed to function as a complete pattern for said circuitry even if it were not for said first conductive film.
US09/995,866 1986-12-24 2001-11-26 Conductive pattern producing method and its applications Abandoned US20020110637A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/995,866 US20020110637A1 (en) 1986-12-24 2001-11-26 Conductive pattern producing method and its applications
US11/048,767 US7288437B2 (en) 1986-12-24 2005-02-03 Conductive pattern producing method and its applications

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP61310493A JPS63160352A (en) 1986-12-24 1986-12-24 Method for packaging semiconductor device
JP61-310493 1986-12-24
US13656787A 1987-12-22 1987-12-22
US44245389A 1989-11-30 1989-11-30
US80774791A 1991-12-17 1991-12-17
US08/219,853 US6383327B1 (en) 1986-12-24 1994-03-30 Conductive pattern producing method
US09/995,866 US20020110637A1 (en) 1986-12-24 2001-11-26 Conductive pattern producing method and its applications

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US08/219,853 Division US6383327B1 (en) 1986-12-24 1994-03-30 Conductive pattern producing method

Related Child Applications (1)

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US11/048,767 Division US7288437B2 (en) 1986-12-24 2005-02-03 Conductive pattern producing method and its applications

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US20020110637A1 true US20020110637A1 (en) 2002-08-15

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US08/219,853 Expired - Lifetime US6383327B1 (en) 1986-12-24 1994-03-30 Conductive pattern producing method
US09/995,866 Abandoned US20020110637A1 (en) 1986-12-24 2001-11-26 Conductive pattern producing method and its applications
US11/048,767 Expired - Fee Related US7288437B2 (en) 1986-12-24 2005-02-03 Conductive pattern producing method and its applications

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Application Number Title Priority Date Filing Date
US08/219,853 Expired - Lifetime US6383327B1 (en) 1986-12-24 1994-03-30 Conductive pattern producing method

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Application Number Title Priority Date Filing Date
US11/048,767 Expired - Fee Related US7288437B2 (en) 1986-12-24 2005-02-03 Conductive pattern producing method and its applications

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Country Link
US (3) US6383327B1 (en)
EP (1) EP0272678A3 (en)
JP (1) JPS63160352A (en)
CN (1) CN1021875C (en)

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US20070215376A1 (en) * 2004-04-19 2007-09-20 Man Roland Druckmaschinen Ag Method For Printing Electrical And/Or Electronic Structures And Film For Use In Such A Method
US20060192915A1 (en) * 2004-12-02 2006-08-31 Semiconductor Energy Laboratory Co., Ltd. Display device
US7916263B2 (en) 2004-12-02 2011-03-29 Semiconductor Energy Laboratory Co., Ltd. Display device
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US10455696B2 (en) 2013-09-06 2019-10-22 Solvay Specialty Polymers Italy S.P.A. Electrically conducting assemblies
US10506710B1 (en) 2013-09-06 2019-12-10 Solvay Specialty Polymers Italy S.P.A. Electrically conducting assemblies

Also Published As

Publication number Publication date
US6383327B1 (en) 2002-05-07
CN1021875C (en) 1993-08-18
US7288437B2 (en) 2007-10-30
JPH0432541B2 (en) 1992-05-29
JPS63160352A (en) 1988-07-04
US20050148165A1 (en) 2005-07-07
EP0272678A3 (en) 1990-04-25
EP0272678A2 (en) 1988-06-29
CN87105952A (en) 1988-07-27

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