JPS58148434A - Manufacture of electric parts mounting substrate - Google Patents
Manufacture of electric parts mounting substrateInfo
- Publication number
- JPS58148434A JPS58148434A JP3199782A JP3199782A JPS58148434A JP S58148434 A JPS58148434 A JP S58148434A JP 3199782 A JP3199782 A JP 3199782A JP 3199782 A JP3199782 A JP 3199782A JP S58148434 A JPS58148434 A JP S58148434A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- solder
- solder balls
- electrode conductor
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 53
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 11
- 238000005219 brazing Methods 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 abstract description 4
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はアリツブチップＸＯなどの微小な電気部品が
実装される電気部品実装基板の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an electrical component mounting board on which minute electrical components such as an Arrival Chip XO are mounted.
従来この種の製造方法としてオ１図に示すものがあった
。Conventionally, there was a manufacturing method of this type as shown in Figure O1.
図において（１）はセラミック材等を使用した絶縁性基
板、帽）は絶縁性基板（１）上に配置され九電極導体、
（３）は絶縁性基板（１）および電極導体（創の所定領
域を覆うようにガラス材でスクリーン印刷形成され九膜
厚ＳＯμｍのはんだダム、（４１ｄ仁のはんだダム（３
）で形成された開口部（８ａ）にディップはんだ付けさ
れたはんだバンプ、（６）はフリップチップｘＯであｐ
＠ （ｓ ａ ）はその接続用端子となるバンプで、
このバンプ（５ａ）が電極導体（幻に電気的１機械的に
接続される。In the figure, (1) is an insulating substrate made of ceramic material, etc.;
(3) is an insulating substrate (1), an electrode conductor (a solder dam screen-printed with a glass material to cover a predetermined area of the wound, and a solder dam with a thickness of 90 μm, and a solder dam with a thickness of 41 d (3
) solder bumps dip-soldered in the openings (8a) formed in
@ (s a ) is the bump that becomes the connection terminal,
This bump (5a) is electrically and mechanically connected to the electrode conductor (phantom).
オ１図において絶縁性基板１１］上に厚膜印刷によシ、
所定のパターンで電極導体（幻を形成する。Thick film printing is performed on the insulating substrate 11 in Figure 1.
Electrode conductors (form a phantom) in a predetermined pattern.
次に電極導体（！１上に形成される開口部（ｌ ａ）を
除く領域にガラス材を用いてスクリーン印刷し。Next, screen printing was performed using a glass material in the area excluding the opening (la) formed on the electrode conductor (!1).
はんだダム（３）を形成する。次にこのはんだダム（３
１が形成された絶縁性基板（１）をはんだディップ槽中
に浸漬し、はんだバンプ（４）を形成する。その後、プ
リップチップＩＣ（６）のバンプ（５ａ）の位置とはん
だバンプ（４１との位置合わせを行ないフリップチップ
ＩＣ（５）を絶縁性基板上に置く。Form a solder dam (3). Next, this solder dam (3
The insulating substrate (1) on which 1 is formed is immersed in a solder dip bath to form solder bumps (4). Thereafter, the positions of the bumps (5a) of the flip chip IC (6) and the solder bumps (41) are aligned, and the flip chip IC (5) is placed on the insulating substrate.
そしてこの絶縁性基板（１）をＳＳＯ℃のヒータブロッ
ク上に設置してはんだバンプ（４）を溶融し。Then, this insulating substrate (1) was placed on a heater block at SSO° C. to melt the solder bumps (4).
固化することによυプリップチップＩＣ（５）のバンプ
（５ａ ）と電極導体（２）との電気的接続がなされ、
フリップチップエＯｆｉｌ ｄ絶縁性基板（１１上に実
装固定される。By solidifying, an electrical connection is made between the bump (5a) of the υplip chip IC (5) and the electrode conductor (2),
The flip chip is mounted and fixed on an insulating substrate (11).
従来のガラス材を用いたスクリーン印刷法によるはんだ
ダム形成法では次のような欠点があった。The conventional method of forming solder dams by screen printing using a glass material has the following drawbacks.
１） スクリーン印刷時のガラス材の膜厚の不均一によ
シ、はんだディップ槽から引き上げた後のはんだバンプ
（４）の膜厚Ｃはんだ付着量）のばらつきが大きい。1) Due to the non-uniform film thickness of the glass material during screen printing, there is a large variation in the film thickness C (solder adhesion amount) of the solder bumps (4) after being lifted from the solder dip bath.
匂 微小な電気部品を実装例えば直径が０．１ ｗｘ〜
ｏｓｔｎｘの開口部（８ａ）を形成する場合、ガラス材
によるスクリーン印刷ではエツジ部の切れが悪くはんだ
バンプ（４）が精度よく形成されない。Implementing small electrical components, for example, diameter 0.1 wx~
When forming the openings (8a) of the ostnx, screen printing using a glass material does not cut the edges well and the solder bumps (4) cannot be formed with high precision.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、１−１んだダムの形成を従来のス
クリーン印刷法から感光性樹脂を用いた写真製版法に代
えると共にそのはんだダム開口部Ｋ１−１んだポールを
装填し。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it replaced the conventional screen printing method for forming a 1-1 solder dam with a photolithography method using a photosensitive resin, and also Load the pole into the dam opening K1-1.
それを溶融固化することにより、電気部品の実装歩留シ
の向上および倍額性の向上が図れる電気部品実装基板の
製造方法を提供することをその目的としている。The object of the present invention is to provide a method of manufacturing an electrical component mounting board that can improve the mounting yield of electrical components and increase the double cost by melting and solidifying it.
この発明の一実施例について説明する。第８図において
＋１１は絶縁性基板、（！１は絶縁性基板（１）上にパ
ターン形成された電極導体、−は電極導体（２）の所定
領域を榎うために施された膜厚５ Ｇ ４ａ程度の感光
性樹脂で構成されたはんだダム ■はこのはんだダム−
で形成された開口部（３０ａ）に装填されたはんだポー
ル、＋５１（ｄプリップチップＩＣであり、（５ａ）ｔ
ｊそのバンプである。An embodiment of this invention will be described. In Fig. 8, +11 is an insulating substrate, (!1 is an electrode conductor patterned on the insulating substrate (1), and - is a film thickness 5 applied to cover a predetermined area of the electrode conductor (2). Solder dam made of G 4a photosensitive resin ■This solder dam-
The solder pole loaded in the opening (30a) formed by +51(d) is a prep chip IC, and (5a)t
j That's the bump.
第２図において、絶縁性基板１１）上に厚膜印刷により
、所定のパターンで電極導体（２）を形成する。次に、
この絶縁性基板＋１１上全面に厚さ５０２℃程度の感光
性樹脂層Ｃソルダ・レジストフィルム）を１２０℃にて
ラミネートする。そして。In FIG. 2, electrode conductors (2) are formed in a predetermined pattern on an insulating substrate 11) by thick film printing. next,
A photosensitive resin layer C (solder resist film) having a thickness of about 502°C is laminated on the entire surface of this insulating substrate +11 at 120°C. and.
７ ＩＪップチツプエＯ＋５１の接続予定領域すなわち
バンプ（５ａ ）に対応する電極導体（２）上の感光性
樹脂層を除去して開口部（８０ａ）を形成するため、＊
光マスク（ポジフィルム）を絶縁性基板ＩＩＩ上に装荷
して８５秒程度露光する。7 To form an opening (80a) by removing the photosensitive resin layer on the electrode conductor (2) corresponding to the planned connection area of IJ chip O+51, that is, the bump (5a), *
A photomask (positive film) is loaded onto the insulating substrate III and exposed for about 85 seconds.
この露光後、露光マスクを取り除き絶縁性基板Ｉｌ＋を
現像、洗浄することにより、開口部（８０ａ ）を有す
るはんだダム−が形成される。次にはんだポール（転）
の装填治具を絶縁性基板＋１１上に形成された開口部（
３１０ａ）に合わせはんだポール働を装填し、不要はん
だポール−をふき取る。なお、この場合、／ｒ！んだフ
ラックスを用いてはんだポール輪を仮固定するようにし
てもよい。After this exposure, the exposure mask is removed and the insulating substrate Il+ is developed and cleaned, thereby forming a solder dam having an opening (80a). Next, solder pole (roll)
The loading jig is inserted into the opening formed on the insulating substrate +11 (
310a), load the solder pole function and wipe off the unnecessary solder poles. In this case, /r! The solder pole ring may be temporarily fixed using solder flux.
次にツリップチツプエＣ１５）のバンプ（５ａ）と開口
部（８０ａ）すなわちはんだポール員装填部との位置決
めをして７リツプチツプＩ Ｏ（Ｉｓｌを絶縁性基板（
１）上に置き、これをＳＳＯ℃程度のヒータブロック上
に載置し、はんだポール（至）を溶融させてフリップチ
ップＩＣ＋６１のバンプ（５ａ）を電極導体（！１に接
続する。Next, position the bump (5a) of the trip chip C15) and the opening (80a), that is, the solder pole member loading section, and attach the 7 lip chip IO (Isl) to the insulating substrate (
1) Place it on a heater block at about SSO°C, melt the solder pole (to), and connect the bump (5a) of the flip chip IC+61 to the electrode conductor (!1).
第８図はこの発明の他の実施例を示すものでで、上記実
施例では電極導体（２）の上に直接はんだポール−を装
填したのに対し、この実施例では電極導体（２）上には
んだペースト印刷法、はんだディッピング法などの手法
によシ予備はんだ■を形成して、はんだポール■と電極
導体（＝）とのはんだ慮れ性の改善、トータルはんだ量
ｔＢんだポール（至）と予備はんだ（ロ）との合計はん
だ量）の増加によるはんだ付の倍額性向上を図ったもの
である。FIG. 8 shows another embodiment of the present invention. In the above embodiment, the solder poles were directly mounted on the electrode conductor (2), whereas in this embodiment, the solder poles were mounted directly on the electrode conductor (2). Preliminary solder ■ is formed using methods such as solder paste printing and solder dipping to improve the solderability between the solder pole ■ and the electrode conductor (=), and to reduce the total solder amount tB solder pole (maximum). ) and preliminary solder (b), the total amount of solder) is increased to increase the cost of soldering.
なお、上記実施例ではろう材としてはんだポール−を用
いた場合について説明したが、その他のろう材、あるい
はその他の形状のものを用いても同様の効果を奏する。In the above embodiment, a case was explained in which a solder pole was used as the brazing material, but the same effect can be obtained by using other brazing materials or other shapes.
以上のように、この発明によれば、絶縁性基板およびそ
の基板上に形成された電極導体上に虞光性樹脂層により
所要パターンのけんだダムを形成し、そのはんだダム開
口部にはんだポールを装填して溶融固化することにより
、電気部品を電極導体に接続して基板上に実装するよう
にしたので、高密度で多数かつ微小の電気部品を生産性
良く実装できる効果がある。As described above, according to the present invention, a solder dam with a desired pattern is formed using a fluorescent resin layer on an insulating substrate and an electrode conductor formed on the substrate, and a solder dam is formed in the opening of the solder dam. By loading and melting and solidifying the electrical components, the electrical components are connected to the electrode conductors and mounted on the substrate, so it is possible to mount a large number of small electrical components with high density and with good productivity.
オ１図は従来の半導体素子実装基板を示す断四図、オ８
図はこの発明の一実施例による半導体素子実装基板を示
す断面図、オ８図はこの発明の他の実施例による半導体
素子実装基板を示す（断面図である。
図中、（１１は絶縁性基板、（２）け電極導体１国はは
んだダム、 （８０ａ７は開口部、■はけんだボール、
（財）は予備はんだである。
なお１図中、同一符号は同一、又は相当部分を示す。
第２図
りFigure O1 is a cut-away diagram showing a conventional semiconductor element mounting board.
The figure is a sectional view showing a semiconductor element mounting board according to one embodiment of the present invention, and Figure 8 shows a semiconductor element mounting board according to another embodiment of the present invention. Board, (2) solder electrode conductor 1, (80a7 is opening, ■ solder ball,
(Foundation) is preliminary solder. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts. Second plan
Claims (1)
形成する工程、上記感光性樹脂層を露光し、上記電極導
体上の電気部品接続予定領域に開口部を形成する工程、
上記開口部にろう材を装填し、それを溶融固化して上記
電気部品を上記電極導体に接続する工程、とを備えたこ
とを特徴とする電気部品実装基板の製造方法。 （２） ろう材を溶融固化する工程において、開口部
の電極導体上に予備はんだを施しておくことを特徴とす
る特許請求の範囲牙１項記載の電気部品実装基板の製造
方法。 （３； ろう材ははんだボールで構成されていること
を特徴とする特許請求の範囲オ１項あるいは第２項記載
の電気部品実装基板の製造方法。[Claims] 11) A step of forming an electrode conductor on an insulating substrate. forming a photosensitive resin layer covering the insulating substrate and the electrode conductor; exposing the photosensitive resin layer to form an opening in a region on the electrode conductor where electrical components are to be connected;
A method for manufacturing an electrical component mounting board, comprising the steps of: loading a brazing material into the opening, melting and solidifying the brazing material, and connecting the electrical component to the electrode conductor. (2) A method for manufacturing an electrical component mounting board according to claim 1, characterized in that in the step of melting and solidifying the brazing material, preliminary soldering is applied on the electrode conductor in the opening. (3) The method for manufacturing an electrical component mounting board according to claim 1 or 2, wherein the brazing material is composed of solder balls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199782A JPS58148434A (en) | 1982-02-26 | 1982-02-26 | Manufacture of electric parts mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199782A JPS58148434A (en) | 1982-02-26 | 1982-02-26 | Manufacture of electric parts mounting substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58148434A true JPS58148434A (en) | 1983-09-03 |
Family
ID=12346544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3199782A Pending JPS58148434A (en) | 1982-02-26 | 1982-02-26 | Manufacture of electric parts mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58148434A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126818A (en) * | 1987-05-26 | 1992-06-30 | Matsushita Electric Works, Ltd. | Semiconductor device |
| EP0522563A3 (en) * | 1991-07-12 | 1994-06-08 | Sumitomo Electric Industries | Semiconductor chip module and method of manufacturing the same |
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5478778A (en) * | 1991-08-30 | 1995-12-26 | Nec Corporation | Method of manufacturing a compact optical semiconductor module capable of being readily assembled with a high precision |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| WO1999000842A1 (en) * | 1997-06-26 | 1999-01-07 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
| EP0896427A3 (en) * | 1997-08-05 | 2001-01-10 | Nec Corporation | Surface acoustic wave device |
| WO2004093183A1 (en) * | 1995-03-17 | 2004-10-28 | Atsushi Hino | Film carrier and semiconductor device using the same |
| US7288437B2 (en) | 1986-12-24 | 2007-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Conductive pattern producing method and its applications |
| WO2010052942A1 (en) * | 2008-11-06 | 2010-05-14 | イビデン株式会社 | Wiring board with built-in electronic component and method for manufacturing the wiring board |
| CN106842647A (en) * | 2017-03-20 | 2017-06-13 | 武汉华星光电技术有限公司 | A kind of display device, binding structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52115176A (en) * | 1976-03-24 | 1977-09-27 | Hitachi Ltd | Ball soldering method |
| JPS5378953A (en) * | 1976-12-23 | 1978-07-12 | Tokyo Shibaura Electric Co | Solder supplying method to integrated circuit board |
-
1982
- 1982-02-26 JP JP3199782A patent/JPS58148434A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52115176A (en) * | 1976-03-24 | 1977-09-27 | Hitachi Ltd | Ball soldering method |
| JPS5378953A (en) * | 1976-12-23 | 1978-07-12 | Tokyo Shibaura Electric Co | Solder supplying method to integrated circuit board |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7288437B2 (en) | 1986-12-24 | 2007-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Conductive pattern producing method and its applications |
| US5126818A (en) * | 1987-05-26 | 1992-06-30 | Matsushita Electric Works, Ltd. | Semiconductor device |
| EP0522563A3 (en) * | 1991-07-12 | 1994-06-08 | Sumitomo Electric Industries | Semiconductor chip module and method of manufacturing the same |
| US5525548A (en) * | 1991-07-12 | 1996-06-11 | Sumitomo Electric Industries, Ltd. | Process of fixing a heat sink to a semiconductor chip and package cap |
| US5478778A (en) * | 1991-08-30 | 1995-12-26 | Nec Corporation | Method of manufacturing a compact optical semiconductor module capable of being readily assembled with a high precision |
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| WO2004093183A1 (en) * | 1995-03-17 | 2004-10-28 | Atsushi Hino | Film carrier and semiconductor device using the same |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
| WO1999000842A1 (en) * | 1997-06-26 | 1999-01-07 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
| US6281450B1 (en) | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
| EP0896427A3 (en) * | 1997-08-05 | 2001-01-10 | Nec Corporation | Surface acoustic wave device |
| WO2010052942A1 (en) * | 2008-11-06 | 2010-05-14 | イビデン株式会社 | Wiring board with built-in electronic component and method for manufacturing the wiring board |
| JPWO2010052942A1 (en) * | 2008-11-06 | 2012-04-05 | イビデン株式会社 | Electronic component built-in wiring board and manufacturing method thereof |
| CN106842647A (en) * | 2017-03-20 | 2017-06-13 | 武汉华星光电技术有限公司 | A kind of display device, binding structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100780829B1 (en) | Bga type semiconductor device, tape carrier for semiconductor device, and semiconductor device using said tape carrier | |
| JPH10125685A (en) | Projection electrode and method for forming the same | |
| JPH05243714A (en) | Film wiring board and manufacturing method thereof | |
| EP0145862B1 (en) | Metallization of a ceramic substrate | |
| US5034345A (en) | Method of fabricating a bump electrode for an integrated circuit device | |
| JPS58148434A (en) | Manufacture of electric parts mounting substrate | |
| JPH05198716A (en) | Manufacture of lead frame | |
| JPH053183A (en) | Semiconductor device and manufacture thereof | |
| JP3568869B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| US3767397A (en) | Photographic treatment for semiconductor devices or the like | |
| JPH11354591A (en) | Semiconductor carrier and its manufacture | |
| KR100459361B1 (en) | Magnetoelectric Transducer and Method for Producing the Same | |
| TW201826480A (en) | Lead frame | |
| JP3084648B2 (en) | Semiconductor device | |
| JPH0410235B2 (en) | ||
| JPH05315732A (en) | Manufacture of wiring board | |
| JP2001077142A (en) | Semiconductor device and manufacturing method thereof | |
| JP2980402B2 (en) | Manufacturing method of intermediate board for mounting circuit parts | |
| JP3877691B2 (en) | Semiconductor device | |
| JP2921179B2 (en) | Flip chip mounting method | |
| JPH02232947A (en) | Semiconductor integrated circuit device and mounting thereof | |
| KR100294910B1 (en) | A bump grid array package and a method of manufacturing the same | |
| JPH09266369A (en) | Printed circuit board and its processing | |
| JPH01238044A (en) | Semiconductor device | |
| JPH0955448A (en) | Manufacture of semiconductor device |