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JP3084648B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3084648B2
JP3084648B2 JP06223524A JP22352494A JP3084648B2 JP 3084648 B2 JP3084648 B2 JP 3084648B2 JP 06223524 A JP06223524 A JP 06223524A JP 22352494 A JP22352494 A JP 22352494A JP 3084648 B2 JP3084648 B2 JP 3084648B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
conductor pattern
chip mounting
mounting portion
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP06223524A
Other languages
Japanese (ja)
Other versions
JPH0888295A (en
Inventor
淳 福井
高士 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP06223524A priority Critical patent/JP3084648B2/en
Publication of JPH0888295A publication Critical patent/JPH0888295A/en
Application granted granted Critical
Publication of JP3084648B2 publication Critical patent/JP3084648B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To obtain a semiconductor device which is easily surface mounted and has high heat dissipation properties by using a conductor pattern at the center of a TAB board as a semiconductor chip placing part, providing an opening in a chip placing area in an insulating tape, exposing the conductor pattern, and integrally supporting the placing part and the periphery with the end of a lead. CONSTITUTION: A solder ball 5 protrudes from the contact hole of an insulating film 13 so formed as to cover the lead 1b of the peripheral edge of a TAB board, and further a conductor pattern disposed at the center of the board is remained as a semiconductor chip placing part 1a. Further, the insulating tape of the board has an opening at the chip placing area as well, the pattern is exposed, and the peripheral edge of the part 1a and the end of the lead are integrally supported except the bonding area of a lead 1b. In this case, a hole 7b is formed at the bonding area of the tape. Thus, the surface mounting is facilitated, and heat dissipation properties can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に係り、特
に、ＳＢＣ（ソルダボールコネクト）法を用いた半導体
装置の実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to mounting of a semiconductor device using an SBC (solder ball connect) method.

【０００２】[0002]

【従来の技術】ＩＣ、ＬＳＩ等の半導体装置は、実装基
板上の回路パターンに半田等を用いて接続されている。
近年、素子の微細化および装置の小型化に対応して、Ｓ
ＢＣ法と指称される、半田ボールを用いて回路基板上に
半導体パッケージを接続する方法が提案されている。こ
の方法は、実装基板上の回路パターンに半田ボールの位
置決めを行い、載置して加熱固着せしめればよく、実装
が容易であることから、注目されている方法である。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are connected to circuit patterns on a mounting board by using solder or the like.
In recent years, in response to miniaturization of elements and miniaturization of devices, S
A method called a BC method for connecting a semiconductor package on a circuit board using a solder ball has been proposed. This method has attracted attention because solder balls can be positioned on a circuit pattern on a mounting board, placed and fixed by heating, and mounting is easy.

【０００３】この一例として、図６に示すように、スル
ーホールを有し、両面に回路パターンの形成されたＰＣ
Ｂ基板１０１上に半導体チップ１０２を搭載し、ワイヤ
１０３によって電気的接続を行うとともに、該ＰＣＢ基
板１０１の裏面側にソルダーボール１０４を配設し、表
面側を封止樹脂１０５によって封止してなるいわゆるＰ
ＢＧＡ（Plastic Ball Grid Aray）方式がある。As an example of this, as shown in FIG. 6, a PC having a through hole and having a circuit pattern formed on both surfaces is provided.
A semiconductor chip 102 is mounted on a B substrate 101, and electrical connection is made by wires 103. Solder balls 104 are provided on the back side of the PCB substrate 101, and the front side is sealed with a sealing resin 105. So-called P
There is a BGA (Plastic Ball Grid Aray) system.

【０００４】また、他の例として、図７に示すように両
面に回路パターンの形成されたＴＡＢテープ２０１上に
フェイスダウンで半導体チップ２０２を接続し、この周
囲に金属板からなる支持体２０３を接着剤を介して固着
するとともに、このＴＡＢテープ２０１に形成されたコ
ンタクトホールＨを介して裏面にソルダーボール２０４
を配設し、表面側を封止樹脂２０５によって封止してな
るいわゆるＴＢＧＡ（Tape Ball Grid Aray ）方式があ
る。As another example, as shown in FIG. 7, a semiconductor chip 202 is connected face-down on a TAB tape 201 having a circuit pattern formed on both sides, and a support 203 made of a metal plate is provided around the semiconductor chip 202. It is fixed with an adhesive and solder balls 204 are formed on the back surface through contact holes H formed in the TAB tape 201.
And a so-called TBGA (Tape Ball Grid Aray) system in which the surface side is sealed with a sealing resin 205.

【０００５】しかしながら、ＴＢＧＡ方式では、両面に
回路パターンの形成されたＰＣＢ基板あるいはＴＡＢ基
板を用いているため、コストが高いという問題があっ
た。また、チップとの接続はＣ4 テクノロジーを使用し
ており、特殊な接続技術を要する。またパワーＩＣのよ
うに大電流を流すデバイスを実装する場合に、十分な放
熱性を得ることができないという問題があった。However, the TBGA method has a problem that the cost is high because a PCB substrate or a TAB substrate having circuit patterns formed on both sides is used. The connection to the chip uses C4 technology and requires special connection technology. In addition, when mounting a device that flows a large current such as a power IC, there is a problem that sufficient heat dissipation cannot be obtained.

【０００６】[0006]

【発明が解決しようとする課題】上述したように、従来
の方法では、コストが高くまた、特殊な接続技術を要す
るという問題があった。As described above, the conventional method has problems that the cost is high and a special connection technique is required.

【０００７】本発明は、前記実情に鑑みてなされたもの
で、低コストで、かつ放熱性が良好で、特殊な組み立て
技術を要することなく、実装が容易で信頼性の高い半導
体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and provides a semiconductor device which is inexpensive, has good heat radiation properties, requires no special assembly technology, is easy to mount, and has high reliability. The purpose is to:

【０００８】[0008]

【課題を解決するための手段】本発明の半導体装置の特
徴は、半導体チップ搭載部と、前記半導体チップ搭載部
から所定の間隔を隔てて放射状に伸長する複数のリード
とから構成される導体パターンと、前記半導体チップ搭
載部のチップ搭載領域に開口を有し、前記複数のリード
のボンディング領域を除く領域に貼着された絶縁性テー
プと、前記導体パターンの半導体チップ搭載部に接合せ
しめられ、前記ボンディング領域で前記リードに電気的
に接続された半導体チップと、前記半導体チップおよび
前記導体パターンを覆うように、前記絶縁性テープ面側
に形成された樹脂封止容器と、前記導体パターンを担持
した絶縁性テープの半導体チップ搭載部を除く領域を被
覆する絶縁部材と、前記絶縁部材に形成された孔を介し
て前記リードに接続せしめられ、前記絶縁部材の裏面側
に突出せしめられた半田ボールとを具備したことにあ
る。A semiconductor device according to the present invention is characterized in that a conductor pattern comprising a semiconductor chip mounting portion and a plurality of leads radially extending from the semiconductor chip mounting portion at predetermined intervals. Having an opening in a chip mounting region of the semiconductor chip mounting portion, an insulating tape attached to a region other than the bonding region of the plurality of leads, and bonded to the semiconductor chip mounting portion of the conductor pattern, A semiconductor chip electrically connected to the leads in the bonding area, a resin sealing container formed on the insulating tape side so as to cover the semiconductor chip and the conductor pattern, and carrying the conductor pattern. An insulating member covering an area excluding a semiconductor chip mounting portion of the insulating tape, and a lead connected to the lead through a hole formed in the insulating member. Allowed is, lies in the and a solder ball which is caused to protruded from the back surface of the insulating member.

【０００９】[0009]

【作用】本発明は、ＴＡＢ基板の中心部に位置する導体
パターンを半導体チップ搭載部として残すようにしさら
に、絶縁性テープが、チップ搭載領域に開口を有し、該
導体パターンを露呈せしめるようにするとともに、リー
ドのボンディング領域を除いて、半導体チップ搭載部の
周縁部とリードの先端部とを一体的に支持するようにし
たことを特徴とし、面実装が容易で、放熱性の高い半導
体装置を提供するものである。本発明によれば、半導体
チップ裏面に導体パターンが接合され裏面側に露呈して
おり、放熱性が極めて良好である。またこの半導体チッ
プ搭載部の導体パターンと、リード部を構成する導体パ
ターンとが絶縁性テープにより、電気的に絶縁されかつ
一体的に固着されており、変形が防止され支持強度も高
いものとなっている。またこの半導体チップ搭載部を構
成する導体（パターン）とリードを構成する導体パター
ンとは絶縁性テープに貼着した状態でパターニングする
ことにより、容易にかつ位置ずれもなく形成することが
でき、製造が極めて容易である上、微細化に際しても信
頼性の高いものである。According to the present invention, a conductor pattern located at the center of a TAB substrate is left as a semiconductor chip mounting portion. Further, the insulating tape has an opening in a chip mounting region to expose the conductor pattern. The semiconductor device is characterized in that the peripheral portion of the semiconductor chip mounting portion and the tip of the lead are integrally supported except for the bonding region of the lead, and the surface mounting is easy and the heat dissipation is high. Is provided. According to the present invention, the conductor pattern is bonded to the back surface of the semiconductor chip and is exposed on the back surface side, and the heat dissipation is extremely good. In addition, the conductor pattern of the semiconductor chip mounting portion and the conductor pattern forming the lead portion are electrically insulated and integrally fixed by an insulating tape, so that deformation is prevented and support strength is high. ing. Further, by patterning the conductor (pattern) constituting the semiconductor chip mounting portion and the conductor pattern constituting the lead in a state of being adhered to an insulating tape, the conductor pattern can be formed easily and without any positional displacement. Is extremely easy, and is highly reliable even when miniaturized.

【００１０】また、片面に導体パターンを形成したＴＡ
Ｂ基板の裏面側から、この基板に設けられた孔内に半田
ボールを固着するようにしているため、極めて高精度で
微細な半田ボールの形成が可能となり、パッドピッチを
微細化することが可能となる。望ましくはここで半田ボ
ールの形成に先だち、孔内にフラックス層を形成し、こ
のフラックス層上に半田ボールを供給し加熱することに
より、コンタクトホール内に露呈する導体パターンと固
溶状態になり、半田ボールはコンタクトホール内にのみ
選択性よく、良好に固着せしめられる。そして最後に、
余剰のフラックスを除去する工程を付加するようにして
もよい。このようにして高精度の半田ボールの形成が可
能となる。Further, a TA having a conductor pattern formed on one side is provided.
Since the solder balls are fixed from the back side of the B substrate into the holes provided in this substrate, it is possible to form extremely high-precision and fine solder balls and to make the pad pitch finer. Becomes Desirably, prior to the formation of the solder ball, a flux layer is formed in the hole, and the solder ball is supplied and heated on the flux layer to be in a solid solution state with the conductor pattern exposed in the contact hole, Solder balls can be satisfactorily fixed only in the contact holes with good selectivity. And finally,
A step of removing excess flux may be added. In this way, it is possible to form a solder ball with high precision.

【００１１】また上記半導体装置の製造に際しては、樹
脂封止した後、ＴＡＢ基板の裏面側に、孔を介して表面
側の前記導体パターンに接続するように半田ボールを配
設すれば、生産性が大幅に向上しかつ信頼性の高い半導
体装置を得ることが可能となる。In the manufacture of the above-mentioned semiconductor device, after encapsulating with a resin, a solder ball is provided on the back surface of the TAB substrate so as to be connected to the conductor pattern on the front surface via a hole, thereby improving productivity. Is significantly improved, and a highly reliable semiconductor device can be obtained.

【００１２】このように、本発明によれば、片面に導体
パターンを形成した絶縁性テープすなわちＴＡＢ基板を
用いて実装しているため、表面と裏面のパターンのマス
ク合わせの必要もなくまた、スルーホールめっきも不要
であり、絶縁膜または絶縁性テープに形成した孔に半田
ボールを配置し、加熱等により導体パターン表面に固着
するのみでよく、さらには通常の樹脂封止を行えばよい
ため、スティフナーとしての金属板も不要であり、従来
の装置をそのまま使用することができ、生産性も高く製
造が容易かつ高精度で安価である。As described above, according to the present invention, since mounting is performed using an insulating tape having a conductor pattern formed on one surface, that is, a TAB substrate, there is no need to align the masks on the front and rear surfaces, and the through-hole is not required. Hole plating is also unnecessary, since it is only necessary to arrange solder balls in the holes formed in the insulating film or insulating tape and fix them to the surface of the conductor pattern by heating or the like, and furthermore, it is only necessary to perform normal resin sealing, A metal plate as a stiffener is not necessary, and a conventional apparatus can be used as it is, and the productivity is high, the production is easy, the precision is high, and the cost is low.

【００１３】[0013]

【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００１４】本発明の第１の実施例の半導体装置は図１
乃至図３（図２は、図１の上面図（封止樹脂については
省略）、図３は図１の下面図（裏面図））に示すよう
に、ＴＡＢ基板Ｔの周縁部のリード１ｂを覆うように形
成した絶縁膜１３のコンタクト孔Ｈから半田ボール５を
突出せしめるとともに、さらにＴＡＢ基板の中心部に位
置する導体パターンを半導体チップ搭載部１ａとして残
すようにしさらに、このＴＡＢ基板Ｔの絶縁性テープ
も、チップ搭載領域に開口Ｏを有し、該導体パターンを
露呈せしめるようにするとともに、リード１ｂのボンデ
ィング領域を除いて、半導体チップ搭載部１ａの周縁部
とリードの先端部とを一体的に支持し、面実装を容易に
するとともに放熱性を向上させたことを特徴とする。こ
こで、絶縁性テープのボンディング領域には図４に示す
ように孔７ｂが形成されている。FIG. 1 shows a semiconductor device according to a first embodiment of the present invention.
As shown in FIG. 3 to FIG. 3 (FIG. 2 is a top view of FIG. 1 (the sealing resin is omitted), and FIG. 3 is a bottom view (back view) of FIG. The solder balls 5 are made to protrude from the contact holes H of the insulating film 13 formed so as to cover, and the conductor pattern located at the center of the TAB substrate is left as the semiconductor chip mounting portion 1a. The conductive tape also has an opening O in the chip mounting area so that the conductive pattern is exposed, and the periphery of the semiconductor chip mounting portion 1a and the tip of the lead are integrated except for the bonding area of the lead 1b. It is characterized in that it is supported in a simple manner, facilitates surface mounting and improves heat dissipation. Here, a hole 7b is formed in the bonding region of the insulating tape as shown in FIG.

【００１５】すなわち、半導体チップ搭載部１ａと、前
記半導体チップ搭載部１ａから所定の間隔を隔てて放射
状に伸長する複数のリード１ｂとから構成される導体パ
ターン１と、前記複数のリード１ｂのボンディング領域
を除く領域に貼着されこれらを一体的に支持するととも
にさらにリード１ｂの先端から前記半導体チップ搭載部
の周縁部にかけて貼着されこれらを一体的に支持する絶
縁性テープ２と、前記導体パターン１の半導体チップ搭
載部１ａに、導電性接着剤１２を介して接合せしめら
れ、前記ボンディング領域に一端を接続されたボンディ
ングワイヤ７を介して前記リード１ｂに電気的に接続さ
れた半導体チップ３と、前記半導体チップ３および前記
導体パターン１を覆うように前記絶縁性テープ２面側に
形成されたエポキシ樹脂からなる樹脂封止容器８と、前
記導体パターンを担持した絶縁性テープ２の半導体チッ
プ搭載部１ａを除く領域を被覆するポリイミド膜等から
なる絶縁膜１３と、前記絶縁膜１３に形成されたコンタ
クト孔Ｈを介して前記リード１ｂに接続せしめられ、前
記絶縁膜１３の裏面側に突出せしめられた半田ボール５
とを具備したことを特徴とする。That is, a conductor pattern 1 composed of a semiconductor chip mounting portion 1a, a plurality of leads 1b extending radially from the semiconductor chip mounting portion 1a at a predetermined interval, and bonding of the plurality of leads 1b. An insulating tape 2 attached to a region excluding the region and integrally supporting them, and further attached from the tip of the lead 1b to a peripheral portion of the semiconductor chip mounting portion to integrally support them; 1 and a semiconductor chip 3 which is bonded to the semiconductor chip mounting portion 1a via a conductive adhesive 12 and is electrically connected to the lead 1b via a bonding wire 7 having one end connected to the bonding region. Epoxy formed on the surface of the insulating tape 2 so as to cover the semiconductor chip 3 and the conductor pattern 1 A resin sealing container 8 made of a resin, an insulating film 13 made of a polyimide film or the like covering an area excluding the semiconductor chip mounting portion 1a of the insulating tape 2 carrying the conductor pattern, and the insulating film 13 The solder ball 5 connected to the lead 1b through the contact hole H and protruding from the back surface of the insulating film 13
And characterized in that:

【００１６】この半導体装置の製造方法について説明す
る。A method for manufacturing the semiconductor device will be described.

【００１７】まず、図５(a) に示すような、膜厚７５μ
m のポリイミド樹脂からなる絶縁性テープ２に、図５
(b) に示すように、デバイスホールとなる開口Ｏを形成
するとともに、ボンディング領域に対応して孔７ｂを形
成する（図４参照）。ここで６は接着剤層である。First, as shown in FIG.
5 m on an insulating tape 2 made of polyimide resin.
As shown in (b), an opening O serving as a device hole is formed, and a hole 7b is formed corresponding to the bonding region (see FIG. 4). Here, reference numeral 6 denotes an adhesive layer.

【００１８】次いで、図５(c) に示すようにこの絶縁性
テープに厚さ３５μm の銅箔を貼着し、この銅箔をフォ
トリソグラフィによりパターニングし、半導体チップ搭
載部１ａとリード１ｂとからなるパターンを形成する。
このパターンに、図５(d) に示すように膜厚０．５μm
ニッケルめっき層および膜厚０．５μm の金めっき層を
形成し、導体パターン１を有するＴＡＢ基板を構成す
る。このとき導体パターン１は孔Ｈ内に露呈しているた
めこの領域ではＣｕの両面にＮｉ層（図示せず）および
Ａｕ層の形成された５層構造となっている。Next, as shown in FIG. 5 (c), a copper foil having a thickness of 35 μm is adhered to the insulating tape, and the copper foil is patterned by photolithography so that the semiconductor chip mounting portion 1a and the lead 1b are separated from each other. Is formed.
This pattern has a thickness of 0.5 μm as shown in FIG.
A nickel plating layer and a gold plating layer having a thickness of 0.5 μm are formed to form a TAB substrate having the conductor pattern 1. At this time, since the conductor pattern 1 is exposed in the hole H, this region has a five-layer structure in which a Ni layer (not shown) and an Au layer are formed on both surfaces of Cu.

【００１９】そして、このＴＡＢ基板を支持台で支持し
つつ半導体チップ３をこの導体パターン１上に位置決め
し、導電性接着剤１２を介して固着した後、ボンディン
グワイヤ７を用いてワイヤボンディングを行う。そして
表面全体を樹脂封止する。Then, the semiconductor chip 3 is positioned on the conductive pattern 1 while supporting the TAB substrate on a support table, and is fixed via a conductive adhesive 12, and then wire bonding is performed using the bonding wires 7. . Then, the entire surface is sealed with resin.

【００２０】この後、封止容器側を下にして支持し、図
５(e) に示すように、ポリイミド膜からなる絶縁膜１３
を形成するとともにこの絶縁膜にコンタクト孔Ｈを形成
して、コンタクト孔Ｈ内にフラックスを印刷し、Ｐｂ１
０％、Ｓｎ９０％の半田からなる直径０．７mmの半田ボ
ール５を供給し、３２０℃１０秒間（ピーク温度維持時
間）の加熱工程を経て、表面をリード１ｂに固着する。Thereafter, the support is held with the sealed container side down, and as shown in FIG.
And a contact hole H is formed in the insulating film, and a flux is printed in the contact hole H to form Pb1.
A solder ball 5 made of 0% and 90% Sn solder and having a diameter of 0.7 mm is supplied, and the surface is fixed to the lead 1b through a heating process at 320 ° C. for 10 seconds (peak temperature maintaining time).

【００２１】そして最後に必要に応じて、洗浄を行い、
余剰のフラックスを除去し、図１乃至３に示した半導体
装置が完成する。[0021] Finally, if necessary, washing is performed.
Excess flux is removed, and the semiconductor device shown in FIGS. 1 to 3 is completed.

【００２２】かかる構造によれば、面実装が極めて容易
でかつ、半導体チップの裏面側からの放熱が極めて良好
である。According to this structure, surface mounting is extremely easy, and heat radiation from the back side of the semiconductor chip is extremely good.

【００２３】なお、ここで絶縁性テープとして、あらか
じめ孔を形成しておき、銅箔を貼着してこの銅箔をパタ
ーニングするようにしたが、銅箔のパターニング後フォ
トリソグラフィにより孔を形成するようにしてもよい。Here, a hole is formed in advance as an insulating tape, and a copper foil is adhered and the copper foil is patterned. However, after the copper foil is patterned, a hole is formed by photolithography. You may do so.

【００２４】また、孔ピッチや孔径は前記実施例に限定
されることなく適宜変形可能であり、例えば格子ピッチ
が１mmであれば、孔径は０．５５mm、格子ピッチが１．
５mmであれば、孔径は０．７５mmというように適宜変更
可能である。Further, the hole pitch and the hole diameter are not limited to those in the above-described embodiment, but can be appropriately changed. For example, if the lattice pitch is 1 mm, the hole diameter is 0.55 mm and the lattice pitch is 1.
If it is 5 mm, the hole diameter can be appropriately changed to 0.75 mm.

【００２５】さらに半田ボールの組成についても適宜選
択可能であり、例えばＰｂ３７％Ｓｎ６３％の共晶半田
を用いた場合には固着工程での加熱温度は２３０℃程度
でよい。Further, the composition of the solder ball can be appropriately selected. For example, when eutectic solder of Pb 37% Sn 63% is used, the heating temperature in the fixing step may be about 230 ° C.

【００２６】また、絶縁膜１３にコンタクト孔Ｈを形成
する方法としては、パターン印刷法あるいは、ソルダー
レジストなどの感光性樹脂膜を塗布し、パターン露光を
行う方法など適宜変更可能である。The method of forming the contact holes H in the insulating film 13 can be changed as appropriate, such as a pattern printing method or a method of applying a photosensitive resin film such as a solder resist and performing pattern exposure.

【００２７】[0027]

【発明の効果】以上説明してきたように、本発明によれ
ば、低コスト化および信頼性の向上をはかることが可能
となる。As described above, according to the present invention, it is possible to reduce the cost and improve the reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明実施例の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

【図２】本発明実施例の半導体装置を示す図FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention;

【図３】本発明実施例の半導体装置を示す図FIG. 3 is a diagram showing a semiconductor device according to an embodiment of the present invention;

【図４】同実施例の半導体装置で用いられる絶縁性テー
プを示す図FIG. 4 is a view showing an insulating tape used in the semiconductor device of the embodiment.

【図５】同半導体装置の製造工程を示す図FIG. 5 is a view showing a manufacturing process of the semiconductor device.

【図６】従来例の半導体装置を示す図FIG. 6 is a diagram showing a conventional semiconductor device.

【図７】従来例の半導体装置を示す図FIG. 7 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 導体パターン １ａ 半導体チップ搭載部 １ｂ リード ２ 絶縁性チップ ３ 半導体チップ ４ 金属基板 ５ 半田ボール ６ 絶縁性接着剤 ７ ボンディングワイヤ ７ｂ 孔 ８ 封止樹脂 ９ バンプ １０ 基板 １０１ ＰＣＢ基板 １０２ 半導体チップ １０３ ワイヤ １０４ ソルダーボール １０５ 封止樹脂 ２０１ ＴＡＢテープ ２０２ 半導体チップ ２０３ 支持体 ２０４ ソルダーボール ２０５ 封止樹脂 Reference Signs List 1 conductor pattern 1a semiconductor chip mounting portion 1b lead 2 insulating chip 3 semiconductor chip 4 metal substrate 5 solder ball 6 insulating adhesive 7 bonding wire 7b hole 8 sealing resin 9 bump 10 substrate 101 PCB substrate 102 semiconductor chip 103 wire 104 Solder ball 105 Sealing resin 201 TAB tape 202 Semiconductor chip 203 Support 204 Solder ball 205 Sealing resin

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 311 H01L 23/02 H01L 23/50 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60 311 H01L 23/02 H01L 23/50

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップ搭載部と、前記半導体チッ
プ搭載部から所定の間隔を隔てて放射状に伸長する複数
のリードとから構成される導体パターンと、 前記半導体チップ搭載部のチップ搭載領域に開口を有
し、前記複数のリードのボンディング領域を除く領域に
貼着された絶縁性テープと、 前記導体パターンの半導体チップ搭載部に接合せしめら
れ、前記ボンディング領域で前記リードに電気的に接続
された半導体チップと、 前記半導体チップおよび前記導体パターンを覆うよう
に、前記絶縁性テープ面側に形成された樹脂封止容器
と、 前記導体パターンを担持した絶縁性テープの半導体チッ
プ搭載部を除く領域を被覆する絶縁部材と、 前記絶縁部材に形成された孔を介して前記リードに接続
せしめられ、前記絶縁部材の裏面側に突出せしめられた
半田ボールとを具備したことを特徴とする半導体装置。A conductor pattern comprising a semiconductor chip mounting portion, a plurality of leads radially extending at a predetermined interval from the semiconductor chip mounting portion, and an opening in a chip mounting region of the semiconductor chip mounting portion. An insulating tape attached to a region except for a bonding region of the plurality of leads; and an adhesive tape bonded to a semiconductor chip mounting portion of the conductor pattern, and electrically connected to the leads in the bonding region. A semiconductor chip, a resin sealing container formed on the insulating tape surface side so as to cover the semiconductor chip and the conductor pattern, and an area excluding a semiconductor chip mounting portion of the insulating tape carrying the conductor pattern. An insulating member to be covered, connected to the lead via a hole formed in the insulating member, and protruding from a back surface side of the insulating member. The semiconductor device is characterized in that; and a crimped solder balls.
JP06223524A 1994-09-19 1994-09-19 Semiconductor device Expired - Lifetime JP3084648B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06223524A JP3084648B2 (en) 1994-09-19 1994-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06223524A JP3084648B2 (en) 1994-09-19 1994-09-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0888295A JPH0888295A (en) 1996-04-02
JP3084648B2 true JP3084648B2 (en) 2000-09-04

Family

ID=16799499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06223524A Expired - Lifetime JP3084648B2 (en) 1994-09-19 1994-09-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3084648B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100209259B1 (en) * 1996-04-25 1999-07-15 이해규 Ic card and method for manufacture of the same
SG71046A1 (en) 1996-10-10 2000-03-21 Connector Systems Tech Nv High density connector and method of manufacture
KR100251860B1 (en) * 1996-12-06 2000-04-15 김규현 Structure of csp and its making method
KR100292033B1 (en) * 1998-05-13 2001-07-12 윤종용 Semiconductor chip package and method for manufacturing same
US7772107B2 (en) * 2006-10-03 2010-08-10 Sandisk Corporation Methods of forming a single layer substrate for high capacity memory cards

Also Published As

Publication number Publication date
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