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US20020052056A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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Publication number
US20020052056A1
US20020052056A1 US09/983,524 US98352401A US2002052056A1 US 20020052056 A1 US20020052056 A1 US 20020052056A1 US 98352401 A US98352401 A US 98352401A US 2002052056 A1 US2002052056 A1 US 2002052056A1
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US
United States
Prior art keywords
wiring substrate
wiring
electrode
semiconductor device
process step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/983,524
Inventor
Masanori Minamio
Hiroaki Fujimoto
Ryuichi Sahara
Toshiyuki Fukuda
Toru Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJIMOTO, HIROAKI, FUKUDA, TOSHIYUKI, MINAMIO, MASANORI, NOMURA, TORU, SAHARA, RYUICHI
Publication of US20020052056A1 publication Critical patent/US20020052056A1/en
Priority to US10/152,725 priority Critical patent/US6680220B2/en
Abandoned legal-status Critical Current

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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Definitions

  • the present invention relates to a single-side-molded semiconductor device, which includes a wiring substrate having a ball grid array (BGA) arranged on the lower surface and a semiconductor chip molded with a resin encapsulant on the upper surface.
  • BGA ball grid array
  • the present invention also relates to a method for fabricating the device.
  • a semiconductor device of the BGA type has been available as a semiconductor device of an area array type.
  • a semiconductor chip is mounted and molded with a resin encapsulant on the upper surface of a substrate, and ball electrodes are attached to the lower surface thereof.
  • FIG. 12 is a plan view illustrating a known semiconductor device of the BGA type.
  • FIG. 13 is a bottom view illustrating the known BGA type semiconductor device.
  • FIG. 14 is a cross-sectional view thereof taken along the line XIV-XIV in FIG. 12.
  • the known semiconductor device includes a wiring substrate 103 , wiring electrodes 101 , a semiconductor chip 104 , metal fine wires 105 , ball electrodes 102 and a resin encapsulant 106 .
  • the wiring substrate 103 is made of an insulating resin.
  • the wiring electrodes 101 are formed on the wiring substrate 103 .
  • the semiconductor chip 104 is mounted on the wiring substrate 103 with the principal surface of the semiconductor chip 104 facing upward. Electrode pads (not shown) formed on the semiconductor chip 104 and the wiring electrodes 101 are electrically connected to each other with the metal fine wires 105 .
  • the ball electrodes 102 are formed on the lower surface of the wiring substrate 103 .
  • the known semiconductor device has an approximately rectangular planar shape and the adjacent side faces thereof are perpendicular to each other.
  • the outer shape has been determined so that the fabrication process of the semiconductor device can be simplified.
  • marks 107 representing product name, product number, model number, manufacturer name, and symbol, for example, are inscribed on the upper surface of the resin encapsulant 106 by a laser marking process step.
  • FIGS. 15A and 15B are respectively a plan view and a bottom view illustrating a wiring substrate in the known semiconductor device.
  • FIGS. 16A and 16B are plan views illustrating a substrate preparation process step and a die bonding process step, respectively, in the fabrication process of the known semiconductor device.
  • FIGS. 17A and 17B are plan views illustrating a wire bonding process step and a resin molding process step, respectively, in the fabrication process of the known semiconductor device.
  • FIG. 18 is a plan view illustrating a cutting process step in the fabrication process of the known semiconductor device.
  • the multiple wiring electrodes 101 are formed on the upper surface of the wiring substrate, and external pad electrodes 107 are formed on the lower surface of the wiring substrate.
  • the external pad electrodes 107 are electrically connected to the wiring electrodes 101 through the substrate.
  • the ball electrodes will be attached to the external pad electrodes 107 in the subsequent process step.
  • the wiring substrate is a large-sized substrate on which multiple semiconductor chips will be mounted and which will be separated into individual semiconductor devices.
  • the broken lines shown in FIGS. 15A and 15B are cutting lines, which will be used to separate the substrate into the individual semiconductor devices.
  • a central area surrounded by each array of the wiring electrodes 101 is a chip mounting area where each of the semiconductor chips is mounted by bonding.
  • the wiring substrate with the structure shown in FIGS. 15A and 15B is prepared in the substrate preparation process step shown in FIG. 16A.
  • each of the semiconductor chips 104 is bonded, with an adhesive, onto each of the chip mounting areas of the wiring substrate in the die bonding process step shown in FIG. 16B.
  • the electrode pads (not shown) formed on the principal surface of each of the semiconductor chips 104 and their associate wiring electrodes 101 formed on the wiring substrate are electrically connected to each other with the metal fine wires 105 in the wire bonding process step shown in FIG. 17A.
  • the members disposed on the upper surface of the wiring substrate e.g., the semiconductor chips 104 , wiring electrodes 101 , metal fine wires 105
  • the resin encapsulant 106 is transfer-molded with the resin encapsulant 106 in the resin molding process step shown in FIG. 17B.
  • the marks 107 such as product name, product number, model number, manufacturer name, and symbol, for example, are inscribed on the upper surface of the resin encapsulant 106 for each of the semiconductor devices by a laser marker.
  • the wiring electrodes 101 and semiconductor chips 104 are indicated by the broken lines in FIG. 17B. However, the metal fine wires 105 are not shown in the figure.
  • the wiring substrate having the upper surface entirely molded with the resin encapsulant 106 is cut along the cutting lines using a rotary blade, thereby obtaining individual semiconductor devices 109 of the BGA type.
  • the semiconductor devices 109 with the structure shown in FIGS. 13 and 14 can be obtained.
  • the wiring substrate is cut, using the rotary blade, along the cutting lines indicated by the broken lines shown in FIGS. 15A and 15B.
  • the individual semiconductor devices can be obtained accurately.
  • the separation by the rotary blade is performed using a dicing machine used in the fabrication process of the semiconductor device.
  • the wiring substrate is cut from either the lower surface or the resin encapsulant 106 side thereof.
  • the marking process step is performed after the members disposed on the upper surface of the wiring substrate have been molded with the resin encapsulant 106 .
  • the marks are inscribed on the upper surface of the resin encapsulant 106 for each of the semiconductor devices by the laser marker in the process step shown in FIG. 17B.
  • An object of this invention is to provide 1) a semiconductor device of the BGA type, which is easy to handle and which can be fabricated at low cost, by taking measures to put highly visible marks on a large number of semiconductor devices by a single process step, and 2) a method for fabricating the device.
  • An inventive semiconductor device includes: a wiring substrate; a semiconductor chip; an electrode; a connecting member; a resin encapsulant; and a mark member.
  • the wiring substrate includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate.
  • the external electrode is to be electrically connected to the wiring electrode.
  • the semiconductor chip is mounted on the wiring substrate.
  • the electrode is formed on the semiconductor chip.
  • the connecting member is used to connect the electrode of the semiconductor chip and the wiring electrode on the wiring substrate electrically to each other.
  • the resin encapsulant molds the wiring substrate, the semiconductor chip, the connecting member and the wiring electrode.
  • the mark member is visible and is embedded in the upper surface of the resin encapsulant.
  • the mark member is embedded in the upper surface of the resin encapsulant.
  • the visibility of the mark increases.
  • the device preferably further includes a ball electrode which is attached to the external electrode of the wiring substrate.
  • An inventive method for fabricating a semiconductor device includes the step of a) preparing a wiring substrate, which includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate.
  • the external electrode is to be electrically connected to the wiring electrode.
  • the method further includes the step of b) mounting semiconductor chips on the wiring substrate.
  • the method further includes the step of c) connecting an electrode of each of the semiconductor chips and the wiring electrode on the wiring substrate electrically to each other with a connecting member.
  • the method further includes the step of d) disposing the wiring substrate on a face of one die of a molding die after the step c) has been performed; disposing a transfer sheet, on which a mark member has been formed, on a face of the other die of the molding die; and performing a resin molding process.
  • the method further includes the step of e) removing the transfer sheet and embedding the mark member in the upper surface of a resin encapsulant by transcription, after the step d) has been performed.
  • the mark is formed quickly by a single transfer method. Therefore, the fabrication cost can be reduced and the mark can be formed efficiently.
  • the wiring substrate in the step e), may be separated into individual semiconductor devices by using a rotary blade.
  • a ball electrode may be attached to the external electrode on the lower surface of the wiring substrate between the steps d) and e).
  • a semiconductor device of the BGA type can be fabricated easily.
  • the wiring substrate, on which the semiconductor chips can be mounted and which can be separated into individual semiconductor devices is preferably prepared.
  • a side of the transfer sheet may face the wiring substrate and the transfer sheet may be airtightly fixed on the face of the die of the molding die.
  • the side includes the mark member formed thereon.
  • the transfer sheet in the step d), preferably includes the mark member formed thereon that is visible and that can be separated from the transfer sheet.
  • FIG. 1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 2 is a bottom view illustrating the semiconductor device of the embodiment.
  • FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1, illustrating the semiconductor device of the embodiment.
  • FIGS. 4A, 4B and 4 C are respectively plan view, cross-sectional view taken along the line IVb-IVb, and bottom view illustrating a wiring substrate in accordance with the embodiment.
  • FIGS. 5A and 5B are respectively a plan view, and a cross-sectional view taken along the line IVb-IVb, illustrating a substrate preparation process step in the fabrication process of the semiconductor device of the embodiment.
  • FIGS. 6A and 6B are respectively a plan view, and a cross-sectional view taken along the line VIb-VIb, illustrating a die bonding process step in the fabrication process of the semiconductor device of the embodiment.
  • FIGS. 7A and 7B are respectively a plan view, and a cross-sectional view taken along the line VIIb-VIIb, illustrating a wire bonding process step in the fabrication process of the semiconductor device of the embodiment.
  • FIGS. 8A and 8B are respectively a plan view, and a cross-sectional view taken along the line XIIIb-XIIIb, illustrating a resin molding process step in the fabrication process of the semiconductor device of the embodiment.
  • FIGS. 9A and 9B are respectively a plan view, and a cross-sectional view taken along the line IXb-IXb, illustrating a cutting process step in the fabrication process of the semiconductor device of the embodiment.
  • FIG. 10 is a cross-sectional view illustrating an exemplary method for transferring mark members in the resin molding process step in the fabrication process of the semiconductor device of the embodiment.
  • FIG. 11 is a cross-sectional view illustrating another exemplary method for transferring the mark members in the resin molding process step in the fabrication process of the semiconductor device of the embodiment.
  • FIG. 12 is a plan view illustrating a known semiconductor device of the BGA type.
  • FIG. 13 is a bottom view illustrating the known BGA type semiconductor device.
  • FIG. 14 is a cross-sectional view thereof taken along the line XIV-XIV in FIG. 12.
  • FIGS. 15A and 15B are respectively a plan view and a bottom view illustrating a wiring substrate in the known semiconductor device.
  • FIGS. 16A and 16B are plan views illustrating a substrate preparation process step and a die bonding process step, respectively, in the fabrication process of the known semiconductor device.
  • FIGS. 17A and 17B are plan views illustrating a wire bonding process step and a resin molding process step, respectively, in the fabrication process of the known semiconductor device.
  • FIG. 18 is a plan view illustrating a cutting process step in the fabrication process of the known semiconductor device.
  • FIG. 1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 2 is a bottom view illustrating the semiconductor device of the embodiment.
  • FIG. 3 is a cross-sectional view thereof taken along the line III-III in FIG. 1.
  • the semiconductor device of this embodiment includes a wiring substrate 3 , wiring electrodes 1 , a semiconductor chip 4 , metal fine wires 5 , ball electrodes 2 and a resin encapsulant 6 .
  • the wiring substrate 3 is made of an insulating resin.
  • the wiring electrodes 1 are formed on the wiring substrate 3 .
  • the semiconductor chip 4 is mounted on the wiring substrate 3 . Electrode pads (not shown) formed on the principal surface of the semiconductor chip 4 and the wiring electrodes 1 are electrically connected to each other with the metal fine wires 5 .
  • the ball electrodes 2 are formed on the lower surface of the wiring substrate 3 .
  • the semiconductor chip 4 , wiring electrodes 1 , metal fine wires 5 and the like are molded with the resin encapsulant 6 on the upper surface of the wiring substrate 3 .
  • mark members 10 representing product name, product number, model number, manufacturer name, and symbol, for example, are embedded in the upper surface of the resin encapsulant 6 on the upper surface of the wiring substrate 3 .
  • the mark members 10 are, e.g., characters and symbols which are made of ink such as pigment or dyestuff, for example, or other easily visible materials.
  • external pad electrodes are formed on the lower surface of the wiring substrate 3 .
  • the external pad electrodes are electrically connected to the wiring electrodes 1 through the substrate.
  • the ball electrodes 2 are formed on the external pad electrodes.
  • the semiconductor device of this embodiment has the structure of a semiconductor device of the BGA type.
  • an integrated circuit on which e.g., a large number of transistors are disposed, is formed near the principal surface in the semiconductor chip.
  • electrode pads to be used for connection with outside units are also formed on wiring layers formed near the principal surface in the semiconductor chip.
  • one end of each of the metal fine wires 5 is connected to the associated one of the electrode pads on the semiconductor chip.
  • the mark members 10 are embedded in the upper surface of the resin encapsulant 6 .
  • the marks of the semiconductor device of this embodiment have higher visibility than those inscribed by a laser marking process.
  • the fabricating costs are lower as compared to the laser marking. This is to say, according to the semiconductor device of this embodiment, the marking visibility can be increased and the marking costs can be reduced as well.
  • FIGS. 7A and 7B are respectively a plan view, and a cross-sectional view taken along the line VIIb-VIIb, illustrating a wire bonding process step in the fabrication process of the semiconductor device of this embodiment.
  • FIGS. 8A and 8B are respectively a plan view, and a cross-sectional view taken along the line XIIIb-XIIIb, illustrating a resin molding process step in the fabrication process of the semiconductor device of this embodiment.
  • FIGS. 9A and 9B are respectively a plan view, and a cross-sectional view taken along the line IXb-IXb, illustrating a cutting process step in the fabrication process of the semiconductor device of this embodiment.
  • the multiple wiring electrodes 1 are formed on the upper surface of the wiring substrate, and external pad electrodes 7 are formed on the lower surface of the wiring substrate.
  • the external pad electrodes 7 are electrically connected to the wiring electrodes 1 through the substrate.
  • the ball electrodes will be attached to the external pad electrodes 7 in the subsequent process step.
  • the wiring substrate prepared is a large-sized substrate on which multiple semiconductor chips will be mounted and which will be later separated into individual semiconductor devices.
  • the broken lines shown in FIGS. 4A and 4C are cutting lines, which will be used to separate the substrate into the individual semiconductor devices.
  • a central area surrounded by the arrays of the wiring electrodes 1 is a chip mounting area where each of the semiconductor chips is mounted by bonding.
  • the wiring substrate with the structure shown in FIGS. 4A through 4C is prepared in the substrate preparation process step shown in FIGS. 5A and 5B.
  • each of the semiconductor chips 4 is bonded, with an adhesive, onto each of the chip mounting areas of the wiring substrate, with the principal surface of the semiconductor chip 4 facing upward. Specifically, the bottom face of the semiconductor chip 4 and the upper surface of the wiring substrate are secured to each other with the adhesive in this embodiment.
  • the members disposed on the upper surface of the wiring substrate e.g., the semiconductor chips 4 , wiring electrodes 1 and metal fine wires 5
  • the resin encapsulant 6 in the resin molding process step shown in FIGS. 8A and 8B.
  • the molding process step is performed by transfer-molding, and the substantially entire region of the wiring substrate except for a marginal portion thereof, which will be used to carry the substrate, for example, is molded.
  • the wiring electrodes 1 and semiconductor chips 4 are indicated by the broken lines in FIG. 8A. However, the metal fine wires 5 are not shown in the figure.
  • marking and resin molding are performed at the same time in the resin molding process step.
  • a transfer sheet on which the mark members have been formed, is interposed between the upper surface region of the wiring substrate and a die used for the resin molding.
  • the mark members 10 can be embedded in the upper surface of the resin encapsulant 6 .
  • the transfer sheet is removed, whereby the mark members is transferred to and formed in the upper surface of the resin encapsulant 6 .
  • the transfer sheet is removed, for example, by peeling, from the resin encapsulant.
  • the wiring substrate having the upper surface entirely molded with the resin encapsulant 6 is cut along the cutting lines using a rotary blade in the cutting process step shown in FIGS. 9A and 9B, thereby obtaining individual semiconductor devices 11 of the BGA type.
  • the semiconductor devices 11 with the structure shown in FIGS. 1, 2, and 3 can be obtained.
  • the wiring substrate is cut along the cutting lines indicated by the broken lines shown in FIGS. 4A and 4C by using the rotary blade. In this manner, the individual semiconductor devices can be obtained accurately. Normally, the separation by the rotary blade is performed using a dicing machine used in the fabrication process of the semiconductor device. Also, the wiring substrate is cut from either the lower surface or the resin encapsulant 6 side thereof in the known cutting process step. In the fabrication process of this embodiment, the wiring substrate is cut from the lower surface thereof. In this manner, the substrate can be kept immobile while being cut.
  • solder balls are attached to the external pad electrodes 7 formed on the lower surface of the wiring substrate 3 , thereby forming the ball electrodes 2 which will be used as external terminals.
  • the ball electrodes 2 may be formed on the external pad electrodes 7 on the lower surface of the wiring substrate, for each of the large-sized wiring substrates. In this manner, the ball electrodes 2 can be formed more efficiently.
  • FIG. 10 is a cross-sectional view illustrating an exemplary method for transferring the mark members in the resin molding process step.
  • a molding die includes a lower die 12 and an upper die 14 .
  • the semiconductor chips 4 are mounted and the wiring electrodes 1 and the semiconductor chips 4 are connected to each other via the metal fine wires 5 .
  • the wiring substrate is disposed on the lower die 12 with the semiconductor chips 4 facing upward.
  • the mark members 10 such as characters, for example, made of ink including pigment or dyestuff, or other visible materials, have been formed on the transfer sheet 13 .
  • the transfer sheet 13 is airtightly fixed on the upper die 14 in the cavity.
  • FIG. 11 is a cross-sectional view illustrating another exemplary method for transferring the mark members in the resin molding process step.
  • the transfer sheet 13 is airtightly fixed on the lower die 12 in the cavity, while the wiring substrate is disposed on the upper die 14 with the semiconductor chips 4 facing downward.
  • the positions of the wiring substrate and the transfer sheet 13 are interchanged, i.e., the positions are upside down as compared to those shown in FIG. 10.
  • the resin molding process step may be performed with the transfer sheet 11 interposed between the face of the wiring substrate on which the semiconductor chips 4 are mounted and the lower or upper die 12 or 14 facing the wiring substrate.
  • the transfer sheet 13 with the mark members 10 formed thereon is airtightly fixed on the die facing the semiconductor chips 4 on the wiring substrate in the cavity, as shown in FIGS. 10 and 11.
  • marks which are the mark members 10 embedded in the upper surface of the resin encapsulant, can be obtained easily through the single resin molding process step. Accordingly, the highly visible marks can be efficiently formed at low cost.
  • the usage of the transfer sheet in the resin molding process step enables the resin encapsulant to be molded airtightly in the cavity, preventing resin leakage or resin burr, for example.
  • the semiconductor device of the BGA type of high quality can be obtained.
  • this method can be a transfer method.
  • the transfer sheet with the mark members 10 may be temporarily adhered to the die to be airtightly fixed thereon, if necessary.
  • the transfer sheet used in the present invention may be made from material which contains polyethylene terephthalate as a major constituent and which has resistance to heat and heat shrinkage during the resin molding process step.
  • the strength of adhesion between the mark members and the transfer sheet and between the mark members and the resin encapsulant is adjusted so that the mark members can be separated from the transfer sheet and transferred to the resin encapsulant when the transfer sheet is removed after the resin molding process step has been performed.
  • the present invention has been described as being applied to a semiconductor device in which members disposed on the upper surface of a wiring substrate are molded.
  • the present invention is not limited to this embodiment but is applicable to a semiconductor device including a leadframe instead of the wiring substrate, and a double-side-molded semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; a resin encapsulant; and a mark member. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. The mark member is embedded in the upper surface of the resin encapsulant. The mark member, which is transferred from a transfer sheet in a single process step, is highly visible and can be formed efficiently.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to a single-side-molded semiconductor device, which includes a wiring substrate having a ball grid array (BGA) arranged on the lower surface and a semiconductor chip molded with a resin encapsulant on the upper surface. The present invention also relates to a method for fabricating the device. [0001]
  • A semiconductor device of the BGA type has been available as a semiconductor device of an area array type. In the BGA type semiconductor device, a semiconductor chip is mounted and molded with a resin encapsulant on the upper surface of a substrate, and ball electrodes are attached to the lower surface thereof. [0002]
  • FIG. 12 is a plan view illustrating a known semiconductor device of the BGA type. FIG. 13 is a bottom view illustrating the known BGA type semiconductor device. FIG. 14 is a cross-sectional view thereof taken along the line XIV-XIV in FIG. 12. [0003]
  • As shown in FIGS. 12, 13 and [0004] 14, the known semiconductor device includes a wiring substrate 103, wiring electrodes 101, a semiconductor chip 104, metal fine wires 105, ball electrodes 102 and a resin encapsulant 106. The wiring substrate 103 is made of an insulating resin. The wiring electrodes 101 are formed on the wiring substrate 103. The semiconductor chip 104 is mounted on the wiring substrate 103 with the principal surface of the semiconductor chip 104 facing upward. Electrode pads (not shown) formed on the semiconductor chip 104 and the wiring electrodes 101 are electrically connected to each other with the metal fine wires 105. The ball electrodes 102 are formed on the lower surface of the wiring substrate 103. The resin encapsulant 106 is provided on the upper surface of the wiring substrate 103. The semiconductor chip 104, wiring electrodes 101, metal fine wires 105 and the like are molded with the resin encapsulant 106 on the upper surface of the wiring substrate 103. Although not shown in FIG. 14, external pad electrodes are formed on the lower surface of the wiring substrate 103. The external pad electrodes are electrically connected to the wiring electrodes 101 through the substrate. The ball electrodes 102 are formed on the external pad electrodes.
  • The known semiconductor device has an approximately rectangular planar shape and the adjacent side faces thereof are perpendicular to each other. The outer shape has been determined so that the fabrication process of the semiconductor device can be simplified. Also, [0005] marks 107 representing product name, product number, model number, manufacturer name, and symbol, for example, are inscribed on the upper surface of the resin encapsulant 106 by a laser marking process step.
  • In addition, in the known semiconductor device, the [0006] ball electrodes 102 attached to the wiring substrate 103 are solder balls. The solder balls are attached to the wiring substrate 103 so that the overall semiconductor device can be highly reliably mounted and bonded onto a motherboard. Also, as shown in FIG. 14, the ball electrodes 102 are arranged on the lower surface of the wiring substrate 103 in a latticed shape.
  • Next, the fabrication process of the known semiconductor device will be described. FIGS. 15A and 15B are respectively a plan view and a bottom view illustrating a wiring substrate in the known semiconductor device. FIGS. 16A and 16B are plan views illustrating a substrate preparation process step and a die bonding process step, respectively, in the fabrication process of the known semiconductor device. FIGS. 17A and 17B are plan views illustrating a wire bonding process step and a resin molding process step, respectively, in the fabrication process of the known semiconductor device. FIG. 18 is a plan view illustrating a cutting process step in the fabrication process of the known semiconductor device. [0007]
  • As shown in FIGS. [0008] 15A and 1SB, the multiple wiring electrodes 101 are formed on the upper surface of the wiring substrate, and external pad electrodes 107 are formed on the lower surface of the wiring substrate. The external pad electrodes 107 are electrically connected to the wiring electrodes 101 through the substrate. The ball electrodes will be attached to the external pad electrodes 107 in the subsequent process step. The wiring substrate is a large-sized substrate on which multiple semiconductor chips will be mounted and which will be separated into individual semiconductor devices. The broken lines shown in FIGS. 15A and 15B are cutting lines, which will be used to separate the substrate into the individual semiconductor devices. Also, in each of the regions defined by the cutting lines in FIG. 15A, a central area surrounded by each array of the wiring electrodes 101 is a chip mounting area where each of the semiconductor chips is mounted by bonding.
  • First, the wiring substrate with the structure shown in FIGS. 15A and 15B is prepared in the substrate preparation process step shown in FIG. 16A. [0009]
  • Next, each of the [0010] semiconductor chips 104 is bonded, with an adhesive, onto each of the chip mounting areas of the wiring substrate in the die bonding process step shown in FIG. 16B.
  • Subsequently, the electrode pads (not shown) formed on the principal surface of each of the [0011] semiconductor chips 104 and their associate wiring electrodes 101 formed on the wiring substrate are electrically connected to each other with the metal fine wires 105 in the wire bonding process step shown in FIG. 17A.
  • Then, the members disposed on the upper surface of the wiring substrate, e.g., the [0012] semiconductor chips 104, wiring electrodes 101, metal fine wires 105, are transfer-molded with the resin encapsulant 106 in the resin molding process step shown in FIG. 17B. Thereafter, the marks 107 such as product name, product number, model number, manufacturer name, and symbol, for example, are inscribed on the upper surface of the resin encapsulant 106 for each of the semiconductor devices by a laser marker. The wiring electrodes 101 and semiconductor chips 104 are indicated by the broken lines in FIG. 17B. However, the metal fine wires 105 are not shown in the figure.
  • Next, in the cutting process step shown in FIG. 18, the wiring substrate having the upper surface entirely molded with the [0013] resin encapsulant 106 is cut along the cutting lines using a rotary blade, thereby obtaining individual semiconductor devices 109 of the BGA type. Hence, the semiconductor devices 109 with the structure shown in FIGS. 13 and 14 can be obtained.
  • In this example, the wiring substrate is cut, using the rotary blade, along the cutting lines indicated by the broken lines shown in FIGS. 15A and 15B. In this manner, the individual semiconductor devices can be obtained accurately. Normally, the separation by the rotary blade is performed using a dicing machine used in the fabrication process of the semiconductor device. Also, in the cutting process step, the wiring substrate is cut from either the lower surface or the [0014] resin encapsulant 106 side thereof.
  • In the subsequent process step, which is not shown, in each of the [0015] individual semiconductor devices 109, solder balls are attached to the external pad electrodes 107 formed on the lower surface of the wiring substrate 103. In this manner, the multiple ball electrodes are formed and will be used as external terminals.
  • The process steps for fabricating the known BGA type semiconductor device have been performed in the abovedescribed manner, i.e., the large-sized substrate on which the multiple semiconductor chips can be mounted is used. Then, a large number of semiconductor chips are mounted on the substrate, the associate members are electrically connected, the members on the wiring substrate are molded with the resin encapsulant, and the marking is performed. Thereafter, the wiring substrate is cut into the individual semiconductor devices of the BGA type in the end. [0016]
  • Particularly, the marking process step is performed after the members disposed on the upper surface of the wiring substrate have been molded with the [0017] resin encapsulant 106. The marks are inscribed on the upper surface of the resin encapsulant 106 for each of the semiconductor devices by the laser marker in the process step shown in FIG. 17B.
  • However, it is inefficient to inscribe the marks by using the laser marker for each of such a large number of semiconductor devices, thus becoming an obstacle to increase in productivity in the assembly process. Also, depending on environments, the laser marks inscribed on the upper surface of the resin encapsulant sometimes have a low visibility and might be misidentified. [0018]
    • SUMMARY OF THE INVENTION
  • An object of this invention is to provide 1) a semiconductor device of the BGA type, which is easy to handle and which can be fabricated at low cost, by taking measures to put highly visible marks on a large number of semiconductor devices by a single process step, and 2) a method for fabricating the device. [0019]
  • An inventive semiconductor device includes: a wiring substrate; a semiconductor chip; an electrode; a connecting member; a resin encapsulant; and a mark member. The wiring substrate includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate. The external electrode is to be electrically connected to the wiring electrode. The semiconductor chip is mounted on the wiring substrate. The electrode is formed on the semiconductor chip. The connecting member is used to connect the electrode of the semiconductor chip and the wiring electrode on the wiring substrate electrically to each other. The resin encapsulant molds the wiring substrate, the semiconductor chip, the connecting member and the wiring electrode. The mark member is visible and is embedded in the upper surface of the resin encapsulant. [0020]
  • According to the present invention, the mark member is embedded in the upper surface of the resin encapsulant. Thus, the visibility of the mark increases. [0021]
  • In one embodiment of the present invention, the device preferably further includes a ball electrode which is attached to the external electrode of the wiring substrate. [0022]
  • An inventive method for fabricating a semiconductor device includes the step of a) preparing a wiring substrate, which includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate. The external electrode is to be electrically connected to the wiring electrode. The method further includes the step of b) mounting semiconductor chips on the wiring substrate. The method further includes the step of c) connecting an electrode of each of the semiconductor chips and the wiring electrode on the wiring substrate electrically to each other with a connecting member. The method further includes the step of d) disposing the wiring substrate on a face of one die of a molding die after the step c) has been performed; disposing a transfer sheet, on which a mark member has been formed, on a face of the other die of the molding die; and performing a resin molding process. The method further includes the step of e) removing the transfer sheet and embedding the mark member in the upper surface of a resin encapsulant by transcription, after the step d) has been performed. [0023]
  • According to the present invention, the mark is formed quickly by a single transfer method. Therefore, the fabrication cost can be reduced and the mark can be formed efficiently. [0024]
  • In one embodiment of the present invention, in the step e), the wiring substrate may be separated into individual semiconductor devices by using a rotary blade. [0025]
  • In another embodiment of the present invention, a ball electrode may be attached to the external electrode on the lower surface of the wiring substrate between the steps d) and e). In such an embodiment, a semiconductor device of the BGA type can be fabricated easily. [0026]
  • In still another embodiment, in the step a), the wiring substrate, on which the semiconductor chips can be mounted and which can be separated into individual semiconductor devices, is preferably prepared. [0027]
  • In still another embodiment, in the step d), a side of the transfer sheet may face the wiring substrate and the transfer sheet may be airtightly fixed on the face of the die of the molding die. The side includes the mark member formed thereon. [0028]
  • In still another embodiment, in the step d), the transfer sheet preferably includes the mark member formed thereon that is visible and that can be separated from the transfer sheet.[0029]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention. [0030]
  • FIG. 2 is a bottom view illustrating the semiconductor device of the embodiment. [0031]
  • FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1, illustrating the semiconductor device of the embodiment. [0032]
  • FIGS. 4A, 4B and [0033] 4C are respectively plan view, cross-sectional view taken along the line IVb-IVb, and bottom view illustrating a wiring substrate in accordance with the embodiment.
  • FIGS. 5A and 5B are respectively a plan view, and a cross-sectional view taken along the line IVb-IVb, illustrating a substrate preparation process step in the fabrication process of the semiconductor device of the embodiment. [0034]
  • FIGS. 6A and 6B are respectively a plan view, and a cross-sectional view taken along the line VIb-VIb, illustrating a die bonding process step in the fabrication process of the semiconductor device of the embodiment. [0035]
  • FIGS. 7A and 7B are respectively a plan view, and a cross-sectional view taken along the line VIIb-VIIb, illustrating a wire bonding process step in the fabrication process of the semiconductor device of the embodiment. [0036]
  • FIGS. 8A and 8B are respectively a plan view, and a cross-sectional view taken along the line XIIIb-XIIIb, illustrating a resin molding process step in the fabrication process of the semiconductor device of the embodiment. [0037]
  • FIGS. 9A and 9B are respectively a plan view, and a cross-sectional view taken along the line IXb-IXb, illustrating a cutting process step in the fabrication process of the semiconductor device of the embodiment. [0038]
  • FIG. 10 is a cross-sectional view illustrating an exemplary method for transferring mark members in the resin molding process step in the fabrication process of the semiconductor device of the embodiment. [0039]
  • FIG. 11 is a cross-sectional view illustrating another exemplary method for transferring the mark members in the resin molding process step in the fabrication process of the semiconductor device of the embodiment. [0040]
  • FIG. 12 is a plan view illustrating a known semiconductor device of the BGA type. [0041]
  • FIG. 13 is a bottom view illustrating the known BGA type semiconductor device. [0042]
  • FIG. 14 is a cross-sectional view thereof taken along the line XIV-XIV in FIG. 12. [0043]
  • FIGS. 15A and 15B are respectively a plan view and a bottom view illustrating a wiring substrate in the known semiconductor device. [0044]
  • FIGS. 16A and 16B are plan views illustrating a substrate preparation process step and a die bonding process step, respectively, in the fabrication process of the known semiconductor device. [0045]
  • FIGS. 17A and 17B are plan views illustrating a wire bonding process step and a resin molding process step, respectively, in the fabrication process of the known semiconductor device. [0046]
  • FIG. 18 is a plan view illustrating a cutting process step in the fabrication process of the known semiconductor device.[0047]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention. FIG. 2 is a bottom view illustrating the semiconductor device of the embodiment. FIG. 3 is a cross-sectional view thereof taken along the line III-III in FIG. 1. [0048]
  • As shown in FIGS. 1, 2, and [0049] 3, the semiconductor device of this embodiment includes a wiring substrate 3, wiring electrodes 1, a semiconductor chip 4, metal fine wires 5, ball electrodes 2 and a resin encapsulant 6. The wiring substrate 3 is made of an insulating resin. The wiring electrodes 1 are formed on the wiring substrate 3. The semiconductor chip 4 is mounted on the wiring substrate 3. Electrode pads (not shown) formed on the principal surface of the semiconductor chip 4 and the wiring electrodes 1 are electrically connected to each other with the metal fine wires 5. The ball electrodes 2 are formed on the lower surface of the wiring substrate 3. The semiconductor chip 4, wiring electrodes 1, metal fine wires 5 and the like are molded with the resin encapsulant 6 on the upper surface of the wiring substrate 3.
  • According to the semiconductor device of this embodiment, [0050] mark members 10 representing product name, product number, model number, manufacturer name, and symbol, for example, are embedded in the upper surface of the resin encapsulant 6 on the upper surface of the wiring substrate 3. The mark members 10 are, e.g., characters and symbols which are made of ink such as pigment or dyestuff, for example, or other easily visible materials.
  • Although not shown in FIG. 2, external pad electrodes are formed on the lower surface of the [0051] wiring substrate 3. The external pad electrodes are electrically connected to the wiring electrodes 1 through the substrate. The ball electrodes 2 are formed on the external pad electrodes. This is to say, the semiconductor device of this embodiment has the structure of a semiconductor device of the BGA type. Although not shown in FIGS. 3 and 4, an integrated circuit, on which e.g., a large number of transistors are disposed, is formed near the principal surface in the semiconductor chip. In addition, electrode pads to be used for connection with outside units are also formed on wiring layers formed near the principal surface in the semiconductor chip. And one end of each of the metal fine wires 5 is connected to the associated one of the electrode pads on the semiconductor chip.
  • In addition, in the semiconductor device of this embodiment, the [0052] ball electrodes 2 attached to the wiring substrate 3 are solder balls. The solder balls are attached so that the overall semiconductor device can be mounted and bonded onto a motherboard highly reliably. Also, as shown in FIG. 2, the ball electrodes 2 are arranged on the lower surface of the wiring substrate 3 in a latticed shape.
  • According to the semiconductor device of this embodiment, the [0053] mark members 10 are embedded in the upper surface of the resin encapsulant 6. Thus the marks of the semiconductor device of this embodiment have higher visibility than those inscribed by a laser marking process. Also, as will be described, since the mark members 10 are formed by transcription performed in a single process step, the fabricating costs are lower as compared to the laser marking. This is to say, according to the semiconductor device of this embodiment, the marking visibility can be increased and the marking costs can be reduced as well.
  • Next, the fabrication process of the semiconductor device of this embodiment will be described. FIGS. 4A, 4B and [0054] 4C are respectively plan view, cross-sectional view taken along the line IVb-IVb, and bottom view illustrating a wiring substrate in accordance with this embodiment. FIGS. 5A and 5B are respectively a plan view, and a cross-sectional view taken along the line Vb-Vb, illustrating a substrate preparation process step in the fabrication process of the semiconductor device of this embodiment. FIGS. 6A and 6B are respectively a plan view, and a cross-sectional view taken along the line VIb-VIb, illustrating a die bonding process step in the fabrication process of the semiconductor device of this embodiment. FIGS. 7A and 7B are respectively a plan view, and a cross-sectional view taken along the line VIIb-VIIb, illustrating a wire bonding process step in the fabrication process of the semiconductor device of this embodiment. FIGS. 8A and 8B are respectively a plan view, and a cross-sectional view taken along the line XIIIb-XIIIb, illustrating a resin molding process step in the fabrication process of the semiconductor device of this embodiment. FIGS. 9A and 9B are respectively a plan view, and a cross-sectional view taken along the line IXb-IXb, illustrating a cutting process step in the fabrication process of the semiconductor device of this embodiment.
  • As shown in FIGS. 4A thorough [0055] 4C, the multiple wiring electrodes 1 are formed on the upper surface of the wiring substrate, and external pad electrodes 7 are formed on the lower surface of the wiring substrate. The external pad electrodes 7 are electrically connected to the wiring electrodes 1 through the substrate. The ball electrodes will be attached to the external pad electrodes 7 in the subsequent process step. The wiring substrate prepared is a large-sized substrate on which multiple semiconductor chips will be mounted and which will be later separated into individual semiconductor devices. The broken lines shown in FIGS. 4A and 4C are cutting lines, which will be used to separate the substrate into the individual semiconductor devices. Also, in each of the regions defined by the cutting lines in FIG. 4A, a central area surrounded by the arrays of the wiring electrodes 1 is a chip mounting area where each of the semiconductor chips is mounted by bonding.
  • First, the wiring substrate with the structure shown in FIGS. 4A through 4C is prepared in the substrate preparation process step shown in FIGS. 5A and 5B. [0056]
  • Next, in the die bonding process step shown in FIGS. 6A and 6B, each of the [0057] semiconductor chips 4 is bonded, with an adhesive, onto each of the chip mounting areas of the wiring substrate, with the principal surface of the semiconductor chip 4 facing upward. Specifically, the bottom face of the semiconductor chip 4 and the upper surface of the wiring substrate are secured to each other with the adhesive in this embodiment.
  • Subsequently, the electrode pads (not shown) of the [0058] semiconductor chips 4 and their associate wiring electrodes 1 formed on the wiring substrate are electrically connected to each other with the metal fine wires 5 in the wire bonding process step shown in FIGS. 7A and 7B.
  • Then, the members disposed on the upper surface of the wiring substrate, e.g., the [0059] semiconductor chips 4, wiring electrodes 1 and metal fine wires 5, are molded with the resin encapsulant 6 in the resin molding process step shown in FIGS. 8A and 8B. The molding process step is performed by transfer-molding, and the substantially entire region of the wiring substrate except for a marginal portion thereof, which will be used to carry the substrate, for example, is molded. The wiring electrodes 1 and semiconductor chips 4 are indicated by the broken lines in FIG. 8A. However, the metal fine wires 5 are not shown in the figure.
  • As will be described in detail, marking and resin molding are performed at the same time in the resin molding process step. In this case, when the upper surface of the wiring substrate is molded with the [0060] resin encapsulant 6, a transfer sheet, on which the mark members have been formed, is interposed between the upper surface region of the wiring substrate and a die used for the resin molding. In this manner, the mark members 10 can be embedded in the upper surface of the resin encapsulant 6. After the resin molding process step has been performed, the transfer sheet is removed, whereby the mark members is transferred to and formed in the upper surface of the resin encapsulant 6. The transfer sheet is removed, for example, by peeling, from the resin encapsulant.
  • Next, the wiring substrate having the upper surface entirely molded with the [0061] resin encapsulant 6, is cut along the cutting lines using a rotary blade in the cutting process step shown in FIGS. 9A and 9B, thereby obtaining individual semiconductor devices 11 of the BGA type. Hence, the semiconductor devices 11 with the structure shown in FIGS. 1, 2, and 3 can be obtained.
  • In this embodiment, the wiring substrate is cut along the cutting lines indicated by the broken lines shown in FIGS. 4A and 4C by using the rotary blade. In this manner, the individual semiconductor devices can be obtained accurately. Normally, the separation by the rotary blade is performed using a dicing machine used in the fabrication process of the semiconductor device. Also, the wiring substrate is cut from either the lower surface or the [0062] resin encapsulant 6 side thereof in the known cutting process step. In the fabrication process of this embodiment, the wiring substrate is cut from the lower surface thereof. In this manner, the substrate can be kept immobile while being cut.
  • In the subsequent process step, which is not shown, in each of the [0063] individual semiconductor devices 11, solder balls are attached to the external pad electrodes 7 formed on the lower surface of the wiring substrate 3, thereby forming the ball electrodes 2 which will be used as external terminals.
  • Alternatively, before cutting the wiring substrate into the [0064] individual semiconductor devices 11, the ball electrodes 2 may be formed on the external pad electrodes 7 on the lower surface of the wiring substrate, for each of the large-sized wiring substrates. In this manner, the ball electrodes 2 can be formed more efficiently.
  • Next, it will be described how the mark members are transferred and formed during the process step for molding the upper surface of the wiring substrate. [0065]
  • FIG. 10 is a cross-sectional view illustrating an exemplary method for transferring the mark members in the resin molding process step. As shown in FIG. 10, a molding die includes a [0066] lower die 12 and an upper die 14. On the wiring substrate, the semiconductor chips 4 are mounted and the wiring electrodes 1 and the semiconductor chips 4 are connected to each other via the metal fine wires 5. The wiring substrate is disposed on the lower die 12 with the semiconductor chips 4 facing upward. The mark members 10 such as characters, for example, made of ink including pigment or dyestuff, or other visible materials, have been formed on the transfer sheet 13. The transfer sheet 13 is airtightly fixed on the upper die 14 in the cavity. In this case, the side of the transfer sheet 13, on which the mark members 10 have been formed, faces the wiring substrate. Then, the upper and lower dies 14 and 12 are closed and the resin encapsulant is injected into the cavity, whereby the members disposed on the upper surface of the wiring substrate are entirely molded with the resin encapsulant. The transfer sheet 13 is tensile, i.e., tension is applied to the transfer sheet 13 during the resin molding process step. In this manner, wrinkles caused by the thermal shrinkage of the transfer sheet 13 can be prevented and thus the upper surface of the resin encapsulant can be planarized.
  • FIG. 11 is a cross-sectional view illustrating another exemplary method for transferring the mark members in the resin molding process step. As shown in FIG. 11, the [0067] transfer sheet 13 is airtightly fixed on the lower die 12 in the cavity, while the wiring substrate is disposed on the upper die 14 with the semiconductor chips 4 facing downward. Hence, when the resin molding process step is performed in this method, the positions of the wiring substrate and the transfer sheet 13 are interchanged, i.e., the positions are upside down as compared to those shown in FIG. 10.
  • In the both methods shown in FIGS. 10 and 11, the resin molding process step may be performed with the [0068] transfer sheet 11 interposed between the face of the wiring substrate on which the semiconductor chips 4 are mounted and the lower or upper die 12 or 14 facing the wiring substrate.
  • According to the method for fabricating the semiconductor device in accordance with this embodiment, when the resin encapsulant is injected into the cavity, the [0069] transfer sheet 13 with the mark members 10 formed thereon is airtightly fixed on the die facing the semiconductor chips 4 on the wiring substrate in the cavity, as shown in FIGS. 10 and 11. In this manner, marks, which are the mark members 10 embedded in the upper surface of the resin encapsulant, can be obtained easily through the single resin molding process step. Accordingly, the highly visible marks can be efficiently formed at low cost.
  • Also, the usage of the transfer sheet in the resin molding process step enables the resin encapsulant to be molded airtightly in the cavity, preventing resin leakage or resin burr, for example. Thus, the semiconductor device of the BGA type of high quality can be obtained. [0070]
  • When the transfer sheet is peeled off after the resin molding process step has been performed, only the [0071] mark members 10 remain in the upper surface of the resin encapsulant 6. Therefore, this method can be a transfer method.
  • It should be noted that the transfer sheet with the [0072] mark members 10 may be temporarily adhered to the die to be airtightly fixed thereon, if necessary.
  • The transfer sheet used in the present invention may be made from material which contains polyethylene terephthalate as a major constituent and which has resistance to heat and heat shrinkage during the resin molding process step. The strength of adhesion between the mark members and the transfer sheet and between the mark members and the resin encapsulant is adjusted so that the mark members can be separated from the transfer sheet and transferred to the resin encapsulant when the transfer sheet is removed after the resin molding process step has been performed. [0073]
  • The [0074] mark members 10 used in the present invention may be made of, for example, ink including pigment or dyestuff, or other visible materials which have resistance to heat and thermal shrinkage. Also, a clear color is preferably selected for the mark members 10 considering coloration and contrast to the resin encapsulant. The mark members 10 in this embodiment have a white color.
  • In the foregoing embodiment, the present invention has been described as being applied to a semiconductor device in which members disposed on the upper surface of a wiring substrate are molded. However, the present invention is not limited to this embodiment but is applicable to a semiconductor device including a leadframe instead of the wiring substrate, and a double-side-molded semiconductor device. [0075]

Claims (8)

What is claimed is:
1. A semiconductor device comprising:
a wiring substrate, which includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate, the external electrode being to be electrically connected to the wiring electrode;
a semiconductor chip, which is mounted on the wiring substrate;
an electrode, which is formed on the semiconductor chip;
a connecting member, which is used to connect the electrode of the semiconductor chip and the wiring electrode on the wiring substrate electrically to each other;
a resin encapsulant, which molds the wiring substrate, the semiconductor chip, the connecting member and the wiring electrode; and
a mark member, which is visible and which is embedded in the upper surface of the resin encapsulant.
2. The device of claim 1, further comprising a ball electrode which is attached to the external electrode of the wiring substrate.
3. A method for fabricating a semiconductor device, comprising the steps of:
a) preparing a wiring substrate, which includes a wiring electrode and an external electrode, respectively, on the upper surface and the lower surface of the wiring substrate, the external electrode being to be electrically connected to the wiring electrode;
b) mounting semiconductor chips on the wiring substrate;
c) connecting an electrode of each of the semiconductor chips and the wiring electrode on the wiring substrate electrically to each other with a connecting member;
d) disposing the wiring substrate on a face of one die of a molding die after the step c) has been performed, disposing a transfer sheet, on which a mark member has been formed, on a face of the other die of the molding die, and
performing a resin molding process; and
e) removing the transfer sheet and embedding the mark member in the upper surface of a resin encapsulant by transcription, after the step d) has been performed.
4. The method of claim 3, wherein in the step e), the wiring substrate is separated into individual semiconductor devices by using a rotary blade.
5. The method of claim 3, wherein a ball electrode is attached to the external electrode on the lower surface of the wiring substrate between the steps d) and e).
6. The method of claim 3, wherein in the step a), the wiring substrate, on which the semiconductor chips can be mounted and which can be separated into individual semiconductor devices, is prepared.
7. The method of claim 3, wherein in the step d), a side of the transfer sheet faces the wiring substrate and the transfer sheet is airtightly fixed on the face of the die of the molding die, the side including the mark member formed thereon.
8. The method of claim 3, wherein in the step d), the transfer sheet includes the mark member formed thereon that is visible and that can be separated from the transfer sheet.
US09/983,524 2000-10-26 2001-10-24 Semiconductor device and method for fabricating the same Abandoned US20020052056A1 (en)

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