JP4033969B2 - Semiconductor package, manufacturing method thereof and wafer carrier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package, a manufacturing method thereof, and a wafer carrier used therefor.
[0002]
[Prior art]
Conventionally, a semiconductor package is composed of a semiconductor chip (particularly an IC chip), a gold wire, a lead frame, and a mold package.
[0003]
In a semiconductor package manufacturing method, a wafer that has been processed in a wafer process is subjected to a wafer mounting process in which the wafer is attached to an adhesive film, and a non-defective chip is selected after a scribing process in which chips in the wafer are divided.
[0004]
After that, through a die bonding process for bonding the chip to the lead frame and a wire bonding process for wiring the lead frame and the chip, the wired wires are selected and sealed with an epoxy resin (mold) for protection including this member. To do.
[0005]
After that, the surface treatment and outer lead shape processing on the outer lead considering the mounting are finished, and characters taking into consideration the characteristics of the IC are generally stamped on the surface of the package and are completed through a characteristic inspection.
[0006]
In recent years, IC chips have been highly integrated, and the size of the chip has been increased. On the other hand, high-density mounting is required. Therefore, it is inevitable that the semiconductor package is thinned.
[0007]
Since the conventional package has chip and lead frame wiring inside the package, there is a limit to making the package size close to the chip size.
[0008]
Therefore, recently, lead pins are attached to the electrode pads of the IC chip, the dicing sheet to which the IC chip is bonded is stretched to set the upper form between the IC chips, and then the sealing resin liquid is potted and cured Then, after the dicing sheet is peeled off, an IC package that approximates the cured chip size has been proposed in which a lower mold is set and a sealing resin solution is potted.
[0009]
[Problems to be solved by the invention]
However, such an IC package and its manufacturing method require a step of stretching or peeling the dicing sheet and a step of preparing upper and lower frame molds and molding them separately in the upper and lower sides. was there.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention is provided with a plurality of grooves formed obliquely so as not to come into contact with the cutting line of the wafer in order to mount the wafer and allow the mold resin to reach the back surface of the wafer . A wafer carrier composed of a base member and a carrier frame is used, a wafer is mounted on the base member, and molded in a state where the chips are divided.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor package of the present invention, and FIG. 2 is a perspective view of the same.
[0012]
The semiconductor chip 1 has a plurality of bonding pads. The bumps 2 are formed by bonding to the pads, and the back surface is mounted on the base member 3 by bonding. An adhesive for adhering the chip 1 is applied to the upper surface of the base member 3, and a groove 31 is formed to allow the liquid mold resin to reach the back surface of the chip 1.
[0013]
The mold resin is solidified in the groove 31 to become the sealing resin layer 4, and the adhesion strength between the chip 1 and the sealing resin layers 4 and 5 is increased. The sealing resin layer 4 is formed at the same time when the wafer is mounted on the base member 3 to divide the chip and molded in that state with a mold resin to form the sealing resin layer 5.
[0014]
The sealing resin layer 5 is formed on the outer surface of the chip 1 and the back surface of the base member 3 to protect the whole.
[0015]
The bump 2 is exposed on the surface of the sealing resin layer 5 formed on the upper surface of the chip 1 and serves as a connection terminal to the outside.
[0016]
FIG. 3 is a plan view showing an embodiment of the wafer carrier of the present invention with a wafer mounted thereon, and FIG. 4 is a front view thereof.
[0017]
The wafer carrier 6 includes a base member 3 and a carrier frame 7 which is an outer frame, and the wafer 8 is bonded to the base member 3 and mounted on the wafer carrier 6.
[0018]
The base member 3 is formed of a synthetic resin or a material having a heat dissipation effect such as metal. In the case of a hard synthetic resin or metal, the base member 3 is fixed to the carrier frame 7 by caulking, screwing or the like, and soft synthetic resin such as vinyl is used. In this case, it is thickened and attached to the carrier frame 7 with an adhesive.
[0019]
In addition, a groove 31 is provided on the surface of the base member 3 for allowing the liquid mold resin to reach the back surface of the wafer 8. A plurality of the grooves 31 are formed obliquely in parallel so as not to contact the side of the cutting line 81 of the wafer 8. The reason why it is formed obliquely is to form it in the direction of point contact with the cutting line 81.
[0020]
The carrier frame 7 is formed of, for example, metal or the like, and guide holes 71 used for positioning to a manufacturing apparatus in each manufacturing process are formed at four locations at each corner.
[0021]
The wafer carrier 6 serves as a conventional film carrier in the wafer mounting process, and serves as a transfer jig for preventing the divided chips from being separated in the scribe process.
[0022]
FIG. 5 is an enlarged cross-sectional view of a part of the wafer carrier. A groove 31 is formed in the base member 3 of the wafer carrier 6.
[0023]
An adhesive for mounting the wafer 8 is applied to the upper surface of the base member 3, but this adhesive is one whose adhesive strength is reduced by UV (ultraviolet light), and heat is applied during molding. Thermosetting materials are desirable.
[0024]
Further, the adhesive may be applied by screen printing or the like after forming the groove 31, or the groove 31 may be formed after applying the adhesive.
[0025]
FIG. 6 is a plan view showing another embodiment of the wafer carrier of the present invention, which is the same as FIG. 3 except that the groove provided in the base member is different.
[0026]
The base member 3 of the wafer carrier 6 is provided with grooves 32 formed in a lattice shape so as not to make side contact with the cutting line 81 of the wafer 8. This is because, when the side contact is made, cutting is performed at that portion, which affects the adhesion strength.
[0027]
In the case of the grid-like grooves 32, the density strength of the wafer 8 and the sealing resin layers 4 and 5 is further increased as compared with the parallel case.
[0028]
7 to 12 are views showing an embodiment of a method for manufacturing a semiconductor package of the present invention, and each drawing shows a manufacturing process.
[0029]
As shown in FIG. 3, a wafer carrier 6 having a base member 3 having a groove 31 on the surface is prepared, and the wafer 8 that has been subjected to the wafer processing is mounted on the base member 3 to select non-defective products.
[0030]
The wafer 8 is mounted on the base member 3 having the groove 31 on the surface, and a bonding material is applied to the bonding pad 9 shown in FIG. 7 by screen printing or the like, or bumps 2 are formed by plating as shown in FIG. Form.
[0031]
Next, in order to divide the wafer 8 into individual pieces, as shown in FIG. 9, the blade 8 is accurately cut by the cutting line 81 by the blade 10, and is divided into chips, that is, divided into individual chips 1.
[0032]
As shown in FIG. 10, the wafer 8 is divided into chips 1 and is sealed with mold resin while being mounted on the base member 3 of the wafer carrier 6, and the outer surface including the cutting portion of the wafer 8 and the base member. The sealing resin layer 5 is formed on the back surface of 3. At this time, the molding resin is caused to flow through the groove 31 of the base member 3 to form the sealing resin layer 4 in the groove 31. By forming the sealing resin layer 4, the lower surface of the chip 1 is in close contact with the sealing resin layer 4 .
[0033]
In order to expose the bump 2 on the surface of the sealing resin layer 5 at this time, a mold structure for exposing is used, or the surface of the sealing resin layer 5 formed on the surface of the wafer 8 after the molding process. Is added to expose the bump 2 on the surface of the sealing resin layer 5.
[0034]
The bump 2 is exposed on the surface of the sealing resin layer 5 and is used as an external terminal. Conventionally, the bump height of 70 to 100 μm is about 200 μm or more.
[0035]
In FIG. 11, the probe needle 11 is connected to the bump 2 to perform an electrical property inspection.
[0036]
After the characteristic inspection, in the package dividing step shown in FIG. 12, the wafer 8 that is entirely covered with the sealing resin layer 5 is fully cut together with the base member 3 of the wafer carrier 6 to form individual packages. The completed semiconductor package is the one shown in FIGS.
[0037]
As described above, according to the embodiment of the present invention, the bumps 2 serving as the external terminals are formed on the bonding pads 9 of the semiconductor chip 1, so that no lead pins are required, and gold wires, silver paste, lead frames, etc. It is not necessary to use expensive members, and the conventional wire bonding process, wire selection process, and die bonding process can be omitted.
[0038]
In addition, since the wafer 8 is mounted on the base member 3 of the wafer carrier 6 and molded in the state of being divided into chips, the dicing sheet is stretched or peeled off, and the upper and lower frame molds are prepared and the upper and lower molds are molded separately. Is not necessary, the manufacturing process is simplified, and the cost of parts and man-hours is reduced.
[0039]
Further, since the grooves 31 and 32 are provided on the surface of the base member 3 of the wafer carrier 6 to improve the flow of the mold resin and the sealing resin layer 4 is formed, the wafer 8 and the sealing resin layers 4 and 5 are formed. As a result, the reliability of the quality of the semiconductor package is improved.
[0040]
Further, if the base member 3 of the wafer carrier 6 is formed of a material having a heat dissipation effect such as metal, the wafer 8 is molded together with the base member 3, so that the heat dissipation can be improved.
[0041]
Furthermore, since the carrier frame 7 of the wafer carrier 6 is provided with a guide hole 71 used for positioning in each manufacturing process, the entire process can be handled using one type of carrier frame 7.
[0042]
【The invention's effect】
As described above, according to the present invention, the wafer is mounted on the base member of the wafer carrier and molded in the state of being divided into chips, so that the manufacturing process can be simplified and the cost can be reduced.
[0043]
Further, since the sealing resin layer is formed by providing a groove on the surface of the base member, the adhesion strength between the chip and the sealing resin layer is increased, and the reliability of the semiconductor package is improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor package of the present invention.
FIG. 2 is a perspective view showing an embodiment of the present invention.
FIG. 3 is a plan view showing an embodiment of a wafer carrier of the present invention.
FIG. 4 is a front view showing an embodiment of the present invention.
FIG. 5 is a partially enlarged sectional view of a wafer carrier.
FIG. 6 is a plan view showing another embodiment of the wafer carrier of the present invention.
FIG. 7 is a diagram showing an embodiment of a production method of the present invention.
FIG. 8 shows a manufacturing process.
FIG. 9 shows a manufacturing process.
FIG. 10 shows a manufacturing process.
FIG. 11 shows a manufacturing process.
FIG. 12 shows a manufacturing process.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Bump 3 Base member 31, 32 Groove 4, 5 Sealing resin layer 6 Wafer carrier 7 Carrier frame 71 Guide hole 8 Wafer 81 Cutting line 9 Bonding pad 10, 12 Blade 11 Probe needle

Claims (5)

A semiconductor chip having a plurality of bonding pads;
On the surface, there are a plurality of grooves formed obliquely so as not to make side contact with the cutting line of the wafer, and a base member for mounting the chip on the surface;
A sealing resin layer molded in the chip and the groove;
A bump formed by bonding to the bonding pad and exposed on the surface of the sealing resin layer;
A semiconductor package comprising: 2. The semiconductor package according to claim 1, wherein the base member is made of metal .   Preparing a base member having a plurality of grooves formed obliquely on the surface so as not to make side contact with the cutting line of the wafer;
  Mounting a wafer on the base member;
  Forming bumps to be bonded to the bonding pads of the wafer;
  Cutting the wafer on the base member and dividing the chip;
  Forming a sealing resin layer by molding the inside of the wafer and the groove with a sealing resin in a state where the chip is divided;
  Full-cutting the wafer covered with the sealing resin layer and dividing the package;
A method for manufacturing a semiconductor package, comprising:   A wafer carrier used in a semiconductor package manufacturing method,
  Consists of a base member provided with a plurality of grooves formed obliquely so as not to contact the side of the wafer cutting line on the upper surface on which the wafer is mounted, and a carrier frame provided with a guide hole for positioning in each manufacturing process A wafer carrier characterized by that.   The wafer carrier according to claim 4, wherein the base member is made of metal.

Images