US12506114B2 - Directly bonded metal structures having aluminum features and methods of preparing same - Google Patents
Directly bonded metal structures having aluminum features and methods of preparing sameInfo
- Publication number
- US12506114B2 US12506114B2 US18/148,332 US202218148332A US12506114B2 US 12506114 B2 US12506114 B2 US 12506114B2 US 202218148332 A US202218148332 A US 202218148332A US 12506114 B2 US12506114 B2 US 12506114B2
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- US
- United States
- Prior art keywords
- aluminum
- feature
- field region
- conductive
- bonding
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Definitions
- the field relates to bonded structures and methods of forming direct metal bonds that include aluminum features.
- Microelectronic elements such as integrated device dies or chips, may be mounted or stacked on other elements thereby forming a bonded structure.
- Direct metal bonding can be conducted at low temperatures and without external pressure.
- direct hybrid bonding involves directly bonding non-conductive features (e.g., inorganic dielectrics) of different elements together, without intervening adhesives, while also directly bonding conductive features (e.g., metal pads or lines) of the elements together.
- a microelectronic element can be mounted to a carrier, such as an interposer, a reconstituted wafer or element, etc.
- a microelectronic element can be stacked on top of another microelectronic element, e.g., a first integrated device die can be stacked on a second integrated device die.
- Each of the microelectronic elements can have conductive pads for mechanically and electrically bonding the elements to one another.
- FIG. 5 H is a schematic cross-sectional side view of a bonded structure that includes the element formed in FIG. 5 F and a plurality of second elements (such as dies).
- the bonding layers 108 a and/or 108 b can comprise a non-conductive material such as a dielectric material, for example, silicon oxide, or an undoped semiconductor material, for example, undoped silicon.
- Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, and can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SiCOH dielectrics, silicon carbonitride, glass, ceramics, glass-ceramics, or diamond-like carbon or a material comprising a diamond surface.
- one of the device portions 110 a and 110 b comprises a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other one of the device portions 110 a and 110 b can comprise a non-III-V semiconductor material, such as silicon (Si) and/or germanium (Ge), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass.
- a III-V single semiconductor material such as gallium arsenide (GaAs) or gallium nitride (GaN)
- the other one of the device portions 110 a and 110 b can comprise a non-III-V semiconductor material, such as silicon (Si) and/or germanium (Ge), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass.
- direct hybrid bonds can be formed without an intervening adhesive.
- nonconductive bonding surfaces 112 a and 112 b can be polished to a high degree of smoothness.
- the nonconductive bonding surfaces 112 a and 112 b can be polished using, for example, chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- the roughness of the polished bonding surfaces 112 a and 112 b can be less than 30 ⁇ rms.
- the roughness of the bonding surfaces 112 a and 112 b can be in a range of about 0.1 ⁇ rms to 15 ⁇ rms, 0.5 ⁇ rms to 10 ⁇ rms, or 1 ⁇ rms to 5 ⁇ rms.
- the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surfaces 112 a and 112 b .
- the bonding surfaces 112 a and 112 b can be terminated in a separate treatment to provide the additional species for direct bonding.
- the terminating species can comprise nitrogen.
- the bonding surface(s) 112 a , 112 b can be exposed to a nitrogen-containing plasma.
- the bonding surfaces 112 a and 112 b can be exposed to fluorine.
- conductive features 106 a of the first element 102 can also be directly bonded to corresponding conductive features 106 b of the second element 104 .
- a direct hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along the bond interface 118 that includes covalently direct bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces, prepared as described above.
- the conductor-to-conductor e.g., conductive feature 106 a to conductive feature 106 b
- direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques similar to those disclosed at least in U.S. Pat. Nos.
- non-conductive (e.g., dielectric) bonding surfaces 112 a , 112 b can be prepared and directly bonded to one another without an intervening adhesive as explained above.
- Conductive contact features e.g., conductive features 106 a and 106 b which may be partially or fully surrounded by non-conductive dielectric field regions within the bonding layers 108 a , 108 b
- the conductive features 106 a , 106 b can comprise discrete pads or traces at least partially embedded in the non-conductive field regions.
- the conductive contact features can comprise exposed contact surfaces of through substrate vias (e.g., through silicon vias (TSVs)).
- TSVs through silicon vias
- the respective conductive features 106 a and 106 b can be recessed below exterior (e.g., upper) surfaces (non-conductive bonding surfaces 112 a and 112 b ) of the dielectric field region or non-conductive bonding layers 108 a and 108 b , for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm.
- DBI® Direct Bond Interconnect
- the use of Direct Bond Interconnect, or DBI®, techniques commercially available from Adeia of San Jose, CA, can enable high density of conductive features 106 a and 106 b to be connected across the direct bond interface 118 (e.g., small or fine pitches for regular arrays).
- the conductive features 106 a and 106 b and/or traces can comprise copper or copper alloys, although other metals may be suitable.
- the conductive features disclosed herein, such as the conductive features 106 a and 106 b can comprise fine-grain metal (e.g., a fine-grain copper).
- at least one of the conductive features 106 a and 106 b is predominantly aluminum or includes a predominantly aluminum portion.
- wafer-to-wafer W2W
- D2D die-to-die
- D2W die-to-wafer
- W2W wafer-to-wafer
- two or more wafers can be directly bonded to one another (e.g., direct hybrid bonded) and subsequently singulated using a suitable singulation process.
- side edges of the singulated structure e.g., the side edges of the two bonded elements
- the first and second elements 102 and 104 can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface compared to a deposition.
- a width of the first element 102 in the bonded structure is similar to a width of the second element 104 .
- a width of the first element 102 in the bonded structure 100 is different from a width of the second element 104 .
- the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element.
- the first and second elements 102 and 104 can accordingly comprise non-deposited elements.
- directly bonded structures 100 can include a defect region along the bond interface 118 in which nanometer-scale voids (nanovoids) are present.
- the nanovoids may be formed due to activation of the bonding surfaces 112 a and 112 b (e.g., exposure to a plasma).
- the bond interface 118 can include concentration of materials from the activation and/or last chemical treatment processes.
- a nitrogen peak can be formed at the bond interface 118 .
- the nitrogen peak can be detectable using secondary ion mass spectroscopy (SIMS) techniques.
- SIMS secondary ion mass spectroscopy
- a nitrogen termination treatment e.g., exposing the bonding surface to a nitrogen-containing plasma
- a nitrogen-containing plasma can replace OH groups of a hydrolyzed (OH-terminated) surface with NH 2 molecules, yielding a nitrogen-terminated surface.
- an oxygen peak can be formed at the bond interface 118 .
- a fluorine peak can be formed at the bond interface 118 .
- the bond interface 118 can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.
- the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds.
- the bonding layers 108 a and 108 b can also comprise polished surfaces that are planarized to a high degree of smoothness.
- the bond interface 118 can extend substantially entirely to at least a portion of the bonded conductive features 106 a and 106 b , such that there is substantially no gap between the non-conductive bonding layers 108 a and 108 b at or near the bonded conductive features 106 a and 106 b .
- a barrier layer may be provided under and/or laterally surrounding the conductive features 106 a and 106 b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features 106 a and 106 b , for example, as described in U.S. Pat. No. 11,195,748, which is incorporated by reference herein in its entirety and for all purposes.
- the use of the direct hybrid bonding techniques described herein can enable extremely fine pitch between adjacent conductive features 106 a and 106 b , and/or small pad sizes.
- the pitch p i.e., the distance from edge-to-edge or center-to-center, as shown in FIG. 1 A
- the pitch p can be in a range of 0.5 microns to 100 microns, 0.5 microns to 50 microns, in a range of 0.75 microns to 25 microns, in a range of 1 micron to 25 microns, in a range of 1 micron to 10 microns, or in a range of 1 micron to 5 microns.
- a major lateral dimension (e.g., a pad diameter) can be small as well, e.g., in a range of 0.25 microns to 30 microns, in a range of 0.25 microns to 5 microns, or in a range of 0.5 microns to 5 microns.
- the non-conductive bonding layers 108 a , 108 b can be directly bonded to one another without an adhesive and, subsequently, the bonded structure 100 can be annealed.
- the conductive features 106 a , 106 b can expand and contact one another to form a metal-to-metal direct bond.
- the materials of the conductive features 106 a , 106 b can interdiffuse during the annealing process.
- FIG. 2 is a schematic cross-sectional side view of a bonded structure 1 .
- the bonded structure 1 includes a first element 10 and a second element 12 bonded by way of solder balls 14 .
- the first element 10 includes a first back end of line (BEOL) layer 16 and aluminum pads 18 .
- a polymer layer 20 can be disposed over a surface of the BEOL layer 16 for supporting the solder balls 14 .
- the second element 12 includes a second BEOL layer 26 and aluminum pads 28 .
- the solder balls 14 are provided with the first element 10 and bonded to the aluminum pads 28 of the second element 12 .
- solder balls 14 may not be feasible for relatively fine pitch interconnects, such as an interconnect pitch of less than 20 microns, or less than 2 microns. Additionally, because the mechanical connection between the elements 10 and 12 is limited to the solder joints, the mechanical connection can be weak and subject to separation from physical stresses or shocks because of the brittle intermetallic compound (IMC) typically formed with the solder balls. After bonding, the gap between the top surfaces of the BEOL layers 16 , 26 are cleaned and filled with a dielectric underfill material (not shown) to encapsulate the solder balls 14 and corresponding contacts. The resistivity of the alloy formed with the solder which is typically at least 3 times higher than that of an aluminum pad or copper post, can cause electrical losses.
- IMC brittle intermetallic compound
- the dielectric underfill that mechanically connects the top surfaces of the BEOL layers 16 , 26 impedes heat transfer between the first element 10 and the second element 12 . Therefore, it can be beneficial to provide a bond surface that can directly hybrid bond the elements 10 , 12 together.
- FIGS. 3 A- 3 E show a method of forming copper pads 32 over aluminum pads or interconnects 34 formed with a BEOL layer 16 of an element 30 .
- the BEOL layer 16 can be provided.
- the BEOL layer 16 can include a planar dielectric surface and aluminum pads or interconnects 34 that are at least partially embedded in the dielectric.
- the method includes forming a planarized dielectric layer 36 over the BEOL layer 16 .
- cavities 38 are formed in the dielectric layer 36 .
- the aluminum pads or interconnects 34 can be exposed through the cavities 38 .
- a barrier layer 40 and/or a seed layer can be formed over the dielectric layer 36 and surfaces of the cavities 38 .
- Copper 42 is provided at least in the cavities over the barrier layer 40 .
- copper 42 is overfilled and excess copper 42 is present over the surface of the dielectric layer 36 .
- the element 30 may be annealed at a temperature, for example, below 200° C., to at least partially stabilize the microstructure of copper 42 , if needed.
- the excess copper 42 can be removed in FIG. 3 E to form the copper pads 32 .
- the excess copper 42 can be removed, for example, by way of polishing, such as chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- the polishing process can also remove portions of the barrier layer 40 from over the surface of the dielectric layer 36 , and form a direct bonding surface of the element 30 after activation and/or termination as described above.
- aluminum pads 44 can be formed in a similar manner as the method of forming the copper pads 32 shown in FIGS. 3 A- 3 E .
- aluminum 46 can be provided in FIG. 4 D , and excess aluminum 46 can be removed to form the aluminum pads 44 .
- a blanket layer of aluminum can be deposited over the structure of FIG. 4 A and patterned with an appropriate masking process and the unwanted portions of the aluminum subsequently etched (e.g., by reactive ion etch).
- the dielectric bonding layer 36 is deposited over the patterned aluminum layer and polished back to the aluminum pads 44 to form a smooth dielectric bonding surface.
- the conductive features 72 are patterned from the aluminum layer 60 and thus can be considered aluminum features, but in other embodiments the conductive features 72 may comprise one or more other metal layers, while still constituting singular features defined by a single mask and still comprising more than 50% aluminum by volume. Thus, each of the conductive features 72 may have continuous sidewalls characteristic of definition by a single mask process.
- a dielectric layer 74 can be provided over the conductive features 72 and over portions of the BEOL layer 62 .
- the dielectric layer 74 can comprise an oxide layer.
- the oxide layer can be deposited at about 350° C. or other desirable temperatures by known methods.
- multiple dielectric coating steps with other intermediary process(es) may be applied to form the dielectric layer 74 .
- the dielectric coating may comprise a conformal coating (as shown) or nonconformal coating.
- the dielectric layer 74 may comprise a combination of conformal and nonconformal dielectric coatings.
- the dielectric layer 74 can be referred to as a nonconductive field region.
- the dielectric layer 74 is formed by sputtering, spin-on-deposition or other low temperature process.
- portions of the dielectric layer 74 can be removed (e.g., polished) to expose surfaces of the conductive features 72 .
- the surfaces of the conductive features 72 and surface of the remaining dielectric layer 74 can define the bonding surface 76 a of the element 76 .
- the bonding surface 76 a of the element 76 can be polished using, for example, chemical mechanical polishing (CMP), as disclosed herein. Either the CMP chemistry or a subsequent selective etch can recess the surface of the conductive features 72 below the dielectric layer 74 .
- the roughness of the polished bonding surface 76 a can be less than 30 ⁇ rms.
- the roughness of the bonding surface 76 a can be in a range of about 0.1 ⁇ rms to 15 ⁇ rms, 0.5 ⁇ rms to 10 ⁇ rms, or 1 ⁇ rms to 5 ⁇ rms.
- the conductive features 72 and surrounding dielectric layer 74 can be formed during the back-end-of-line process, such that element 76 may be as supplied by an integrated circuit manufacturer, before or after singulation.
- a thickness of the conductive features 72 can be in a range of about 0.5 ⁇ m to 7 ⁇ m or 1 ⁇ m to 5 ⁇ m.
- the barrier layer 153 may be omitted, and the fine grain aluminum layer 154 can be coated directly over the larger grain aluminum 73 .
- Fine grain aluminum can be defined as aluminum having an average grain dimension (e.g., width) less than 15 nm, less than 20 nm, less than 50 nm, less than 100 nm, less than 200 nm, less than 300 nm, or less than 500 nm.
- the fine grain aluminum layer 154 can be provided by way of a low temperature deposition.
- the fine grain aluminum layer 154 can be deposited at a temperature less than about 100° C., less than about 65° C., or less than about 20° C.
- a deposition temperature for depositing the fine grain aluminum layer 154 can be in a range between about 10° C. and 100° C., about 10° C. and 65° ° C., about 10° C. and 50° C., or about 10° C. and 20° C.
- a thickness of the fine grain aluminum layer 154 can be the same as or thicker than the depth of the recess 152 .
- the rinsing solution can comprise 1-ethyl-3-methylimidazolium tetrafluoroborate, 1-butyl-3-methylimidazolium tetrafluoroborate, tetramethylammonium tetrafluoroborate, tetramethylammonium tetrafluoroborate, hydrogen fluoride (HF), buffered hydrogen fluoride (BHF), or any suitable combination thereof.
- the bonding surface 150 a can be spin dried without rinsing with deionized (DI) water.
- the treated surface may be rinsed with DI water or other suitable solvents and dried by known methods, for example, by spin drying.
- the fluorine termination may be accomplished by way of a plasma process as described above.
- the bonding surface 150 a of the element 150 can be formed without a high temperature process. Therefore, the relatively small grain sizes of the fine grain aluminum layer 154 can be maintained, which can be advantageous for subsequent metal bonding.
- FIG. 6 F is a schematic cross-sectional side view of a bonded structure 3 that includes the element 150 and a second element 160 bonded to the element 150 .
- the second element 160 can have the same or generally similar structure as the element 150 .
- the second element 160 can include a BEOL layer 162 including interconnect features, a dielectric layer 164 , and conductive features 165 that includes an aluminum layer 166 and a fine grain aluminum layer 168 that together can serve as a pad.
- the bonding surface 150 a of the element 150 can be directly bonded to a bonding surface 160 a of the second element 160 along a bond interface 170 such that the dielectric layer 74 is directly bonded to the dielectric layer 164 .
- This initial direct bond of the dielectric materials can form strong covalent bonds between the dielectric layers 74 , 164 of the opposing elements 150 , 160 at room temperature.
- the second element 160 may be bonded to another substrate of interest.
- the bonded structure 3 formed in FIG. 6 F can be heated (e.g., annealed).
- the structure formed in FIG. 6 F can be annealed at a temperature lower than about 350° C., lower than about 300° C. or a temperature lower than about 250° C. for less than or equal to about 2 hours.
- the annealing temperature can be in a range between about 150° C. and 300° C., between about 200° C. and 300° C., or between about 200° C. and 250° C.
- the annealing process can cause expansion of the fine grain aluminum layers 154 , 168 across the gap left by the recessed aluminum surfaces and cause metal bonding between the fine grain aluminum layers 154 , 168 .
- Annealing can also strengthen the bond between the dielectric layers 74 , 164 .
- the grains of the fine grain aluminum layer 154 can grow due to the heating process. In some embodiments, the grains of the fine grain layer 154 can still be smaller than the grains of the aluminum layer 73 .
- an average grain dimension (e.g., width) of the grains in the fine grain aluminum layer 154 after annealing can be less than 1000 nm, 750 nm or 500 nm.
- the maximum width of the largest grain in the fine grain aluminum layer 154 after annealing can be in a range of about 20 nm to 500 nm.
- most of the grains in the fine grain aluminum layer 154 after annealing can have a width in a range of about 200 nm to 500 nm.
- the fine grain aluminum layer 154 can be deposited only on one of the bonded substrates.
- the fine grain aluminum layer 154 may comprise aluminum nanoparticles formed by physical vapor deposition (PVD) methods or atomic layer deposition (ALD) or other known methods.
- the element 150 can be a die or a wafer and the second element 160 can be a die or a wafer.
- the process for bonding the element 150 and the second element 160 can include wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes.
- the bonded structure 3 can include additional wafers, substrates, or dies stacked and bonded over the second element 160 .
- the stacked elements can be electrically connected via, for example, various TSVs.
- FIG. 6 H is a cross-sectional side view of singulated bonded structures 3 a , 3 b , 3 c .
- the singulated bonded structures 3 a , 3 b , 3 c can be formed by W2W bonding the element 150 and the second element 160 of FIG. 6 F followed by a singulation process.
- the singulation process can include attaching a bonded W2W structure to a dicing film or tape 172 , forming a protective layer 174 on the bonded W2W structure, and singulating the bonded W2W structure into a plurality of singulated structures, such as the singulated bonded structures 3 a , 3 b , 3 c .
- Each of the singulated bonded structures 3 a , 3 b , 3 c can include a die from the element 150 and a die from the second element 160 .
- FIG. 6 I is a cross-sectional side view of singulated elements 151 a , 151 b , 151 c after at least partial preparation for direct hybrid bonding but before actual bonding.
- the element 150 shown in FIG. 6 D can comprise a wafer from which the singulated elements 151 a , 151 b , 151 c can be formed.
- the element 150 in form of a wafer can be positioned on a dicing film or tape 172 .
- a protective layer 174 can be formed on the element 150 .
- the element 150 can be singulated into the singulated elements 151 a , 151 b , 151 c . After singulation, the protective layer 174 can be removed as shown in FIG. 6 J .
- FIGS. 7 A to 7 E show a method of forming a bonding surface 200 a of an element 200 according to an embodiment.
- FIG. 7 A is a schematic cross-sectional side view showing aluminum layer 202 and dielectric layer 74 formed over a back end of line (BEOL) or RDL layer 62 that includes an interconnect structure 66 .
- BEOL back end of line
- RDL layer 62 that includes an interconnect structure 66 .
- the structure of FIG. 7 A can be the same as or generally similar to the structure of FIGS. 5 E and 6 A .
- At least a portion of the aluminum layer 202 can be removed to form a recess 152 over each aluminum layer 202 .
- a depth of the recess can be in a range of 0.1 ⁇ m to 0.5 ⁇ m, 0.1 ⁇ m to 0.35 ⁇ m, or 0.15 ⁇ m to 0.25 ⁇ m.
- the portion of the aluminum layer 202 can be removed by way of, for example, dry etching (e.g., vapor or plasma etching) or wet etching.
- a barrier layer 153 and a different type of conductive material, such as the illustrated copper layer 204 can be provided in the recess 152 and over the surface 74 a of the dielectric layer 74 .
- the copper layer 204 is an example of the different type of conductive material and another example can include a silver layer.
- the copper layer 204 can comprise fine grain copper having an average grain width less than about 15 nm, less than about 20 nm, less than about 50 nm, less than about 100 nm, less than about 200 nm, less than about 300 nm, or less than about 500 nm.
- the maximum width of grains in the copper layer 204 can be in a range of about 10 nm to 500 nm, about 10 nm to 300 nm, about 15 nm to 500 nm, about 15 nm to 300 nm, about 15 nm to 100 nm, about 15 nm to 50 nm, about 50 nm to 500 nm, about 50 nm to 300 nm, or about 100 nm to 300 nm.
- most of the grains in the fine grain copper layer 204 can have a width in a range of about 10 nm to 500 nm, about 10 nm to 300 nm, about 15 nm to 500 nm, about 15 nm to 300 nm, about 15 nm to 100 nm, about 15 nm to 50 nm, about 50 nm to 500 nm, about 50 nm to 300 nm, or about 100 nm to 300 nm.
- the different conductive layer may be coated by electroless or electroplating methods.
- the different conductive layer may be coated by printing methods, or by physical vapor deposition (PVD) methods, such as evaporation or sputtering.
- the different conductive layer may comprise nanoparticle copper, nanoparticle silver, or other nanoparticle metals. The nanoparticle metals may be coated by electroless or electrolytic or by low temperature sputtering, amongst other methods.
- the copper layer 204 can be provided by way of a low temperature deposition.
- the copper layer 204 can be deposited at a temperature less than 100° C., less than 65° ° C., or less than 20° C.
- a deposition temperature for depositing the copper layer 204 can be in a range between 1° C. and 10° C., 10° C. and 100° C., 10° C. and 65° C., 10° C. and 50° C., or 10° C. and 35° C.
- a thickness of the copper layer 204 can be the same as or generally similar to the depth of the recess 152 .
- the copper layer 204 can be deposited by physical deposition (e.g., sputtered) rather than plated. By the nature of the deposition process, the copper layer 204 can have a mostly 111 texture, and a randomly oriented grain structure.
- portions of the barrier layer 153 and the copper layer 204 over the surface 74 a of the dielectric layer 74 can be removed.
- the portion of the barrier layer 153 and the copper layer 204 over the dielectric layer 74 can be removed by way of polishing (e.g., chemical mechanical polishing (CMP)) to define the bonding surface 200 a of the element 200 that includes the surface 74 a of the dielectric layer 74 and a surface 204 a of the copper layer 204 .
- polishing e.g., chemical mechanical polishing (CMP)
- CMP chemical mechanical polishing
- the CMP process to form the dielectric bonding surface 200 a may polish off very small portion of the dielectric material 74 in the barrier layer 153 removal step.
- the upper copper layer 204 and lower aluminum layer 202 have their sidewalls or lateral extents defined by the same mask (e.g., mask for etching either aluminum to form the aluminum layer 202 or for etching dielectric layer 74 for filling with aluminum), the sidewalls of the upper and lower portions are continuous, without discontinuities (e.g., corners) typical of misalignment when the upper and lower portions are defined by separate masks.
- At least the lower aluminum layer 202 comprises aluminum.
- the copper layer 204 comprises copper or other conductive material (e.g., silver), though in other embodiments the upper portion can also comprise fine grain aluminum.
- the conductive feature 206 can have a first portion (e.g., the aluminum layer 73 ) and a second portion (e.g., the upper copper layer 204 ).
- the second portion can have a microstructure different from the first portion.
- a thickness of the conductive feature 206 can be in a range of about 0.5 ⁇ m to 7 ⁇ m or 1 ⁇ m to 5 ⁇ m.
- the bonding surface 200 a of the element 200 can be cleaned and exposed to a plasma and/or etchants to activate the bonding surface 200 a .
- the bonding surface 200 a of the element 200 can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes).
- the activation process can be performed to break chemical bonds at the bonding surface 200 a of the element 200 , and the termination process can provide additional chemical species at the bonding surface 200 a that improves the bonding energy during direct bonding.
- the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the bonding surface 200 a of the element 200 .
- the bonding surface 200 a of the element 200 can be terminated in a separate treatment to provide the additional species for direct bonding.
- the bonding surface 200 a can include concentration of materials from the activation and/or last chemical treatment processes.
- a nitrogen peak can be formed at the bonding surface 200 a .
- the nitrogen peak can be detectable using secondary ion mass spectroscopy (SIMS) techniques.
- a nitrogen termination treatment e.g., exposing the bonding surface to a nitrogen-containing plasma
- a nitrogen-containing plasma can replace OH groups of a hydrolyzed (OH-terminated) surface with NH 2 molecules, yielding a nitrogen-terminated surface.
- an oxygen peak can be formed at the bonding surface 200 a .
- the bonding surface 200 a can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.
- the element 200 can be a die or a wafer, and the element 200 can be bonded to another element (e.g., a wafer or a die).
- FIG. 7 F is a schematic cross sectional side view of a bonded structure 5 that includes the element 200 in form of a wafer and a second element 220 (another wafer) bonded to the element 200 along a bond interface 221 .
- the second element 220 can comprise a BEOL layer 222 , a dielectric layer 224 , and a conductive feature 232 that can also include a lower portion 228 (e.g., aluminum) and an upper portion 230 (e.g., copper) as shown.
- the dielectric layer 74 and the dielectric layer 224 can be directly bonded to one another without an intervening adhesive, and the copper layer 204 and the upper layer 230 (e.g., copper layer) can be directly bonded to one another without an intervening adhesive.
- additional wafers or substrates e.g., 1 to 8 wafers
- the bonded wafer or substrate stack may be singulated for subsequent processes.
- additional dies e.g., 1 to 40 dies
- the wafer or substrate with bonded dies can be singulated for subsequent processing.
- One of the subsequent processes can comprise encapsulating the sides of the singulated stack in a dielectric layer.
- the encapsulating dielectric layer comprises a molding material.
- the element 200 can be singulated into singulated elements prior to bonding, in some embodiments.
- the singulated elements can be bonded to another element (e.g., a wafer or a die) as described herein.
- any two or more elements disclosed herein can be bonded to define various bonded structures.
- any two or more of the elements 76 , 150 , 200 can be bonded to define a bonded structure.
- aluminum-based features such as contact pads
- an aluminum feature can be defined and, without additional high temperature depositions or masking steps, treated for direct hybrid bonding.
- no masking steps or insulating layer depositions are shown after the aluminum features are defined (e.g., at the stage of FIG. 5 E ). Consequently, in all of the illustrated embodiments, a metal contact feature prepared for direct hybrid bonding can have a continuous sidewall, characteristic of definition with a single masking process, with a lower aluminum portion and either an upper aluminum portion with fluorine treatment or an upper copper portion.
- FIGS. 6 A- 6 L and 7 A- 7 F can employ recessing and redeposition of metal to form different upper portions of the contact feature compared to lower portions (e.g., different aluminum grain structures or copper on top and aluminum on the bottom), but even these embodiments do not rely on additional insulator depositions or mask steps, such that the contact feature having a lower aluminum portion and a different metal upper portion still has a continuous sidewall characteristic of definition by a single masking process.
- the recessing, metal redeposition and CMP steps of FIGS. 6 A- 7 F can all be performed at low temperatures compared to oxide deposition.
- a method of forming a bonding surface for direct hybrid bonding can include providing an element having a nonconductive field region and an aluminum feature, and exposing a surface of the aluminum feature to fluorine. The surface of the aluminum feature and the surface of the nonconductive field region define the direct bonding surface.
- exposing the surface of the aluminum feature to fluorine suppresses aluminum oxide formation.
- the method further includes providing an aluminum layer over a back-end-of-line (BEOL) layer, removing at least a portion of the aluminum layer to define the aluminum feature, and providing a dielectric material proximate to the aluminum feature to define the nonconductive field region.
- BEOL back-end-of-line
- the aluminum feature includes a first portion and a second portion over the first portion and at least partially defining the surface of the aluminum feature.
- the second portion can include an average grain size smaller than an average grain size of the first portion.
- the method can further include removing metal from an initial aluminum feature to leave the first portion below a recess of about 0.1 ⁇ m to 0.3 ⁇ m relative to the surface of the nonconductive field region, and depositing the second portion into the recess over the first portion.
- the second portion can have a microstructure different from the first portion.
- the second portion can be deposited at a deposition temperature below about 100° C. Most of the grains in the second portion can have a width in a range of 10 nm to 500 nm.
- the aluminum feature can have a continuous sidewall along a sidewall of the first portion and a sidewall of the second portion.
- a thickness of the aluminum feature is in a range of about 0.5 ⁇ m to 7 ⁇ m.
- the thickness of the aluminum feature can be in a range of about 1 ⁇ m to 5 ⁇ m.
- the element includes an aluminum interconnect structure electrically connected to the aluminum feature.
- exposing the surface of the aluminum feature to fluorine includes forming aluminum fluoride, aluminum fluoride oxide, or aluminum fluoride boron oxide. Exposing the surface of the aluminum feature to fluorine can include forming at least a portion that is free from aluminum oxide.
- exposing the surface of the aluminum feature to fluorine includes exposing the surface to a rinsing solution comprising 1-ethyl-3-methylimidazolium tetrafluoroborate, 1-butyl-3-methylimidazolium tetrafluoroborate, tetramethylammonium tetrafluoroborate, tetramethylammonium tetrafluoroborate, or hydrogen fluoride (HF).
- a rinsing solution comprising 1-ethyl-3-methylimidazolium tetrafluoroborate, 1-butyl-3-methylimidazolium tetrafluoroborate, tetramethylammonium tetrafluoroborate, tetramethylammonium tetrafluoroborate, or hydrogen fluoride (HF).
- exposing the surface of the aluminum feature to fluorine without exposing the aluminum feature to nitrogen plasma or ammonium dip.
- a forming method of forming a bonded structure includes providing the element formed using the method, providing a second element having a second nonconductive field region and a conductive feature, directly bonding the nonconductive field region and the second nonconductive field region without an intervening adhesive, and directly bonding the aluminum feature and the conductive feature without an intervening adhesive.
- a direct hybrid bonded structure can include a first element having a first nonconductive field region and a first aluminum feature. A surface of the first nonconductive field region and a surface of the first aluminum feature at least partially define a bonding surface of the first element.
- the bonded structure can include a second element having a second nonconductive field region and a second aluminum feature. A surface of the second nonconductive field region is directly bonded to the first nonconductive field region without an intervening adhesive along a bond interface and a surface of the second aluminum feature is directly bonded to the second aluminum feature without an intervening adhesive along the bond interface.
- the surface of the first aluminum feature includes a higher fluorine content than a portion of the first aluminum feature further away from the surface.
- the bond interface between the first and second aluminum features include one or multiple fluorine peaks.
- the first aluminum feature includes a first gradient of fluorine concentration decreasing away from the bond interface.
- the second aluminum feature can include a second gradient of fluorine concentration decreasing away from the bond interface.
- the first aluminum feature includes a first portion and a second portion over the first portion and at least partially defining the surface of the first aluminum feature.
- the second portion can include an average grain size smaller than an average grain size of the first portion. Most of the grains in the second portion can have a width in a range of 10 nm to 500 nm.
- the first aluminum feature can further include a barrier layer between the first and second portions.
- the bond interface between the first and second aluminum features includes less than 1000 ppm of oxygen.
- the bond interface between the first and second aluminum features includes less than 100 ppm of nitrogen.
- an element having a bonding surface configured to directly hybrid bond to another element can include a nonconductive field region, and an aluminum feature. A surface of the nonconductive field region and a surface of the aluminum feature together define the bonding surface of the element.
- the surface of the aluminum feature includes aluminum and fluorine.
- the aluminum feature has a thickness in a range of about 0.5 ⁇ m to 5 ⁇ m.
- the thickness of the aluminum feature can be in a range of about 1 ⁇ m to 3 ⁇ m.
- the aluminum feature includes a first portion and a second portion over the first portion.
- the second portion can define the surface of the aluminum feature.
- the second portion can include an average grain size smaller than an average grain size of the first portion. Most of the grains in the second portion can have a width in a range of 10 nm to 500 nm.
- a thickness of the second portion can be in a range of 0.1 ⁇ m to 0.3 ⁇ m.
- the surface of the aluminum feature is recessed from the surface of the nonconductive field region by about 2 nm to 20 nm.
- a bonded structure can include a first element having a first nonconductive field region and a first conductive feature. A surface of the first nonconductive field region and a surface of the first conductive feature at least partially define a bonding surface of the first element.
- the first conductive feature includes a first portion and a second portion over the first portion and at least partially defines the surface of the first conductive feature.
- the first portion includes aluminum.
- the first conductive feature has a continuous sidewall along the first portion and the second portion.
- the second portion includes different metal composition from the first portion or includes fluorine at the surface of the first conductive feature.
- the bonded structure can include a second element having a second nonconductive field region and a second conductive feature. A surface of the second nonconductive field region that is directly bonded to the first nonconductive field region without an intervening adhesive along a bond interface and a surface of the second conductive feature that is directly bonded to the second conductive feature without an intervening adhesive along the bond interface.
- the second portion has an average grain size that is smaller than an average grain size of the second portion. Most of grains in the second portion can have a width in a range of 10 nm to 500 nm.
- the aluminum feature has a thickness in a range of 0.5 ⁇ m to 5 ⁇ m, and the second portion has a thickness in a range of 0.1 ⁇ m to 0.3 ⁇ m.
- the first and second portions can have different metal structures.
- the second portion can include aluminum.
- the surface of the conductive feature can include aluminum fluoride.
- the second portion can include copper.
- an element having a bonding surface configured to directly bond to another element can include a nonconductive field region and a conductive feature that includes a first portion and a second portion over the first portion and at least partially defines a surface of the conductive feature.
- the first portion includes aluminum.
- the conductive feature has a continuous sidewall along the first portion and the second portion.
- the second portion includes different metal composition from the first portion or includes fluorine at the surface of the first conductive feature.
- a surface of the nonconductive field region and a surface of the aluminum feature together define the bonding surface of the element.
- the second portion has an average grain size that is smaller than an average grain size of the second portion. Most of grains in the second portion can have a width in a range of 10 nm to 500 nm.
- the aluminum feature has a thickness in a range of about 0.5 ⁇ m to 5 ⁇ m
- the second portion has a thickness in a range of about 0.1 ⁇ m to 0.3 ⁇ m.
- the second portion can include aluminum.
- the surface of the conductive feature can include aluminum fluoride.
- the second portion can include copper.
- a method of forming an element having a bonding surface configured to directly bond to another element can include forming a nonconductive field region and a first portion of a conductive feature.
- the first portion comprising aluminum.
- the method can include forming a second portion of the conductive feature over the first portion.
- the second portion at least partially defines a surface of the conductive feature.
- the first and second portions are defined by a single masking process.
- the second portion includes a different metal composition from the first portion or includes fluorine at the surface of the first conductive feature.
- a surface of the nonconductive field region and a surface of the conductive feature together define the bonding surface of the element.
- the second portion includes fine grain aluminum.
- the second portion includes aluminum and fluorine.
- the method further includes exposing the surface of the conductive feature to fluorine. Exposing the surface of the conductive feature to fluorine can suppress aluminum oxide formation. Exposing the surface of the aluminum feature to fluorine can be conducted without exposing the aluminum feature to nitrogen plasma or ammonium dip.
- the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.”
- the word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
- the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
- conditional language used herein such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing & Machinery (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Wire Bonding (AREA)
Abstract
Description
| TABLE 1 | |||||
| Materials | Melting point | Thermal Expansion | |||
| Al | 660° | C. | 23 | ppmK−1 | |
| Al2O3 | 2977° | C. | 4.5 | ppmK−1 | |
| AlN | 2200° | C. | 5.3 | ppmK−1 |
| AlF3 | 1250° | C. | αv - 86 ppmK−1 | ||
Claims (51)
Priority Applications (7)
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| US18/148,332 US12506114B2 (en) | 2022-12-29 | 2022-12-29 | Directly bonded metal structures having aluminum features and methods of preparing same |
| PCT/US2023/084424 WO2024145034A1 (en) | 2022-12-29 | 2023-12-15 | Directly bonded metal structures having aluminum features and methods of preparing same |
| CN202380092789.5A CN120604336A (en) | 2022-12-29 | 2023-12-15 | Directly bonded metal structure with aluminum features and method for making the same |
| KR1020257024457A KR20250130627A (en) | 2022-12-29 | 2023-12-15 | Directly bonded metal structure having aluminum features and method for preparing the same |
| EP23913462.0A EP4643383A1 (en) | 2022-12-29 | 2023-12-15 | Directly bonded metal structures having aluminum features and methods of preparing same |
| JP2025538374A JP2025542482A (en) | 2022-12-29 | 2023-12-15 | Direct bonded metal structure with aluminum features and method of making same |
| TW112149511A TW202429589A (en) | 2022-12-29 | 2023-12-19 | Directly bonded metal structures having aluminum features and methods of preparing same |
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| US18/148,332 US12506114B2 (en) | 2022-12-29 | 2022-12-29 | Directly bonded metal structures having aluminum features and methods of preparing same |
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| US20240222315A1 US20240222315A1 (en) | 2024-07-04 |
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| EP (1) | EP4643383A1 (en) |
| JP (1) | JP2025542482A (en) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20250149499A1 (en) * | 2023-11-08 | 2025-05-08 | Globalfoundries U.S. Inc. | Hybrid bonding with selectively formed dielectric material |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
| US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
| US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
| CN117878055A (en) | 2016-12-28 | 2024-04-12 | 艾德亚半导体接合科技有限公司 | Stacking substrate processing |
| US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
| US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
| US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
| US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
| US10991804B2 (en) | 2018-03-29 | 2021-04-27 | Xcelsis Corporation | Transistor level interconnection methodologies utilizing 3D interconnects |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
| US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
| CN112585740B (en) | 2018-06-13 | 2025-05-13 | 隔热半导体粘合技术公司 | TSV as a pad |
| US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
| US11158606B2 (en) | 2018-07-06 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
| US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
| US12406959B2 (en) | 2018-07-26 | 2025-09-02 | Adeia Semiconductor Bonding Technologies Inc. | Post CMP processing for hybrid bonding |
| US11387202B2 (en) | 2019-03-01 | 2022-07-12 | Invensas Llc | Nanowire bonding interconnect for fine-pitch microelectronics |
| US11610846B2 (en) | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
| US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
| US11355404B2 (en) | 2019-04-22 | 2022-06-07 | Invensas Bonding Technologies, Inc. | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
| US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
| US12374641B2 (en) | 2019-06-12 | 2025-07-29 | Adeia Semiconductor Bonding Technologies Inc. | Sealed bonded structures and methods for forming the same |
| US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
| US11862602B2 (en) | 2019-11-07 | 2024-01-02 | Adeia Semiconductor Technologies Llc | Scalable architecture for reduced cycles across SOC |
| US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
| US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
| US11842894B2 (en) | 2019-12-23 | 2023-12-12 | Adeia Semiconductor Bonding Technologies Inc. | Electrical redundancy for bonded structures |
| US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
| US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
| KR20230097121A (en) | 2020-10-29 | 2023-06-30 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Direct bonding method and structure |
| KR20230125309A (en) | 2020-12-28 | 2023-08-29 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Structures having through-substrate vias and methods for forming the same |
| EP4268274A4 (en) | 2020-12-28 | 2024-10-30 | Adeia Semiconductor Bonding Technologies Inc. | STRUCTURES WITH SUBSTRATE PASSAGES AND METHODS FOR FORMING THE SAME |
| KR20230126736A (en) | 2020-12-30 | 2023-08-30 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Structures with Conductive Features and Methods of Forming The Same |
| EP4315398A4 (en) | 2021-03-31 | 2025-03-05 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding and debonding of carrier |
| KR20240036698A (en) | 2021-08-02 | 2024-03-20 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Protective semiconductor elements for combined structures |
| EP4406020A4 (en) | 2021-09-24 | 2026-01-21 | Adeia Semiconductor Bonding Technologies Inc | STRUCTURE LINKED WITH ACTIVE INTERPOSER |
| WO2023122509A1 (en) | 2021-12-20 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling for die packages |
| US12341083B2 (en) | 2023-02-08 | 2025-06-24 | Adeia Semiconductor Bonding Technologies Inc. | Electronic device cooling structures bonded to semiconductor elements |
Citations (390)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939568A (en) | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
| US4998665A (en) | 1988-09-07 | 1991-03-12 | Nec Corporation | Bonding structure of substrates and method for bonding substrates |
| US5087585A (en) | 1989-07-11 | 1992-02-11 | Nec Corporation | Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit |
| US5236118A (en) | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
| US5322593A (en) | 1991-11-21 | 1994-06-21 | Nec Corporation | Method for manufacturing polyimide multilayer wiring substrate |
| US5413952A (en) | 1994-02-02 | 1995-05-09 | Motorola, Inc. | Direct wafer bonded structure method of making |
| US5421953A (en) | 1993-02-16 | 1995-06-06 | Nippondenso Co., Ltd. | Method and apparatus for direct bonding two bodies |
| US5442235A (en) | 1993-12-23 | 1995-08-15 | Motorola Inc. | Semiconductor device having an improved metal interconnect structure |
| CN1112286A (en) | 1994-05-19 | 1995-11-22 | 陆敬良 | Durable neon lamp and its making technique |
| US5489804A (en) | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5501003A (en) | 1993-12-15 | 1996-03-26 | Bel Fuse Inc. | Method of assembling electronic packages for surface mount applications |
| US5503704A (en) | 1993-01-06 | 1996-04-02 | The Regents Of The University Of California | Nitrogen based low temperature direct bonding |
| US5516727A (en) | 1993-04-19 | 1996-05-14 | International Business Machines Corporation | Method for encapsulating light emitting diodes |
| US5610431A (en) | 1995-05-12 | 1997-03-11 | The Charles Stark Draper Laboratory, Inc. | Covers for micromechanical sensors and other semiconductor devices |
| US5734199A (en) | 1995-12-18 | 1998-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having improved test electrodes |
| US5753536A (en) | 1994-08-29 | 1998-05-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and associated fabrication method |
| US5771555A (en) | 1993-11-01 | 1998-06-30 | Matsushita Electric Industrial Co., Ltd. | Method for producing an electronic component using direct bonding |
| US5821692A (en) | 1996-11-26 | 1998-10-13 | Motorola, Inc. | Organic electroluminescent device hermetic encapsulation package |
| US5866942A (en) | 1995-04-28 | 1999-02-02 | Nec Corporation | Metal base package for a semiconductor device |
| US5904860A (en) | 1995-09-12 | 1999-05-18 | Nippondenso Co., Ltd. | Method for direct bonding nitride bodies |
| US5985739A (en) | 1994-09-19 | 1999-11-16 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Semiconductor structures having advantageous high-frequency characteristics and processes for producing such semiconductor structures |
| US5998808A (en) | 1997-06-27 | 1999-12-07 | Sony Corporation | Three-dimensional integrated circuit device and its manufacturing method |
| US6008126A (en) | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
| US6063968A (en) | 1996-05-14 | 2000-05-16 | Degussa Aktiengesellschaft | Method for the production of trimethylhydroquinone |
| US6071761A (en) | 1997-03-18 | 2000-06-06 | Jacobs; Richard L. | Method for encapsulated integrated circuits |
| US6080640A (en) | 1997-07-11 | 2000-06-27 | Advanced Micro Devices, Inc. | Metal attachment method and structure for attaching substrates at low temperatures |
| JP2000183061A (en) | 1998-12-18 | 2000-06-30 | Rohm Co Ltd | Manufacture of semiconductor device |
| US6117784A (en) | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| US6123825A (en) | 1998-12-02 | 2000-09-26 | International Business Machines Corporation | Electromigration-resistant copper microstructure and process of making |
| US6147000A (en) | 1998-08-11 | 2000-11-14 | Advanced Micro Devices, Inc. | Method for forming low dielectric passivation of copper interconnects |
| US6232150B1 (en) | 1998-12-03 | 2001-05-15 | The Regents Of The University Of Michigan | Process for making microstructures and microstructures made thereby |
| US6259160B1 (en) | 1999-04-21 | 2001-07-10 | Advanced Micro Devices, Inc. | Apparatus and method of encapsulated copper (Cu) Interconnect formation |
| US6258625B1 (en) | 1999-05-18 | 2001-07-10 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
| US6265775B1 (en) | 1997-01-24 | 2001-07-24 | Micron Technology, Inc. | Flip chip technique for chip assembly |
| US6297072B1 (en) | 1998-04-17 | 2001-10-02 | Interuniversitair Micro-Elktronica Centrum (Imec Vzw) | Method of fabrication of a microstructure having an internal cavity |
| US6316786B1 (en) | 1998-08-29 | 2001-11-13 | International Business Machines Corporation | Organic opto-electronic devices |
| US6333206B1 (en) | 1996-12-24 | 2001-12-25 | Nitto Denko Corporation | Process for the production of semiconductor device |
| US6333120B1 (en) | 1999-10-27 | 2001-12-25 | International Business Machines Corporation | Method for controlling the texture and microstructure of plated copper and plated structure |
| US20020000328A1 (en) | 2000-06-22 | 2002-01-03 | Kabushiki Kaisha Toshiba | Printed wiring board and manufacturing method thereof |
| US20020003307A1 (en) | 2000-07-05 | 2002-01-10 | Tadatomo Suga | Semiconductor device and method for fabricating the device |
| US6348709B1 (en) | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
| US20020025665A1 (en) | 2000-08-29 | 2002-02-28 | Werner Juengling | Method of forming a metal to polysilicon contact in oxygen environment |
| US6374770B1 (en) | 1995-10-26 | 2002-04-23 | Applied Materials, Inc. | Apparatus for improving film stability of halogen-doped silicon oxide films |
| US20020047208A1 (en) | 1999-08-18 | 2002-04-25 | Cyprian Emeka Uzoh | Method and structure for improving electromigration of chip interconnects |
| US20020074670A1 (en) | 1999-04-13 | 2002-06-20 | Tadatomo Suga | Method for manufacturing an interconnect structure for stacked semiconductor device |
| US6409904B1 (en) | 1998-12-01 | 2002-06-25 | Nutool, Inc. | Method and apparatus for depositing and controlling the texture of a thin film |
| US20020094661A1 (en) | 1999-10-01 | 2002-07-18 | Ziptronix | Three dimensional device intergration method and intergrated device |
| US6423640B1 (en) | 2000-08-09 | 2002-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Headless CMP process for oxide planarization |
| US6433402B1 (en) | 2000-11-16 | 2002-08-13 | Advanced Micro Devices, Inc. | Selective copper alloy deposition |
| JP2002353416A (en) | 2001-05-25 | 2002-12-06 | Sony Corp | Semiconductor storage device and method of manufacturing the same |
| US6528894B1 (en) | 1996-09-20 | 2003-03-04 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| US6552436B2 (en) | 2000-12-08 | 2003-04-22 | Motorola, Inc. | Semiconductor device having a ball grid array and method therefor |
| US6555917B1 (en) | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
| US20030092220A1 (en) | 2000-06-08 | 2003-05-15 | Salman Akram | Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed |
| US6579744B1 (en) | 1998-02-27 | 2003-06-17 | Micron Technology, Inc. | Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive |
| US6583515B1 (en) | 1999-09-03 | 2003-06-24 | Texas Instruments Incorporated | Ball grid array package for enhanced stress tolerance |
| US6589813B1 (en) | 1999-06-28 | 2003-07-08 | Hyundai Electronics Industries Co., Ltd. | Chip size stack package and method of fabricating the same |
| US6600224B1 (en) | 2000-10-31 | 2003-07-29 | International Business Machines Corporation | Thin film attachment to laminate using a dendritic interconnection |
| US20030157748A1 (en) | 2002-02-20 | 2003-08-21 | Kim Sarah E. | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| US6624003B1 (en) | 2002-02-06 | 2003-09-23 | Teravicta Technologies, Inc. | Integrated MEMS device and package |
| US6627814B1 (en) | 2002-03-22 | 2003-09-30 | David H. Stark | Hermetically sealed micro-device package with window |
| US6632377B1 (en) | 1998-10-23 | 2003-10-14 | International Business Machines Corporation | Chemical-mechanical planarization of metallurgy |
| US6660564B2 (en) | 2002-01-25 | 2003-12-09 | Sony Corporation | Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby |
| US6667225B2 (en) | 2001-12-17 | 2003-12-23 | Intel Corporation | Wafer-bonding using solder and method of making the same |
| US20040052390A1 (en) | 2002-09-12 | 2004-03-18 | Nelson Morales | Method and apparatus for programming a hearing device |
| US20040052930A1 (en) | 2000-04-27 | 2004-03-18 | Bulent Basol | Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization |
| US20040084414A1 (en) | 2002-08-19 | 2004-05-06 | Kenji Sakai | Polishing method and polishing composition used for polishing |
| US6758388B1 (en) | 2001-02-27 | 2004-07-06 | Rohr, Inc. | Titanium aluminide honeycomb panel structures and fabrication method for the same |
| US20040238492A1 (en) | 2003-04-23 | 2004-12-02 | Catabay Wilbur G. | Planarization with reduced dishing |
| US6864585B2 (en) | 2000-03-22 | 2005-03-08 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
| WO2005043584A2 (en) | 2003-10-21 | 2005-05-12 | Ziptronix, Inc. | Single mask via method and device |
| US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US6909194B2 (en) | 1999-08-27 | 2005-06-21 | Micron Technology, Inc. | Electronic assembly having semiconductor component with polymer support member and method of fabrication |
| US6908027B2 (en) | 2003-03-31 | 2005-06-21 | Intel Corporation | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process |
| US6962835B2 (en) | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
| US20060024950A1 (en) | 2004-08-02 | 2006-02-02 | Suk-Hun Choi | Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same |
| US20060057945A1 (en) | 2004-09-16 | 2006-03-16 | Chia-Lin Hsu | Chemical mechanical polishing process |
| US7045453B2 (en) | 2002-10-24 | 2006-05-16 | International Business Machines Corporation | Very low effective dielectric constant interconnect structures and methods for fabricating the same |
| US7105980B2 (en) | 2002-07-03 | 2006-09-12 | Sawtek, Inc. | Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics |
| US7109063B2 (en) | 2003-02-12 | 2006-09-19 | Micron Technology, Inc. | Semiconductor substrate for build-up packages |
| US20060220197A1 (en) | 2005-03-16 | 2006-10-05 | Kobrinsky Mauro J | Method of forming self-passivating interconnects and resulting devices |
| US7193423B1 (en) | 2005-12-12 | 2007-03-20 | International Business Machines Corporation | Wafer-to-wafer alignments |
| US20070096294A1 (en) | 2003-06-06 | 2007-05-03 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
| US7238919B2 (en) | 2005-03-15 | 2007-07-03 | Kabushiki Kaisha Toshiba | Heating element movement bonding method for semiconductor components |
| US20080073795A1 (en) | 2006-09-24 | 2008-03-27 | Georgia Tech Research Corporation | Integrated circuit interconnection devices and methods |
| US7354798B2 (en) | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
| US20080122092A1 (en) | 2006-11-29 | 2008-05-29 | Ji Ho Hong | Semiconductor Device and Method of Manufacturing the Same |
| KR20080050129A (en) | 2006-12-01 | 2008-06-05 | 삼성전자주식회사 | Photodiode and image sensor using it |
| US20080237053A1 (en) | 2002-12-04 | 2008-10-02 | International Business Machines Corporation | Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel |
| US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
| WO2009021266A1 (en) | 2007-08-15 | 2009-02-19 | Christophe Alain Guex | Vessel transporting apparatus and method |
| US20090197408A1 (en) | 2008-01-31 | 2009-08-06 | Matthias Lehr | Increasing electromigration resistance in an interconnect structure of a semiconductor device by forming an alloy |
| US20090200668A1 (en) | 2008-02-07 | 2009-08-13 | International Business Machines Corporation | Interconnect structure with high leakage resistance |
| US7750488B2 (en) | 2006-07-10 | 2010-07-06 | Tezzaron Semiconductor, Inc. | Method for bonding wafers to produce stacked integrated circuits |
| US7803693B2 (en) | 2007-02-15 | 2010-09-28 | John Trezza | Bowed wafer hybridization compensation |
| US20100255262A1 (en) | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| US20100327443A1 (en) | 2008-02-22 | 2010-12-30 | Barun Electronics, Co., Ltd. | Joining structure and a substrate-joining method using the same |
| US20110074040A1 (en) | 2009-09-29 | 2011-03-31 | Manfred Frank | Semiconductor Device And Method For Making Same |
| US20110076787A1 (en) | 2009-09-25 | 2011-03-31 | Iftikhar Ahmad | Method and apparatus for uniform microwave treatment of semiconductor wafers |
| US20110084403A1 (en) | 2009-10-08 | 2011-04-14 | International Business Machines Corporation | Pad bonding employing a self-aligned plated liner for adhesion enhancement |
| US7998335B2 (en) | 2005-06-13 | 2011-08-16 | Cabot Microelectronics Corporation | Controlled electrochemical polishing method |
| US8039966B2 (en) | 2009-09-03 | 2011-10-18 | International Business Machines Corporation | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects |
| US8101858B2 (en) | 2006-03-14 | 2012-01-24 | Corus Technology B.V. | Chalcopyrite semiconductor based photovoltaic solar cell comprising a metal substrate, coated metal substrate for a photovoltaic solar cell and manufacturing method thereof |
| US8168532B2 (en) | 2007-11-14 | 2012-05-01 | Fujitsu Limited | Method of manufacturing a multilayer interconnection structure in a semiconductor device |
| US8242600B2 (en) | 2009-05-19 | 2012-08-14 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
| US8241961B2 (en) | 2008-12-09 | 2012-08-14 | Young Hae KIM | Method for manufacturing hetero-bonded wafer |
| US20120212384A1 (en) | 2011-02-17 | 2012-08-23 | International Business Machines Corporation | Integrated antenna for rfic package applications |
| US20120211894A1 (en) | 2011-02-23 | 2012-08-23 | Sony Corporation | Joining electrode, method of manufacturing the same, semiconductor device, and method of manufacturing the same |
| US8314007B2 (en) | 2009-12-23 | 2012-11-20 | Soitec | Process for fabricating a heterostructure with minimized stress |
| US8349635B1 (en) | 2008-05-20 | 2013-01-08 | Silicon Laboratories Inc. | Encapsulated MEMS device and method to form the same |
| US20130009321A1 (en) | 2011-07-05 | 2013-01-10 | Sony Corporation | Semiconductor device, fabrication method for a semiconductor device and electronic apparatus |
| US20130020704A1 (en) | 2011-07-18 | 2013-01-24 | S.O.I.Tec Silicon On Insulator Technologies | Bonding surfaces for direct bonding of semiconductor structures |
| JP2013033786A (en) | 2011-08-01 | 2013-02-14 | Sony Corp | Semiconductor device and semiconductor device manufacturing method |
| US8377798B2 (en) | 2010-11-10 | 2013-02-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and structure for wafer to wafer bonding in semiconductor packaging |
| US8435421B2 (en) | 2007-11-27 | 2013-05-07 | Cabot Microelectronics Corporation | Metal-passivating CMP compositions and methods |
| US8441131B2 (en) | 2011-09-12 | 2013-05-14 | Globalfoundries Inc. | Strain-compensating fill patterns for controlling semiconductor chip package interactions |
| US8476165B2 (en) | 2009-04-01 | 2013-07-02 | Tokyo Electron Limited | Method for thinning a bonding wafer |
| US8476146B2 (en) | 2010-12-03 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing wafer distortion through a low CTE layer |
| US8501537B2 (en) | 2011-03-31 | 2013-08-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods |
| US20130221527A1 (en) | 2012-02-24 | 2013-08-29 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
| US20130252399A1 (en) | 2012-03-05 | 2013-09-26 | Commissariat A L'energie Atomique Et Aux Ene Alt | Direct bonding process using a compressible porous layer |
| US8620164B2 (en) | 2011-01-20 | 2013-12-31 | Intel Corporation | Hybrid III-V silicon laser formed by direct bonding |
| CN103531492A (en) | 2012-07-05 | 2014-01-22 | 台湾积体电路制造股份有限公司 | Hybrid bonding systems and methods for semiconductor wafers |
| US8647987B2 (en) | 2012-04-16 | 2014-02-11 | The Institute of Microelectronics, Chinese Academy of Science | Method for improving uniformity of chemical-mechanical planarization process |
| US8716105B2 (en) | 2011-03-31 | 2014-05-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods |
| US8728934B2 (en) | 2011-06-24 | 2014-05-20 | Tessera, Inc. | Systems and methods for producing flat surfaces in interconnect structures |
| US20140153210A1 (en) | 2012-12-03 | 2014-06-05 | Invensas Corporation | Advanced device assembly structures and methods |
| US20140175655A1 (en) | 2012-12-22 | 2014-06-26 | Industrial Technology Research Institute | Chip bonding structure and manufacturing method thereof |
| US20140191418A1 (en) | 2013-01-09 | 2014-07-10 | International Business Machines Corporation | Metal to metal bonding for stacked (3d) integrated circuits |
| US8802538B1 (en) | 2013-03-15 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for hybrid wafer bonding |
| US20140225258A1 (en) | 2013-02-08 | 2014-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Packages and Methods for Forming the Same |
| US20140225795A1 (en) | 2013-02-08 | 2014-08-14 | Sj Antenna Design | Shielding module integrating antenna and integrated circuit component |
| US8809123B2 (en) | 2012-06-05 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers |
| US20140252635A1 (en) | 2013-03-08 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding Structures and Methods of Forming the Same |
| US20140264948A1 (en) | 2013-03-15 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air Trench in Packages Incorporating Hybrid Bonding |
| US8841002B2 (en) | 2003-05-19 | 2014-09-23 | Ziptronix, Inc. | Method of room temperature covalent bonding |
| US20140353828A1 (en) | 2013-05-30 | 2014-12-04 | International Business Machines Corporation | Substrate bonding with diffusion barrier structures |
| US9000600B2 (en) | 2012-06-08 | 2015-04-07 | Invensas Corporation | Reduced stress TSV and interposer structures |
| US20150108644A1 (en) | 2013-10-17 | 2015-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Integrated Circuit and Methods of Forming the Same |
| US9028755B2 (en) | 2012-09-21 | 2015-05-12 | Aoi Seiki Co., Ltd. | Specimen transport apparatus, specimen processing apparatus, and specimen transport method |
| US20150206823A1 (en) | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust Through-Silicon-Via Structure |
| US20150206840A1 (en) | 2014-01-23 | 2015-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device structure and method of manufacturing the same |
| US9093350B2 (en) | 2010-07-09 | 2015-07-28 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device having first and second wiring structures with a concave portion between first and second substrates |
| US9142517B2 (en) | 2012-06-05 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding mechanisms for semiconductor wafers |
| US20150279888A1 (en) | 2014-03-28 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| US9184125B2 (en) | 2012-08-30 | 2015-11-10 | Ziptronix, Inc. | Heterogeneous annealing method and device |
| US9190345B1 (en) * | 2014-03-28 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US9190375B2 (en) | 2014-04-09 | 2015-11-17 | GlobalFoundries, Inc. | Solder bump reflow by induction heating |
| US20150340269A1 (en) | 2014-05-21 | 2015-11-26 | Stmicroelectronics (Crolles 2) Sas | Method of planarizing recesses filled with copper |
| US9224704B2 (en) | 2010-10-14 | 2015-12-29 | Soitec | Process for realizing a connecting structure |
| US20150380368A1 (en) | 2013-04-25 | 2015-12-31 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
| US9230941B2 (en) | 2014-03-28 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure for stacked semiconductor devices |
| US20160020183A1 (en) | 2012-01-05 | 2016-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making bond pad |
| JP2016021497A (en) | 2014-07-15 | 2016-02-04 | パナソニックIpマネジメント株式会社 | Semiconductor device and manufacturing method thereof |
| US9269612B2 (en) | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
| US9337235B2 (en) | 2013-02-18 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
| US20160133598A1 (en) | 2013-06-03 | 2016-05-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Direct metal bonding method |
| US9343330B2 (en) | 2006-12-06 | 2016-05-17 | Cabot Microelectronics Corporation | Compositions for polishing aluminum/copper and titanium in damascene structures |
| KR20160066272A (en) | 2014-12-02 | 2016-06-10 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
| US9394161B2 (en) | 2014-11-14 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | MEMS and CMOS integration with low-temperature bonding |
| US9433093B2 (en) | 2011-11-10 | 2016-08-30 | Invensas Corporation | High strength through-substrate vias |
| US9437572B2 (en) | 2013-12-18 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pad structure for hybrid bonding and methods of forming same |
| US20160276383A1 (en) | 2013-03-15 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for stacked device and method |
| US9461007B2 (en) | 2014-07-11 | 2016-10-04 | Samsung Electronics Co., Ltd. | Wafer-to-wafer bonding structure |
| US9496239B1 (en) | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
| US20160343682A1 (en) | 2013-12-11 | 2016-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9536848B2 (en) | 2014-10-16 | 2017-01-03 | Globalfoundries Inc. | Bond pad structure for low temperature flip chip bonding |
| US20170025381A1 (en) | 2015-07-23 | 2017-01-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bond using a copper alloy for yield improvement |
| US9559081B1 (en) | 2015-08-21 | 2017-01-31 | Apple Inc. | Independent 3D stacking |
| US20170047307A1 (en) | 2015-07-10 | 2017-02-16 | Invensas Corporation | Structures and methods for low temperature bonding |
| US20170062366A1 (en) * | 2015-08-25 | 2017-03-02 | Ziptronix, Inc. | Conductive barrier direct hybrid bonding |
| US20170069575A1 (en) | 2015-09-08 | 2017-03-09 | Invensas Corporation | Microelectronic assembly with redistribution structure formed on carrier |
| US20170086320A1 (en) | 2014-07-31 | 2017-03-23 | Skyworks Solutions, Inc. | Transient liquid phase material bonding and sealing structures and methods of forming same |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US20170141079A1 (en) | 2015-11-12 | 2017-05-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package and method of forming the same |
| US9656852B2 (en) | 2015-07-06 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS-MEMS device structure, bonding mesa structure and associated method |
| US9666573B1 (en) | 2016-10-26 | 2017-05-30 | Micron Technology, Inc. | Methods of forming integrated circuitry |
| US20170194271A1 (en) | 2016-01-06 | 2017-07-06 | Mediatek Inc. | Semiconductor package with three-dimensional antenna |
| US9723716B2 (en) | 2013-09-27 | 2017-08-01 | Infineon Technologies Ag | Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure |
| US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
| US20170271242A1 (en) | 2012-04-27 | 2017-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection Structure with Confinement Layer |
| US9776270B2 (en) | 2013-10-01 | 2017-10-03 | Globalfoundries Inc. | Chip joining by induction heating |
| US9799587B2 (en) | 2011-05-24 | 2017-10-24 | Sony Corporation | Semiconductor device |
| US20170330855A1 (en) | 2016-05-13 | 2017-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for Immersion Bonding |
| US20170355040A1 (en) | 2014-12-22 | 2017-12-14 | Mitsubishi Heavy Industries Machine Tool Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
| US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
| US9893004B2 (en) | 2011-07-27 | 2018-02-13 | Broadpak Corporation | Semiconductor interposer integration |
| US9899442B2 (en) | 2014-12-11 | 2018-02-20 | Invensas Corporation | Image sensor device |
| US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
| US9941243B2 (en) | 2016-06-09 | 2018-04-10 | Samsung Electronics Co., Ltd. | Wafer-to-wafer bonding structure |
| US9941241B2 (en) | 2016-06-30 | 2018-04-10 | International Business Machines Corporation | Method for wafer-wafer bonding |
| US20180151523A1 (en) | 2013-08-29 | 2018-05-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing interconnect structure |
| US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20180175012A1 (en) | 2016-12-15 | 2018-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structures and methods of forming same |
| US20180182666A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Microelectronic assembly from processed substrate |
| US20180182639A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processing Stacked Substrates |
| US20180190583A1 (en) | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US20180190580A1 (en) | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US10026605B2 (en) | 2014-06-04 | 2018-07-17 | Semiconductor Components Industries, Llc | Method of reducing residual contamination in singulated semiconductor die |
| US20180219038A1 (en) | 2017-02-01 | 2018-08-02 | Semiconductor Components Industries, Llc | Edge seals for semiconductor packages |
| JP2018129475A (en) | 2017-02-10 | 2018-08-16 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method thereof |
| US10075657B2 (en) | 2015-07-21 | 2018-09-11 | Fermi Research Alliance, Llc | Edgeless large area camera system |
| US20180273377A1 (en) | 2017-03-21 | 2018-09-27 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
| US20180295718A1 (en) | 2011-11-15 | 2018-10-11 | Invensas Corporation | Cavities Containing Multi-wiring Structures And Devices |
| JP2018160519A (en) | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US20180323177A1 (en) | 2016-04-15 | 2018-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC Formation with Dies Bonded to Formed RDLs |
| US20180323227A1 (en) | 2017-05-03 | 2018-11-08 | United Microelectronics Corp. | Wafer level packaging method |
| US20180331066A1 (en) | 2017-05-11 | 2018-11-15 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
| US20180350674A1 (en) | 2017-06-05 | 2018-12-06 | Invensas Corporation | Flat Metal Features for Microelectronics Applications |
| US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
| US20190096741A1 (en) | 2017-09-27 | 2019-03-28 | Invensas Corporation | Interconnect structures and methods for forming same |
| US20190115277A1 (en) | 2016-12-05 | 2019-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package Structure for Heat Dissipation |
| US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
| US10276909B2 (en) | 2016-12-30 | 2019-04-30 | Invensas Bonding Technologies, Inc. | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein |
| US10276619B2 (en) | 2016-01-12 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with a conductive feature passing through a passivation layer |
| US20190131277A1 (en) | 2017-11-01 | 2019-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Die stack structure and method of fabricating the same and package |
| US10314175B2 (en) | 2015-02-26 | 2019-06-04 | Japan Aviation Electronics Industry, Limited | Electric connection structure and electric connection member |
| US20190198409A1 (en) | 2017-12-22 | 2019-06-27 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20190198407A1 (en) | 2017-12-22 | 2019-06-27 | Invensas Bonding Technologies, Inc. | Cavity packages |
| US20190244909A1 (en) | 2018-02-07 | 2019-08-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages |
| US20190265411A1 (en) | 2018-02-26 | 2019-08-29 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
| CN107256852B (en) | 2017-06-20 | 2019-09-13 | 上海集成电路研发中心有限公司 | Metal bonding point array with improved arrangement and semiconductor device having the same |
| US10418277B2 (en) | 2016-08-09 | 2019-09-17 | International Business Machines Corporation | Air gap spacer formation for nano-scale semiconductor devices |
| US20190295954A1 (en) | 2018-03-20 | 2019-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US10446456B2 (en) | 2014-03-12 | 2019-10-15 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
| US10446532B2 (en) | 2016-01-13 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Systems and methods for efficient transfer of semiconductor elements |
| US20190319007A1 (en) | 2018-04-11 | 2019-10-17 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US20190333550A1 (en) | 2018-04-30 | 2019-10-31 | Invensas Corporation | Multi-die module with low power operation |
| US20190348336A1 (en) | 2018-05-14 | 2019-11-14 | Invensas Bonding Technologies, Inc. | Structures for bonding elements |
| US20190385966A1 (en) | 2018-06-13 | 2019-12-19 | Invensas Bonding Technologies, Inc. | Large metal pads over tsv |
| US20190385935A1 (en) | 2018-06-13 | 2019-12-19 | Invensas Bonding Technologies, Inc. | Tsv as pad |
| US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
| US10522499B2 (en) | 2017-02-09 | 2019-12-31 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20200006280A1 (en) | 2018-06-29 | 2020-01-02 | Priyal Shah | Bond pads for low temperature hybrid bonding |
| US20200013637A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
| US20200013765A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
| US20200035641A1 (en) | 2018-07-26 | 2020-01-30 | Invensas Bonding Technologies, Inc. | Post cmp processing for hybrid bonding |
| US20200075520A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
| US20200075553A1 (en) | 2018-08-28 | 2020-03-05 | Xcelsis Corporation | Integrated voltage regulator and passive components |
| US20200075534A1 (en) | 2018-08-31 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US20200098711A1 (en) | 2018-09-20 | 2020-03-26 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
| US20200126906A1 (en) | 2018-10-22 | 2020-04-23 | Invensas Bonding Technologies, Inc. | Interconnect structures |
| US20200194396A1 (en) | 2018-12-18 | 2020-06-18 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
| US20200227367A1 (en) | 2019-01-14 | 2020-07-16 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20200258857A1 (en) | 2019-02-11 | 2020-08-13 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same |
| US20200279821A1 (en) | 2019-03-01 | 2020-09-03 | Invensas Corporation | Nanowire bonding interconnect for fine-pitch microelectronics |
| US20200294908A1 (en) | 2019-03-11 | 2020-09-17 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US10784191B2 (en) | 2017-03-31 | 2020-09-22 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US20200328162A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
| US20200328165A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
| US20200328164A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
| US20200335408A1 (en) | 2019-04-22 | 2020-10-22 | lnvensas Bonding Technologies, Inc., | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US20200365575A1 (en) | 2018-02-15 | 2020-11-19 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
| US20200371154A1 (en) | 2019-05-23 | 2020-11-26 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
| US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
| US20200395321A1 (en) | 2019-06-12 | 2020-12-17 | Invensas Bonding Technologies, Inc. | Sealed bonded structures and methods for forming the same |
| US20200411483A1 (en) | 2019-06-26 | 2020-12-31 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
| US10886177B2 (en) | 2016-10-07 | 2021-01-05 | Xcelsis Corporation | 3D chip with shared clock distribution network |
| US20210028136A1 (en) | 2019-07-26 | 2021-01-28 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
| US20210028144A1 (en) | 2019-07-24 | 2021-01-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US10908173B2 (en) | 2014-11-14 | 2021-02-02 | Sysmex Corporation | Sample measurement apparatus and method of measuring samples |
| US10923413B2 (en) | 2018-05-30 | 2021-02-16 | Xcelsis Corporation | Hard IP blocks with physically bidirectional passageways |
| US10950547B2 (en) | 2016-10-07 | 2021-03-16 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
| US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
| US20210098411A1 (en) | 2019-09-26 | 2021-04-01 | Intel Corporation | Mixed hybrid bonding structures and methods of forming the same |
| US20210098359A1 (en) | 2019-09-26 | 2021-04-01 | Intel Corporation | Methods & structures for improved electrical contact between bonded integrated circuit interfaces |
| US20210098412A1 (en) | 2019-09-26 | 2021-04-01 | Invensas Bonding Technologies, Inc. | Direct gang bonding methods and structures |
| US20210118864A1 (en) | 2019-10-21 | 2021-04-22 | Invensas Corporation | Non-Volatile Dynamic Random Access Memory |
| US10991804B2 (en) | 2018-03-29 | 2021-04-27 | Xcelsis Corporation | Transistor level interconnection methodologies utilizing 3D interconnects |
| US20210143125A1 (en) | 2019-11-07 | 2021-05-13 | Invensas Corporation | Scalable Architecture for Reduced Cycles Across SoC |
| US11011503B2 (en) | 2017-12-15 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Direct-bonded optoelectronic interconnect for high-density integrated photonics |
| US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
| US20210181510A1 (en) | 2019-12-17 | 2021-06-17 | Invensas Bonding Technologies, Inc. | Bonded optical devices |
| US20210193625A1 (en) | 2019-12-23 | 2021-06-24 | Invensas Bonding Technologies, Inc. | Electrical redundancy for bonded structures |
| US20210193624A1 (en) | 2019-12-20 | 2021-06-24 | Invensas Corporation | Apparatus For Non-Volatile Random Access Memory Stacks |
| US20210193603A1 (en) | 2019-12-23 | 2021-06-24 | Invensas Bonding Technologies, Inc. | Circuitry for electrical redundancy in bonded structures |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| US20210234070A1 (en) | 2012-05-04 | 2021-07-29 | Unm Rainforest Innovations | Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure |
| US20210242152A1 (en) | 2020-02-05 | 2021-08-05 | Invensas Bonding Technologies, Inc. | Selective alteration of interconnect pads for direct bonding |
| US20210242050A1 (en) | 2020-02-04 | 2021-08-05 | Nanya Technology Corporation | Semiconductor device having hybrid bonding interface, method of manufacturing the semiconductor device, and method of manufacturing semiconductor device assembly |
| US20210257333A1 (en) | 2020-02-17 | 2021-08-19 | Yangtze Memory Technologies Co., Ltd. | Hybrid wafer bonding method and structure thereof |
| US11127738B2 (en) | 2018-02-09 | 2021-09-21 | Xcelsis Corporation | Back biasing of FD-SOI circuit blocks |
| US20210296282A1 (en) | 2020-03-19 | 2021-09-23 | Invensas Bonding Technologies, Inc. | Dimension compensation control for directly bonded structures |
| US20210305202A1 (en) | 2020-03-31 | 2021-09-30 | Invensas Bonding Technologies, Inc. | Reliable hybrid bonded apparatus |
| US11158606B2 (en) | 2018-07-06 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
| US11171117B2 (en) | 2018-06-12 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Interlayer connection of stacked microelectronic components |
| US11176450B2 (en) | 2017-08-03 | 2021-11-16 | Xcelsis Corporation | Three dimensional circuit implementing machine trained network |
| US20210366820A1 (en) | 2020-05-19 | 2021-11-25 | Invensas Bonding Technologies, Inc. | Laterally unconfined structure |
| US20210407941A1 (en) | 2020-06-30 | 2021-12-30 | Invensas Bonding Technologies, Inc. | Integrated device packages |
| US11256004B2 (en) | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
| US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
| US20220077063A1 (en) | 2020-09-04 | 2022-03-10 | Invensas Bonding Technologies, Inc. | Bonded structure with interconnect structure |
| US20220077087A1 (en) | 2020-09-04 | 2022-03-10 | Invensas Bonding Technologies, Inc. | Bonded structure with interconnect structure |
| US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
| US20220139867A1 (en) | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US20220139975A1 (en) | 2019-03-14 | 2022-05-05 | Sony Semiconductor Solutions Corporation | Solid-state image pickup apparatus and manufacturing method therefor, and electronic equipment |
| US20220139869A1 (en) | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US11329034B2 (en) | 2017-03-16 | 2022-05-10 | Invensas Corporation | Direct-bonded LED structure contacts and substrate contacts |
| US20220149002A1 (en) | 2020-11-10 | 2022-05-12 | Sandisk Technologies Llc | Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners |
| US20220157752A1 (en) | 2020-11-16 | 2022-05-19 | Commissariat à l'énergie atomique et aux énergies alternatives | Electronic circuit for a hybrid molecular bonding |
| US20220165692A1 (en) | 2018-04-11 | 2022-05-26 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US11348898B2 (en) | 2018-06-22 | 2022-05-31 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
| US11355443B2 (en) | 2018-05-03 | 2022-06-07 | Invensas Corporation | Dielets on flexible and stretchable packaging for microelectronics |
| US20220208702A1 (en) | 2020-12-30 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Structure with conductive feature and method of forming same |
| US20220208723A1 (en) | 2020-12-30 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Directly bonded structures |
| US20220208650A1 (en) | 2020-12-28 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| WO2022147429A1 (en) | 2020-12-28 | 2022-07-07 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| US20220285303A1 (en) | 2021-03-03 | 2022-09-08 | Invensas Bonding Technologies, Inc. | Contact structures for direct bonding |
| US20220319901A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
| US20220320035A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US20220320036A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
| US20230005849A1 (en) | 2021-07-01 | 2023-01-05 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| US20230005850A1 (en) | 2021-06-30 | 2023-01-05 | Invensas Bonding Technologies, Inc. | Element with routing structure in bonding layer |
| US20230019869A1 (en) | 2021-07-16 | 2023-01-19 | Invensas Bonding Technologies, Inc. | Optically occlusive protective element for bonded structures |
| US20230036441A1 (en) | 2021-08-02 | 2023-02-02 | Invensas Bonding Technologies, Inc. | Protective semiconductor elements for bonded structures |
| US20230067677A1 (en) | 2021-09-01 | 2023-03-02 | Invensas Bonding Technologies, Inc. | Sequences and equipment for direct bonding |
| US20230069183A1 (en) | 2021-09-01 | 2023-03-02 | Invensas Llc | Stacked structure with interposer |
| US20230100032A1 (en) | 2021-09-24 | 2023-03-30 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with active interposer |
| US20230115122A1 (en) | 2021-09-14 | 2023-04-13 | Adeia Semiconductor Bonding Technologies Inc. | Method of bonding thin substrates |
| US20230120352A1 (en) | 2021-10-19 | 2023-04-20 | Sandisk Technologies Llc | Non-volatile memory with adjusted bit line voltage during verify |
| US20230122531A1 (en) | 2021-10-18 | 2023-04-20 | Invensas Llc | Reduced parasitic capacitance in bonded structures |
| US20230123423A1 (en) | 2021-10-19 | 2023-04-20 | Adeia Semiconductor Bonding Technologies Inc | Stacked inductors in multi-die stacking |
| US20230125395A1 (en) | 2021-10-27 | 2023-04-27 | Adeia Semiconductor Bonding Technologies Inc. | Stacked structures with capacitive coupling connections |
| US20230130259A1 (en) | 2021-10-22 | 2023-04-27 | Invensas Llc | Radio frequency device packages |
| US20230132632A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Diffusion barriers and method of forming same |
| US20230140107A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
| US20230142680A1 (en) | 2021-10-28 | 2023-05-11 | Adeia Semiconductor Bonding Technologies Inc. | Stacked electronic devices |
| US20230154816A1 (en) | 2021-11-17 | 2023-05-18 | Adeia Semiconductor Bonding Technologies Inc. | Thermal bypass for stacked dies |
| US20230154828A1 (en) | 2021-11-18 | 2023-05-18 | Adeia Semiconductor Bonding Technologies Inc. | Fluid cooling for die stacks |
| US20230187317A1 (en) | 2021-12-13 | 2023-06-15 | Adeia Semiconductor Bonding Technologies Inc. | Interconnect structures |
| US20230187412A1 (en) | 2021-10-25 | 2023-06-15 | Adeia Semiconductor Bonding Technologies Inc. | Power distribution for stacked electronic devices |
| US20230187264A1 (en) | 2021-12-13 | 2023-06-15 | Adeia Semiconductor Technologies Llc | Methods for bonding semiconductor elements |
| US20230197453A1 (en) | 2021-12-17 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Structure with conductive feature for direct bonding and method of forming same |
| US20230197496A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding and debonding of elements |
| US20230197560A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling in microelectronics |
| US20230197559A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling for die packages |
| US20230197655A1 (en) | 2021-12-22 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Low stress direct hybrid bonding |
| US20230207514A1 (en) | 2021-12-23 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Apparatuses and methods for die bond control |
| US20230207402A1 (en) | 2021-12-27 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded frame wafers |
| US20230207474A1 (en) | 2021-12-23 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with interconnect assemblies |
| US20230207437A1 (en) | 2021-11-05 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Multi-channel device stacking |
| US20230215836A1 (en) | 2021-12-23 | 2023-07-06 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding on package substrates |
| US20230245950A1 (en) | 2022-01-31 | 2023-08-03 | Adeia Semiconductor Bonding Technologies Inc. | Heat dissipating system for electronic devices |
| US20230268300A1 (en) | 2022-02-24 | 2023-08-24 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures |
| US20230299029A1 (en) | 2022-03-16 | 2023-09-21 | Adeia Semiconductor Bonding Technologies Inc. | Expansion control for bonding |
| US11769747B2 (en) | 2020-12-16 | 2023-09-26 | Kioxia Corporation | Semiconductor device and method of manufacturing the same |
| US20230343734A1 (en) | 2022-04-25 | 2023-10-26 | Adeia Semiconductor Bonding Technologies Inc. | Expansion controlled structure for direct bonding and method of forming same |
| US20230360950A1 (en) | 2022-05-05 | 2023-11-09 | Adeia Semiconductor Bonding Technologies Inc. | Gang-flipping of dies prior to bonding |
| US20230361074A1 (en) | 2022-05-05 | 2023-11-09 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature direct bonding |
| US20230369136A1 (en) | 2022-05-13 | 2023-11-16 | Adeia Semiconductor Bonding Technologies Inc. | Bonding surface validation on dicing tape |
| US20230375613A1 (en) | 2022-05-23 | 2023-11-23 | Adeia Semiconductor Bonding Technologies Inc. | Testing elements for bonded structures |
| US20240038702A1 (en) | 2022-07-27 | 2024-02-01 | Adeia Semiconductor Bonding Technologies Inc. | High-performance hybrid bonded interconnect systems |
| US20240055407A1 (en) | 2022-08-11 | 2024-02-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded debugging elements for integrated circuits and methods for debugging integrated circuits using same |
| US20240079376A1 (en) | 2022-09-07 | 2024-03-07 | Adeia Semiconductor Bonding Technologies Inc. | Rapid thermal processing for direct bonding |
| US20240105674A1 (en) | 2022-09-07 | 2024-03-28 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure and method of forming same |
| US20240170411A1 (en) | 2022-11-18 | 2024-05-23 | Adeia Semiconductor Bonding Technologies Inc. | Scribe lane reinforcement |
| US20240186248A1 (en) | 2022-12-01 | 2024-06-06 | Adeia Semiconductor Bonding Technologies Inc. | Backside power delivery network |
| US20240186268A1 (en) | 2022-12-01 | 2024-06-06 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded structure with frame structure |
| US20240186269A1 (en) | 2022-12-02 | 2024-06-06 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with security die |
| US20240213191A1 (en) | 2021-12-23 | 2024-06-27 | Adeia Semiconductor Bonding Technologies Inc. | Controlled grain growth for bonding and bonded structure with controlled grain growth |
| US20240213210A1 (en) | 2022-12-23 | 2024-06-27 | Adeia Semiconductor Bonding Technologies Inc. | System and method for using acoustic waves to counteract deformations during bonding |
| US20240222239A1 (en) | 2022-12-28 | 2024-07-04 | Adeia Semiconductor Bonding Technologies Inc. | Semiconductor element with bonding layer having functional and non-functional conductive pads |
| US20240217210A1 (en) | 2022-12-29 | 2024-07-04 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded metal structures having aluminum features and methods of preparing same |
| US20240222319A1 (en) | 2022-12-28 | 2024-07-04 | Adeia Semiconductor Bonding Technologies Inc. | Debonding repair devices |
| US20240266255A1 (en) | 2023-02-08 | 2024-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Electronic device cooling structures |
| US20240298454A1 (en) | 2023-03-01 | 2024-09-05 | Adeia Semiconductor Bonding Technologies Inc. | Multichannel memory with serdes |
| US20240304593A1 (en) | 2023-03-06 | 2024-09-12 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
| US20240312951A1 (en) | 2023-03-14 | 2024-09-19 | Adeia Semiconductor Bonding Technologies Inc. | System and method for bonding transparent conductor substrates |
| US20240332184A1 (en) | 2023-03-31 | 2024-10-03 | Adeia Semiconductor Bonding Technologies, Inc. | Direct bonding on buried power rails |
| US20240332227A1 (en) | 2023-03-31 | 2024-10-03 | Adeia Semiconductor Bonding Technologies Inc | Semiconductor element with bonding layer having low-k dielectric material |
| US20240332231A1 (en) | 2023-03-31 | 2024-10-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct hybrid bonding in topographic packages |
| US20240332267A1 (en) | 2023-03-31 | 2024-10-03 | Adeia Semiconductor Bonding Technologies, Inc. | Interposer for backside power delivery network |
| US20240387419A1 (en) | 2023-05-18 | 2024-11-21 | Adeia Semiconductor Bonding Technologies Inc. | Direct hybrid bond pad having tapered sidewall |
| US20250006689A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Structures and methods for bonding dies |
| US20250006642A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Chiplet-to-chiplet protocol switch |
| US20250004197A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded optical components |
| US20250006674A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Methods and structures for low temperature hybrid bonding |
| US20250006679A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Conductive materials for direct bonding |
| US20250006632A1 (en) | 2023-06-30 | 2025-01-02 | Adeia Semiconductor Bonding Technologies Inc. | Embedded chiplets with backside power delivery network |
| US20250054854A1 (en) | 2023-06-30 | 2025-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Heavily doped semiconductor devices for power distribution |
| US20250079364A1 (en) | 2023-09-06 | 2025-03-06 | Adeia Semiconductor Bonding Technologies Inc. | Methods and structures employing metal oxide for direct metal bonding |
| US20250096191A1 (en) | 2023-09-18 | 2025-03-20 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures for dies |
| US20250112123A1 (en) | 2023-09-29 | 2025-04-03 | Adeia Semiconductor Bonding Technologies Inc. | Through substrate via structures and processes |
| US20250185163A1 (en) | 2023-12-05 | 2025-06-05 | Adeia Semiconductor Bonding Technologies Inc. | Organic-to-inorganic bonding methods and structures |
| US20250212554A1 (en) | 2023-12-22 | 2025-06-26 | Adeia Semiconductor Bonding Technologies Inc. | Transfer of multiple small elements to a carrier |
| US20250210585A1 (en) | 2023-12-22 | 2025-06-26 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding of semiconductor elements |
| US20250218903A1 (en) | 2023-12-28 | 2025-07-03 | Adeia Semiconductor Bonding Technologies Inc. | Via reveal processing and structures |
-
2022
- 2022-12-29 US US18/148,332 patent/US12506114B2/en active Active
-
2023
- 2023-12-15 JP JP2025538374A patent/JP2025542482A/en active Pending
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- 2023-12-15 CN CN202380092789.5A patent/CN120604336A/en active Pending
- 2023-12-15 EP EP23913462.0A patent/EP4643383A1/en active Pending
- 2023-12-15 KR KR1020257024457A patent/KR20250130627A/en active Pending
- 2023-12-19 TW TW112149511A patent/TW202429589A/en unknown
Patent Citations (460)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939568A (en) | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
| US4998665A (en) | 1988-09-07 | 1991-03-12 | Nec Corporation | Bonding structure of substrates and method for bonding substrates |
| US5087585A (en) | 1989-07-11 | 1992-02-11 | Nec Corporation | Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit |
| US5489804A (en) | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5322593A (en) | 1991-11-21 | 1994-06-21 | Nec Corporation | Method for manufacturing polyimide multilayer wiring substrate |
| US6008126A (en) | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
| US5236118A (en) | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
| US5503704A (en) | 1993-01-06 | 1996-04-02 | The Regents Of The University Of California | Nitrogen based low temperature direct bonding |
| US5421953A (en) | 1993-02-16 | 1995-06-06 | Nippondenso Co., Ltd. | Method and apparatus for direct bonding two bodies |
| US5516727A (en) | 1993-04-19 | 1996-05-14 | International Business Machines Corporation | Method for encapsulating light emitting diodes |
| US5771555A (en) | 1993-11-01 | 1998-06-30 | Matsushita Electric Industrial Co., Ltd. | Method for producing an electronic component using direct bonding |
| US5501003A (en) | 1993-12-15 | 1996-03-26 | Bel Fuse Inc. | Method of assembling electronic packages for surface mount applications |
| US5442235A (en) | 1993-12-23 | 1995-08-15 | Motorola Inc. | Semiconductor device having an improved metal interconnect structure |
| US5413952A (en) | 1994-02-02 | 1995-05-09 | Motorola, Inc. | Direct wafer bonded structure method of making |
| CN1112286A (en) | 1994-05-19 | 1995-11-22 | 陆敬良 | Durable neon lamp and its making technique |
| US5753536A (en) | 1994-08-29 | 1998-05-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and associated fabrication method |
| US5985739A (en) | 1994-09-19 | 1999-11-16 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Semiconductor structures having advantageous high-frequency characteristics and processes for producing such semiconductor structures |
| US5866942A (en) | 1995-04-28 | 1999-02-02 | Nec Corporation | Metal base package for a semiconductor device |
| US5610431A (en) | 1995-05-12 | 1997-03-11 | The Charles Stark Draper Laboratory, Inc. | Covers for micromechanical sensors and other semiconductor devices |
| US5904860A (en) | 1995-09-12 | 1999-05-18 | Nippondenso Co., Ltd. | Method for direct bonding nitride bodies |
| US6374770B1 (en) | 1995-10-26 | 2002-04-23 | Applied Materials, Inc. | Apparatus for improving film stability of halogen-doped silicon oxide films |
| US5734199A (en) | 1995-12-18 | 1998-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having improved test electrodes |
| US6063968A (en) | 1996-05-14 | 2000-05-16 | Degussa Aktiengesellschaft | Method for the production of trimethylhydroquinone |
| US6528894B1 (en) | 1996-09-20 | 2003-03-04 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| US5821692A (en) | 1996-11-26 | 1998-10-13 | Motorola, Inc. | Organic electroluminescent device hermetic encapsulation package |
| US6333206B1 (en) | 1996-12-24 | 2001-12-25 | Nitto Denko Corporation | Process for the production of semiconductor device |
| US6265775B1 (en) | 1997-01-24 | 2001-07-24 | Micron Technology, Inc. | Flip chip technique for chip assembly |
| US6071761A (en) | 1997-03-18 | 2000-06-06 | Jacobs; Richard L. | Method for encapsulated integrated circuits |
| US5998808A (en) | 1997-06-27 | 1999-12-07 | Sony Corporation | Three-dimensional integrated circuit device and its manufacturing method |
| US6080640A (en) | 1997-07-11 | 2000-06-27 | Advanced Micro Devices, Inc. | Metal attachment method and structure for attaching substrates at low temperatures |
| US6097096A (en) | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
| US6117784A (en) | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| US6579744B1 (en) | 1998-02-27 | 2003-06-17 | Micron Technology, Inc. | Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive |
| US6297072B1 (en) | 1998-04-17 | 2001-10-02 | Interuniversitair Micro-Elktronica Centrum (Imec Vzw) | Method of fabrication of a microstructure having an internal cavity |
| US6147000A (en) | 1998-08-11 | 2000-11-14 | Advanced Micro Devices, Inc. | Method for forming low dielectric passivation of copper interconnects |
| US6316786B1 (en) | 1998-08-29 | 2001-11-13 | International Business Machines Corporation | Organic opto-electronic devices |
| US6632377B1 (en) | 1998-10-23 | 2003-10-14 | International Business Machines Corporation | Chemical-mechanical planarization of metallurgy |
| US6409904B1 (en) | 1998-12-01 | 2002-06-25 | Nutool, Inc. | Method and apparatus for depositing and controlling the texture of a thin film |
| US6837979B2 (en) | 1998-12-01 | 2005-01-04 | Asm-Nutool Inc. | Method and apparatus for depositing and controlling the texture of a thin film |
| US6123825A (en) | 1998-12-02 | 2000-09-26 | International Business Machines Corporation | Electromigration-resistant copper microstructure and process of making |
| US6232150B1 (en) | 1998-12-03 | 2001-05-15 | The Regents Of The University Of Michigan | Process for making microstructures and microstructures made thereby |
| JP2000183061A (en) | 1998-12-18 | 2000-06-30 | Rohm Co Ltd | Manufacture of semiconductor device |
| US6348709B1 (en) | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
| US6465892B1 (en) | 1999-04-13 | 2002-10-15 | Oki Electric Industry Co., Ltd. | Interconnect structure for stacked semiconductor device |
| US20020074670A1 (en) | 1999-04-13 | 2002-06-20 | Tadatomo Suga | Method for manufacturing an interconnect structure for stacked semiconductor device |
| US6259160B1 (en) | 1999-04-21 | 2001-07-10 | Advanced Micro Devices, Inc. | Apparatus and method of encapsulated copper (Cu) Interconnect formation |
| US6258625B1 (en) | 1999-05-18 | 2001-07-10 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
| US6589813B1 (en) | 1999-06-28 | 2003-07-08 | Hyundai Electronics Industries Co., Ltd. | Chip size stack package and method of fabricating the same |
| US6828686B2 (en) | 1999-06-28 | 2004-12-07 | Hyundai Electronics Industries Co., Ltd. | Chip size stack package and method of fabricating the same |
| US20020047208A1 (en) | 1999-08-18 | 2002-04-25 | Cyprian Emeka Uzoh | Method and structure for improving electromigration of chip interconnects |
| US6909194B2 (en) | 1999-08-27 | 2005-06-21 | Micron Technology, Inc. | Electronic assembly having semiconductor component with polymer support member and method of fabrication |
| US6583515B1 (en) | 1999-09-03 | 2003-06-24 | Texas Instruments Incorporated | Ball grid array package for enhanced stress tolerance |
| US20020094661A1 (en) | 1999-10-01 | 2002-07-18 | Ziptronix | Three dimensional device intergration method and intergrated device |
| US9431368B2 (en) | 1999-10-01 | 2016-08-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US7126212B2 (en) | 1999-10-01 | 2006-10-24 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US6333120B1 (en) | 1999-10-27 | 2001-12-25 | International Business Machines Corporation | Method for controlling the texture and microstructure of plated copper and plated structure |
| US9391143B2 (en) | 2000-02-16 | 2016-07-12 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US6864585B2 (en) | 2000-03-22 | 2005-03-08 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US20040052930A1 (en) | 2000-04-27 | 2004-03-18 | Bulent Basol | Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization |
| US6974769B2 (en) | 2000-04-27 | 2005-12-13 | Asm Nutool, Inc. | Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization |
| US20030092220A1 (en) | 2000-06-08 | 2003-05-15 | Salman Akram | Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed |
| US20020000328A1 (en) | 2000-06-22 | 2002-01-03 | Kabushiki Kaisha Toshiba | Printed wiring board and manufacturing method thereof |
| US20020003307A1 (en) | 2000-07-05 | 2002-01-10 | Tadatomo Suga | Semiconductor device and method for fabricating the device |
| US7078811B2 (en) | 2000-07-05 | 2006-07-18 | Tadatomo Suga | Semiconductor device and method for fabricating the device |
| US6423640B1 (en) | 2000-08-09 | 2002-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Headless CMP process for oxide planarization |
| US20020025665A1 (en) | 2000-08-29 | 2002-02-28 | Werner Juengling | Method of forming a metal to polysilicon contact in oxygen environment |
| US6600224B1 (en) | 2000-10-31 | 2003-07-29 | International Business Machines Corporation | Thin film attachment to laminate using a dendritic interconnection |
| US6433402B1 (en) | 2000-11-16 | 2002-08-13 | Advanced Micro Devices, Inc. | Selective copper alloy deposition |
| US6552436B2 (en) | 2000-12-08 | 2003-04-22 | Motorola, Inc. | Semiconductor device having a ball grid array and method therefor |
| US6758388B1 (en) | 2001-02-27 | 2004-07-06 | Rohr, Inc. | Titanium aluminide honeycomb panel structures and fabrication method for the same |
| JP2002353416A (en) | 2001-05-25 | 2002-12-06 | Sony Corp | Semiconductor storage device and method of manufacturing the same |
| US6555917B1 (en) | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
| US6667225B2 (en) | 2001-12-17 | 2003-12-23 | Intel Corporation | Wafer-bonding using solder and method of making the same |
| US6660564B2 (en) | 2002-01-25 | 2003-12-09 | Sony Corporation | Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby |
| US6624003B1 (en) | 2002-02-06 | 2003-09-23 | Teravicta Technologies, Inc. | Integrated MEMS device and package |
| US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
| US20030157748A1 (en) | 2002-02-20 | 2003-08-21 | Kim Sarah E. | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| US20070111386A1 (en) | 2002-02-20 | 2007-05-17 | Kim Sarah E | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| US6627814B1 (en) | 2002-03-22 | 2003-09-30 | David H. Stark | Hermetically sealed micro-device package with window |
| US7105980B2 (en) | 2002-07-03 | 2006-09-12 | Sawtek, Inc. | Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics |
| US20040084414A1 (en) | 2002-08-19 | 2004-05-06 | Kenji Sakai | Polishing method and polishing composition used for polishing |
| US20040052390A1 (en) | 2002-09-12 | 2004-03-18 | Nelson Morales | Method and apparatus for programming a hearing device |
| US7045453B2 (en) | 2002-10-24 | 2006-05-16 | International Business Machines Corporation | Very low effective dielectric constant interconnect structures and methods for fabricating the same |
| US20080237053A1 (en) | 2002-12-04 | 2008-10-02 | International Business Machines Corporation | Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel |
| US7354798B2 (en) | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
| US8524533B2 (en) | 2003-02-07 | 2013-09-03 | Ziptronix, Inc. | Room temperature metal direct bonding |
| US9385024B2 (en) | 2003-02-07 | 2016-07-05 | Ziptronix, Inc. | Room temperature metal direct bonding |
| US6962835B2 (en) | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
| US7109063B2 (en) | 2003-02-12 | 2006-09-19 | Micron Technology, Inc. | Semiconductor substrate for build-up packages |
| US6908027B2 (en) | 2003-03-31 | 2005-06-21 | Intel Corporation | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process |
| US20040238492A1 (en) | 2003-04-23 | 2004-12-02 | Catabay Wilbur G. | Planarization with reduced dishing |
| US10434749B2 (en) | 2003-05-19 | 2019-10-08 | Invensas Bonding Technologies, Inc. | Method of room temperature covalent bonding |
| US20150064498A1 (en) | 2003-05-19 | 2015-03-05 | Ziptronix, Inc. | Method of room temperature covalent bonding |
| US8841002B2 (en) | 2003-05-19 | 2014-09-23 | Ziptronix, Inc. | Method of room temperature covalent bonding |
| US20070096294A1 (en) | 2003-06-06 | 2007-05-03 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
| WO2005043584A2 (en) | 2003-10-21 | 2005-05-12 | Ziptronix, Inc. | Single mask via method and device |
| US20060024950A1 (en) | 2004-08-02 | 2006-02-02 | Suk-Hun Choi | Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same |
| US20060057945A1 (en) | 2004-09-16 | 2006-03-16 | Chia-Lin Hsu | Chemical mechanical polishing process |
| US7238919B2 (en) | 2005-03-15 | 2007-07-03 | Kabushiki Kaisha Toshiba | Heating element movement bonding method for semiconductor components |
| US20060220197A1 (en) | 2005-03-16 | 2006-10-05 | Kobrinsky Mauro J | Method of forming self-passivating interconnects and resulting devices |
| US7998335B2 (en) | 2005-06-13 | 2011-08-16 | Cabot Microelectronics Corporation | Controlled electrochemical polishing method |
| US10147641B2 (en) | 2005-08-11 | 2018-12-04 | Invensas Bonding Technologies, Inc. | 3D IC method and device |
| US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
| US9171756B2 (en) | 2005-08-11 | 2015-10-27 | Ziptronix, Inc. | 3D IC method and device |
| US7193423B1 (en) | 2005-12-12 | 2007-03-20 | International Business Machines Corporation | Wafer-to-wafer alignments |
| US8101858B2 (en) | 2006-03-14 | 2012-01-24 | Corus Technology B.V. | Chalcopyrite semiconductor based photovoltaic solar cell comprising a metal substrate, coated metal substrate for a photovoltaic solar cell and manufacturing method thereof |
| US8183127B2 (en) | 2006-07-10 | 2012-05-22 | Tezzaron Semiconductor, Inc. | Method for bonding wafers to produce stacked integrated circuits |
| US7750488B2 (en) | 2006-07-10 | 2010-07-06 | Tezzaron Semiconductor, Inc. | Method for bonding wafers to produce stacked integrated circuits |
| US20100255262A1 (en) | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| US20080073795A1 (en) | 2006-09-24 | 2008-03-27 | Georgia Tech Research Corporation | Integrated circuit interconnection devices and methods |
| US20080122092A1 (en) | 2006-11-29 | 2008-05-29 | Ji Ho Hong | Semiconductor Device and Method of Manufacturing the Same |
| KR20080050129A (en) | 2006-12-01 | 2008-06-05 | 삼성전자주식회사 | Photodiode and image sensor using it |
| US9343330B2 (en) | 2006-12-06 | 2016-05-17 | Cabot Microelectronics Corporation | Compositions for polishing aluminum/copper and titanium in damascene structures |
| US7803693B2 (en) | 2007-02-15 | 2010-09-28 | John Trezza | Bowed wafer hybridization compensation |
| WO2009021266A1 (en) | 2007-08-15 | 2009-02-19 | Christophe Alain Guex | Vessel transporting apparatus and method |
| US8168532B2 (en) | 2007-11-14 | 2012-05-01 | Fujitsu Limited | Method of manufacturing a multilayer interconnection structure in a semiconductor device |
| US8435421B2 (en) | 2007-11-27 | 2013-05-07 | Cabot Microelectronics Corporation | Metal-passivating CMP compositions and methods |
| US20090197408A1 (en) | 2008-01-31 | 2009-08-06 | Matthias Lehr | Increasing electromigration resistance in an interconnect structure of a semiconductor device by forming an alloy |
| US20090200668A1 (en) | 2008-02-07 | 2009-08-13 | International Business Machines Corporation | Interconnect structure with high leakage resistance |
| US20100327443A1 (en) | 2008-02-22 | 2010-12-30 | Barun Electronics, Co., Ltd. | Joining structure and a substrate-joining method using the same |
| US8349635B1 (en) | 2008-05-20 | 2013-01-08 | Silicon Laboratories Inc. | Encapsulated MEMS device and method to form the same |
| US8241961B2 (en) | 2008-12-09 | 2012-08-14 | Young Hae KIM | Method for manufacturing hetero-bonded wafer |
| US8476165B2 (en) | 2009-04-01 | 2013-07-02 | Tokyo Electron Limited | Method for thinning a bonding wafer |
| US8242600B2 (en) | 2009-05-19 | 2012-08-14 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
| US8039966B2 (en) | 2009-09-03 | 2011-10-18 | International Business Machines Corporation | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects |
| US20110076787A1 (en) | 2009-09-25 | 2011-03-31 | Iftikhar Ahmad | Method and apparatus for uniform microwave treatment of semiconductor wafers |
| US20110074040A1 (en) | 2009-09-29 | 2011-03-31 | Manfred Frank | Semiconductor Device And Method For Making Same |
| US20110084403A1 (en) | 2009-10-08 | 2011-04-14 | International Business Machines Corporation | Pad bonding employing a self-aligned plated liner for adhesion enhancement |
| US8482132B2 (en) | 2009-10-08 | 2013-07-09 | International Business Machines Corporation | Pad bonding employing a self-aligned plated liner for adhesion enhancement |
| US8314007B2 (en) | 2009-12-23 | 2012-11-20 | Soitec | Process for fabricating a heterostructure with minimized stress |
| US9093350B2 (en) | 2010-07-09 | 2015-07-28 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device having first and second wiring structures with a concave portion between first and second substrates |
| US9224704B2 (en) | 2010-10-14 | 2015-12-29 | Soitec | Process for realizing a connecting structure |
| US8377798B2 (en) | 2010-11-10 | 2013-02-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and structure for wafer to wafer bonding in semiconductor packaging |
| US8476146B2 (en) | 2010-12-03 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing wafer distortion through a low CTE layer |
| US8620164B2 (en) | 2011-01-20 | 2013-12-31 | Intel Corporation | Hybrid III-V silicon laser formed by direct bonding |
| US20120212384A1 (en) | 2011-02-17 | 2012-08-23 | International Business Machines Corporation | Integrated antenna for rfic package applications |
| US8988299B2 (en) | 2011-02-17 | 2015-03-24 | International Business Machines Corporation | Integrated antenna for RFIC package applications |
| US20120211894A1 (en) | 2011-02-23 | 2012-08-23 | Sony Corporation | Joining electrode, method of manufacturing the same, semiconductor device, and method of manufacturing the same |
| US8501537B2 (en) | 2011-03-31 | 2013-08-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods |
| US8716105B2 (en) | 2011-03-31 | 2014-05-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods |
| US9799587B2 (en) | 2011-05-24 | 2017-10-24 | Sony Corporation | Semiconductor device |
| US8728934B2 (en) | 2011-06-24 | 2014-05-20 | Tessera, Inc. | Systems and methods for producing flat surfaces in interconnect structures |
| US9123703B2 (en) | 2011-06-24 | 2015-09-01 | Tessera, Inc. | Systems and methods for producing flat surfaces in interconnect structures |
| US9318385B2 (en) | 2011-06-24 | 2016-04-19 | Tessera, Inc. | Systems and methods for producing flat surfaces in interconnect structures |
| US20130009321A1 (en) | 2011-07-05 | 2013-01-10 | Sony Corporation | Semiconductor device, fabrication method for a semiconductor device and electronic apparatus |
| US20130020704A1 (en) | 2011-07-18 | 2013-01-24 | S.O.I.Tec Silicon On Insulator Technologies | Bonding surfaces for direct bonding of semiconductor structures |
| US8697493B2 (en) | 2011-07-18 | 2014-04-15 | Soitec | Bonding surfaces for direct bonding of semiconductor structures |
| US9893004B2 (en) | 2011-07-27 | 2018-02-13 | Broadpak Corporation | Semiconductor interposer integration |
| JP2013033786A (en) | 2011-08-01 | 2013-02-14 | Sony Corp | Semiconductor device and semiconductor device manufacturing method |
| US8441131B2 (en) | 2011-09-12 | 2013-05-14 | Globalfoundries Inc. | Strain-compensating fill patterns for controlling semiconductor chip package interactions |
| US9433093B2 (en) | 2011-11-10 | 2016-08-30 | Invensas Corporation | High strength through-substrate vias |
| US20180295718A1 (en) | 2011-11-15 | 2018-10-11 | Invensas Corporation | Cavities Containing Multi-wiring Structures And Devices |
| US9269612B2 (en) | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
| US20160020183A1 (en) | 2012-01-05 | 2016-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making bond pad |
| US20130221527A1 (en) | 2012-02-24 | 2013-08-29 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
| US20130252399A1 (en) | 2012-03-05 | 2013-09-26 | Commissariat A L'energie Atomique Et Aux Ene Alt | Direct bonding process using a compressible porous layer |
| US8647987B2 (en) | 2012-04-16 | 2014-02-11 | The Institute of Microelectronics, Chinese Academy of Science | Method for improving uniformity of chemical-mechanical planarization process |
| US20170271242A1 (en) | 2012-04-27 | 2017-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection Structure with Confinement Layer |
| US20210234070A1 (en) | 2012-05-04 | 2021-07-29 | Unm Rainforest Innovations | Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure |
| US9142517B2 (en) | 2012-06-05 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding mechanisms for semiconductor wafers |
| US8809123B2 (en) | 2012-06-05 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers |
| US9349669B2 (en) | 2012-06-08 | 2016-05-24 | Invensas Corporation | Reduced stress TSV and interposer structures |
| US9000600B2 (en) | 2012-06-08 | 2015-04-07 | Invensas Corporation | Reduced stress TSV and interposer structures |
| CN103531492A (en) | 2012-07-05 | 2014-01-22 | 台湾积体电路制造股份有限公司 | Hybrid bonding systems and methods for semiconductor wafers |
| US9184125B2 (en) | 2012-08-30 | 2015-11-10 | Ziptronix, Inc. | Heterogeneous annealing method and device |
| US9028755B2 (en) | 2012-09-21 | 2015-05-12 | Aoi Seiki Co., Ltd. | Specimen transport apparatus, specimen processing apparatus, and specimen transport method |
| US20140153210A1 (en) | 2012-12-03 | 2014-06-05 | Invensas Corporation | Advanced device assembly structures and methods |
| US20140175655A1 (en) | 2012-12-22 | 2014-06-26 | Industrial Technology Research Institute | Chip bonding structure and manufacturing method thereof |
| US20140191418A1 (en) | 2013-01-09 | 2014-07-10 | International Business Machines Corporation | Metal to metal bonding for stacked (3d) integrated circuits |
| US20140225795A1 (en) | 2013-02-08 | 2014-08-14 | Sj Antenna Design | Shielding module integrating antenna and integrated circuit component |
| US20140225258A1 (en) | 2013-02-08 | 2014-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Packages and Methods for Forming the Same |
| US9368866B2 (en) | 2013-02-08 | 2016-06-14 | Sj Antenna Design | Shielding module integrating antenna and integrated circuit component |
| US9337235B2 (en) | 2013-02-18 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
| US20140252635A1 (en) | 2013-03-08 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding Structures and Methods of Forming the Same |
| US20160276383A1 (en) | 2013-03-15 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for stacked device and method |
| US9312229B2 (en) | 2013-03-15 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with air-gap structure |
| US20140264948A1 (en) | 2013-03-15 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air Trench in Packages Incorporating Hybrid Bonding |
| US9443796B2 (en) | 2013-03-15 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air trench in packages incorporating hybrid bonding |
| US20150364434A1 (en) | 2013-03-15 | 2015-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with air-gap structure |
| US8802538B1 (en) | 2013-03-15 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for hybrid wafer bonding |
| US9960142B2 (en) | 2013-03-15 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with air-gap structure |
| US20150380368A1 (en) | 2013-04-25 | 2015-12-31 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
| US20140353828A1 (en) | 2013-05-30 | 2014-12-04 | International Business Machines Corporation | Substrate bonding with diffusion barrier structures |
| US9620481B2 (en) | 2013-05-30 | 2017-04-11 | Globalfoundries Inc. | Substrate bonding with diffusion barrier structures |
| US20160133598A1 (en) | 2013-06-03 | 2016-05-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Direct metal bonding method |
| US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
| US20180151523A1 (en) | 2013-08-29 | 2018-05-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing interconnect structure |
| US9723716B2 (en) | 2013-09-27 | 2017-08-01 | Infineon Technologies Ag | Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure |
| US9776270B2 (en) | 2013-10-01 | 2017-10-03 | Globalfoundries Inc. | Chip joining by induction heating |
| US9257399B2 (en) | 2013-10-17 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D integrated circuit and methods of forming the same |
| US20150108644A1 (en) | 2013-10-17 | 2015-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Integrated Circuit and Methods of Forming the Same |
| US20160343682A1 (en) | 2013-12-11 | 2016-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9437572B2 (en) | 2013-12-18 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pad structure for hybrid bonding and methods of forming same |
| US20150206823A1 (en) | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust Through-Silicon-Via Structure |
| US20150206840A1 (en) | 2014-01-23 | 2015-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device structure and method of manufacturing the same |
| US10446456B2 (en) | 2014-03-12 | 2019-10-15 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
| US9190345B1 (en) * | 2014-03-28 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US9230941B2 (en) | 2014-03-28 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure for stacked semiconductor devices |
| US9299736B2 (en) | 2014-03-28 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| US20150279888A1 (en) | 2014-03-28 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| US9190375B2 (en) | 2014-04-09 | 2015-11-17 | GlobalFoundries, Inc. | Solder bump reflow by induction heating |
| US20150340269A1 (en) | 2014-05-21 | 2015-11-26 | Stmicroelectronics (Crolles 2) Sas | Method of planarizing recesses filled with copper |
| US10026605B2 (en) | 2014-06-04 | 2018-07-17 | Semiconductor Components Industries, Llc | Method of reducing residual contamination in singulated semiconductor die |
| US9461007B2 (en) | 2014-07-11 | 2016-10-04 | Samsung Electronics Co., Ltd. | Wafer-to-wafer bonding structure |
| JP2016021497A (en) | 2014-07-15 | 2016-02-04 | パナソニックIpマネジメント株式会社 | Semiconductor device and manufacturing method thereof |
| US20170086320A1 (en) | 2014-07-31 | 2017-03-23 | Skyworks Solutions, Inc. | Transient liquid phase material bonding and sealing structures and methods of forming same |
| US9536848B2 (en) | 2014-10-16 | 2017-01-03 | Globalfoundries Inc. | Bond pad structure for low temperature flip chip bonding |
| US9394161B2 (en) | 2014-11-14 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | MEMS and CMOS integration with low-temperature bonding |
| US10908173B2 (en) | 2014-11-14 | 2021-02-02 | Sysmex Corporation | Sample measurement apparatus and method of measuring samples |
| KR20160066272A (en) | 2014-12-02 | 2016-06-10 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
| US9899442B2 (en) | 2014-12-11 | 2018-02-20 | Invensas Corporation | Image sensor device |
| US20170355040A1 (en) | 2014-12-22 | 2017-12-14 | Mitsubishi Heavy Industries Machine Tool Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
| US10314175B2 (en) | 2015-02-26 | 2019-06-04 | Japan Aviation Electronics Industry, Limited | Electric connection structure and electric connection member |
| US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
| US9656852B2 (en) | 2015-07-06 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS-MEMS device structure, bonding mesa structure and associated method |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10892246B2 (en) | 2015-07-10 | 2021-01-12 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US20170047307A1 (en) | 2015-07-10 | 2017-02-16 | Invensas Corporation | Structures and methods for low temperature bonding |
| US10075657B2 (en) | 2015-07-21 | 2018-09-11 | Fermi Research Alliance, Llc | Edgeless large area camera system |
| US20170025381A1 (en) | 2015-07-23 | 2017-01-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bond using a copper alloy for yield improvement |
| US9728521B2 (en) | 2015-07-23 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bond using a copper alloy for yield improvement |
| US9559081B1 (en) | 2015-08-21 | 2017-01-31 | Apple Inc. | Independent 3D stacking |
| US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
| US20170062366A1 (en) * | 2015-08-25 | 2017-03-02 | Ziptronix, Inc. | Conductive barrier direct hybrid bonding |
| US10262963B2 (en) | 2015-08-25 | 2019-04-16 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
| US20170069575A1 (en) | 2015-09-08 | 2017-03-09 | Invensas Corporation | Microelectronic assembly with redistribution structure formed on carrier |
| US20170141079A1 (en) | 2015-11-12 | 2017-05-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package and method of forming the same |
| CN106711131A (en) | 2015-11-12 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| US9496239B1 (en) | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
| US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
| US10269708B2 (en) | 2015-12-18 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
| US9881882B2 (en) | 2016-01-06 | 2018-01-30 | Mediatek Inc. | Semiconductor package with three-dimensional antenna |
| US20170194271A1 (en) | 2016-01-06 | 2017-07-06 | Mediatek Inc. | Semiconductor package with three-dimensional antenna |
| US10276619B2 (en) | 2016-01-12 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with a conductive feature passing through a passivation layer |
| US10446532B2 (en) | 2016-01-13 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Systems and methods for efficient transfer of semiconductor elements |
| US20180323177A1 (en) | 2016-04-15 | 2018-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC Formation with Dies Bonded to Formed RDLs |
| US20170330855A1 (en) | 2016-05-13 | 2017-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for Immersion Bonding |
| US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
| US9941243B2 (en) | 2016-06-09 | 2018-04-10 | Samsung Electronics Co., Ltd. | Wafer-to-wafer bonding structure |
| US9941241B2 (en) | 2016-06-30 | 2018-04-10 | International Business Machines Corporation | Method for wafer-wafer bonding |
| US10418277B2 (en) | 2016-08-09 | 2019-09-17 | International Business Machines Corporation | Air gap spacer formation for nano-scale semiconductor devices |
| US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US10886177B2 (en) | 2016-10-07 | 2021-01-05 | Xcelsis Corporation | 3D chip with shared clock distribution network |
| US10950547B2 (en) | 2016-10-07 | 2021-03-16 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
| US9666573B1 (en) | 2016-10-26 | 2017-05-30 | Micron Technology, Inc. | Methods of forming integrated circuitry |
| US20190115277A1 (en) | 2016-12-05 | 2019-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package Structure for Heat Dissipation |
| US20180175012A1 (en) | 2016-12-15 | 2018-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structures and methods of forming same |
| US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
| US20200243380A1 (en) | 2016-12-28 | 2020-07-30 | Invensas Bonding Technologies, Inc. | Microelectronic assembly from processed substrate |
| US10707087B2 (en) | 2016-12-28 | 2020-07-07 | Invensas Bonding Technologies, Inc. | Processing stacked substrates |
| US20180182639A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processing Stacked Substrates |
| US20180182666A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Microelectronic assembly from processed substrate |
| US20180190580A1 (en) | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US20180190583A1 (en) | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US10276909B2 (en) | 2016-12-30 | 2019-04-30 | Invensas Bonding Technologies, Inc. | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein |
| US20180219038A1 (en) | 2017-02-01 | 2018-08-02 | Semiconductor Components Industries, Llc | Edge seals for semiconductor packages |
| US10522499B2 (en) | 2017-02-09 | 2019-12-31 | Invensas Bonding Technologies, Inc. | Bonded structures |
| JP2018129475A (en) | 2017-02-10 | 2018-08-16 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method thereof |
| US11329034B2 (en) | 2017-03-16 | 2022-05-10 | Invensas Corporation | Direct-bonded LED structure contacts and substrate contacts |
| US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
| US20210335737A1 (en) | 2017-03-17 | 2021-10-28 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
| US20240203917A1 (en) | 2017-03-17 | 2024-06-20 | Adeia Semiconductor Bonding Technologies Inc. | Multi-metal contact structure |
| US11088099B2 (en) | 2017-03-17 | 2021-08-10 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure in microelectronic component |
| US20180273377A1 (en) | 2017-03-21 | 2018-09-27 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
| US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
| JP2018160519A (en) | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US10784191B2 (en) | 2017-03-31 | 2020-09-22 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US10985133B2 (en) | 2017-04-21 | 2021-04-20 | Invensas Bonding Technologies, Inc. | Die processing |
| US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
| US20180323227A1 (en) | 2017-05-03 | 2018-11-08 | United Microelectronics Corp. | Wafer level packaging method |
| US20180331066A1 (en) | 2017-05-11 | 2018-11-15 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
| US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
| US20250022752A1 (en) | 2017-06-05 | 2025-01-16 | Adeia Semiconductor Technologies Llc | Flat metal features for microelectronics applications |
| US20190393086A1 (en) * | 2017-06-05 | 2019-12-26 | Invensas Corporation | Flat metal features for microelectronics applications |
| US10840135B2 (en) | 2017-06-05 | 2020-11-17 | Invensas Corporation | Flat metal features for microelectronics applications |
| US20180350674A1 (en) | 2017-06-05 | 2018-12-06 | Invensas Corporation | Flat Metal Features for Microelectronics Applications |
| US11908739B2 (en) | 2017-06-05 | 2024-02-20 | Adeia Semiconductor Technologies Llc | Flat metal features for microelectronics applications |
| CN107256852B (en) | 2017-06-20 | 2019-09-13 | 上海集成电路研发中心有限公司 | Metal bonding point array with improved arrangement and semiconductor device having the same |
| US11176450B2 (en) | 2017-08-03 | 2021-11-16 | Xcelsis Corporation | Three dimensional circuit implementing machine trained network |
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US20190096741A1 (en) | 2017-09-27 | 2019-03-28 | Invensas Corporation | Interconnect structures and methods for forming same |
| US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
| US20190131277A1 (en) | 2017-11-01 | 2019-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Die stack structure and method of fabricating the same and package |
| US11011503B2 (en) | 2017-12-15 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Direct-bonded optoelectronic interconnect for high-density integrated photonics |
| US20190198407A1 (en) | 2017-12-22 | 2019-06-27 | Invensas Bonding Technologies, Inc. | Cavity packages |
| US20190198409A1 (en) | 2017-12-22 | 2019-06-27 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
| US20190244909A1 (en) | 2018-02-07 | 2019-08-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages |
| US11127738B2 (en) | 2018-02-09 | 2021-09-21 | Xcelsis Corporation | Back biasing of FD-SOI circuit blocks |
| US20200365575A1 (en) | 2018-02-15 | 2020-11-19 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
| US20190265411A1 (en) | 2018-02-26 | 2019-08-29 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
| US11256004B2 (en) | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
| US20190295954A1 (en) | 2018-03-20 | 2019-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US10991804B2 (en) | 2018-03-29 | 2021-04-27 | Xcelsis Corporation | Transistor level interconnection methodologies utilizing 3D interconnects |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| US20250096172A1 (en) | 2018-04-11 | 2025-03-20 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US20240113059A1 (en) | 2018-04-11 | 2024-04-04 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US20190319007A1 (en) | 2018-04-11 | 2019-10-17 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US12132020B2 (en) | 2018-04-11 | 2024-10-29 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US20220165692A1 (en) | 2018-04-11 | 2022-05-26 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US20200381389A1 (en) | 2018-04-11 | 2020-12-03 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US12100676B2 (en) | 2018-04-11 | 2024-09-24 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
| US12046571B2 (en) | 2018-04-11 | 2024-07-23 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US11515279B2 (en) | 2018-04-11 | 2022-11-29 | Adeia Semiconductor Bonding Technologies Inc. | Low temperature bonded structures |
| US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
| US20190333550A1 (en) | 2018-04-30 | 2019-10-31 | Invensas Corporation | Multi-die module with low power operation |
| US11355443B2 (en) | 2018-05-03 | 2022-06-07 | Invensas Corporation | Dielets on flexible and stretchable packaging for microelectronics |
| US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20190348336A1 (en) | 2018-05-14 | 2019-11-14 | Invensas Bonding Technologies, Inc. | Structures for bonding elements |
| US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
| US10923413B2 (en) | 2018-05-30 | 2021-02-16 | Xcelsis Corporation | Hard IP blocks with physically bidirectional passageways |
| US11171117B2 (en) | 2018-06-12 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Interlayer connection of stacked microelectronic components |
| US20190385966A1 (en) | 2018-06-13 | 2019-12-19 | Invensas Bonding Technologies, Inc. | Large metal pads over tsv |
| US20190385935A1 (en) | 2018-06-13 | 2019-12-19 | Invensas Bonding Technologies, Inc. | Tsv as pad |
| US10998292B2 (en) | 2018-06-13 | 2021-05-04 | Invensas Bonding Technologies, Inc. | Offset pads over TSV |
| US11348898B2 (en) | 2018-06-22 | 2022-05-31 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
| US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
| US20200006280A1 (en) | 2018-06-29 | 2020-01-02 | Priyal Shah | Bond pads for low temperature hybrid bonding |
| US20200013765A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
| US11158606B2 (en) | 2018-07-06 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
| US20200013637A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
| US20200035641A1 (en) | 2018-07-26 | 2020-01-30 | Invensas Bonding Technologies, Inc. | Post cmp processing for hybrid bonding |
| US20200075553A1 (en) | 2018-08-28 | 2020-03-05 | Xcelsis Corporation | Integrated voltage regulator and passive components |
| US20200075520A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
| US20200075534A1 (en) | 2018-08-31 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US20200098711A1 (en) | 2018-09-20 | 2020-03-26 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
| US20200126906A1 (en) | 2018-10-22 | 2020-04-23 | Invensas Bonding Technologies, Inc. | Interconnect structures |
| US20220130787A1 (en) | 2018-12-18 | 2022-04-28 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
| US20200194396A1 (en) | 2018-12-18 | 2020-06-18 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
| US11244920B2 (en) | 2018-12-18 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
| US12154880B2 (en) | 2018-12-18 | 2024-11-26 | Adeia Semiconductor Bonding Technologies Inc. | Method and structures for low temperature device bonding |
| US20250087616A1 (en) | 2018-12-18 | 2025-03-13 | Adeia Semiconductor Bonding Technologies Inc. | Method and structures for low temperature device bonding |
| US20200227367A1 (en) | 2019-01-14 | 2020-07-16 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US20200258857A1 (en) | 2019-02-11 | 2020-08-13 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same |
| US20200279821A1 (en) | 2019-03-01 | 2020-09-03 | Invensas Corporation | Nanowire bonding interconnect for fine-pitch microelectronics |
| US20200294908A1 (en) | 2019-03-11 | 2020-09-17 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
| US20220139975A1 (en) | 2019-03-14 | 2022-05-05 | Sony Semiconductor Solutions Corporation | Solid-state image pickup apparatus and manufacturing method therefor, and electronic equipment |
| US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
| US20200328165A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
| US20200328162A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
| US20200328164A1 (en) | 2019-04-12 | 2020-10-15 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
| US20200335408A1 (en) | 2019-04-22 | 2020-10-22 | lnvensas Bonding Technologies, Inc., | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
| US20200371154A1 (en) | 2019-05-23 | 2020-11-26 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
| US20200395321A1 (en) | 2019-06-12 | 2020-12-17 | Invensas Bonding Technologies, Inc. | Sealed bonded structures and methods for forming the same |
| US20200411483A1 (en) | 2019-06-26 | 2020-12-31 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
| US20210028144A1 (en) | 2019-07-24 | 2021-01-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US20210028136A1 (en) | 2019-07-26 | 2021-01-28 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
| US20210098359A1 (en) | 2019-09-26 | 2021-04-01 | Intel Corporation | Methods & structures for improved electrical contact between bonded integrated circuit interfaces |
| US20210098411A1 (en) | 2019-09-26 | 2021-04-01 | Intel Corporation | Mixed hybrid bonding structures and methods of forming the same |
| US20210098412A1 (en) | 2019-09-26 | 2021-04-01 | Invensas Bonding Technologies, Inc. | Direct gang bonding methods and structures |
| US20210118864A1 (en) | 2019-10-21 | 2021-04-22 | Invensas Corporation | Non-Volatile Dynamic Random Access Memory |
| US20210143125A1 (en) | 2019-11-07 | 2021-05-13 | Invensas Corporation | Scalable Architecture for Reduced Cycles Across SoC |
| US20210181510A1 (en) | 2019-12-17 | 2021-06-17 | Invensas Bonding Technologies, Inc. | Bonded optical devices |
| US20210193624A1 (en) | 2019-12-20 | 2021-06-24 | Invensas Corporation | Apparatus For Non-Volatile Random Access Memory Stacks |
| US20210193625A1 (en) | 2019-12-23 | 2021-06-24 | Invensas Bonding Technologies, Inc. | Electrical redundancy for bonded structures |
| US20210193603A1 (en) | 2019-12-23 | 2021-06-24 | Invensas Bonding Technologies, Inc. | Circuitry for electrical redundancy in bonded structures |
| US20210242050A1 (en) | 2020-02-04 | 2021-08-05 | Nanya Technology Corporation | Semiconductor device having hybrid bonding interface, method of manufacturing the semiconductor device, and method of manufacturing semiconductor device assembly |
| US20210242152A1 (en) | 2020-02-05 | 2021-08-05 | Invensas Bonding Technologies, Inc. | Selective alteration of interconnect pads for direct bonding |
| US20210257333A1 (en) | 2020-02-17 | 2021-08-19 | Yangtze Memory Technologies Co., Ltd. | Hybrid wafer bonding method and structure thereof |
| US20210296282A1 (en) | 2020-03-19 | 2021-09-23 | Invensas Bonding Technologies, Inc. | Dimension compensation control for directly bonded structures |
| US20210305202A1 (en) | 2020-03-31 | 2021-09-30 | Invensas Bonding Technologies, Inc. | Reliable hybrid bonded apparatus |
| US20210366820A1 (en) | 2020-05-19 | 2021-11-25 | Invensas Bonding Technologies, Inc. | Laterally unconfined structure |
| US20210407941A1 (en) | 2020-06-30 | 2021-12-30 | Invensas Bonding Technologies, Inc. | Integrated device packages |
| US20220077087A1 (en) | 2020-09-04 | 2022-03-10 | Invensas Bonding Technologies, Inc. | Bonded structure with interconnect structure |
| US20220077063A1 (en) | 2020-09-04 | 2022-03-10 | Invensas Bonding Technologies, Inc. | Bonded structure with interconnect structure |
| US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
| US20220139867A1 (en) | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US20220139869A1 (en) | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US20220149002A1 (en) | 2020-11-10 | 2022-05-12 | Sandisk Technologies Llc | Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners |
| US20220157752A1 (en) | 2020-11-16 | 2022-05-19 | Commissariat à l'énergie atomique et aux énergies alternatives | Electronic circuit for a hybrid molecular bonding |
| US11769747B2 (en) | 2020-12-16 | 2023-09-26 | Kioxia Corporation | Semiconductor device and method of manufacturing the same |
| US20220246497A1 (en) | 2020-12-28 | 2022-08-04 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| WO2022147429A1 (en) | 2020-12-28 | 2022-07-07 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| US20220208650A1 (en) | 2020-12-28 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| US20220208723A1 (en) | 2020-12-30 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Directly bonded structures |
| US20220208702A1 (en) | 2020-12-30 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Structure with conductive feature and method of forming same |
| US20220285303A1 (en) | 2021-03-03 | 2022-09-08 | Invensas Bonding Technologies, Inc. | Contact structures for direct bonding |
| US20220320036A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
| US20220320035A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US20220319901A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
| US20230005850A1 (en) | 2021-06-30 | 2023-01-05 | Invensas Bonding Technologies, Inc. | Element with routing structure in bonding layer |
| US20230005849A1 (en) | 2021-07-01 | 2023-01-05 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| US20230019869A1 (en) | 2021-07-16 | 2023-01-19 | Invensas Bonding Technologies, Inc. | Optically occlusive protective element for bonded structures |
| US20230036441A1 (en) | 2021-08-02 | 2023-02-02 | Invensas Bonding Technologies, Inc. | Protective semiconductor elements for bonded structures |
| US20230067677A1 (en) | 2021-09-01 | 2023-03-02 | Invensas Bonding Technologies, Inc. | Sequences and equipment for direct bonding |
| US20230069183A1 (en) | 2021-09-01 | 2023-03-02 | Invensas Llc | Stacked structure with interposer |
| US20230115122A1 (en) | 2021-09-14 | 2023-04-13 | Adeia Semiconductor Bonding Technologies Inc. | Method of bonding thin substrates |
| US20230100032A1 (en) | 2021-09-24 | 2023-03-30 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with active interposer |
| US20230122531A1 (en) | 2021-10-18 | 2023-04-20 | Invensas Llc | Reduced parasitic capacitance in bonded structures |
| US20230123423A1 (en) | 2021-10-19 | 2023-04-20 | Adeia Semiconductor Bonding Technologies Inc | Stacked inductors in multi-die stacking |
| US20230120352A1 (en) | 2021-10-19 | 2023-04-20 | Sandisk Technologies Llc | Non-volatile memory with adjusted bit line voltage during verify |
| US20230130259A1 (en) | 2021-10-22 | 2023-04-27 | Invensas Llc | Radio frequency device packages |
| US20230187412A1 (en) | 2021-10-25 | 2023-06-15 | Adeia Semiconductor Bonding Technologies Inc. | Power distribution for stacked electronic devices |
| US20230125395A1 (en) | 2021-10-27 | 2023-04-27 | Adeia Semiconductor Bonding Technologies Inc. | Stacked structures with capacitive coupling connections |
| US20230142680A1 (en) | 2021-10-28 | 2023-05-11 | Adeia Semiconductor Bonding Technologies Inc. | Stacked electronic devices |
| US20230140107A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
| US20230132632A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Diffusion barriers and method of forming same |
| US20230207437A1 (en) | 2021-11-05 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Multi-channel device stacking |
| US20230154816A1 (en) | 2021-11-17 | 2023-05-18 | Adeia Semiconductor Bonding Technologies Inc. | Thermal bypass for stacked dies |
| US20230154828A1 (en) | 2021-11-18 | 2023-05-18 | Adeia Semiconductor Bonding Technologies Inc. | Fluid cooling for die stacks |
| US20230187264A1 (en) | 2021-12-13 | 2023-06-15 | Adeia Semiconductor Technologies Llc | Methods for bonding semiconductor elements |
| US20230187317A1 (en) | 2021-12-13 | 2023-06-15 | Adeia Semiconductor Bonding Technologies Inc. | Interconnect structures |
| US20230197453A1 (en) | 2021-12-17 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Structure with conductive feature for direct bonding and method of forming same |
| US20230197559A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling for die packages |
| US20230197560A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling in microelectronics |
| US20230197496A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding and debonding of elements |
| US20230197655A1 (en) | 2021-12-22 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Low stress direct hybrid bonding |
| US20230207474A1 (en) | 2021-12-23 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with interconnect assemblies |
| US20240213191A1 (en) | 2021-12-23 | 2024-06-27 | Adeia Semiconductor Bonding Technologies Inc. | Controlled grain growth for bonding and bonded structure with controlled grain growth |
| US20230207514A1 (en) | 2021-12-23 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Apparatuses and methods for die bond control |
| US20230215836A1 (en) | 2021-12-23 | 2023-07-06 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding on package substrates |
| US20230207402A1 (en) | 2021-12-27 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded frame wafers |
| US20230245950A1 (en) | 2022-01-31 | 2023-08-03 | Adeia Semiconductor Bonding Technologies Inc. | Heat dissipating system for electronic devices |
| US20230268300A1 (en) | 2022-02-24 | 2023-08-24 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures |
| US20230299029A1 (en) | 2022-03-16 | 2023-09-21 | Adeia Semiconductor Bonding Technologies Inc. | Expansion control for bonding |
| US20230343734A1 (en) | 2022-04-25 | 2023-10-26 | Adeia Semiconductor Bonding Technologies Inc. | Expansion controlled structure for direct bonding and method of forming same |
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| US20240079376A1 (en) | 2022-09-07 | 2024-03-07 | Adeia Semiconductor Bonding Technologies Inc. | Rapid thermal processing for direct bonding |
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| US20240186248A1 (en) | 2022-12-01 | 2024-06-06 | Adeia Semiconductor Bonding Technologies Inc. | Backside power delivery network |
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Non-Patent Citations (138)
| Title |
|---|
| Akolkar, R., "Current status and advances in Damascene Electrodeposition," Encyclopedia of Interfacial Chemistry: Surface Science and Electrochemistry, 2017, 8 pages. |
| Basol et al., "Electrochemical mechanical deposition (ECMDT technique for semiconductor interconnect applications," Microelectronic Engineering, 2002, vol. 64, pp. 43-51. |
| Basol et al., "Planar copper plating and electropolishing techniques, "Chemical Engineering Communication, Jul. 2006, 14 pages. |
| Basol et al., "Study on the Mechanism of Electrochemical Mechanical Deposition of Copper Layers,"Nu Tool Inc., 1655 McCandless Drive, Milpitas, CA 95035, Electrochemical Processes in ULSI and MEMS, Proceedings of the International Symposium; Proceedings vol. 2004-17, pp. 155-160. |
| Berla et al., "A Model for Power Law Creep Controlled Hillock Growth". Materials Science and Engineering: A. Aug. 15, 2008;488(1-2): 594-600. |
| Bush, Steve, "Electronica: Automotive power modules from On Semi," ElectronicsWeekly.com, indicating an ONSEMI AR0820 product was to be demonstrated at a Nov. 2018 trade show, https://www.electronicsweekly.com/news/products/power-supplies/electronica-automotive-power-modules-semi-2018-11/ (published Nov. 8, 2018; downloaded Jul. 26, 2023). |
| Che, F.X. et al., "Study on Cu protrusion of through-silicon via," IEEE Transactions on Components, Packaging and Manufacturing Technology, May 2013, vol. 3, No. 5, pp. 732-739. |
| Chen et al., "Wafer Level Bonding Using Localized Radio-Frequency Induction Heating". Science China Technological Sciences. May 2010;53: 1252-1257. |
| Chiu et al., "Low-Temperature Wafer-to-Wafer Hybrid Bonding by Nanocrystalline Copper". In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) May 31, 2022 (pp. 679-684). |
| Classone Technologies, "Copper RDL Plating"—Using the Solstice® CopperMax™ Reactor, downloaded from https://classone.com/electroplating/copper-rdl-plating/ on Sep. 11, 2024; 3 pages. |
| Das et al., "Theory of welding of metallic parts in microwave cavity applicator," Fundamental J. Modern Physics. 2012;3(2): 125-155. |
| De Messemaeker, Joke et al., "Correlation between Cu microstructure and TSV Cu pumping," 2014 Electronic Components & Technology Conference, pp. 613-619. |
| Dela Pena, Eden M. et al., "Electrodeposited copper using direct and pulse currents from electrolytes containing low concentration of additives," School of Chemical and Process Engineering, University of Strathclyde, 2018 Surface and Coating Technology, 40 pages. |
| Di Cioccio, L. et al., "An overview of patterned metal/dielectric surface bonding: Mechanism, alignment and characterization," Journal of The Electrochemical Society, 2011, vol. 158, No. 6, pp. P81-P86. |
| Diehm et al., "Low temperature processing of highly integrated assemblies by selective microwave heating". 2006 1st Electronic Systemintegration Technology Conference, Dresden, Germany, 2006, pp. 608-611, doi: 10.1109/ESTC.2006.280066. |
| Ericson et al., A transmission electron microscopy study of hillocks in Thin Aluminum Films. J Vac Sci Technol. B: Jan. 1, 1991;9(1): 58-63. |
| Ganesan, Kousik, "Capable copper electrodeposition process for integrated circuit-substrate packaging manufacturing," A dissertation presented in partial fulfillment of the requirments for the degree Doctor of Philosophy, Arizona State University, May 2018, 320 pages. |
| Gondcharton, P. et al., "Kinetics of low temperature direct copper-copper bonding," Microsyst Technol, 2015, vol. 21, pp. 995-1001. |
| Heryanto, A. et al., "Effect of copper TSV annealing on via protrustion for TSV wafer fabrication," Journal of Electronic Materials, 2012, vol. 41, No. 9, pp. 2533-2542. |
| Hobbs, Anthony et al., "Evolution of grain and micro-void structure in electroplated copper interconnects," Materials Transactions, 2002, vol. 43, No. 7, pp. 1629-1632. |
| Hofmann et al., "Localized Induction Heating of Cu—Sn Layers for Rapid Solid-Liquid Interdiffusion Bonding Based on Miniaturized Coils," Micromachines. Aug. 12, 2022;13(8): 1307 in 24 pages. |
| Hu et al., "Two-Step Ar/N2 Plasma-Activated Al Surface for Al—Al Direct Bonding". In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) May 31, 2022 (pp. 324-329); doi: 10.1109/ECTC51906.2022.00060. |
| Huang, Q., "Effects of impurity elements on isothermal grain growth of electroplated copper," Journal of The Electrochemical Society, 2018, vol. 165, No. 7, pp. D251-D257. |
| Huang, Q., "Impurities in the electroplated sub-50 nm Cu lines: The effects of the plating additives," Journal of The Electrochemical Society, 2014, vol. 161, No. 9, pp. D388-D394. |
| Hwang et al., "A Model for Hillock Growth in Al Thin Films Controlled by Plastic Deformation". Acta Materialia. Sep. 1, 2007;55(15): 5297-5301. |
| Hwang et al., "Effect of Film Thickness and Annealing Temperature on Hillock Distributions in Pure Al Films". Scripta materialia. Jan. 1, 2007;56(1): 17-20. |
| International Search Report and Written Opinion for PCT/US2023/084424, dated Apr. 1, 2024, 11 pages. |
| Iwai, T. et al., "Influence of microwave annealing on optical and electrical properties of plasma-induced defect structures in Si substrate," Journal of Vacuum Science & Technology A, 2015, vol. 33, Issue 6, pp. 061403-1-061403-9. |
| Iwamura et al., "Effect of Aluminum Oxide Caps on Hillock Formation in Aluminum Allow Films". Thin Solid Films. Jul. 30, 1999;349(1-2): 191-198. |
| Jiang, T. et al., "Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects," Applied Physics Letters, 2013, vol. 103, pp. 211906-1-211906-5. |
| Juang, Jing-Ye et al., "Copper-to-copper direct bonding on highly (111)-oriented nanotwinned copper in no-vacuum ambient," Scientific Reports, Sep. 17, 2018, vol. 8, 11 pages. |
| Ker, Ming-Dou et al., "Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICS," IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. |
| Khan, Muhammed et al., "Damascene Process and Chemical Mechanical Planarization," http://www.ece.umd.edu/class/enee416/GroupActivities/Damascene%20Presentation.pdf, 25 pages. |
| Kim, Myung Jun et al., "Characteristics of pulse-reverse electrodeposited Cu thin film," I. Effects of Anodic Step in the Absence of an Organic Additives, Journal of The Electrochemical Society, 2012, vol. 159, No. 9, pp. D538-D543. |
| Kim, Myung Jun et al., "Characteristics of pulse-reverse electrodeposited Cu thin film," II. Effects of Organic Additives, Journal of The Electrochemical Society, 2012, vol. 159, No. 9, pp. D544-D548. |
| Kimura, M. et al., "Investigation of implantation damage recovery using microwave annealing for high performance image sensing devices," ITE Trans. on MTA, 2016, vol. 4, No. 2, pp. 85-90. |
| Kowalski et al., "Microwave annealing for low temperature activation". In 2007 15th International Conference on Advanced Thermal Processing of Semiconductors Oct. 2, 2007 (pp. 51-56). IEEE. |
| Lee, I.K. et al., "Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor," ACS Appl Mater Interfaces, Dec. 2014, vol. 6, No. 24, pp. 22680-22686. |
| Liu, C. et al., "Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu," Scientific Reports, May 12, 2015, 5:09734, pp. 1-11. |
| Liu, Chien-Min et al., "Effect of grain orientations of Cu seed layers on the growth of <111>-oriented nanotwinned Cu," Scientific Reports, 2014, vol. 4, No. 6123, 4 pages. |
| Liu, Zi-Yu et al. "Detection and formation mechanism of micro-defects in ultrafine pitch Cu-Cu direct bonding," Chin. Phys. B, 2016, vol. 25, No. 1, pp. 018103-1-018103-7. |
| Lu, L. et al., "Grain growth and strain release in nanocrystalline copper," Journal of Applied Physics, vol. 89, Issue 11, pp. 6408. |
| Mendez, Julie Marie, "Characterization of copper electroplating and electropolishing processes for semiconductor interconnect metallization," Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy, Department of Chemical Engineering, Case Western Reserve University, Aug. 2009, 140 pages. |
| Menk, L.A. et al., "Galvanostatic plating with a single additive electrolyte for bottom-up filling of copper in Mesoscale TSVs," Microsystems and Engineering Sciences Applications (MESA) Complex, Sandia National Laboratories, Albuquerque, New Mexico, 2019 J. Electrochem. Soc. 166, 17 pages. |
| Mori E., "Suppression of Byproduct Accumulation in Rechargeable Aluminum-Air Batteries Using Non-Oxide Ceramic Materials as Air Cathode Materials". Sustainable Energy & Fuels. 2017;1(5): 1082-1089. |
| Moriceau, H. et al., "Overview of recent direct wafer bonding advances and applications," Advances in Natural Sciences-Nanoscience and Nanotechnology, 2010, 11 pages. |
| Morrison, Jim et al., "Samsung Galaxy S7 Edge Teardown," Tech Insights (posted Apr. 24, 2016), includes description of hybrid bonded Sony IMX260 dual-pixel sensor, https://www.techinsights.com/blog/samsung-galaxy-s7-edge-teardown, downloaded Jul. 11, 2023, 9 pages. |
| Mott, D. et al., "Synthesis of size-controlled and shaped copper nanoparticles," Langmuir, 2007, vol. 23, No. 10, pp. 5740-5745. |
| Nakanishi, H. et al., "Studies on SiO2—SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS," Sensors and Actuators, 2000, vol. 79, pp. 237-244. |
| Oberhammer, J. et al., "Sealing of adhesive bonded devices on wafer level," Sensors and Actuators A, 2004, vol. 110, No. 1-3, pp. 407-412, see pp. 407-412, and Figures 1(a)-1(l), 6 pages. |
| Onsemi AR0820 image, cross section of a CMOS image sensor product. The part in the image was shipped on Sep. 16, 2021. Applicant makes no representation that the part in the image is identical to the part identified in the separately submitted reference BUSH, Nov. 8, 2018, ElectronicsWeekly.com ("BUSH article"); however, the imaged part and the part shown in the BUSH article share the part number "ONSEMI AR0820.". |
| Ortleb, Thomas et al., "Controlling macro and micro surface topography for a 45nm copper CMP process using a high resolution profiler," Proc. of SPIE, 2008, vol. 6922, 11 pages. |
| Pankratov, E.L., "Redistribution of dopant during microwave annealing of a multilayer structure for production p-n junction," Journal of Applied Physics, 2008, vol. 103, Issue 6, pp. 064320-1-064320-10. |
| Parthasaradhy, N.V., "Practical Electroplating Handbook," 1989, Prentice-Hall, Inc., pp. 54-56. |
| Plobi, A. et al., "Wafer direct bonding: tailoring adhesion between brittle materials," Materials Science and Engineering Review Journal, 1999, R25, 88 pages. |
| Rebhan et al., "Low-Temperature Aluminum-Aluminum Wafer Bonding". ECS Transactions. Aug. 24, 2016;75(9): 15; 10 pages. |
| Roy, A. et al., "Annealing effects on the surface properties of Cu—TiC thin films," Materials Today: Proceedings, 2021, vol. 44, Part 1, pp. 170-175. |
| Santoro C.J., "Thermal Cycling and Surface Reconstruction in Aluminum Thin Films". Journal of the Electrochemical Society. Mar. 1, 1969;116(3):361-364. |
| Saraswat, Stanford Presentation, Cu Interconnect slides, web page web.stanford.edu/class/ee311/NOTES/Cu_Interconnect_Slides.pdf, 19 pages. |
| Song, Xiaohui, "Atomic study of copper-copper bonding using nanoparticles," Journal of Electronic Packaging, Jun. 2020, vol. 142, 5 pages. |
| Song, Xiaoning, "Microstructure and mechanical properties of electrodeposited copper films," A thesis submitted to the College of Engineering and Physical Sciences of the University of Birmingham, 2011, web page etheses.bham.ac.uk/id/eprint/1764/, 111 pages. |
| Sony IMX260 images, showing various cross sections and materials analyses for a hybrid bonded back side illuminated CMOS image sensor. The part in the images was shipped in Apr. 2016. Applicant makes no representation that the part in the images is identical to the part identified in the separately submitted reference Morrison et al. (Tech Insights article dated Apr. 24, 2016), describing and showing a similar sensor product within the Samsung Galaxy S7; however the imaged part and the part shown in the Morrison et al. article share the part name "Sony IMX260 image." (8 pages). |
| Suga et al., "Bump-less interconnect for next generation system packaging," Electronic Components and Technology Conference, 2001, IEEE, pp. 1003-1008. |
| Suga, T., "Feasibility of surface activated bonding for ultra-fine pitch interconnection—A new concept of bump-less direct bonding for system level packaging," The University of Tokyo, Research Center for Science and Technology, 2000 Electronic Components and Technology Conference, 2000 IEEE, pp. 702-705. |
| Swingle, Karen D., "Nanograin Copper Deposition Using an Impinging Jet Electrode," A Thesis submitted in partial satisfaction of the requirements of the degree of Master of Science, University of California, San Diego, 2013, 102 pages. |
| Takahashi, K. et al., "Transport phenomena that control electroplated copper filling of submicron vias and trenches," Journal of The Electrochemical Society, 1999, vol. 146, No. 12, pp. 4499-4503. |
| Zhang, Q.X. et al., "The effects of rapid thermal annealing and microwave annealing on the electrical properties of ZrO2 metal-insulator-metal capacitors," Optik, Feb. 2019, vol. 179, pp. 1057-1062. |
| Zheng, Z. et al., "Study of grain size effect of Cu metallization on interfacial microstructures of solder joints," Microelectronics Reliability, 2019, vol. 99, pp. 44-51. |
| Zik, N. et al., "Thermally produced nano catalyst for biodiesel production: A review," Journal of Advanced Research in Fluid Mechanics and Thermal Sciences, 2018, vol. 52, Issue 2, pp. 139-147. |
| Akolkar, R., "Current status and advances in Damascene Electrodeposition," Encyclopedia of Interfacial Chemistry: Surface Science and Electrochemistry, 2017, 8 pages. |
| Basol et al., "Electrochemical mechanical deposition (ECMDT technique for semiconductor interconnect applications," Microelectronic Engineering, 2002, vol. 64, pp. 43-51. |
| Basol et al., "Planar copper plating and electropolishing techniques, "Chemical Engineering Communication, Jul. 2006, 14 pages. |
| Basol et al., "Study on the Mechanism of Electrochemical Mechanical Deposition of Copper Layers,"Nu Tool Inc., 1655 McCandless Drive, Milpitas, CA 95035, Electrochemical Processes in ULSI and MEMS, Proceedings of the International Symposium; Proceedings vol. 2004-17, pp. 155-160. |
| Berla et al., "A Model for Power Law Creep Controlled Hillock Growth". Materials Science and Engineering: A. Aug. 15, 2008;488(1-2): 594-600. |
| Bush, Steve, "Electronica: Automotive power modules from On Semi," ElectronicsWeekly.com, indicating an ONSEMI AR0820 product was to be demonstrated at a Nov. 2018 trade show, https://www.electronicsweekly.com/news/products/power-supplies/electronica-automotive-power-modules-semi-2018-11/ (published Nov. 8, 2018; downloaded Jul. 26, 2023). |
| Che, F.X. et al., "Study on Cu protrusion of through-silicon via," IEEE Transactions on Components, Packaging and Manufacturing Technology, May 2013, vol. 3, No. 5, pp. 732-739. |
| Chen et al., "Wafer Level Bonding Using Localized Radio-Frequency Induction Heating". Science China Technological Sciences. May 2010;53: 1252-1257. |
| Chiu et al., "Low-Temperature Wafer-to-Wafer Hybrid Bonding by Nanocrystalline Copper". In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) May 31, 2022 (pp. 679-684). |
| Classone Technologies, "Copper RDL Plating"—Using the Solstice® CopperMax™ Reactor, downloaded from https://classone.com/electroplating/copper-rdl-plating/ on Sep. 11, 2024; 3 pages. |
| Das et al., "Theory of welding of metallic parts in microwave cavity applicator," Fundamental J. Modern Physics. 2012;3(2): 125-155. |
| De Messemaeker, Joke et al., "Correlation between Cu microstructure and TSV Cu pumping," 2014 Electronic Components & Technology Conference, pp. 613-619. |
| Dela Pena, Eden M. et al., "Electrodeposited copper using direct and pulse currents from electrolytes containing low concentration of additives," School of Chemical and Process Engineering, University of Strathclyde, 2018 Surface and Coating Technology, 40 pages. |
| Di Cioccio, L. et al., "An overview of patterned metal/dielectric surface bonding: Mechanism, alignment and characterization," Journal of The Electrochemical Society, 2011, vol. 158, No. 6, pp. P81-P86. |
| Diehm et al., "Low temperature processing of highly integrated assemblies by selective microwave heating". 2006 1st Electronic Systemintegration Technology Conference, Dresden, Germany, 2006, pp. 608-611, doi: 10.1109/ESTC.2006.280066. |
| Ericson et al., A transmission electron microscopy study of hillocks in Thin Aluminum Films. J Vac Sci Technol. B: Jan. 1, 1991;9(1): 58-63. |
| Ganesan, Kousik, "Capable copper electrodeposition process for integrated circuit-substrate packaging manufacturing," A dissertation presented in partial fulfillment of the requirments for the degree Doctor of Philosophy, Arizona State University, May 2018, 320 pages. |
| Gondcharton, P. et al., "Kinetics of low temperature direct copper-copper bonding," Microsyst Technol, 2015, vol. 21, pp. 995-1001. |
| Heryanto, A. et al., "Effect of copper TSV annealing on via protrustion for TSV wafer fabrication," Journal of Electronic Materials, 2012, vol. 41, No. 9, pp. 2533-2542. |
| Hobbs, Anthony et al., "Evolution of grain and micro-void structure in electroplated copper interconnects," Materials Transactions, 2002, vol. 43, No. 7, pp. 1629-1632. |
| Hofmann et al., "Localized Induction Heating of Cu—Sn Layers for Rapid Solid-Liquid Interdiffusion Bonding Based on Miniaturized Coils," Micromachines. Aug. 12, 2022;13(8): 1307 in 24 pages. |
| Hu et al., "Two-Step Ar/N2 Plasma-Activated Al Surface for Al—Al Direct Bonding". In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) May 31, 2022 (pp. 324-329); doi: 10.1109/ECTC51906.2022.00060. |
| Huang, Q., "Effects of impurity elements on isothermal grain growth of electroplated copper," Journal of The Electrochemical Society, 2018, vol. 165, No. 7, pp. D251-D257. |
| Huang, Q., "Impurities in the electroplated sub-50 nm Cu lines: The effects of the plating additives," Journal of The Electrochemical Society, 2014, vol. 161, No. 9, pp. D388-D394. |
| Hwang et al., "A Model for Hillock Growth in Al Thin Films Controlled by Plastic Deformation". Acta Materialia. Sep. 1, 2007;55(15): 5297-5301. |
| Hwang et al., "Effect of Film Thickness and Annealing Temperature on Hillock Distributions in Pure Al Films". Scripta materialia. Jan. 1, 2007;56(1): 17-20. |
| International Search Report and Written Opinion for PCT/US2023/084424, dated Apr. 1, 2024, 11 pages. |
| Iwai, T. et al., "Influence of microwave annealing on optical and electrical properties of plasma-induced defect structures in Si substrate," Journal of Vacuum Science & Technology A, 2015, vol. 33, Issue 6, pp. 061403-1-061403-9. |
| Iwamura et al., "Effect of Aluminum Oxide Caps on Hillock Formation in Aluminum Allow Films". Thin Solid Films. Jul. 30, 1999;349(1-2): 191-198. |
| Jiang, T. et al., "Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects," Applied Physics Letters, 2013, vol. 103, pp. 211906-1-211906-5. |
| Juang, Jing-Ye et al., "Copper-to-copper direct bonding on highly (111)-oriented nanotwinned copper in no-vacuum ambient," Scientific Reports, Sep. 17, 2018, vol. 8, 11 pages. |
| Ker, Ming-Dou et al., "Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICS," IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. |
| Khan, Muhammed et al., "Damascene Process and Chemical Mechanical Planarization," http://www.ece.umd.edu/class/enee416/GroupActivities/Damascene%20Presentation.pdf, 25 pages. |
| Kim, Myung Jun et al., "Characteristics of pulse-reverse electrodeposited Cu thin film," I. Effects of Anodic Step in the Absence of an Organic Additives, Journal of The Electrochemical Society, 2012, vol. 159, No. 9, pp. D538-D543. |
| Kim, Myung Jun et al., "Characteristics of pulse-reverse electrodeposited Cu thin film," II. Effects of Organic Additives, Journal of The Electrochemical Society, 2012, vol. 159, No. 9, pp. D544-D548. |
| Kimura, M. et al., "Investigation of implantation damage recovery using microwave annealing for high performance image sensing devices," ITE Trans. on MTA, 2016, vol. 4, No. 2, pp. 85-90. |
| Kowalski et al., "Microwave annealing for low temperature activation". In 2007 15th International Conference on Advanced Thermal Processing of Semiconductors Oct. 2, 2007 (pp. 51-56). IEEE. |
| Lee, I.K. et al., "Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor," ACS Appl Mater Interfaces, Dec. 2014, vol. 6, No. 24, pp. 22680-22686. |
| Liu, C. et al., "Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu," Scientific Reports, May 12, 2015, 5:09734, pp. 1-11. |
| Liu, Chien-Min et al., "Effect of grain orientations of Cu seed layers on the growth of <111>-oriented nanotwinned Cu," Scientific Reports, 2014, vol. 4, No. 6123, 4 pages. |
| Liu, Zi-Yu et al. "Detection and formation mechanism of micro-defects in ultrafine pitch Cu-Cu direct bonding," Chin. Phys. B, 2016, vol. 25, No. 1, pp. 018103-1-018103-7. |
| Lu, L. et al., "Grain growth and strain release in nanocrystalline copper," Journal of Applied Physics, vol. 89, Issue 11, pp. 6408. |
| Mendez, Julie Marie, "Characterization of copper electroplating and electropolishing processes for semiconductor interconnect metallization," Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy, Department of Chemical Engineering, Case Western Reserve University, Aug. 2009, 140 pages. |
| Menk, L.A. et al., "Galvanostatic plating with a single additive electrolyte for bottom-up filling of copper in Mesoscale TSVs," Microsystems and Engineering Sciences Applications (MESA) Complex, Sandia National Laboratories, Albuquerque, New Mexico, 2019 J. Electrochem. Soc. 166, 17 pages. |
| Mori E., "Suppression of Byproduct Accumulation in Rechargeable Aluminum-Air Batteries Using Non-Oxide Ceramic Materials as Air Cathode Materials". Sustainable Energy & Fuels. 2017;1(5): 1082-1089. |
| Moriceau, H. et al., "Overview of recent direct wafer bonding advances and applications," Advances in Natural Sciences-Nanoscience and Nanotechnology, 2010, 11 pages. |
| Morrison, Jim et al., "Samsung Galaxy S7 Edge Teardown," Tech Insights (posted Apr. 24, 2016), includes description of hybrid bonded Sony IMX260 dual-pixel sensor, https://www.techinsights.com/blog/samsung-galaxy-s7-edge-teardown, downloaded Jul. 11, 2023, 9 pages. |
| Mott, D. et al., "Synthesis of size-controlled and shaped copper nanoparticles," Langmuir, 2007, vol. 23, No. 10, pp. 5740-5745. |
| Nakanishi, H. et al., "Studies on SiO2—SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS," Sensors and Actuators, 2000, vol. 79, pp. 237-244. |
| Oberhammer, J. et al., "Sealing of adhesive bonded devices on wafer level," Sensors and Actuators A, 2004, vol. 110, No. 1-3, pp. 407-412, see pp. 407-412, and Figures 1(a)-1(l), 6 pages. |
| Onsemi AR0820 image, cross section of a CMOS image sensor product. The part in the image was shipped on Sep. 16, 2021. Applicant makes no representation that the part in the image is identical to the part identified in the separately submitted reference BUSH, Nov. 8, 2018, ElectronicsWeekly.com ("BUSH article"); however, the imaged part and the part shown in the BUSH article share the part number "ONSEMI AR0820.". |
| Ortleb, Thomas et al., "Controlling macro and micro surface topography for a 45nm copper CMP process using a high resolution profiler," Proc. of SPIE, 2008, vol. 6922, 11 pages. |
| Pankratov, E.L., "Redistribution of dopant during microwave annealing of a multilayer structure for production p-n junction," Journal of Applied Physics, 2008, vol. 103, Issue 6, pp. 064320-1-064320-10. |
| Parthasaradhy, N.V., "Practical Electroplating Handbook," 1989, Prentice-Hall, Inc., pp. 54-56. |
| Plobi, A. et al., "Wafer direct bonding: tailoring adhesion between brittle materials," Materials Science and Engineering Review Journal, 1999, R25, 88 pages. |
| Rebhan et al., "Low-Temperature Aluminum-Aluminum Wafer Bonding". ECS Transactions. Aug. 24, 2016;75(9): 15; 10 pages. |
| Roy, A. et al., "Annealing effects on the surface properties of Cu—TiC thin films," Materials Today: Proceedings, 2021, vol. 44, Part 1, pp. 170-175. |
| Santoro C.J., "Thermal Cycling and Surface Reconstruction in Aluminum Thin Films". Journal of the Electrochemical Society. Mar. 1, 1969;116(3):361-364. |
| Saraswat, Stanford Presentation, Cu Interconnect slides, web page web.stanford.edu/class/ee311/NOTES/Cu_Interconnect_Slides.pdf, 19 pages. |
| Song, Xiaohui, "Atomic study of copper-copper bonding using nanoparticles," Journal of Electronic Packaging, Jun. 2020, vol. 142, 5 pages. |
| Song, Xiaoning, "Microstructure and mechanical properties of electrodeposited copper films," A thesis submitted to the College of Engineering and Physical Sciences of the University of Birmingham, 2011, web page etheses.bham.ac.uk/id/eprint/1764/, 111 pages. |
| Sony IMX260 images, showing various cross sections and materials analyses for a hybrid bonded back side illuminated CMOS image sensor. The part in the images was shipped in Apr. 2016. Applicant makes no representation that the part in the images is identical to the part identified in the separately submitted reference Morrison et al. (Tech Insights article dated Apr. 24, 2016), describing and showing a similar sensor product within the Samsung Galaxy S7; however the imaged part and the part shown in the Morrison et al. article share the part name "Sony IMX260 image." (8 pages). |
| Suga et al., "Bump-less interconnect for next generation system packaging," Electronic Components and Technology Conference, 2001, IEEE, pp. 1003-1008. |
| Suga, T., "Feasibility of surface activated bonding for ultra-fine pitch interconnection—A new concept of bump-less direct bonding for system level packaging," The University of Tokyo, Research Center for Science and Technology, 2000 Electronic Components and Technology Conference, 2000 IEEE, pp. 702-705. |
| Swingle, Karen D., "Nanograin Copper Deposition Using an Impinging Jet Electrode," A Thesis submitted in partial satisfaction of the requirements of the degree of Master of Science, University of California, San Diego, 2013, 102 pages. |
| Takahashi, K. et al., "Transport phenomena that control electroplated copper filling of submicron vias and trenches," Journal of The Electrochemical Society, 1999, vol. 146, No. 12, pp. 4499-4503. |
| Zhang, Q.X. et al., "The effects of rapid thermal annealing and microwave annealing on the electrical properties of ZrO2 metal-insulator-metal capacitors," Optik, Feb. 2019, vol. 179, pp. 1057-1062. |
| Zheng, Z. et al., "Study of grain size effect of Cu metallization on interfacial microstructures of solder joints," Microelectronics Reliability, 2019, vol. 99, pp. 44-51. |
| Zik, N. et al., "Thermally produced nano catalyst for biodiesel production: A review," Journal of Advanced Research in Fluid Mechanics and Thermal Sciences, 2018, vol. 52, Issue 2, pp. 139-147. |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20250149499A1 (en) * | 2023-11-08 | 2025-05-08 | Globalfoundries U.S. Inc. | Hybrid bonding with selectively formed dielectric material |
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| TW202429589A (en) | 2024-07-16 |
| WO2024145034A1 (en) | 2024-07-04 |
| CN120604336A (en) | 2025-09-05 |
| US20240222315A1 (en) | 2024-07-04 |
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| JP2025542482A (en) | 2025-12-25 |
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