[go: up one dir, main page]

US12121733B2 - Energy generation from tiny sources - Google Patents

Energy generation from tiny sources Download PDF

Info

Publication number
US12121733B2
US12121733B2 US17/774,032 US202017774032A US12121733B2 US 12121733 B2 US12121733 B2 US 12121733B2 US 202017774032 A US202017774032 A US 202017774032A US 12121733 B2 US12121733 B2 US 12121733B2
Authority
US
United States
Prior art keywords
capacitor
capacitors
stack
capacitor stack
charged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US17/774,032
Other languages
English (en)
Other versions
US20230006468A1 (en
Inventor
Gerd TEEPE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Celtro GmbH
Original Assignee
Celtro GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celtro GmbH filed Critical Celtro GmbH
Assigned to CELTRO GMBH reassignment CELTRO GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TEEPE, Gerd
Publication of US20230006468A1 publication Critical patent/US20230006468A1/en
Application granted granted Critical
Publication of US12121733B2 publication Critical patent/US12121733B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61M—DEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
    • A61M37/00—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin
    • A61M37/0015—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin by using microneedles
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/362—Heart stimulators
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/37211—Means for communicating with stimulators
    • A61N1/37235—Aspects of the external programmer
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/37512—Pacemakers
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/378—Electrical supply
    • A61N1/3785—Electrical supply generated by biological activity or substance, e.g. body movement
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/001—Energy harvesting or scavenging
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering using capacitors as storage or buffering devices
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/3756—Casings with electrodes thereon, e.g. leadless stimulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/50—Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2310/00—The network for supplying or distributing electric power characterised by its spatial reach or by the load
    • H02J2310/10—The network having a local or delimited stationary reach
    • H02J2310/20—The network being internal to a load
    • H02J2310/23—The load being a medical device, a medical implant, or a life supporting device

Definitions

  • the invention discloses a device for collection of tiny charges in the Nano-Coulomb-range and below, comprising at least one capacitor stack build by n capacitors and 2n switches (n ⁇ N), at least one further capacitor outside the capacitor stack as buffer capacity, at least two additional switches and a DC input source.
  • the n capacitors are dedicated to be sequentially charged by the DC input source one after the other, wherein the 2n switches in the capacitor stack couple the n capacitors sequentially to the DC input source.
  • the at least one further capacitor is dedicated to be charged from the n capacitors of the capacitor stack at once.
  • the invention discloses a method for small charge collection, comprising the steps of sequentially charging the n capacitors of the at least one capacitor stack by coupling one capacitor after the other to the DC input source by selectively closing the switches and discharging the n capacitors of the capacitor stack into at least one further capacitor outside the capacitor stack (n ⁇ N). Additionally, the usage of the device or the method according to the invention to collect charges from sources with electrical potentials of a few millivolts is disclosed.
  • batteries are used as power supply in pacemakers. If the life time of the battery is over, it must either be recharged or even be replaced by a new one.
  • Conventional recharging systems use for example magnetic induction (U.S. Pat. No. 3,867,950 A1) or solar cells (US 2009326597 AA). These systems suffer from the fact that additional technical devices outside the patient's body must be used to charge the pacemaker, which still makes it necessary to check the pacemaker's performance status and perform a battery charging procedure either by a technician or by the patient if necessary. A procedure which is usually unfavorable for the patient.
  • IoT Internet of Things
  • IoT describes a system of interrelated computing devices, mechanical and digital machines, objects, animals or people that are provided with unique identifiers enabling the transfer of data over a network without requiring human-to-human or human-to-computer interaction.
  • unique identifiers need wireless power supply and it is highly desirable if no recharging by an external power source (e.g. power outlet) or even replacement of the power supply is necessary.
  • the invention provides a device and a method to collect small charges from electrical energy sources e.g. from the surrounding environment in the amount that a power supply can be provided for portable electronics, wherein the small voltage levels of the source themselves are too low to be used as power supply for any kind of portable electronics.
  • the invention targets electrical energy sources like bioelectric signals, radio signals, thermal sources or vibrations, which means the electrical energy voltage levels are in the range of a few millivolt.
  • the present invention provides a device for charge collection comprising
  • the present invention provides a method for charge collection, comprising at least one capacitor stack build by n capacitors and 2n switches, at least one further capacitor outside the capacitor stack as buffer capacitor, at least two additional switches and a DC input source, comprising the steps
  • the device according to the invention comprises at least one DC input source.
  • the DC input source has an electric potential of a few millivolts.
  • the electric potential of the DC input source is between 1 mV and 100 mV, more preferably between 1 mV and 50 mV, most preferably between 1 mV and 10 mV.
  • Suitable energy sources with electrical potentials in this range are for example bioelectric signals, radio signals, thermal sources or vibrations.
  • bioelectric signals from nerve potential are used as DC input.
  • Bioelectric signals of nerve cells have typically an electric potential of 60 mV and an internal resistance of 20 to 200 kOhm.
  • the device is dedicated to collect small charges in the Nano-Coulomb-range and below.
  • the device according to the invention comprises at least one capacitor stack, wherein the capacitor stack is built by n capacitors and 2n switches, wherein n ⁇ N.
  • the capacitor stack can comprise as much capacitors as can be accommodated constructively.
  • n is between 2 and 20, more preferably between 2 and 14.
  • the n capacitors of the capacitors stack are dedicated to be sequentially charged by the DC input source one after the other.
  • the 2n switches of the capacitor stack couple the n capacitors selectively to the DC input source in a way that every capacitor is sequentially charged by the DC input source one after the other.
  • the controlling and sequencing of the switches is generated from a usual CMOS-Logic, which is common to Microelectronics.
  • At least one further capacitor is situated outside the capacitor stack, which works as a buffer capacitor.
  • the at least one further capacitor is dedicated to be charged from the n capacitors of the at least one capacitor stack at once.
  • the device comprises one further capacitor outside the capacitor stack as buffer capacitor.
  • the device comprises two further capacitors outside the capacitor stack as buffer capacitors.
  • the device comprises at least two additional switches outside the capacitor stack.
  • the device comprises two additional switches outside the capacitor stack.
  • the additional switches are dedicated to selectively couple the capacitor stack to the at least one further capacitor outside the capacitor stack or to a further capacitor stack.
  • the device comprises four additional switches outside the capacitor stack.
  • the device comprises four additional switches outside the at least one capacitor stack if the device comprises a first further capacitor outside the at least one capacitor stack and a second further capacitor outside the at least one capacitor stack.
  • two additional switches are dedicated to selectively connect the at least one capacitor stack to the first further capacitor outside the capacitor stack and the two further additional switches are dedicated to selectively connect the at least one capacitor stack to the second further capacitor outside the capacitor stack.
  • the device according to the invention comprises two further capacitors outside the capacitor stack as buffer capacitors outside the at least one capacitor stack and four additional switch outside the at least one capacitor stack.
  • the at least one capacitor stack comprises at least three conductive plates wherein the conductive plates have a top-side and a bottom-side and wherein the top-side of at least one conductive plate is part of a first capacitor and the bottom-side of the at least one conductive plate is part of a neighboring further capacitor.
  • the capacitor stack comprises an isolating material between the conductive plates in a way that a capacitor is built.
  • the capacitance of the capacitors built according to the invention is quite wide ranging from 1 nF down to 1 fF and even below. It depends on plate geometries and the dielectric material employed between the plates.
  • Parasitic capacitances are well known in the art. They arise at the interfaces of capacitors to the surrounding and are unwanted as those have to be charged at every charge cycle of the capacitor. This process lowers the charging efficiency of the capacitor and therefore its end-charging voltage. Accordingly, in the state of the art every capacitor has two interfaces to the surrounding and therefore two interfaces where parasitic capacitances arise.
  • the capacitor stack according to the invention is able to provide n capacitors, wherein only the first and the last capacitor have a substantial interface to the surrounding. Therefore, advantageously, only at these two interfaces parasitic capacitances will form. Accordingly, the charging efficiency of the n capacitors of the capacitor stack is increased as well as the end-charging voltage.
  • all capacitors are connected in series electrically.
  • the device is an integrated circuit wherein switches are realized as transistors and capacitors are realized by conductive plates from integrated circuit technology.
  • the conductive plates are made of material selected from the group comprising metal or polysilicon or any other conductive material from integrated circuit technology. Suitable metals are copper and aluminum and tungsten.
  • the isolating material is selected from the group comprising SiO 2 , SiN and Hf 2 O and stacks thereof.
  • an inductor can be applied to perform intermediate storage in a resonant circuit configuration.
  • the device comprises additionally an inductor.
  • the switching frequency is chosen high enough so that the resonant frequency of the parasitic capacitor and the inductivity equals the inverse of the total charging/discharging cycle time of the capacitor stack.
  • the charging/discharging timing of the capacitor stack should be adapted such that a sine-curve is approximated.
  • the device comprises several capacitor stacks wherein every capacitor stack is dedicated to charge another capacitor stack and one capacitor stack is dedicated to charge at least one further capacitor outsides the capacitor stacks.
  • the device comprises x capacitor stacks and 2x switches outside the capacitor stacks.
  • the device comprises 1 to 20 capacitor stacks, preferably 5 to 15, most preferably 13 to 15, as this is within the capabilities of current semiconductor production technologies.
  • the charging frequency of a further capacitor stack is n-times slower than the charging frequency of the first capacitor stack (with n being the number of capacitors in the first capacitor stack).
  • the n capacitors of the first capacitor stack are charged by the DC input source one after the other. Afterwards the n capacitors of the first capacitor stack are discharged at once to one capacitor of a further capacitor stack.
  • the further capacitor stack is built by k capacitors, k charging cycles are needed to charge the k capacitors of the further capacitor stack one after the other. If all capacitors of the further capacitor stack are charged they are discharged to a further capacitor outside the capacitor stack at once. In total, the entire discharge occurs at a frequency k ⁇ n lower than the charging frequency of the first capacitor stack.
  • the maximum voltage of the second stack is k ⁇ n the feeding voltage of the DC input source. For example with 10 mV at the DC input source, and 10 capacitors on each capacitors stack, 1 V can be realized as output at maximum.
  • every further capacitor stack is dedicated to be fed by positive or negative voltages from another capacitor stack. Therefore, the switches outside the capacitor stacks connecting the capacitor stacks have to be sequenced accordingly. If the first capacitor stack provides positive or negative charge, charging of the second capacitor stack has to be done accordingly.
  • the device according to the invention provides a needle or a needle bed in contact with nerve cells as DC input source.
  • the device according to the invention enables the collection of low charges from multiple cells in the tissue.
  • the needles of the needle bed are isolated against each other and connected through to the back-side by soldering bumps.
  • An integrated circuit ideally has a solder bump at the same location, so that a connection can be made from a needle to an input on an integrated circuit.
  • the input functions as DC input source according to the invention.
  • the DC input source is a needle or a needle bed in contact with nerve cells, wherein the needles of the needle bed are isolated against each other and connected through to the back-side by a soldering bump.
  • the needle or the needles of the needle bed are connected to a capacitor stack by a soldering bump.
  • the device according to the invention can easily be multiplied up to the number of needles of the needle bed.
  • the needle bed has 2-2000 needles, more preferably 50-1500 and most preferably 100-1000 needles.
  • an integrated circuit is provided with the same number of devices, according to the invention, as the number of needles of the needle bed.
  • the DC input source is a needle bed in contact with nerve cells, wherein every needle of the needle bed is connected to a capacitor stack by a soldering bump.
  • the sequencing of the switches is generated from a usual CMOS-Logic, which is common to Microelectronics.
  • CMOS-logic For the CMOS-logic to function, voltages of a few hundred millivolts are required. Typical state of the art semiconductor technology operates at around 1 Volt or slightly below. Since the device according to the invention collects energy starting with a few millivolts at the source, this voltage is too low to operate the CMOS-logic.
  • the device additionally comprises a coil, which is dedicated to receive a startup energy by magnetic coupling with another coil.
  • a further aspect of the invention concerns a method for collecting charges, especially for collecting small charges in the Nano-Coulomb range and below.
  • the advantages and advantageous embodiments according to the invention also apply to the method according to the invention and vice versa.
  • the invention provides a method for charge collection, comprising at least one capacitor stack build by n capacitors and 2n switches, at least one further capacitor outside the capacitor stack as buffer capacitor, at least two additional switches and a DC input source, comprising the steps
  • the n capacitors of the capacitor stack are sequentially charged one after the other in n charging cycles and the n capacitors of the capacitor stack are discharged in an n+1 st cycle into at least one further capacitor outside the capacitor stack at once.
  • the capacitors of a capacitor stack could be charged in any order.
  • the following charging scheme is proposed.
  • the n capacitors of the capacitor stack are sequentially charged one after the other in n charging cycles, wherein the first capacitor is charged, afterwards the capacitor which is next to the first one is charged, afterwards the capacitor which is next to the one charged before is charged until all n capacitors are charged.
  • the capacitors of the capacitor stack are all discharged into at least one further capacitor outside the capacitor stack at once. This is done by selectively closing the switches of the capacitor stack and the switches outside the capacitor stack.
  • a bipolar charging of the capacitor stack can be done.
  • each capacitor of a capacitor stack can be charged to positive or negative voltages, depending which plate of the capacitor is grounded.
  • capacitors in the capacitor stack are being loaded sequentially. While one plate is grounded, the other plate is charged to a fraction of the input voltage. Which means, that capacitors in the capacitor stack above the currently grounded plate are pushed to positive voltages, whereas the plates below the currently grounded plate are pushed to negative voltages. Accordingly, the capacitors of the capacitor stack can be charged to positive or negative voltages, by closing the switches inside the capacitor stack in an appropriate manner, thereby selecting the grounded plate of the each capacitor in the capacitor stack.
  • the at least one capacitor stack is first charged with positive voltages and after all capacitors in the capacitor stack are charged, all capacitors of the capacitor stack are discharged into the first further capacitor outside the capacitor stack. Afterwards the capacitors of the capacitor stack are charged with negative voltages and after all capacitors in the capacitor stack are charged all capacitors of the capacitor stack are discharged into the second further capacitor outside the capacitor stack.
  • the n capacitors of the capacitor stack are sequentially charged the n capacitors are discharged into a first further capacitor outside the capacitor stack, afterwards the n capacitors of the capacitor stack are sequentially charged in the reversed order and after the n capacitors are charged the n capacitors are discharged into a second further capacitor outside the capacitor stack.
  • the n capacitors of a capacitor stack can be discharged at once into one capacitor of a further capacitor stack.
  • the charging sequence for the second capacitor stack is derived from the first stack and couples to its timing. Instead of discharging the first capacitor stack into a buffer capacitance, it is discharged into one of the capacitors forming the second capacitor stack. Fundamentally it could be any of capacitors of the second capacitor stack, but practically the charging of the second capacitor stack should follow the same method already described. Which means charging of the capacitors of a capacitor stack should be done by charging neighboring capacitors. As the second capacitor stack is also loaded with some parasitic capacitance to the outside, sequentially charging the second stack as described will keep the charge flown into the parasitic capacitances to a minimum at each step.
  • One of the embodiments of the discharge circuit is a bipolar setting. This allows the charging of the second capacitor stack with negative and positive charge depending on the sequence.
  • FIG. 1 illustrates the capacitors of a capacitor stack
  • FIG. 2 shows a general MIM-Capacitance with parasitic capacitance to ground
  • FIGS. 3 A and B show a capacitor stack comprising an inductor
  • FIG. 4 shows a needle bed as DC input source
  • FIG. 5 show the device comprising an additional coil
  • FIG. 6 illustrates the device comprising two capacitor stacks
  • FIG. 7 shows an electrical circuit for charging and discharging of 3 capacitors of a capacitor stack
  • FIG. 8 shows an electrical circuit for charging and discharging of n capacitors of a capacitor stack (A) and the timing of the switches (B);
  • FIG. 9 shows an electrical circuit for charging 3 capacitors of a capacitor stack with negative voltages and discharging them
  • FIG. 10 shows an electrical circuit for charging 3 capacitors of a capacitor stack with negative or positive voltages and discharging them
  • FIG. 11 shows the timing of the switches (A) and a simplified timing of the voltage of the capacitances (B) during charging of 3 capacitors of a capacitor stack with negative and positive voltages and discharging them;
  • FIG. 12 shows an electrical circuit with integrated transistors for charging the capacitors with positive voltage (A) and for charging the capacitors with positive or negative voltages (B);
  • FIG. 13 shows bipolar discharge of a capacitor stack.
  • FIG. 1 illustrates the structure of a capacitor stack according to the invention.
  • M 1 to Mn+1 are conductive plates which are separated by layers of isolating material I 1 to In.
  • a first capacitor C 1 is built by the bottom-side of the conductive plate M 1 , the isolating material layer I 1 and the top-side of the conductive plate M 2 .
  • the neighboring capacitor C 2 is built by the bottom-side of the conductive plate M 2 , the isolating material layer I 2 and the top-side of the conductive plate M 3 .
  • Further capacitors are built in the same way up to the capacitor Cn which is built by the bottom-side of the conductive plate Mn, the isolating layer In and the top-side of the conductive plate Mn+1.
  • the capacitor stack according to the invention only the top-side of the conductive plate M 1 and the bottom-side of the conductive plate Mn+1 have substantial interfaces to the surrounding, at which parasitic capacitances will arise.
  • FIG. 2 The structure of a MIM-Capacitor according to the state of the art is illustrated in FIG. 2 .
  • the conductive plates M 2 and M 1 are separated by a layer of isolating material I 1 , forming the capacitor C 1 .
  • the top-side of the conductive plate M 2 has an interface to the surrounding air, whereby a parasitic capacitance CA is arises.
  • the bottom-side of the conductive plate M 1 has an interface to an isolator 1 and a substrate 2 .
  • the isolator 1 is made of SiO 2 and the substrate 2 is made of silicon.
  • a parasitic capacitance CS arises. According to the state of the art at every capacitor two parasitic capacitances arise which lowers the charging efficiency of the capacitor.
  • the charging efficiency is increased by using the design of a capacitor stack according to the invention.
  • the capacitor stack is built by n capacitors, wherein the capacitor stack comprises at least three conductive plates wherein at least one conductive plate is part of a first capacitor and the bottom-side of the conductive plate is part of a neighboring second capacitor.
  • the invention comprises an inductor as shown in FIGS. 3 (A) and (B).
  • FIG. 3 (A) illustrates the capacitor stack with its typical layered design, wherein M 1 to Mn+1 are conductive plates and I 1 to In are layers of isolating material. Connected to the capacitor stack is an inductor 3 .
  • FIG. 3 (B) illustrates the parasitic capacitance arising from the capacitor stack as a whole as one parasitic capacitor 4 and the inductor 3 as part of an electrical circuit.
  • FIG. 4 shows a needle bed formed by several needles 10 which are fixed by a needle support 11 . Every needle 10 is connected to a capacitor stack by a bump 12 . Using an integrated circuit the capacitor stacks are arranged on a microchip 13 .
  • the design according to the invention enables to harvest energy from multiple nerve cells.
  • the device additionally comprises a coil 22 , which is dedicated to receive a startup energy by magnetic coupling with another external coil 21 , whereby the external coil 21 is connected to an AC voltage source 20 .
  • the coil 22 is connected to other parts 23 of the device in a way that the CMOS-logic can be powered with energy over the magnetic field, thus providing energy for startup.
  • FIG. 6 shows an embodiment of the invention, wherein the device comprises two capacitor stacks 31 , 32 .
  • the electrical circuits of the capacitors stacks are illustrated as grey blocks 30 , 33 .
  • the first capacitor stack 31 is charged by the small charges collected from the source UB of nerve cells by a needle 10 , wherein the nerve tissue has a resistance R.
  • the capacitors of the capacitor stack are charged according to the invention until all capacitors of the capacitor stack 31 are charged.
  • the first capacitor stack 31 is connected to the second capacitor stack 32 and its electrical circuit 33 by switches E 1 and E 2 . If E 1 and E 2 are closed one capacitor of the capacitor stack 32 is charged by the capacitors of the capacitors stack 31 at once.
  • the capacitors of the capacitor stack 31 are charged again by the source UB and after all capacitors of capacitor stack 31 are charged they are discharged at once in a further capacitor of capacitor stack 32 , by closing switches E 1 and E 2 in an appropriate manner.
  • This charging scheme is repeated until all capacitors of capacitor stack 32 are charged.
  • all capacitors of capacitor stack 32 are discharged at once in a further capacitor 34 outside the capacitor stacks by closing the switches E 3 and E 4 .
  • the output voltage is illustrated as UE.
  • the capacitors of the capacitor stacks are charged one after the other by charging always neighboring capacitors.
  • the charging and discharging scheme of the device according to the invention is used in analogue manner if the device comprises more than two capacitor stacks, e.g. up to 20 capacitor stacks.
  • the electrical circuit of one embodiment of the device is illustrated in FIG. 7 .
  • the device comprises one capacitor stack which is built by three capacitors C 1 , C 2 , C 3 and switches LB 1 , LB 2 , LB 3 , LM 1 , LM 2 and LM 3 .
  • Two additional switches E 1 and E 2 outside the capacitor stack one further capacitor CA outside the capacitor stack and a DC input source UB.
  • DC input source UB a needle 10 is used which collects small charges form nerve cells, the resistance of the nerve tissue is illustrated as R.
  • the capacitors are all stacked up according to the invention and are charged sequentially. Capacitor C 1 is charged by closing switches LB 1 and LM 1 simultaneously.
  • capacitor CA is charged by the capacitors of the capacitors stack (C 1 , C 2 , C 3 ) at once and functions as a buffer capacitor.
  • the circuit of FIG. 3 requires one more cycle than capacitors in the capacitor stack, meaning in this particular case 3 cycles are required for the charging of C 1 , C 2 and C 3 and one additional cycle to discharge the stack into capacitor CA.
  • the exit is marked with reference sign 41 .
  • the electrical circuit can be used in the same way for any number of capacitors in the capacitor stack.
  • Each additional capacitor in the capacitor stack has to be complemented with two additional loading switches. Also this means that for each additional capacitor in the capacitor stack, an additional loading cycle has to be introduced.
  • the appropriate electrical circuit is shown in FIG. 8 (A) for a capacitor stack with n capacitors illustrated as C 1 , C 2 , C 3 up to Cn.
  • the timing of the switches is illustrated in FIG. 8 (B).
  • the graph shows the status of the switches depending on the time t. Closed state of the switches is illustrated as a box.
  • One charging cycle of all capacitors in a capacitor stack including discharging all capacitors into a further capacitor outside the capacitor stack is marked with reference sign 50 .
  • LB 1 and LM 1 are closed to charge capacitor C 1 .
  • LB 1 and LM 1 are opened and LM 2 and LB 2 are closed to charge C 2 , and so on until LBn and LMn are closed to charge capacitor Cn.
  • switches E 1 and E 2 are closed to discharge all capacitors of the capacitor stack at once into a further capacitor outside the capacitor stack. The discharging is additionally marked with reference sign 51 .
  • the device according to the invention is also able to generate negative readout voltages. Therefore, an electrical circuit according to FIG. 9 is used.
  • the device shown comprises three capacitors (C 1 , C 2 , C 3 ) in the capacitor stack. All reference signs correspond to the reference signs already used in the electrical circuit shown in FIG. 8 .
  • To generate negative voltages the charging order of the capacitors of the capacitor stack is reversed. Which means in this case firstly C 3 is charged, next C 2 and afterwards C 1 . For this the top plate is connected to ground by closing E 1 . Capacitances in the capacitor stack are charged sequentially, while one plate is grounded, the other plate is charged to a fraction of the input voltage.
  • FIG. 11 (A) The timing for the switches in the electrical circuit shown in FIG. 10 is illustrated in FIG. 11 (A) together with the timing of the voltages ( FIG. 11 (B)).
  • the capacitances are charged in the order C 1 -C 2 -C 3 by closing sequentially LB 1 , LM 1 -LB 2 , LM 2 -LB 3 , LM 3 , followed by a discharging cycle, wherein switches EP 1 and EP 2 are simultaneously closed.
  • the negative charging cycle is executed in reverse order: C 3 -C 2 -C 1 by closing sequentially LB 3 , LM 3 -LB 2 , LM 2 -LB 1 , LM 1 followed by discharging the capacitors of the capacitor stack in capacitor 45 by simultaneously closing switches EN 1 and EN 2 .
  • FIG. 11 (B) illustrates the timing of the voltage. It should be noted that this is a largely simplified sketch in view to elaborate the principle.
  • the voltage potentials V 1 through V 4 from FIG. 10 are depicted and correspond to the conductive plates in the capacitor stack.
  • the representation assumes that the circuit charging is settled after many iterations, so that all the capacitors are charged to the full amount and that no output current is unloading the output capacitor 44 or 45 , respectively. It can be seen that the entire capacitor stack oscillates and multiplies the voltage from the charging source 64 by the number of capacitors in the capacitor stack. Mass potential is illustrated by line 65 , the amount of voltage discharged in capacitor 44 is marked with reference sign 62 while the amount of voltage discharged in capacitor 45 is marked with reference sign 63 .
  • FIG. 7 shows how a metal-isolator stack can be used to construct a compact capacitor stack.
  • the implementation of the switching elements with integrated transistors need to consider the diffusions in the semiconductor material in view to consider the diode effects of the MOS-Transistors.
  • FIGS. 12 (A) and (B) show the partial circuit for charging of the capacitor stack from FIG. 7 when it is realized with integrated transistors. The regularity is visible and also the capability to extend the capacitor stack to n capacitors.
  • the capacitor stack generates positive as well as negative voltage, depending whether the top plate or the bottom plate is grounded. There are two mechanisms to make sure that the non-selected transistors do not open.
  • FIG. 12 (A) employs gate voltages between the most positive and the most negative potential in the stack. Also, when using bulk-technology, all p-substrates (of the NMOS-transistors) have to be tied to the most negative voltage in the circuits as otherwise Source/Bulk or Drain/Bulk diode action may disturb the functionality. For SOI- and FDSOI-Technologies this constraints does not exist due to the absence of the bulk-diode.
  • FIG. 12 (B) both positive and negative voltages are being used.
  • the gates of the NMOS-transistors are switched with voltages between 0 and positive supply and the PMOS-transistors are switched between 0 and the negative supply.
  • the non-selected path to the capacitor stack is always open in the sense of not connected.
  • the selected path puts positive supply to NLn and NMn, while PLn and PMn receive the negative supply voltage.
  • Discharge occurs from the top- and bottom-plates of the capacitor stack where the sum of the individual capacitor-voltages can be found. Discharging of a positive or a negative voltage depends on whether the top-conductive plate or the bottom-conductive plate is grounded. A suitable discharge circuit is depicted in FIG. 13 .
  • the top-conductive plate of the capacitor stack is connected through PE 1 to the buffer-capacitor CP outside the capacitor stack.
  • PM 1 and PE 1 are both activated when their gates are connected to the negative supply (VNN). To block the paths through those transistors, the gates are both being pulled to the positive supply (VPP).
  • the top-conductive plate is grounded through NM 2 and the bottom-conductive plate is connected through NE 2 to the buffer-capacitor CN outside the capacitor stack.
  • Both NMOS-transistors are activated when their gate-voltage is pulled to the positive supply VPP.
  • both gate potential are pulled to negative supply (VNN).
  • a device according to the invention with one capacitor stack comprising 9 capacitors is connected to an input voltage source of 10 mV.
  • the inner resistance of the voltage source is 100 kOhm. Every capacitor of the capacitor stack has a capacitance of 100 pF and is charged to 90%.
  • the cycle time for charging one capacitor is 25 ⁇ s.
  • the stack of 9 capacitors requires in general a cycle time of 250 ⁇ s (9 charging cycles+1 discharge cycle of 25 ⁇ s).
  • the input of 10 mV generates an output of 81 mV. This is one setting applied for harvesting of bioelectric energy.
  • a device comprising two capacitor stacks is connected to an input voltage source of 10 mV.
  • Each capacitor stack comprises 10 capacitors with a capacitance of 100 pF.
  • the capacitors of the capacitor stacks are charged one after the other to 100%, which is maximum efficiency. Therefore every capacitor of the first stack is charged to 10 mV.
  • all capacitors of the first capacitor stack are charged, all capacitors of the first capacitor stack are discharged into the top capacitor of the second capacitor stack. Accordingly, the top capacitor of the second capacitor stack is charged to 100 mV.
  • the capacitors of the first capacitor stack are charged again one after the other each to 10 mV.
  • the same device as described in example 2 is used with a charging efficiency of 50% of each capacitor in the first and second capacitor stack. With an input voltage source of 10 mV, an output voltage of 250 mV is realized. This embodiments is provided when charging times are shortened so that the capacitors are charged incompletely.

Landscapes

  • Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Veterinary Medicine (AREA)
  • Biomedical Technology (AREA)
  • Animal Behavior & Ethology (AREA)
  • Public Health (AREA)
  • Radiology & Medical Imaging (AREA)
  • Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
  • Power Engineering (AREA)
  • Heart & Thoracic Surgery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Molecular Biology (AREA)
  • Biophysics (AREA)
  • Cardiology (AREA)
  • Dermatology (AREA)
  • Medical Informatics (AREA)
  • Anesthesiology (AREA)
  • Hematology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrotherapy Devices (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
US17/774,032 2019-11-04 2020-11-03 Energy generation from tiny sources Active 2041-10-28 US12121733B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP19206852.6A EP3817185B1 (fr) 2019-11-04 2019-11-04 Génération d'énergie à partir de sources de taille réduite
EP19206852.6 2019-11-04
EP19206852 2019-11-04
PCT/EP2020/080791 WO2021089530A1 (fr) 2019-11-04 2020-11-03 Production d'énergie à partir de très petites sources

Publications (2)

Publication Number Publication Date
US20230006468A1 US20230006468A1 (en) 2023-01-05
US12121733B2 true US12121733B2 (en) 2024-10-22

Family

ID=68426267

Family Applications (2)

Application Number Title Priority Date Filing Date
US17/774,032 Active 2041-10-28 US12121733B2 (en) 2019-11-04 2020-11-03 Energy generation from tiny sources
US17/773,939 Pending US20220379128A1 (en) 2019-11-04 2020-11-03 Self-sufficient cardiac pacemaker

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/773,939 Pending US20220379128A1 (en) 2019-11-04 2020-11-03 Self-sufficient cardiac pacemaker

Country Status (8)

Country Link
US (2) US12121733B2 (fr)
EP (2) EP3817185B1 (fr)
JP (2) JP2023500899A (fr)
KR (2) KR20220101121A (fr)
CN (2) CN114902525A (fr)
BR (2) BR112022008498A2 (fr)
CA (2) CA3159792A1 (fr)
WO (2) WO2021089530A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4082426B1 (fr) * 2021-04-30 2023-07-26 Celtro GmbH Moniteur de signal auto-suffisant
EP4082603B1 (fr) * 2021-04-30 2024-01-10 Celtro GmbH Stimulateur de tissu neuronal autosuffisant
CN114098740A (zh) * 2021-12-31 2022-03-01 武汉衷华脑机融合科技发展有限公司 一种微针

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0898510A (ja) 1994-09-29 1996-04-12 Citizen Watch Co Ltd 昇圧回路およびその駆動方法
US20110300821A1 (en) * 2010-06-08 2011-12-08 Qualcomm Incorporated Techniques for optimizing gain or noise figure of an rf receiver
EP2426311A2 (fr) 2009-04-28 2012-03-07 Obschestvo S Ogranichennoi Otvetstvennostju "SONOVITA" Procédé et installation de récupération de pétrole utilisant l'énergie de vibrations élastiques
US20170179732A1 (en) * 2015-12-22 2017-06-22 Cooper Technologies Company Dynamic Tuning for Harvesting Energy from Current Transformers
WO2017208231A1 (fr) 2016-06-02 2017-12-07 W.P. Energy (S.B.) Ltd. Collecte d'énergie multibande
US20190072532A1 (en) * 2017-09-01 2019-03-07 3M Innovative Properties Company Wireless power transfer and sensing for monitoring pipelines

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3867950A (en) 1971-06-18 1975-02-25 Univ Johns Hopkins Fixed rate rechargeable cardiac pacemaker
US20070293904A1 (en) * 2006-06-20 2007-12-20 Daniel Gelbart Self-powered resonant leadless pacemaker
US20090326597A1 (en) 2008-06-26 2009-12-31 Ixys Corporation Solar cell for implantable medical device
GB0816501D0 (en) * 2008-09-10 2008-10-15 Imp Innovations Ltd Photo-ionic pacemakers
US9026212B2 (en) * 2008-09-23 2015-05-05 Incube Labs, Llc Energy harvesting mechanism for medical devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0898510A (ja) 1994-09-29 1996-04-12 Citizen Watch Co Ltd 昇圧回路およびその駆動方法
EP2426311A2 (fr) 2009-04-28 2012-03-07 Obschestvo S Ogranichennoi Otvetstvennostju "SONOVITA" Procédé et installation de récupération de pétrole utilisant l'énergie de vibrations élastiques
US20110300821A1 (en) * 2010-06-08 2011-12-08 Qualcomm Incorporated Techniques for optimizing gain or noise figure of an rf receiver
US20170179732A1 (en) * 2015-12-22 2017-06-22 Cooper Technologies Company Dynamic Tuning for Harvesting Energy from Current Transformers
WO2017208231A1 (fr) 2016-06-02 2017-12-07 W.P. Energy (S.B.) Ltd. Collecte d'énergie multibande
US20190072532A1 (en) * 2017-09-01 2019-03-07 3M Innovative Properties Company Wireless power transfer and sensing for monitoring pipelines

Also Published As

Publication number Publication date
JP2023500899A (ja) 2023-01-11
JP2023500901A (ja) 2023-01-11
BR112022008498A2 (pt) 2022-07-26
WO2021089530A1 (fr) 2021-05-14
EP3817185B1 (fr) 2022-06-22
CN114902525A (zh) 2022-08-12
CA3159794A1 (fr) 2021-05-14
EP4055681A1 (fr) 2022-09-14
KR20220101121A (ko) 2022-07-19
BR112022008505A2 (pt) 2022-07-26
CN114902526A (zh) 2022-08-12
CA3159792A1 (fr) 2021-05-14
EP3817185A1 (fr) 2021-05-05
US20220379128A1 (en) 2022-12-01
WO2021089531A1 (fr) 2021-05-14
US20230006468A1 (en) 2023-01-05
KR20220106143A (ko) 2022-07-28

Similar Documents

Publication Publication Date Title
US12121733B2 (en) Energy generation from tiny sources
Maksimovic et al. Switched-capacitor DC-DC converters for low-power on-chip applications
US10348100B2 (en) Battery balance circuit and battery apparatus thereof
AU776542B2 (en) Electric energy storage device with cell energy control, and method of controlling cell energy
US20110012559A1 (en) Circuit arrangement and method for transferring electrical charge between accumulators of an accumulator arrangement
US20110101789A1 (en) Rf power harvesting circuit
EP1388921A2 (fr) Circuit pour égalisation de batterie
US20100079034A1 (en) Circuit and method to improve energy harvesting efficiency in piezoelectric harvesters
JP2010288447A (ja) セルバランス充電システム及び方法
JP2011067021A (ja) 電力供給装置
US8933665B2 (en) Balancing voltages between battery banks
US10756643B2 (en) Flipping-capacitor rectifier circuit
Steyaert et al. When hardware is free, power is expensive! Is integrated power management the solution?
US10587126B2 (en) Power storage device, power storage control device, and power storage control method
KR20150024796A (ko) 배터리 관리 시스템 및 방법
EP2579440A1 (fr) Circuit rectificateur doté d'une fonction de court-circuitage côté CA et récupération de commutation synchronisée sur convertisseur d'inducteur
EP2306628A1 (fr) Conversion de puissance haute efficacité de condensateur commuté
CN117501605A (zh) 一种dc/dc变换电路、dc/dc变换器以及供电设备
US20220329157A1 (en) Device for converting dc-dc based on batteries
JP3728622B2 (ja) 充電装置
JP2011120466A (ja) 電力回生装置
CN112803769A (zh) 一种双输出dc-dc变换器
Ben-Yaakov et al. Resonant rectifier for piezoelectric sources
CN109980797B (zh) 采用直流压泵技术的无线能量接收机及其控制方法
Ben-Yaakov et al. New resonant rectifier for capacitive sources

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

AS Assignment

Owner name: CELTRO GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TEEPE, GERD;REEL/FRAME:059919/0677

Effective date: 20220505

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: SMAL); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE