TWM647066U - Chip packaging structure - Google Patents

Abstract

In an embodiment, a chip packaging structure includes: a substrate; a chip disposed on the substrate; an adhesive surrounding the chip and directly contacting a sidewall of the chip; a thermal interface material disposed on the chip; a heat sink disposed above the thermal interface material, wherein the heat sink has a bottom cavity facing the chip; and a metal thin film disposed between the chip and the heat sink.

Description

Chip packaging structure

Embodiments of the present disclosure relate to chip packaging technology, and in particular to chip packaging structures with thermal interface materials.

Electronic components are developing in the direction of being light, thin, short, small, high-performance, high-transmission, and high-efficiency, and the heat generated per unit area is also getting higher and higher. For example, in the past, Central Processing Unit (CPU) components The heat generated by the Pentium processor is only 20W, while the Pentium 4 exceeds 80W. When the CPU is operating, the temperature can reach over 150°C. According to the International Technology Roadmap for Semiconductors (ITRS), the future development process of the semiconductor industry (Roadmap), in the next few years, the heat generated by low-end computers will increase from about 100W to nearly 120W. The heat generated by the computer will increase significantly from the original 150W to over 180W, and the operating frequency will also increase from 2GHz to over 4GHz.

The heating power of traditional components is small, and the simplest solution is to add a heat sink or a fan to improve the heat dissipation effect. However, as the functionality and thermal power density of electronic components have increased significantly, the requirements for thermal management technology have become increasingly stringent. In the path through which component heat is transferred to the external environment, in addition to the low thermal resistance of the chip itself and the use of high-efficiency heat dissipation components, the connection density between components and the heat transfer properties of the joint materials will become the key to whether the heat dissipation technology can break through. factor. Generally, the mechanical contact interface is rough or even wavy, and there are many insulating gaps between the materials. These gaps will cause considerable heat transfer obstacles. Thermal Interface Materials (TIM) are commonly used in IC structures. It is a material used to assemble and dissipate heat from electronic components. Its main function is to fill the contact gap between the two materials, improve the heat dissipation of the system and effectively reduce the thermal impedance. A good thermal interface material must meet the following conditions: (1) have good heat dissipation characteristics, that is, have high thermal conductivity and low thermal resistance value, (2) be easy to assemble and rework, (3) have high compressibility, so that It can withstand external compressive stress when fixed on the joint surface, and can appropriately fill the gaps between interfaces to facilitate heat flow. (4) It has good wettability with electronic components and heat sinks. (5) High reliability and common service life.

Thermal Grease is one of the earliest thermal interface materials. It is composed of silicone or hydrocarbon oil with different fillers. The thermal resistance of traditional thermal grease is about 1 K·cm ² /W. In recent years, it has been reduced to about 0.2 K·cm ² /W. However, conventional heat dissipation pastes still have many problems. Due to the high viscosity of the material itself, it cannot completely fill the gaps on the joint surface. A pressure of about 300KPa must be applied to achieve ideal heat dissipation performance. In addition, because the thermal paste uses polymer materials, it cannot withstand the relative displacement between the heat sink and the chip, causing a pump-out phenomenon. The thermal paste will also suffer from the effects of being exposed to high temperatures for a long time. The polymer material chemically reacts and separates from the internal filler, greatly reducing the wettability of the joint surface. This phenomenon is called dry-out.

Elastomeric Thermal Pads are thermal interface materials based on polymeric silicone rubber. They are used to replace thermal paste. The thermal resistance value is between 1 and 3K‧cm ² /W. They are not suitable for larger applications. A high-end heat dissipation system has the advantage of being easy to form and assemble, but it requires an additional high pressure of about 700KPa to function properly. Thermal Tapes, another thermal interface material, cover the surface of base materials such as polyimide (PI), glass fiber or aluminum foil with adhesive. Its advantage is that it does not require external mechanical force to clamp, but the heat dissipation Still not ideal.

Phase Change Materials combine the excellent heat dissipation of thermal paste with the ease of processing of elastic thermal pads, and can show good thermal conductivity above or below the melting point (about 50°C to 80°C). However, the adhesion will decrease at temperatures above the melting point, so external mechanical force (about 300KPa) must be applied during use. Although the phase change material has an excellent thermal resistance value (about 0.3 to 0.7) that is comparable to that of the thermal paste. K‧cm ² /W), and can effectively solve the problems of pump-out effect and drying. However, based on the consideration of reworkability, in high-end heat dissipation systems, thermal paste is generally chosen.

In order to solve a series of shortcomings caused by polymer materials, low-melting point alloys (melting point 40 to 200°C) thermal interface materials have been developed, mainly utilizing the low-melting point characteristics of some eutectic indium-based alloys. When electronic components operate, the heat dissipated Melting the low-melting-point alloy into a liquid state can fill the interface pores. In particular, the metal itself has excellent thermal conductivity, so it can achieve a perfect heat dissipation effect. However, this liquid low melting point alloy will interact with electricity The back-crystal metal layer of the sub-component reacts with the heat sink to form a high-melting-point intermetallic compound, and the low-melting-point alloy gradually disappears and is exhausted, thus losing the original liquid, non-porous heat dissipation effect.

One embodiment of the present disclosure provides a chip packaging structure, including: a substrate; a chip disposed on the substrate; adhesive surrounding the chip and in direct contact with the sidewall of the chip; and a thermal interface material disposed on the above the wafer; a heat sink disposed above the thermal interface material, and the heat sink has a bottom groove facing the wafer; and a metal film disposed between the wafer and the heat sink.

The following disclosure provides numerous embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements. , so that they are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in various examples. Such repetition is for the sake of simplicity and clarity and is not intended to represent the relationship between the various embodiments and/or configurations discussed.

Furthermore, words relative to space may be used, such as "under", "below", "lower", "above", "higher" and other similar words, for the convenience of description. The relationship between one component(s) or feature(s) and another(s) component(s) or feature(s) in the diagram. Spatially relative terms are used to encompass different orientations of equipment in use or operation and the orientation depicted in the drawings. When the device is turned at a different orientation (rotated 90 degrees or at any other orientation), the spatially relative adjectives used therein will also be interpreted in accordance with the rotated orientation. When spatially relative terms such as those listed above are used to describe a first component relative to a second component, the first component can be directly on the other component, or it can be interposed between components or layers. When a component or layer is referred to as being "on" another component, it will be directly on and in direct contact with the other component or layer.

The terms used herein are only used to explain specific embodiments and are not intended to limit the concepts of the disclosure. Expressions used in the singular also cover expressions in the plural unless the context has a clearly different meaning. In this specification, it should be understood that terms such as "includes," "has," and "includes" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and It is not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may be present or added.

In addition, when the words "about," "approximately," etc. are used to describe a number or range of numbers, such terms are intended to cover numbers within a reasonable range based on the variations inherent in the manufacturing process as understood by one of ordinary skill in the art. And be considered. For example, the number or range of a number encompasses a reasonable range including the stated number, such as within +/-10% of the stated number, based on known manufacturing tolerances in manufacturing parts having the characteristic to which the number relates.

Some embodiments of the present disclosure are described below in which additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the described stages may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, the steps may be performed in another logical order.

1 to 4 are schematic side views illustrating the process of forming a chip packaging structure according to some embodiments.

Referring to FIG. 1 , the wafer 104 is first fixed on the substrate 102 . The substrate 102 may include a printed circuit board (PCB), a wafer substrate, an integrated circuit (IC) substrate, an interposer, a chip carrier, a circuit carrier, and a display device. The wafer 104 refers to a small piece of semiconductor wafer formed by separating the semiconductor wafer into individual grains after performing a semiconductor process on the semiconductor wafer. The chip 104 may include integrated circuits for processing and/or storing data, such as a field programmable gate array (FPGA), a processing unit (such as a graphics processing unit (GPU)) Or central processing unit (CPU), application specific integrated circuit (ASIC), memory device (for example: memory controller, memory), etc. As mentioned above, the chip 104 can be fixed on the substrate 102 using techniques including using polymer glue and soldering.

Referring to FIG. 2 , adhesive is applied around the wafer 104 and the height of the adhesive is greater than the height of the wafer 104 to form an adhesive embankment 112 . The adhesive embankment 112 can be used as a retaining wall when the thermal interface material 124 is subsequently disposed on the wafer 104 so that the thermal interface material 124 is confined within the adhesive embankment 112 . As mentioned above, applying adhesive around the wafer 104 may include spraying, extruding, dispensing, or a combination of the foregoing. The adhesive may be applied in a curing state such that the adhesive embankment 112 surrounds the wafer 104 at a distance of 0.03 to 2 mm (eg, 1 to 1.5 mm) above the wafer 104 . In some embodiments, if the adhesive embankment 112 is too low, it cannot effectively prevent the material from overflowing when the thermal interface material 124 is subsequently coated; conversely, if the adhesive embankment 112 is too high, it is not conducive to the subsequent lamination process and causes material leakage. of waste. In one embodiment, the adhesive embankments 112 are in direct contact with the sidewalls of the wafer 104 but do not contact the top surface of the wafer 104 so that the thermal interface material 124 subsequently provided can directly contact the top surface of the wafer 104 .

It should be noted that in the embodiment of this case, instead of using the metal frame surrounding the wafer 104 in the conventional technology, adhesive is used as a dike when the thermal interface material 124 is subsequently disposed. In some embodiments, the adhesive embankment 112 has plasticity below a temperature of about 390° C. Since the adhesive is directly coated around the wafer 104 and has plasticity before being completely cured, the advantage of using adhesive instead of the metal frame is It can be applied to wafers 104 of any size to avoid the conventional problem of thermal interface material failure when the metal frame may not fit the wafer (for example, the height of the metal frame is lower than the wafer 104) and the filling amount of the thermal interface material 124 is insufficient. 124 does not directly contact the heat sink to affect the heat dissipation effect. In one embodiment, the adhesive embankment 112 may be a polymer adhesive such as silicone, epoxy resin, polyimide (PI), or a combination thereof.

Referring to FIG. 3 , thermal interface material 124 is disposed within adhesive embankment 112 above wafer 104 . In one embodiment, the thermal interface material 124 is disposed on the wafer 104 by liquid dispensing. Specifically, the thermal interface material 124 can be made into alloy particles (slug) of the thermal interface material 124 by drawing and cutting wires first. The dispensing head 122 is used to heat the alloy particles of the thermal interface material 124 to melt into a liquid state, and then apply the liquid thermal interface material 124 to the adhesive embankment 112 above the wafer 104 with an air pressure of 5 to 20 Psi.

In another embodiment, the thermal interface material 124 is disposed on the wafer 104 in the form of a solid foil. Specifically, the thermal interface material 124 can be rolled into an alloy sheet (foil) of the thermal interface material 124 with a thickness of 10 microns to 10 millimeters, and the thermal interface material 124 is laid in the adhesive embankment 112 above the wafer 104 . Generally speaking, the dimensions of the wafer 104 are subject to tolerances and vary with different packaging applications. Solid-state wafers with a fixed aspect ratio are therefore limited in application. However, the use of liquid dispensing to dispose the thermal interface material 124 can not only break through the limitations of size applications (that is, there is no fixed aspect ratio), but can also fill the holes between the chip 104 and the heat sink 132 to achieve the best Cooling effect.

In this case, "indium-based alloy" refers to alloys including at least indium. The alloy can be formed of (1) indium and (2) bismuth or at least one of tin or silver, such as indium-bismuth-tin alloy, indium-bismuth alloy , indium tin alloy, or indium silver alloy. Thermal interface material 124 used in the present disclosure may include thermal paste, elastomeric thermal pad, phase change material, metal alloy, or any suitable material, preferably an indium-based alloy, selected from one of the following: (a) 30 To 35wt% bismuth (Bi), 15 to 18wt% tin (Sn), and the balance indium (In), and have a melting point of 55 to 65°C; (b) 30 to 35wt% bismuth and the balance Indium, and has a melting point of 70 to 75°C; (c) 52 to 60wt% bismuth, 15 to 18wt% tin, and the balance indium, and has a melting point of 80 to 85°C; (d) 48 to 50wt% tin and the balance indium, and having a melting point of 110 to 120°C; and (e) 0.1 to 15 wt% silver (Ag) and the balance indium, and having a melting point of 140 to 280°C.

In a preferred embodiment, the thermal interface material 124 melts into a liquid state when the chip 104 is operating to dissipate heat from the chip 104, and returns to a solid state when the chip stops operating to maintain the mechanical properties of the packaging structure. The thermal interface material 124 is liquid at least in the temperature range of 40°C to 300°C, such as 55°C to 65°C, 70°C to 75°C, 80°C to 85°C, 110°C to 120°C, and 140°C to 280°C. .

Referring to FIG. 4 , the surface of the heat sink 132 facing the bottom groove 134 of the chip 104 is covered with a metal film 136 . The thermal interface material 124 easily reacts with the heat sink 132 and the back metal layer of the chip 104 to produce high melting temperature. Intermetallic compounds are intermetallic compounds. The melting point of this type of high-melting intermetallic phase is higher than 300°C, and therefore cannot be in a liquid state when the chip 104 is operating to dissipate heat from the chip 104 . The metal film 136 provided between the wafer 104 and the heat sink 132 can prevent the thermal interface material 124 from reacting with the heat sink 132 to produce high melting point intermetallic compounds, reduce the consumption of the thermal interface material 124, ensure the existence of sufficient thermal interface material 124, and Maintains liquid state for a long time and has high heat dissipation function.

In one embodiment, the metal film 136 can be titanium (Ti) or tantalum (Ta) with a thickness in the range of 0.01 to 3 microns (for example: 0.1 to 1 micron). If the thickness is greater than 3 microns, it may affect the heat sink because it is too thick. The heat dissipation effect is reduced, resulting in reduced thermal conductivity. In addition, the metal film 136 may peel off due to poor adhesion; conversely, if the thickness is less than 0.01 micron, it may be too thin to effectively block the thermal interface material 124 and the heat sink 132. The reaction produces a high melting point intermetallic compound, which reduces the consumption of the thermal interface material 124 and thus affects the heat dissipation function.

In some embodiments, the heat sink 132 can be metal and/or metal and gold, such as copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), stainless steel, stainless nickel, a combination of the foregoing, or Made of any suitable metal material. In other embodiments, the heat sink 132 may also be made of a composite material, such as alloy, silicon carbide (SiC), aluminum nitride (AlN), graphite, the like, or a combination of the foregoing. Can use processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma Chemical vapor deposition (Inductively Coupled The metal film 136 is deposited by any suitable method such as Plasma-Chemical Vapor Deposition (ICP-CVD), Physical Vapor Deposition (PVD), spin coating process, or a combination of the above.

Figure 5 is a schematic side view of a chip packaging structure according to some embodiments. The heat sink 132 is pressed to the chip 104 to form the chip packaging structure 100 of this case.

Specifically, the heat sink 132 with the metal film 136 on the surface of the bottom groove 134 is stacked on top of the thermal interface material 124, and the heat sink 132, the thermal interface material 124, the chip 104, and the adhesive embankment 112 are sandwiched together. The structure is packaged, and then the stacked sandwich package structure is placed in a furnace and heated at 60 to 390°C (for example: 50 to 220°C) for 30 seconds to 120 minutes (for example: 30 to 60 minutes) to make the adhesive embankment 112 The adhesive 112' is cured to form, and is fixed with the heat sink 132 and the thermal interface material 124 to form a chip packaging structure 100 with high heat dissipation function. As shown in the figure, in one embodiment, after the heat sink 132 is pressed to the chip 104, the thermal interface material 124 is received in the bottom groove 134, and the bottom of the thermal interface material 124 is the same as the bottom of the heat sink 132. surface. In one embodiment, the adhesive embankments 112 are in direct contact with the sidewalls of the wafer 104 but do not contact the top surface of the wafer 104 so that the thermal interface material 124 subsequently provided can directly contact the top surface of the wafer 104 . Additionally, the bottom groove 134 is preferably wider than the wafer 104 in the cross-sectional view to ensure that the thermal interface material 124 can completely cover the top surface of the wafer 104 .

Please refer to FIG. 6 , which illustrates a chip packaging structure 200 according to other embodiments of the present disclosure. In this embodiment, the metal film 136 is not disposed on the heat sink 132 Instead, the metal film 136 is disposed on the back metal layer of the wafer 104 before the wafer 104 is fixed on the substrate 102 (see FIG. 1 ). As shown in the figure, in one embodiment, after the heat sink 132 is pressed to the wafer 104, the top of the thermal interface material 124 is co-surface with the top of the adhesive 112'. The metal film 136 on the back crystal metal layer of the wafer 104 can prevent the thermal interface material 124 from reacting with the back crystal metal layer to produce high melting point intermetallic compounds, reduce the consumption of the thermal interface material 124, and ensure that sufficient thermal interface material 124 exists for a long time. Maintain liquid state and high heat dissipation function. In some embodiments, the thermal interface material 124 covers at least 80% of the area of the wafer 104, for example: at least 85%, at least 90%, at least 95%, or at least 100%. That is to say, the thermal interface material 124 may not completely cover the area of the wafer 104. (or completely) cover the wafer 104 .

It should be understood that in other embodiments of the present disclosure, the metal film 136 can also be disposed on the back metal layer of the chip 104 and on the surface of the bottom groove 134 of the heat sink (ie, the third Combination of picture 5 and picture 6). In this way, the thermal interface material 124 can be prevented from reacting with the heat sink 132 and the back metal layer of the chip 104 to produce a high melting point intermetallic compound.

The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which this disclosure belongs can more easily understand the concepts of the embodiments of this disclosure. Those with ordinary skill in the technical field of this disclosure should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can be used without departing from the spirit and scope of the present disclosure. make various changes, Replace and replace.

100/200: Chip packaging structure

102:Substrate

104:Chip

112:Viscose embankment

112’:Viscose

122: Dispensing head

124: Thermal interface materials

132:Heat sink

134: Bottom groove

136:Metal film

Various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. It should also be noted that the appended drawings illustrate only typical embodiments of the disclosure and therefore should not be considered limiting of its scope; the disclosure may be applicable to other embodiments as well.

Figures 1 to 4 are schematic cross-sectional views of a process for forming a chip packaging structure according to some embodiments.

Figure 5 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

Figure 6 is a schematic cross-sectional view of a chip packaging structure according to other embodiments.

100: Chip packaging structure

102:Substrate

104:Chip

112’:Viscose

124: Thermal interface materials

132:Heat sink

134: Bottom groove

136:Metal film

Claims (14)

A chip packaging structure includes: a substrate; a chip arranged on the substrate; an adhesive surrounding the chip and in direct contact with the side wall of the chip; a thermal interface material arranged above the chip; a heat sink, The heat sink is disposed above the thermal interface material and has a bottom groove facing the chip; and a metal film is disposed between the chip and the heat sink. For example, the chip packaging structure of claim 1, wherein the adhesive is a polymer adhesive. The chip packaging structure of claim 1, wherein the adhesive is silicone, epoxy resin, polyimide or a combination of the above. The chip packaging structure of claim 1, wherein the adhesive does not directly contact a top surface of the chip. The chip packaging structure of claim 1, wherein the thermal interface material includes an indium-based alloy. Such as the chip packaging structure of claim 5, wherein the indium-based alloy is selected from one of the following: 30 to 35 wt% bismuth, 15 to 18 wt% tin, and the balance indium, and has a melting point of 55 to 65°C; 30 to 35wt% bismuth and the balance indium, and has a melting point of 70 to 75°C; 52 to 60wt% bismuth, 15 to 18wt% tin, and the balance indium, and has a melting point of 80 to 85°C; 48 to 50 wt% tin and the balance indium, with a melting point of 110 to 120°C; and 0.1 to 15 wt% silver and the balance indium, with a melting point of 140 to 280°C. As in the chip packaging structure of claim 1, the metal film is compliantly disposed on the surface of the bottom groove. The chip packaging structure of claim 7, wherein the bottom of the thermal interface material and the bottom of the heat sink have the same surface. The chip packaging structure of claim 1, wherein the thermal interface material completely covers the chip. Such as the chip packaging structure of claim 1, wherein the thermal interface material does not completely cover the chip. The chip packaging structure of claim 1, wherein the heat sink includes copper or aluminum. As in the chip packaging structure of claim 1, the metal film is disposed on a back metal layer of the chip. The chip packaging structure of claim 1, wherein the metal film has titanium or tantalum with a thickness ranging from 0.01 to 3 microns. The chip packaging structure of claim 1, wherein the chip packaging structure does not have a metal frame surrounding the chip.

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