TWI901334B - Package structure and method of manufacturing the same - Google Patents

Abstract

A package structure includes: a substrate, a chip disposed on the substrate, a heat sink having a surface facing the chip disposed on the chip, a barrier layer disposed on the surface of the heat sink, a thermal interface material (TIM) disposed between the substrate and the barrier layer, a dam surrounding the TIM, and at least one transient metal layer disposed between the chip and the barrier layer. The TIM incorporates a metallic element from the transient metal layer. A method for manufacturing the package structure is also provided.

Description

Package structure and manufacturing method thereof

The present invention relates to packaging technology, and more particularly to a packaging structure having a transient metal layer and a manufacturing method thereof.

Electronic components are developing towards being lighter, thinner, shorter, and smaller, with higher performance, higher transmission efficiency, and thus generating increasingly more heat per unit area. For example, a central processing unit (CPU) using a Pentium processor previously generated only 20W of heat, but the Pentium 4 exceeds 80W, with CPU temperatures reaching over 150°C during operation. According to the International Technology Roadmap for Semiconductors (ITRS), which predicts the future semiconductor industry development path, the heat generation of low-end computers will increase from the current approximately 100W to nearly 120W within the next few years, while the heat generation of high-end computers will increase significantly from the current 150W to over 180W. Operating frequencies will also increase from 2GHz to over 4GHz.

Traditional components generate low heat. The simplest solution is to add heat sinks or fans to improve heat dissipation. However, as the functionality and thermal power density of electronic components increase significantly, the requirements for thermal management technology become increasingly stringent. In the path by which component heat is transferred to the external environment, in addition to the chip itself requiring low thermal resistance and the use of high-performance heat sink components, the connection density between components and the thermal conductivity of the bonding material will become key factors in achieving breakthroughs in heat dissipation technology. Typical mechanical contact interfaces are rough or even wavy, with numerous insulating gaps between materials. These gaps create significant thermal conductivity barriers. Thermal interface material (TIM) is a material commonly used in integrated circuit (IC) packaging and electronic component heat dissipation. The main function of thermal interface materials is to fill the contact gap between two materials, improve the heat dissipation of the system and effectively reduce thermal impedance. A good thermal interface material must meet the following conditions: (1) good heat dissipation properties, that is, high thermal conductivity and low thermal impedance; (2) easy assembly and rework; (3) high compressibility so that it can withstand external pressure stress when fixed on the bonding surface and can properly fill the gap between the interfaces to facilitate heat flow; (4) good wettability with electronic components and heat sink fins; and (5) high reliability and long service life.

Thermal grease is one of the earliest thermal interface materials, composed of silicone or hydrocarbon compounds with various fillers. Traditional thermal grease has a thermal resistance of approximately 1K· ^cm2 /W. In recent years, this value has been reduced to approximately 0.2K· ^cm2 /W. However, conventional thermal greases still present numerous problems. Due to the material's inherent high viscosity, it cannot completely fill gaps between bonding surfaces, requiring a pressure of approximately 300kPa to achieve ideal heat dissipation performance. Furthermore, because thermal grease uses polymer materials, it cannot withstand the relative displacement between the heat sink fins and the chip, resulting in a pump-out effect. Furthermore, if thermal paste is exposed to high temperatures for a long time, it will separate from the internal filler due to chemical reactions in the polymer material, significantly reducing the wettability of the joint surface. This phenomenon is called dry-out.

Elastomeric thermal pads are thermal interface materials based on polymer silicone rubber, used to replace thermal paste. Their thermal resistance ranges from 1K• ^cm² /W to 3K• ^cm² /W, making them unsuitable for high-end cooling systems. They are easy to form and assemble, but require the application of a high pressure of approximately 700kPa to function properly. Another type of thermal interface material, thermal tapes, consists of an adhesive coated on a substrate such as polyimide (PI), fiberglass, or aluminum foil. While this tape eliminates the need for mechanical clamping, its heat dissipation remains suboptimal.

Phase change materials (PCMs) combine the excellent heat dissipation of thermal paste with the ease of processing of elastic thermal pads, demonstrating excellent thermal conductivity both above and below their melting point (approximately 50°C to 80°C). However, adhesion decreases above the melting point, requiring additional mechanical force (approximately 300 kPa) to apply. While PCMs offer comparable thermal impedance to thermal paste (approximately 0.3 K• ^cm² /W to 0.7 K• ^cm² /W) and can effectively address pump-out and drying issues, PCMs are generally preferred to thermal paste for high-end cooling systems due to reworkability considerations.

To address the shortcomings of polymer materials, the industry has developed low-melting-point alloys (melting points ranging from approximately 40°C to 200°C) for thermal interface materials. For example, pure solid indium (In) or indium-based alloys with different eutectic compositions can be used as thermal interface materials. However, while the thermal impedance of this solid metal is lower than that of polymer thermal interface materials, it is susceptible to porosity between this solid metal and the backing metal of electronic components (such as aluminum, silver, and gold) and heat sinks after reflow during the packaging process due to incomplete exhaust of flux combustion gases. This increases the thermal impedance of the solid metal. In recent years, the packaging industry has gradually moved toward non-flux packaging technology, but completely avoiding the problem of interface porosity remains difficult.

Another type of low-melting-point metal phase-change thermal interface material utilizes the low melting point of pure indium or eutectic indium-based alloys. When electronic components operate, the heat dissipated causes the low-melting-point metal to melt into a liquid state, filling the interface pores. This metal's inherently excellent thermal conductivity allows for excellent heat dissipation. However, when this low-melting-point phase-change thermal interface metal sheet melts into a liquid state at high temperatures, it rapidly reacts with the electronic component's backing metal and the heat sink to form a high-melting-point intermetallic compound. As the low-melting-point metal is gradually depleted, the original liquid, non-porous heat dissipation effect is lost.

While existing packaging technologies are generally adequate for their intended purposes, they are not yet completely satisfactory in all respects.

One embodiment of the present disclosure relates to a package structure. The package structure includes a substrate, a chip mounted on the substrate, a heat sink mounted above the chip and having a surface facing the chip, a barrier layer mounted on the surface of the heat sink, a thermal interface material disposed between the substrate and the barrier layer, a sealant surrounding the thermal interface material, and at least one transient metal layer disposed between the chip and the barrier layer. The thermal interface material incorporates a metal element from the transient metal layer.

Another embodiment of the present disclosure relates to a method for manufacturing a package structure. The method includes: placing a chip on a substrate, applying a sealant over the chip to form a housing space, placing a thermal interface material in the housing space so that the sealant surrounds the thermal interface material, and performing a press-fit process on a heat sink and the chip. A barrier layer is provided on the surface of the heat sink facing the chip, and during the press-fit process, at least a transient metal layer is disposed between the chip and the barrier layer so that the transient metal layer at least partially dissolves into the thermal interface material.

The following disclosure provides a number of embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are directly in contact, and it may also include an embodiment in which additional elements are formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and/or letters in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and/or configurations discussed.

The following describes some variations of the embodiments. Similar reference numerals are used to designate similar elements throughout the various figures and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, or after the method, and that some of the described steps may be replaced or deleted in other embodiments of the method.

Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used to facilitate describing the relationship of one component or components to another component or components in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or in other orientations, spatially relative adjectives are interpreted based on that orientation.

The terms used herein are intended only to illustrate specific embodiments and are not intended to limit the present inventive concept. Unless the context clearly indicates a different meaning, an expression used in the singular also encompasses the expression in the plural. Throughout this specification, it should be understood that terms such as "comprise," "have," and "include" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed herein, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or be added.

The following describes some embodiments of the present invention. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages described may be replaced or eliminated in different embodiments. Additional components may be added to the package structure. Some of the components described may be replaced or eliminated in different embodiments. Although some embodiments are discussed as performing the steps in a specific order, these steps may also be performed in another logical order.

Low-melting-point liquid metal thermal interface materials (LMMs) have attracted attention due to their fluidity, low melting point, and high electrical conductivity. Among these LMMs, gallium-based alloys have become the most promising thermal interface materials for dissipating heat in large-scale chips, such as artificial intelligence (AI) and advanced three-dimensional integrated circuits (3DIC). However, the inventors of this case discovered that LMMs have poor wettability with most metals. Furthermore, when the chip operates at high temperatures, the LMMs react with the metal material of the heat sink to form a high-melting-point intermetallic compound, significantly increasing the thermal impedance of the LMMs and thus losing the excellent heat dissipation performance originally achieved by the LMMs. It should be noted that the gallium-based alloy is merely an example of a thermal interface material and is not intended to limit the present inventive concept.

The present disclosure provides a packaging structure having a transient metal layer. After the heat sink and chip are pressed together, the transient metal layer can be dissolved into the thermal interface material, thereby improving the wettability between the thermal interface material and the chip and heat sink, allowing the thermal interface material to evenly cover the surfaces of the chip and heat sink. In addition, when the transient metal layer is dissolved into the thermal interface material and contacts the chip and the barrier layer, the thermal interface material and the chip cannot react with each other, and therefore will not dissolve into each other or form an intermetallic compound. In addition, the reaction rate between the thermal interface material and the barrier layer is very slow, thereby ensuring that the thermal interface material can exist for a long time.

Figures 1 to 5 are cross-sectional views of the package structure 100 at different manufacturing stages according to some embodiments of the present disclosure. It should be understood that for clarity of illustration, some elements of the package structure 100 may be omitted in the figures and only some elements are schematically shown.

Referring to FIG. 1 , a chip 104 is placed on a substrate 102. In some embodiments, substrate 102 may include a printed circuit board (PCB), a wafer substrate, an integrated circuit (IC) substrate, an interposer, a chip carrier, a circuit carrier, or a display device. Substrate 102 may be made of polymer, ceramic, glass, or a silicon wafer.

In some embodiments, chip 104 may include a semiconductor chip. A semiconductor chip may be, for example, a small piece of semiconductor wafer formed by performing a semiconductor process on a semiconductor wafer and then separating the semiconductor wafer into individual dies. Chip 104 may include integrated circuits for processing and/or storing data, such as a field programmable gate array (FPGA), a processing unit (GPU) or a central processing unit (CPU), an application-specific integrated circuit (ASIC), a memory device (e.g., a memory controller, memory), and the like. The wafer 104 may include a single crystal of the following materials: silicon (Si), germanium (Ge), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), or gallium nitride (GaN).

In some embodiments, a polymer adhesive, solder, or a combination thereof can be used to physically connect the chip 104 to the substrate 102. The chip 104 can be packaged on the substrate 102 using, for example, a flip chip, ball grid array (BGA), three-dimensional integrated circuits (3DICs), 2.5D, integrated fan-out (InFO), or other suitable packaging technologies. In this embodiment, the chip 104 is flip-chip mounted on the substrate 102 to form a flip-chip assembly chip structure. As shown in the figure, pads (not shown) located on the front surface 104F of the chip 104 can be physically and electrically connected to bonding pads (not shown) on the top surface of the substrate 102 via a plurality of conductive bumps 106. The solder pads may be part of a redistribution layer (RDL) structure. The conductive bumps 106 may include or be tin, lead, and/or silver. The conductive bumps 106 may have a spherical appearance. An underfill 108 may be formed under the chip 104 and around the conductive bumps 106. The underfill 108 is configured to securely secure the chip 104 to the substrate 102 and relieve stress on the conductive bumps 106. The underfill 108 may include a base material and filler particles dispersed in the base material. The base material may include a polymer, a resin, an epoxy resin, and/or the like. The filler particles may be dielectric particles of silicon dioxide, aluminum oxide, boron nitride, or the like.

Next, at least one transient metal layer, such as transient metal layer 124 and/or transient metal layer 224, is disposed between chip 104 and barrier layer 222 (shown in FIG. 4 ) on heat sink 202. Transient metal layer 224 will be described in detail later in conjunction with FIG. Referring first to FIG. 2 , for example, transient metal layer 124 may be formed on backside surface 104B of chip 104. The transient metal layer 124 is configured to dissolve into the thermal interface material 304 (shown in FIG. 4 ) formed later after the heat sink 202 and the chip 104 undergo a press-fit process 404 (shown in FIG. 5 ), thereby enhancing the wetting effect between the thermal interface material 304 and the chip 104 , allowing the thermal interface material 304 to evenly cover the back surface 104B of the chip 104 . In some embodiments, the transient metal layer 124 may include or be at least one of the following: aluminum (Al), indium (In), tin (Sn), tin-zinc (SnZn), indium-zinc (InZn), indium-bismuth (InBi), indium-tin (InSn), bismuth-tin (BiSn), indium-bismuth-tin (InBiSn), and indium-bismuth-tin-zinc (InBiSnZn). The transient metal layer 124 may have a thickness of 0.01 μm to 5 μm (e.g., 0.1 to 3 μm, 0.2 to 1 μm). A thickness less than 0.01 μm may not improve wettability, while a thickness greater than 5 μm may change the composition and melting point of the transient metal layer 124. The transient metal layer 124 can be formed by evaporation, sputtering or electroplating.

In some embodiments, a sealant 126 is disposed on the chip 104 (or on the transient metal layer 124, if present) to form a receiving space 1262. The sealant 126 can serve as a barrier when a thermal interface material 304 (shown in FIG. 4 ) is subsequently disposed on the chip 104, thereby confining the thermal interface material 304 within the receiving space 1262. In some embodiments, the sealant 126 can be disposed on the back surface 104B of the chip 104 and along the periphery of the back surface 104B, so that the thermal interface material 304 in the sealant 126 can cover a large area of the back surface 104B of the chip 104. The frame glue 126 can have a height of 20 to 2000 microns, but the present disclosure is not limited thereto, as long as it can prevent the thermal interface material 304 from overflowing. The frame glue 126 can include silicone, epoxy, polyimide, or a combination thereof. The frame glue 126 can be formed on the chip 104 in an uncured state by spraying, extrusion, dispensing, or a combination thereof.

In an embodiment where a transient metal layer 124 is present, a cleaning process may be performed on the transient metal layer 124 before the frame glue 126 is applied to remove oxidized portions of the transient metal layer 124. This facilitates adhesion between the frame glue 126 and the transient metal layer 124. The cleaning process may include argon or oxygen ion plasma cleaning.

3 , a dispensing head 302 is used to fill thermal interface material 304 into the receiving space 1262 surrounded by the frame glue 126. In some embodiments, the thermal interface material 304 is configured to fill the contact gap between the heat sink 202 (shown in FIG. 5 ) and the chip 104 when the two are pressed together, thereby improving the overall heat dissipation performance of the package structure 100 and effectively reducing the thermal impedance of the package structure 100, for example, by transferring heat generated by the chip 104 to the heat sink 202.

In some embodiments, thermal interface material 304 may include a metal alloy and be fluid (e.g., liquid metal) at room temperature or at the operating temperature of wafer 104 (e.g., approximately 35°C to 200°C). In this embodiment, thermal interface material 304 may include or be a gallium-based alloy. The gallium-based alloy may include or be pure gallium (Ga), gallium-indium (Ga-In), gallium-tin (Ga-Sn), or gallium-indium-tin (Ga-In-Sn). Pure gallium has a melting point of approximately 30°C, while eutectic gallium-based alloys (e.g., gallium-indium alloy, gallium-tin alloy, and gallium-indium-tin alloy) have a melting point of approximately 9°C to 15°C. The thermal conductivity of the gallium-based alloy is approximately 30 W/mC.

It should be noted that when the thermal interface material 304 (gallium-based alloy) contacts the temporary metal layer 124, the temporary metal layer 124 dissolves into the thermal interface material 304. For example, the temporary metal layer 124 may partially dissolve into the thermal interface material 304, causing the thermal interface material 304 to directly contact a portion of the backside surface 104B of the chip 104. Alternatively, the portion of the temporary metal layer 124 that is in direct contact with the thermal interface material 304 may completely dissolve into the thermal interface material 304, causing the thermal interface material 304 to directly contact all of the backside surface 104B of the chip 104 not covered by the sealant 126. To better illustrate the relative positions of the various components, this dissolution phenomenon is not shown in FIG. 3.

Referring to FIG. 4 , a heat sink 202 is provided. In some embodiments, the heat sink 202 may be a metal lid or a fin heat sink, but the present disclosure is not limited thereto. In other embodiments, the heat sink 202 may also be a passive heat sink element such as a heat pipe, or an active heat sink element such as a heat fan or a water cooling cycle. Any type and shape of heat sink may be selected according to actual needs. The material of the heat sink 202 may include or be metal and/or metal alloy, such as copper (Cu), aluminum (Al), or a combination thereof. In other embodiments, the heat sink 202 may also be a composite material, such as an alloy, silicon carbide (SiC), aluminum nitride (AlN), graphite, the like, or a combination thereof.

The present embodiment will be described below using a heat sink metal cap (as shown) as the heat sink 202. In some embodiments, the heat sink 202 has a bottom groove 2022 facing the chip 104. When the heat sink 202 and the chip 104 undergo a pressing process 404 (shown in FIG. 5 ), the chip 104 can be accommodated in the groove 2022. A barrier layer 222 is disposed on a surface 202S of the heat sink 202 facing the chip 104. The barrier layer 222 is configured to slow down the rate at which a transient metal layer 224 formed later directly contacts the heat sink 202 to form a high-melting-point intermetallic compound. Alternatively, the barrier layer 222 can improve the heat dissipation effect of the package structure 100 and reduce the thermal impedance of the package structure 100, but the present disclosure is not limited thereto. The barrier layer 222 may include or be gold (Au), silver (Ag), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), tungsten (W), tungsten titanium (WTi), or a combination thereof. The barrier layer 222 may have a thickness of 0.01 to 10 microns (e.g., 0.5 to 1.6 microns or 0.1 to 2 microns). In some embodiments, the barrier layer 222 may be formed by sputtering, evaporation, electroplating, or any other suitable deposition process.

Still referring to FIG. 4 , the transient metal layer 224 may be alternatively (i.e., the transient metal layer 124 is absent) or additionally (i.e., the transient metal layer 124 and the transient metal layer 224 are both present) disposed on the surface 222S of the barrier layer 222 facing the chip 104. The transient metal layer 224 is configured to dissolve into the thermal interface material 304 after the heat spreader 202 and the chip 104 are pressed together in the lamination process 404 (shown in FIG. 5 ), thereby enhancing the wetting effect between the thermal interface material 304 and the barrier layer 222, so that the thermal interface material 304 can evenly cover the surface 222S of the barrier layer 222. The material, thickness, and formation method of the transient metal layer 224 may refer to the transient metal layer 124 described in FIG. 2 , and for the sake of brevity, they will not be described again here.

5 , the heat spreader 202 and the chip 104 are subjected to a lamination process 404. In some embodiments, the bottom surface 202B of the heat spreader 202 is bonded to the substrate 102 via adhesive 402. At this time, the frame adhesive 126 may directly contact the barrier layer 222 (or the transient metal layer 224, if present) on the surface 202S of the heat spreader 202. Next, a pressing process 404 is performed. The pressing process 404 may include applying a force greater than 1 gram-force/ ^cm² (gf/ ^cm² ) (e.g., 55 gf/ ^cm² , 900 gf/ ^cm² , or 3700 gf/ ^cm² ) to the heat spreader 202 for a period of 2 seconds to 10 minutes (e.g., 5 seconds, 10 seconds, 20 seconds, or 1 minute) to deform the adhesive 402 and the frame adhesive 126 so that the bottom surface 202B of the heat spreader 202 is fixed to the chip 104 and the thermal interface material 304 is in direct contact with the barrier layer 222 (or the transient metal layer 224, if present).

In an embodiment where a temporary metal layer 224 is present, a cleaning process may be performed on the temporary metal layer 224 before the lamination process 404 to remove oxidized portions of the temporary metal layer 224. This facilitates adhesion between the frame adhesive 126 and the temporary metal layer 224. The cleaning process may include argon or oxygen ion plasma cleaning.

It should be noted that when the thermal interface material 304 (gallium-based alloy) contacts the temporary metal layer 224, the temporary metal layer 224 dissolves into the thermal interface material 304, thereby enhancing the wetting effect. For example, the temporary metal layer 224 can partially dissolve into the thermal interface material 304, causing the thermal interface material 304 to directly contact a portion of the surface 222S of the barrier layer 222. Alternatively, the portion of the temporary metal layer 224 that directly contacts the thermal interface material 304 can completely dissolve into the thermal interface material 304, causing the thermal interface material 304 to directly contact all surfaces 222S of the barrier layer 222 that are not covered by the sealant 126. It should be noted that if the portion of the temporary metal layer 124 located on the back surface 104B of the chip 104 and in direct contact with the thermal interface material 304 has not yet completely dissolved into the thermal interface material 304, the dissolution will continue during the pressing process 404 until the temporary metal layer 124 is completely dissolved into the thermal interface material 304.

FIG6 is a cross-sectional view of package structure 100 according to some embodiments of the present disclosure. As shown in FIG6 , after performing the pressing process 404 in FIG5 , a heating process 406 (e.g., a snap curing process) is performed to heat-cure the frame adhesive 126 and the adhesive 402 to form a cured frame adhesive 126′ and a cured adhesive 402′, respectively, thereby forming the package structure 100 of the present invention. In some embodiments, the heating process 406 may include: heating at a temperature of 100°C to 200°C (e.g., 120°C, 140°C, or 180°C) for 2 minutes to 30 minutes (e.g., 3 minutes, 10 minutes, or 20 minutes). Within this condition range, it can be ensured that the frame glue 126 and the adhesive 402 are completely cured and will not shift.

In some embodiments, after performing the pressing process 404 of FIG. 5 or the heating process 406 of FIG. 6 , the portions of the transient metal layers 124 and 224 that are in direct contact with the thermal interface material 304 are completely dissolved into the thermal interface material 304, such that the thermal interface material 304 is in direct contact with and uniformly covers the backside surface 104B of the wafer 104 and the surface 222S of the barrier layer 222. It is noteworthy that because the thermal interface material 304 and the wafer 104 are non-reactive with each other, they are not immiscible or form an intermetallic compound. Furthermore, the reaction rate between the thermal interface material 304 and the barrier layer 222 is very slow, thereby ensuring that the thermal interface material 304 remains in the thermal interface material 304 for a long time.

It should be noted that although FIG. 6 shows that a portion of the temporary metal layer 124 sandwiched between the cured frame glue 126′ and the chip 104 (i.e., an edge portion of the temporary metal layer 124) and a portion of the temporary metal layer 224 sandwiched between the cured frame glue 126′ and the barrier layer 222 (i.e., an edge portion of the temporary metal layer 224) are not dissolved into the thermal interface material 304, the present disclosure is not limited to this. The edge portions of the temporary metal layers 124 and 224 cannot dissolve into the thermal interface material 304 because the contact area between the edge portions and the thermal interface material 304 is too small, making it difficult for the temporary metal layers 124 and 224 at the edge portions to dissolve into the thermal interface material 304. Therefore, in embodiments where the contact area between the edge portions and the thermal interface material 304 is sufficiently large, the edge portions of the temporary metal layers 124 and 224 may also dissolve into the thermal interface material 304. In other words, the temporary metal layers 124 and 224 may be substantially completely dissolved into the thermal interface material 304.

As shown in FIG. 6 , in some embodiments, the package structure 100 includes a substrate 102, a chip 104 disposed on the substrate 102, a heat sink 202 disposed above the chip 104 and having a surface 202S facing the chip 104, a barrier layer 222 disposed on the surface 202S of the heat sink 202, and a thermal interface material 322 disposed between the substrate 102 and the barrier layer 222. 04. A cured sealant 126' surrounding the thermal interface material 304, and at least one transient metal layer (only the transient metal layer 124, only the transient metal layer 224, or both the transient metal layers 124 and 224) disposed between the chip 104 and the barrier layer 222, wherein the thermal interface material 304 is dissolved with metal elements of the transient metal layer 124 and/or the transient metal layer 224.

In some embodiments, the temporary metal layer 124 directly contacts the bottom surface 126B of the cured sealant 126′, while the temporary metal layer 224 directly contacts the top surface 126T of the cured sealant 126′. The temporary metal layers 124 and 224 directly contact the sidewalls 304S of the thermal interface material 304. The thermal interface material 304 is surrounded by the temporary metal layers 124 and 224. The thermal interface material 304 is separated from the heat sink 202 by the barrier layer 222, that is, the thermal interface material 304 does not directly contact the heat sink 202.

It should be understood that after performing the heating process 406, subsequent packaging processes may be performed according to actual needs to complete the manufacture of the package structure 100. Since these processes are not relevant to the focus of this disclosure, they will not be described in detail here.

Figures 7 through 11 illustrate cross-sectional views of package structure 200 at various stages of fabrication according to other embodiments of the present disclosure. It should be noted that processes or components identical or similar to those in the aforementioned embodiments will retain the same reference numerals, and their details will not be repeated. In this embodiment, sealant 126 is not positioned above chip 104, but rather around chip 104.

FIG7 follows FIG1 . In some embodiments, at least one transient metal layer, such as transient metal layer 124 and/or transient metal layer 224, is disposed between chip 104 and barrier layer 222 (shown in FIG9 ) on heat sink 202. Referring first to FIG7 , transient metal layer 124 can be formed, for example, on backside surface 104B of chip 104. Next, a sealant 126 is disposed on substrate 102 and surrounds chip 104 along the sidewalls thereof to form a receiving space 1262. The topmost surface T of the sealant 126 can be raised by a distance D of 0.03 to 10 mm (e.g., 1 to 5 mm) above the back surface 104B of the chip 104, but this disclosure is not limited to this, as long as the thermal interface material 304 can be prevented from overflowing. As shown in FIG. 7 , the sealant 126 is in direct contact with the sidewall 104S of the chip 104, but this disclosure is not limited to this. In other embodiments, the sealant 126 does not directly contact the sidewall 104S of the chip 104. This will be explained in detail later in conjunction with FIG. 12 .

Referring to FIG8 , a dispensing head 302 is used to fill the thermal interface material 304 into the accommodation space 1262 surrounded by the frame glue 126. In some embodiments, when the thermal interface material 304 contacts the temporary metal layer 124, the temporary metal layer 124 can partially dissolve into the thermal interface material 304, so that the thermal interface material 304 directly contacts a portion of the back surface 104B of the chip 104. Alternatively, the temporary metal layer 124 can completely dissolve into the thermal interface material 304, so that the thermal interface material 304 directly contacts the entire back surface 104B of the chip 104. To better illustrate the relative positions of the various components, the dissolution phenomenon is not shown in FIG8 .

9 and 10 , a heat spreader 202 is provided and a press-fit process 404 is performed between the heat spreader 202 and the chip 104 so that the thermal interface material 304 is in direct contact with the barrier layer 222 (or the transient metal layer 224 , if present).

11 , a heating process 406 is performed to heat and cure the frame adhesive 126 and the adhesive 402 to form a cured frame adhesive 126′ and a cured adhesive 402′, respectively, to form the package structure 200 of the present invention. The package structure 200 of FIG. 11 is similar to the package structure 100 of FIG. 6 , except that the cured sealant 126′ is not located above the chip 104, but rather around the chip 104. Since the temporary metal layer 124 is no longer covered by the sealant 126, the thermal interface material 304 can completely contact all top surfaces of the temporary metal layer 124, allowing the temporary metal layer 124 to completely dissolve into the thermal interface material 304. Therefore, the temporary metal layer 124 is no longer visible in the final structure of the package structure 200. This allows the thermal interface material 304 to contact all backside surfaces 104B of the chip 104, further enhancing the heat dissipation performance of the package structure 200.

FIG12 is a cross-sectional view of a package structure 300 according to yet other embodiments of the present disclosure. The package structure 300 of FIG12 is similar to the package structure 200 of FIG11 , except that the package structure 300 includes multiple chips 104, a single thermal interface material 304 is applied to each of the multiple chips 104, and the cured sealant 126' is spaced apart from (i.e., not in direct contact with) the sidewalls 104S of the chips 104. Using a single, large-area thermal interface material 304 simplifies the manufacturing process and ensures coverage of each chip 104. Specifically, in some embodiments, multiple chips 104 are disposed on the substrate 102 via their respective conductive bumps 106 and underfill 108, and a cured sealant 126' is disposed at a certain distance around the outermost chip 104 to surround all chips 104. As a result, these chips 104 are embedded in the thermal interface material 304, allowing the transient metal layer 124 on all chips 104 to completely dissolve into the thermal interface material 304. It should be noted that although FIG. 12 only depicts two chips 104, the present disclosure is not limited thereto, and any number of chips 104 may be disposed on the substrate 102 according to design requirements.

FIG13 is a cross-sectional view of a package structure 400 according to another embodiment of the present disclosure. The package structure 400 of FIG13 is similar to the package structure 100 of FIG6 , except that the package structure 400 further includes a metal layer 122 disposed on the chip 104. Specifically, in some embodiments, the metal layer 122 can be formed on the back surface 104B of the chip 104 before applying the frame glue 126 ( FIG2 ), and a temporary metal layer 124 is disposed on the metal layer 122. The metal layer 122 is configured to improve the heat dissipation effect of the package structure 100 and reduce the thermal impedance of the package structure 100, but the present disclosure is not limited to this.

In some embodiments, the metal layer 122 can have a thickness of 0.01 to 25 microns. The metal layer 122 can be a single-layer film structure or a multi-layer film structure. The film layer can include or be aluminum (Al), titanium (Ti), tungsten (Ta), chromium (Cr), tungsten titanium (WTi), nickel (Ni), nickel vanadium (NiV), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), or a combination thereof. Generally speaking, when a gallium-based alloy (thermal interface material 304) contacts silver, aluminum, and copper, the gallium-based alloy reacts with the silver, aluminum, and copper to form a high-melting-point intermetallic compound. Therefore, in an embodiment where the metal layer 122 is a multi-layer film structure, when the transient metal layer 124 dissolves into the thermal interface material 304 and the thermal interface material 304 contacts the silver, aluminum, or copper in the metal layer 122, the silver, aluminum, or copper reacts with the thermal interface material 304 and is consumed. Subsequently, when the thermal interface material 304 contacts other film layers below the silver, aluminum, or copper, no reaction occurs, and thus no further intermetallic compounds are formed. In other words, the thermal interface material 304 does not directly contact the chip 104.

FIG14 is a cross-sectional view of a package structure 500 according to another embodiment of the present disclosure. The package structure 500 of FIG14 is similar to the package structure 100 of FIG6 , except that the heat sink 202 (heat sink metal cover) is replaced with the heat sink 212 (heat sink fins). Therefore, the barrier layer 222 is disposed on the surface 212S of the heat sink 212 facing the chip 104. In some embodiments, the heat sink 212 (heat sink fins) has a fin structure and thus provides better heat dissipation than the heat sink 202 (heat sink metal cover). The material of the heat sink 212 may include or be a metal and/or metal alloy, such as copper (Cu), aluminum (Al), or a combination thereof.

FIG15 is a cross-sectional view of a package structure 600 according to another embodiment of the present disclosure. The package structure 600 of FIG15 is similar to the package structure 100 of FIG6 , except that the heat sink is a combination of a heat sink metal cover and heat sink fins. In other words, the package structure 600 further includes a heat sink 212 (heat sink fins) disposed above the heat sink 202 (heat sink metal cover) and an additional thermal interface material 504 sandwiched between the heat sinks 202 and 212. In some embodiments, the heat sink 212 and the additional thermal interface material 504 can further enhance the heat dissipation performance of the package structure 600. Specifically, the thermal interface material 304 can transfer heat generated by the chip 104 to the heat sink 202, which is then transferred to the heat sink 212 via the additional thermal interface material 504. The additional thermal interface material 504 can include thermal paste, elastic thermal pads, thermal tape, phase change material, metal alloy (e.g., indium-based alloy or gallium-based alloy), or any other suitable thermal interface material.

As shown in FIG. 15 , in an embodiment where the additional thermal interface material 504 is a gallium-based alloy, an additional curing sealant 502′ is further included between the heat sink 202 and the heat sink 212 to surround the additional thermal interface material 504 and prevent the additional thermal interface material 504 from overflowing. It should be noted that the gallium-based alloy is merely an example and is not intended to limit this disclosure to its specific description. This disclosure is also applicable to other thermal interface materials. The material of the additional curing sealant 502′ can be referenced to the sealant 126 described in FIG. 2 . For the sake of brevity, this description will not be repeated here. In addition, to prevent the thermal interface material 504 from directly contacting the heat sinks 202 and 212 and reacting to form an intermetallic compound, an additional barrier layer (not shown) may be optionally formed on the surface of the heat sink 202 in contact with the thermal interface material 504 and the surface of the heat sink 212 in contact with the thermal interface material 504. The material, thickness, and formation method of the additional barrier layer can be found in the barrier layer 222 described in Figure 3. For the sake of brevity, they will not be described again here.

In summary, some embodiments of the present disclosure provide some benefits. The present disclosure provides a packaging structure having a transient metal layer. After the heat sink and the chip undergo a press-fit process, the transient metal layer of the present disclosure can be dissolved into the thermal interface material, thereby improving the wettability between the thermal interface material and the chip and the heat sink, so that the thermal interface material can be evenly covered on the surface of the chip and the heat sink. In addition, when the transient metal layer is dissolved into the thermal interface material and contacts the chip and the barrier layer, since the thermal interface material and the chip cannot react with each other, they will not dissolve into each other or form an intermetallic compound. In addition, the reaction rate between the thermal interface material and the barrier layer is very slow, thereby ensuring that the thermal interface material exists for a long time.

The above overview of several embodiments is provided to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the present embodiments to achieve the same objectives and/or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

100: Package structure 102: Substrate 104: Chip 104B: Backside surface 104F: Frontside surface 104S: Sidewall 106: Conductive bump 108: Underfill 122: Metal layer 124: Transient metal layer 126, 126': Frame adhesive 1262: Accommodation space 126B: Bottom surface 126T: Top surface 200: Package structure 202: Heat sink 202B: Bottom surface 2022: Recess 202S: Surface 212: Heat sink 212S: Surface 222: Blocking layer 222S: Surface 224: Transient metal layer 300: Package structure 302: Glue dispenser 304: Thermal interface material 304S: Sidewall 400: Package structure 402, 402': Adhesive 404: Pressing process 406: Heating process 500: Package structure 502': Frame adhesive 504: Thermal interface material 600: Package structure D: Distance T: Top surface

The following details various aspects of the present disclosure, accompanied by the accompanying figures. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale and are shown for illustrative purposes only. In fact, the dimensions of components may be arbitrarily enlarged or reduced to clearly illustrate the components of the embodiments of the present invention. It should also be noted that the accompanying figures illustrate only typical embodiments of the present disclosure and should not be considered limiting of its scope. The present disclosure is equally applicable to other embodiments. Figures 1 through 5 are cross-sectional views of package structures at various stages of fabrication according to some embodiments of the present disclosure. Figure 6 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. Figures 7 through 11 are cross-sectional views of a package structure at various stages of fabrication according to other embodiments of the present disclosure, wherein a sealant is disposed around a chip. Figure 12 is a cross-sectional view of a package structure according to yet other embodiments of the present disclosure, wherein the package structure comprises multiple chips, and the sealant is disposed around the chips without directly contacting the chips. Figure 13 is a cross-sectional view of a package structure according to yet another embodiment of the present disclosure, wherein the package structure further includes a metal layer disposed over the chips. Figure 14 is a cross-sectional view of a package structure according to yet another embodiment of the present disclosure, wherein the heat sink is a heat sink fin. Figure 15 is a cross-sectional view of a package structure according to another embodiment of the present disclosure, wherein the heat sink is a combination of a heat sink metal cover and heat sink fins.

100:Packaging structure

102:Substrate

104: Chip

104B: Dorsal surface

106: Conductive bumps

108: Bottom filler

124: Transient metal layer

126': Frame adhesive

126B: Bottom surface

126T: Top surface

202: Radiator

2022: Groove

202S: Surface

222: Barrier layer

222S: Surface

224: Transient metal layer

304: Thermal interface material

304S: Sidewall

402': Adhesive

406: Heating process

Claims (19)

A package structure includes: a substrate; a chip disposed on the substrate; a heat sink disposed above the chip and having a surface facing the chip; a barrier layer disposed on the surface of the heat sink; a thermal interface material disposed between the substrate and the barrier layer; a dam surrounding the thermal interface material; and at least one transient metal layer disposed between the chip and the barrier layer, wherein the thermal interface material is dissolved in The metal element of the transient metal layer, wherein the transient metal layer includes at least one of the following: aluminum (Al), indium (In), tin (Sn), tin-zinc (SnZn), indium-zinc (InZn), indium bismuth (InBi), indium-tin (InSn), bismuth-tin (BiSn), indium bismuth-tin (InBiSn), and indium bismuth-tin-zinc (InBiSnZn), and the transient metal layer has a thickness of 0.01 micrometers to 5 micrometers. The packaging structure of claim 1, wherein the transient metal layer is in direct contact with at least one surface of the frame glue and a side wall of the thermal interface material. The packaging structure of claim 1, wherein the thermal interface material comprises a gallium-based alloy and is fluid at room temperature. The package structure of claim 3, wherein the gallium-based alloy comprises gallium (Ga), gallium-indium (Ga-In), gallium-tin (Ga-Sn) or gallium-indium-tin (Ga-In-Sn). In the package structure of claim 1, the substrate comprises a polymer, ceramic, glass or a silicon chip. The package structure of claim 1, wherein the heat sink comprises copper (Cu) and aluminum (Al). The package structure of claim 1, wherein the barrier layer comprises gold (Au), silver (Ag), nickel (Ni), titanium (Ti), tungsten (W), tungsten titanium (WTi), platinum (Pt), palladium (Pd), or a combination thereof, and the barrier layer has a thickness of 0.01 to 10 microns. The packaging structure of claim 1, wherein the frame glue comprises silicone, epoxy resin, polyimide or a combination thereof. The packaging structure of claim 1, wherein the frame glue is disposed above the chip. The packaging structure of claim 1, wherein the frame glue is arranged around the chip. The package structure of claim 10, wherein the chip is embedded in the thermal interface material. The package structure of claim 1 further includes a metal layer disposed on the chip, wherein the metal layer includes aluminum (Al), titanium (Ti), tungsten (Ta), chromium (Cr), tungsten titanium (WTi), nickel (Ni), nickel vanadium (NiV), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd) or a combination of the foregoing, and the metal layer has a thickness of 0.01 to 25 microns. The package structure of claim 1, wherein the heat sink is a metal lid or a fin heat sink. The package structure of claim 1, wherein the heat sink is a heat dissipation metal lid, and the package structure further includes: a heat dissipation fin disposed above the heat dissipation metal lid; and an additional thermal interface material disposed between the heat dissipation metal lid and the heat dissipation fin. A method for manufacturing a package structure includes: placing a chip on a substrate; applying a sealant on the chip to form a receiving space; placing a thermal interface material in the receiving space so that the sealant surrounds the thermal interface material; and performing a press-fit process on a heat sink and the chip, wherein a barrier layer is provided on a surface of the heat sink facing the chip, and at least one transient metal layer is provided between the chip and the barrier layer during the press-fit process. The transient metal layer is at least partially dissolved into the thermal interface material, wherein the transient metal layer includes at least one of the following: aluminum (Al), indium (In), tin (Sn), tin-zinc (SnZn), indium-zinc (InZn), indium bismuth (InBi), indium-tin (InSn), bismuth-tin (BiSn), indium-bismuth-tin (InBiSn), and indium-bismuth-tin-zinc (InBiSnZn), and the transient metal layer has a thickness of 0.01 micrometers to 5 micrometers. A method for manufacturing a packaging structure as claimed in claim 15, wherein the transient metal layer is arranged on the surface of the barrier layer facing the chip, and when the pressing process is performed, the transient metal layer at least partially dissolves into the thermal interface material so that the barrier layer directly contacts the thermal interface material. A method for manufacturing a packaging structure as claimed in claim 15, wherein the transient metal layer is arranged on a back surface of the chip facing the heat sink, and when the pressing process is performed, the transient metal layer at least partially dissolves into the thermal interface material so that the chip directly contacts the thermal interface material. A method for manufacturing a package structure as claimed in claim 16 or 17, wherein the transient metal layer is completely dissolved into the thermal interface material. The method for manufacturing the package structure of claim 15 further comprises, before applying the frame glue, forming a metal layer on the chip, and the temporary metal layer is disposed on the metal layer.