TWI869064B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate, a well region, a source region, a drain region, a gate and a deep trench isolation structure. The well region is disposed in the substrate, and both the source region and the drain region are disposed in the well region. The gate is disposed on the substrate and is located between the source region and the drain region. The deep trench isolation structure is disposed in the substrate and surrounds the well region. The deep trench isolation structure includes a trench, a dielectric liner and a conductive portion. The bottom surface of the trench is lower than the bottom surface of the well region. The dielectric liner is lined on the sidewalls of the trench. The conductive portion fills up the trench, and includes an extension portion extended downward beyond the bottom surface of the trench.

Description

Semiconductor devices

This disclosure relates to semiconductor technology, and more particularly to semiconductor devices including deep trench isolation structures.

In semiconductor technology, it is usually necessary to set up isolation regions between adjacent components to prevent adjacent components from interfering with each other. PN junctions can be used to isolate adjacent components, but the use of PN junctions requires a larger size to achieve the desired isolation effect, which is not conducive to the miniaturization of semiconductor components. In addition, field oxide (FOX) or shallow trench isolation (STI) technology can also be used to isolate adjacent components. Although field oxidation or shallow trench isolation technology is more advantageous for the miniaturization of semiconductor devices than PN junction, these isolation technologies cannot meet the needs of semiconductor devices in all aspects. For example, current isolation technologies still cannot meet the need to improve the latch-up effect.

In view of this, the present disclosure proposes a semiconductor device including a deep trench isolation (DTI) structure, which can effectively improve the latching effect and avoid electrical interference between adjacent components. It is also beneficial to the miniaturization of the semiconductor device, and the deep trench isolation structure can be manufactured without using an additional mask.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a well region, a source region, a drain region, a gate, and a deep trench isolation structure. The well region is arranged in the substrate, the source region and the drain region are both arranged in the well region, the gate is arranged on the substrate and is located between the source region and the drain region, and the deep trench isolation structure is arranged in the substrate and surrounds the well region. The deep trench isolation structure includes a trench, a dielectric liner, and a conductive part, wherein the bottom surface of the trench is lower than the bottom surface of the well region, the dielectric liner is lined on the side wall of the trench, the conductive part is filled in the trench, and includes an extension portion extending downward beyond the bottom surface of the trench.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the accompanying drawings.

100A, 100B: semiconductor device

101: Base

103, 105: Well area

103B, 121B, 125B: bottom surface

107: Drain area

109: Source region

111: Matrix area

112: Gate dielectric layer

113: Gate

120: Deep trench isolation structure

121: Groove

121S: Sidewall

122: Dielectric material layer

123: Dielectric liner

124: Depression

125: Conductive part

125-1: Main body

125-2: Extension

125S: Side

126: Doped semiconductor materials

131, 132: Shallow trench isolation area

A1: First distance

A2: Second distance

B: The third distance

C: Length

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

Figure 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

Figures 3, 4, 5, 6 and 7 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Figures 8 and 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present disclosure, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device including a deep trench isolation structure. The deep trench isolation structure includes a conductive portion filled in the trench. The conductive portion includes an extension portion, which extends downward beyond the bottom surface of the trench and directly contacts the substrate. The conductive portion is electrically coupled to the ground terminal. The deep trench isolation structure can effectively improve the latching effect and avoid electrical interference between adjacent components. It is also beneficial to the miniaturization of the size of the semiconductor device. The deep trench isolation structure can be manufactured without using an additional mask.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 100A according to an embodiment of the present disclosure, wherein the semiconductor device 100A includes a substrate 101, and a well region 103 is disposed in the substrate 101. In one embodiment, the substrate 101 is a doped semiconductor substrate having a first conductivity type, such as a P-type silicon substrate. The well region 103 has a second conductivity type opposite to the first conductivity type, such as an N-type well region. In addition, another well region 105 is disposed in the well region 103, and the well region 105 has a first conductivity type, such as a P-type well region. The drain region 107 is disposed in the well region 103, the source region 109 and the bulk region 111 are both disposed in the well region 105 and are laterally adjacent to each other, wherein the drain region 107 and the source region 109 both have the second conductivity type, for example, both are N-type heavily doped regions, and the bulk region 111 has the first conductivity type, for example, a P-type heavily doped region. The gate 113 and the gate dielectric layer 112 are both disposed on the substrate 101 and are located directly above the well region 103 and the well region 105, wherein the gate dielectric layer 112 is disposed directly below the gate 113, and the gate 113 is located between the drain region 107 and the source region 109. In one embodiment, the distance between the drain region 107 and the gate 113 may be greater than the distance between the source region 109 and the gate 113. In another embodiment, the distance between the drain region 107 and the gate 113 may be equal to the distance between the source region 109 and the gate 113. In addition, in some embodiments, the gate 113 is composed of, for example, polysilicon, and the gate dielectric layer 112 is composed of, for example, silicon oxide, but is not limited thereto.

According to some embodiments of the present disclosure, the semiconductor device 100A includes a deep trench isolation structure 120 disposed in a substrate 101 and surrounding a well region 103. The deep trench isolation structure 120 includes a trench 121, and a bottom surface 121B of the trench 121 is lower than a bottom surface 103B of the well region 103. The deep trench isolation structure 120 further includes a dielectric liner 123 lining a sidewall of the trench 121, and the dielectric liner 123 may be composed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, the deep trench isolation structure 120 further includes a conductive portion 125 filled in the trench 121, and the conductive portion 125 includes an extension portion 125-2 extending downward beyond the bottom surface 121B of the trench 121. The conductive portion 125 further includes a main portion 125-1 connected to the extension portion 125-2, the main portion 125-1 is located directly above the extension portion 125-2, and the dielectric liner 123 surrounds the side surface of the main portion 125-1. In addition, the dielectric liner 123 does not surround the extension portion 125-2, and the side surface 125S and the bottom surface 125B of the extension portion 125-2 directly contact the substrate 101. In addition, the conductive portion 125 may be electrically coupled to the ground terminal through a via (not shown) and a wire (not shown) disposed thereon, so that the potential of the conductive portion 125 is approximately 0 volts (V). In one embodiment, the conductive portion 125 may be composed of a doped semiconductor material having the same first conductivity type as the substrate 101, such as P-type heavily doped polysilicon, and the doping concentration of the conductive portion 125 is higher than the doping concentration of the substrate 101. In some embodiments, the doping concentration of the conductive portion 125 is, for example, approximately 1E20 to 5E20 ions/cm ³ . Since the conductive portion 125 has an extension portion 125-2, and the side surface 125S and the bottom surface 125B of the extension portion 125-2 directly contact the substrate 101, and the conductive portion 125 is electrically coupled to the ground terminal, the holes in the substrate 101 can be channeled through the conductive portion 125 of the deep trench isolation structure 120 without accumulating a large number of holes in the substrate 101, thereby improving the latch-up effect, effectively preventing the semiconductor device from being damaged, and avoiding electrical interference between adjacent components.

In addition, still referring to FIG. 1, in the X-axis direction, the deep trench isolation structure 120 and the drain region 107 are separated by a first distance A1, and the deep trench isolation structure 120 and the base region 111 are separated by a second distance A2. In some embodiments, the first distance A1 and the second distance A2 are both at least greater than 3 micrometers (μm) to ensure that the deep trench isolation structure 120 can provide sufficient isolation effect and the deep trench isolation structure 120 does not affect the performance of the semiconductor device. For example, the first distance A1 and the second distance A2 can both be greater than 3 micrometers (μm) to about 10 micrometers (μm), and the first distance A1 and the second distance A2 can be different. In addition, in the Z-axis direction, there is a third distance B between the bottom surface 121B of the trench 121 and the bottom surface 103B of the well region 103. In some embodiments, the third distance B is at least greater than 5 micrometers (μm) to ensure that there is a sufficient distance between the trench 121 of the deep trench isolation structure 120 and the well region 103 so as not to affect the performance of the semiconductor device. For example, the third distance B may be between greater than 5 micrometers (μm) and about 30 micrometers (μm). In addition, in the Z-axis direction, the length C of the extension portion 125-2 of the deep trench isolation structure 120 is at least greater than 2 micrometers (μm) to ensure that the contact area between the extension portion 125-2 and the substrate 101 is large enough to effectively improve the latch-up effect. In some embodiments, the length C may be between greater than 2 micrometers (μm) and about 5 micrometers (μm). The numerical ranges of the first distance A1, the second distance A2, the third distance B and the length C are illustrative, but not limited thereto, and may be adjusted according to various requirements and sizes of semiconductor devices.

FIG. 2 is a schematic cross-sectional view of a semiconductor device 100B according to another embodiment of the present disclosure. In one embodiment, the semiconductor device 100B further includes a shallow trench isolation region (STI) 131 disposed in the substrate 101, and the shallow trench isolation region 131 is adjacent to the side surface of the deep trench isolation structure 120, wherein the bottom surface of the shallow trench isolation region 131 is higher than the bottom surface 103B of the well region 103 and the bottom surface of the well region 105, and the bottom surface 121B of the trench 121 of the deep trench isolation structure 120 is much lower than the bottom surface of the shallow trench isolation region 131. In addition, the shallow trench isolation region 131 is located between the body region 111 and the deep trench isolation structure 120 , and the shallow trench isolation region 131 is also located between the drain region 107 and the deep trench isolation structure 120 . In addition, the semiconductor device 100B further includes another shallow trench isolation region 132 disposed in the well region 103, and the shallow trench isolation region 132 is located between the gate 113 and the drain region 107, wherein a portion of the gate 113 extends laterally onto the shallow trench isolation region 132, and this portion of the gate 113 can be used as a field plate to disperse the electric field, thereby increasing the breakdown voltage of the semiconductor device 100B. In this embodiment, the shallow trench isolation region 131 can provide more isolation effects together with the deep trench isolation structure 120 to more effectively prevent electrical interference between adjacent components, and further improve the latching effect. In addition, the details of other components of the semiconductor device 100B in FIG. 2 can refer to the description of the semiconductor device 100A in FIG. 1, and will not be repeated here.

According to some embodiments of the present disclosure, the deep trench isolation structure of the semiconductor device has an extension portion directly contacting the substrate. Compared with the comparative example in which the deep trench isolation structure does not have an extension portion, the semiconductor device of some embodiments of the present disclosure can more effectively improve the latching effect. For example, through the electrical property test results of the semiconductor device, it can be known that the NPNβ(beta) value of the semiconductor device of the embodiment is about 0.01 to 0.1, while the NPNβ(beta) value of the semiconductor device of the comparative example is about 0.2 to 0.7. When the NPNβ(beta) value of the semiconductor device is lower, it means that the parasitic bipolar junction transistor (BJT) effect generated by the semiconductor device is lower, and the effect of improving the latching effect is better. According to the test results, the NPNβ(beta) value of the semiconductor device of some embodiments of the present disclosure is about 7 times lower than that of the comparative example, which means that the semiconductor device of the embodiment of the present disclosure can improve the latching effect more effectively.

FIG. 3, FIG. 4, FIG. 5, FIG. 6 and FIG. 7 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device 100A according to an embodiment of the present disclosure. Referring to FIG. 3, in step S101, a substrate 101 is first provided, such as a P-type silicon substrate. An ion implantation process and a patterned mask are used to first form a well region 103, such as an N-type well region, in the substrate 101. Then, another ion implantation process and another patterned mask are used to form another well region 105, such as a P-type well region, in the well region 103, wherein the bottom surface of the well region 105 is higher than the bottom surface of the well region 103. Next, an etching process and a hard mask are used to etch a trench 121 in the substrate 101, which surrounds the well area 103 and is separated from the well area 103 by a certain distance. The bottom surface of the trench 121 is lower than the bottom surface of the well area 103.

Next, referring to FIG. 4, in step S103, a dielectric material layer 122, such as a silicon oxide layer, is conformally formed on the surface of the substrate 101 and the sidewalls 121S and bottom surface 121B of the trench 121 using a deposition process and a patterned mask.

Then, referring to FIG. 5 , in step S105, an etching process, such as an anisotropic dry etching process, is used to remove the horizontal portion of the dielectric material layer 122 located on the surface of the substrate 101 and on the bottom surface 121B of the trench 121, leaving the vertical portion of the dielectric material layer 122 to form a dielectric liner 123 on the sidewall 121S of the trench 121 and expose the bottom surface 121B of the trench 121. Thereafter, in step S105, another etching process, such as an isotropic wet etching process, is used to etch the substrate 101 through the bottom surface 121B exposed by the trench 121 to form a recess 124 located directly below the trench 121. In one embodiment, in the X-axis direction, the width of the recess 124 may be the same as the width of the bottom surface 121B exposed by the trench 121, and a deep trench isolation structure 120 as shown in FIGS. 1 and 2 is subsequently formed, wherein the width of the extension portion 125-2 of the conductive portion 125 is equal to the width of the main portion 125-1. In another embodiment, as shown in FIG. 5, the width of the recess 124 may be greater than the width of the bottom surface 121B exposed by the trench 121, for example, the width of the recess 124 may be the same as the width of the trench 121, or the width of the recess 124 may be greater than the width of the trench 121. By controlling the parameters of the etching process for forming the recess 124, such as the etching time, the width and depth of the recess 124 can be controlled and adjusted, thereby controlling and adjusting the width and length of the extension portion 125-2 of the conductive portion 125 subsequently filled in the recess 124, and further controlling and adjusting the contact area between the extension portion 125-2 and the substrate 101.

Afterwards, referring to FIG. 6, in step S107, a deposition process and a patterned mask are used to fill the groove 121 and the recess 124 with a doped semiconductor material 126, and the doped semiconductor material is also deposited on the surface of the substrate 101, wherein doping ions may be added during the deposition process. In some embodiments, the doped semiconductor material 126 is, for example, P-type heavily doped polysilicon.

Next, referring to FIG. 7 , in step S109A, a chemical-mechanical planarization (CMP) process is first used to remove the doped semiconductor material 126 on the surface of the substrate 101 to form a conductive portion 125, thereby completing the manufacture of the deep trench isolation structure 120. The conductive portion 125 includes a main portion 125-1 formed in the trench 121 and surrounded by the dielectric liner 123 on the side, and an extension portion 125-2 formed in the recess 124. In this embodiment, in the X-axis direction, the width of the extension portion 125-2 can be greater than the width of the main portion 125-1. Afterwards, an ion implantation process and a patterned mask are used to form a drain region 107 in the well region 103, and a source region 109 is formed in another well region 105. The drain region 107 and the source region 109 are both N-type heavily doped regions, for example. Then, another ion implantation process and another patterned mask are used to form a substrate region 111 in the well region 105, for example, a P-type heavily doped region, wherein the substrate region 111 is adjacent to the source region 109. Then, a deposition and patterning process is used to sequentially form a gate dielectric layer 112 and a gate 113 on the substrate 101 to complete the semiconductor device 100A.

FIG. 8 and FIG. 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device 100B according to another embodiment of the present disclosure. Following step S107 of FIG. 6, referring to FIG. 8, in step S108, a chemical mechanical planarization (CMP) process is first used to remove the doped semiconductor material 126 on the surface of the substrate 101 to form a conductive portion 125, thereby completing the manufacture of the deep trench isolation structure 120. Then, an etching process and a hard mask are used to etch a shallow trench in the substrate 101. Next, a deposition process is used to fill the shallow trench with a dielectric material, and the dielectric material is deposited on the surface of the substrate 101. Afterwards, a chemical mechanical planarization (CMP) process is used to remove the dielectric material on the surface of the substrate 101 to form shallow trench isolation regions 131 and 132, wherein the shallow trench isolation region 131 is adjacent to the side surface of the deep trench isolation structure 120, and the other shallow trench isolation region 132 is located in the well region 103.

Thereafter, referring to FIG. 9 , in step S109B, an ion implantation process and a patterned mask are used to form a drain region 107 in the well region 103, and a source region 109 is formed in another well region 105. The drain region 107 and the source region 109 are, for example, both N-type heavily doped regions, wherein the drain region 107 is located between the shallow trench isolation regions 132 and 131. Then, another ion implantation process and another patterned mask are used to form a substrate region 111 in the well region 105, such as a P-type heavily doped region, wherein the left side of the substrate region 111 is adjacent to the source region 109, and the right side of the substrate region 111 is adjacent to the shallow trench isolation region 131. Then, a gate dielectric layer 112 and a gate 113 are sequentially formed on the substrate 101 using deposition and patterning processes, wherein a portion of the gate 113 extends laterally onto the shallow trench isolation region 132 to complete the semiconductor device 100B.

According to some embodiments disclosed herein, the deep trench isolation structure with an extended portion can be fabricated without using an additional mask, and the extended portion of the deep trench isolation structure can be used to improve the latch-up effect of the semiconductor device, thereby improving the performance and reliability of the semiconductor device. The above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

100A:Semiconductor device

101: Base

103, 105: Well area

103B, 121B, 125B: bottom surface

107: Drain area

109: Source region

111: Matrix area

112: Gate dielectric layer

113: Gate

120: Deep trench isolation structure

121: Groove

123: Dielectric liner

125: Conductive part

125-1: Main body

125-2: Extension

125S: Side

A1: First distance

A2: Second distance

B: The third distance

C: Length

Claims (10)

A semiconductor device comprises: a substrate; a well region disposed in the substrate; a source region and a drain region disposed in the well region; a gate disposed on the substrate and located between the source region and the drain region; and a deep trench isolation structure disposed in the substrate and surrounding the well region, the deep trench isolation structure comprising: a trench, wherein a bottom surface of the trench is lower than a bottom surface of the well region; a A depression is arranged below the bottom surface of the trench and communicates with the trench; a dielectric liner is arranged on the side wall of the trench but is not arranged in the depression; and a conductive part is filled in the trench and includes a main body part arranged in the trench and an extension part arranged in the depression and connected to the main body part, wherein the side surface and bottom surface of the extension part directly contact the substrate. A semiconductor device as described in claim 1, wherein the length of the extension portion of the conductive portion of the deep trench isolation structure is at least greater than 2 micrometers (μm). A semiconductor device as described in claim 1, wherein the conductive portion is electrically coupled to a ground terminal. A semiconductor device as described in claim 1, wherein the conductive part is composed of a doped semiconductor material, the substrate comprises a doped semiconductor substrate, the conductive type of the conductive part is the same as the conductive type of the substrate, and the doping concentration of the conductive part is higher than the doping concentration of the substrate. A semiconductor device as described in claim 4, wherein the conductivity type of the well region is opposite to the conductivity type of the conductive portion. The semiconductor device as described in claim 1 further includes a shallow trench isolation region disposed in the substrate and adjacent to the side surface of the deep trench isolation structure, wherein a bottom surface of the shallow trench isolation region is higher than the bottom surface of the well region, and there is a distance between the bottom surface of the trench of the deep trench isolation structure and the bottom surface of the well region. A semiconductor device as described in claim 6, wherein the shallow trench isolation region is located between the source region and the deep trench isolation structure, and between the drain region and the deep trench isolation structure. The semiconductor device as described in claim 6 further includes another shallow trench isolation region disposed in the well region and between the gate and the drain region, wherein a portion of the gate extends laterally onto the other shallow trench isolation region. The semiconductor device as described in claim 1 further includes a base region disposed in the well region and laterally adjacent to the source region, wherein the distance between the deep trench isolation structure and the base region and the distance between the deep trench isolation structure and the drain region are the same or different and are both at least greater than 3 micrometers (μm). A semiconductor device as described in claim 1, wherein the width of the extension portion is equal to or greater than the width of the main portion.

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