CN209963062U

CN209963062U - Semiconductor structure and semiconductor device

Info

Publication number: CN209963062U
Application number: CN201920400369.XU
Authority: CN
Inventors: 周源; 张小麟; 李静怡; 王超; 张志文; 朱林迪; 牛玉玮; 郭艳华
Original assignee: Beijing Yandong Microelectronics Technology Co Ltd
Current assignee: Beijing Yandong Microelectronics Technology Co Ltd
Priority date: 2019-03-27
Filing date: 2019-03-27
Publication date: 2020-01-17
Anticipated expiration: 2029-03-27

Abstract

The application discloses semiconductor structure and semiconductor device, this semiconductor structure includes: a semiconductor substrate; the epitaxial layer is of a first doping type and is positioned on the first surface of the semiconductor substrate; the well region is of a second doping type and is positioned on the epitaxial layer, the doping concentration of the well region is greater than that of the epitaxial layer, and the second doping type is opposite to the first doping type; a doped region of a first doping type extending from the well region into the epitaxial layer to define at least one well region island in the well region; and the isolation layer is at least partially positioned between the well region and the doped region and used for separating the well region from the doped region, wherein the doped region receives a control voltage, when the control voltage meets a preset range, a channel region which is in an inverse shape with the well region is formed in each well region island, and the channel region is close to the isolation layer and is in contact with the epitaxial layer. Therefore, the concentration of the epitaxial layer, which is a factor for determining the breakdown voltage of the PN junction, is changed into the concentration of the well region, and the breakdown voltage of the PN junction is further changed.

Description

Semiconductor structure and semiconductor device

Technical Field

The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor structure and a semiconductor device.

Background

As is well known, PN junctions are fundamental building blocks in the fabrication of discrete devices or integrated circuits. A well-formed PN junction has excellent switching characteristics, or voltage stabilizing characteristics. Various discrete devices such as PIN transistors, TVS transistors, switching transistors, rectifying transistors, etc. have been derived from different applications. In integrated circuits, various functional regions such as isolation, base, emitter, source and drain are often formed. The reverse voltage of a PN junction is stable, and the reverse breakdown voltage of a PN junction is influenced by the width of the barrier region or space charge region, so that the breakdown voltage of a PN junction tends to be influenced more by the side having a lower concentration. For example, a higher concentration of N-type silicon and a lower concentration of P-type silicon are sintered together, the barrier region will get a larger broadening on the P-type silicon side, and thus the breakdown voltage of the PN junction will be determined by the P-type. If the doping concentration on the low concentration side is not changed any more, the breakdown voltage of the PN junction tends to be stable.

When the PN junction is manufactured, the concentration of the two sides of the PN junction is determined, so that the breakdown voltage of the PN junction is fixed, however, different breakdown voltages are required to meet application requirements in certain specific occasions.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present disclosure provides a semiconductor structure and a semiconductor device, in which a doped region receives a control voltage, and when the control voltage satisfies a predetermined range, a channel region inverse to a well region is formed in each well region island, so that an epitaxial layer concentration, which is a factor that previously determines a PN junction breakdown voltage, is changed into a well region concentration, thereby changing the PN junction breakdown voltage.

According to an aspect of the present disclosure, there is provided a semiconductor structure including: a semiconductor substrate; the epitaxial layer is of a first doping type and is positioned on the first surface of the semiconductor substrate; the well region is of a second doping type and is positioned on the epitaxial layer, the doping concentration of the well region is greater than that of the epitaxial layer, and the second doping type is opposite to the first doping type; a doped region of a first doping type extending from the well region into the epitaxial layer to define at least one well region island in the well region; and the isolation layer is at least partially positioned between the well region and the doped region and is used for separating the well region from the doped region, wherein the doped region receives a control voltage, when the control voltage meets a preset range, a channel region which is in an inverse shape with the well region is formed in each well region island, and the channel region is close to the isolation layer and is in contact with the epitaxial layer.

Preferably, the method further comprises the following steps: a first electrode electrically connected to the semiconductor substrate and/or the epitaxial layer; a second electrode electrically connected to the well region; and a third electrode electrically connected to the doped region to provide the control voltage.

Preferably, at least a portion of the isolation layer is located between the doped region and the epitaxial layer for electrically isolating the epitaxial layer from the doped region.

Preferably, the first electrode is located on a second surface of the semiconductor substrate, the second surface of the semiconductor substrate being opposite to the first surface.

Preferably, the semiconductor device further comprises an insulating layer covering the well region, the doped region and the isolation layer.

Preferably, the second electrode and the third electrode are located on the insulating layer, and the semiconductor structure further includes: the first electric connection structure penetrates through the insulating layer and extends into the well region, and the first electric connection structure is electrically connected with the second electrode; and a second electrical connection structure penetrating the insulating layer and extending into the doped region, the second electrical connection structure being electrically connected to the third electrode.

Preferably, when the control voltage satisfies the predetermined range, the majority carrier concentration of the channel region varies with the control voltage and is higher than the majority carrier concentration of the well region.

Preferably, the doped region comprises polysilicon of the first doping type.

Preferably, the doping concentration of the doping region is greater than that of the epitaxial layer.

Preferably, the substrate is of a first doping type and has a doping concentration greater than that of the epitaxial layer.

Preferably, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

According to another aspect of the present disclosure, there is provided a semiconductor device including: the semiconductor structures are arranged in an array.

Preferably, the first electrodes of the plurality of semiconductor structures are connected, and the second electrodes of the plurality of semiconductor structures are connected.

Preferably, the plurality of semiconductor structures share the same substrate, thereby sharing the first electrode.

Preferably, the second electrodes of the plurality of semiconductor structures are interconnected to form a first conductive region.

Preferably, in each of the semiconductor structures, the doped region includes an extension portion, the third electrode is located above the extension portion and electrically connected to the entire doped region through the extension portion, and the plurality of well region islands and the extension portion are sequentially arranged in the first direction.

Preferably, the plurality of semiconductor structures are arranged in a second direction perpendicular to the first direction, and the third electrode interconnections of the plurality of semiconductor structures form a second conductive region.

According to the semiconductor structure disclosed by the invention, the well region of the second doping type is formed on the epitaxial layer of the first doping type, so that the well region and the epitaxial layer form a PN junction, the doping concentration of the well region is greater than that of the epitaxial layer, the breakdown voltage of the PN junction is determined by the doping concentration of the epitaxial layer, at least one well region island is defined in the well region through the doping region extending from the well region to the epitaxial layer, a control voltage is applied to the doping region through the formation of the isolation layer positioned between the well region and the doping region, and when the control voltage meets a preset range, a channel region which is in an inverse shape with the well region is formed in each well region island, so that the epitaxial layer concentration which is a factor for determining the breakdown voltage of the PN junction is changed into the well region concentration, the breakdown voltage of the PN junction is further changed, and the purpose of changing the breakdown voltage of.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1a to 2b show schematic structural diagrams of a semiconductor device according to an embodiment of the present invention.

Fig. 3 to 11 show cross-sectional views of a method of manufacturing a semiconductor device at various stages according to an embodiment of the present invention.

Fig. 12 shows a schematic structural diagram of an integrated circuit according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be presented in a variety of forms, some of which are described below.

Fig. 1a to 2b show schematic structural diagrams of a semiconductor device according to an embodiment of the present invention. Fig. 1a and 2a show top views of a semiconductor device according to an embodiment of the present invention, fig. 1b shows a cross-sectional view along a-a in fig. 1a, and fig. 2b shows a cross-sectional view along a-a in fig. 2 a.

As shown in fig. 1a and 1b, the semiconductor device according to the embodiment of the present invention includes: the semiconductor device includes a semiconductor substrate 101, an epitaxial layer 110, a well region 120, an isolation layer 130, a doped region 140, an insulating layer 150, a first electrical connection structure 162, a second electrical connection structure 163, a first electrode 171, a second electrode 172, and a third electrode 173, wherein the isolation layer 130 includes a first portion 132 of the isolation layer and a second portion 131 of the isolation layer. The well region 120 is of the second doping type, and the semiconductor substrate 101, the epitaxial layer 110 and the doping region 140 are of the first doping type, wherein the doping concentration of the well region 120 is greater than the doping concentration of the epitaxial layer 110, the doping concentration of the doping region 140 is greater than the doping concentration of the epitaxial layer 110, and the doping concentration of the substrate 101 is greater than the doping concentration of the epitaxial layer 110. The second doping type is opposite to the first doping type. The second doping type is selected from one of P type doping and N type doping, and the first doping type is selected from the other of P type doping and N type doping.

In this embodiment, the second doping type is selected from P-type doping, and the first doping type is selected from N-type doping. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the doping type as needed. For clarity, the insulating layers and the various electrodes in the semiconductor device are not shown in fig. 1 a.

In the present embodiment, the epitaxial layer 110 is located on the first surface of the semiconductor substrate 101. Well region 120 is located on epitaxial layer 110. Doped regions 140 extend from well region 120 into epitaxial layer 110 and surround portions of well region 120 to define at least one well region island 121 therein. The first portion 132 of the isolation layer is located between the well region 120 and the doped region 140, and is used to separate the well region 120 and the doped region 140, so that the well region 120 is electrically isolated from the doped region 140. The second portion 131 of the isolation layer is located between the doped region 140 and the epitaxial layer 110, and is used to separate the epitaxial layer 110 from the doped region 140, so as to electrically isolate the epitaxial layer 110 from the doped region 140. The insulating layer 150 covers the well region 120, the doped region 140, and the isolation layer 130.

The first surface of the semiconductor substrate 101 is opposite to the second surface. The first electrical connection structure 162 extends through the insulating layer 150 into the well region 120. The second electrical connection structure 163 extends through the insulating layer 150 into the doped region 140. The first electrode 171 is located on the second surface of the semiconductor substrate 101 and electrically connected to the semiconductor substrate 101 and/or the epitaxial layer 110, and the second electrode 172 and the third electrode 173 are located on the insulating layer 150 and are in contact with the first electrical connection structure 162 and the second electrical connection structure 163, respectively. The well region 120 is led out to an external circuit through the first electrical connection structure 162 and the second electrode 172, and the doped region 120 is led out to the external circuit through the second electrical connection structure 163 and the third electrode 173.

In the present embodiment, the material of the doped region 140 includes, but is not limited to, polysilicon, the material of the isolation layer 130 includes, but is not limited to, a gate oxide material, the doping concentration of the doped region 140 is greater than that of the epitaxial layer 110, and it can be easily understood from the device principle that: the doped region 140 and the well 120 are isolated by an isolation layer, and a third electrode 173 and a second electrode 172 are respectively led out from the doped region 140 and the well 120, and a lateral MOS capacitor structure is formed between the N-type doped region 140, the isolation layer 130 and the P-type well 120, as shown in fig. 1 c. When the control voltage applied at the third electrode 173 is in a range satisfying a predetermined value, majority carriers (positively charged holes) in the P-type well region 120 will be driven away from the isolation layer 130, whereas minority carriers (negatively charged electrons) will be attracted and accumulated at the interface of the P-type well region 120 and the isolation layer 130. When the minority carrier concentration near the isolation layer 130 is sufficiently high, the minority carrier concentration exceeds the majority carrier concentration in the P-well 120, thereby forming an N-type channel region that is inverted with respect to the P-well 120. And the concentration of the N-type channel region varies with the level of the control voltage applied to the third electrode 173.

As shown in fig. 2a and 2b, in a state where the third electrode 173 is not energized or when the voltage applied by the third electrode 173 does not satisfy a predetermined range, the doping concentration of the P-type well region 120 is greater than the doping concentration of the N-type epitaxial layer 110, and the reverse breakdown voltage of the PN junction formed by the P-type well region 120 and the N-type epitaxial layer 110 is determined by the doping concentration of the N-type epitaxial layer 110. By using the MOS capacitance principle shown in fig. 1c, when the control voltage received by the doped region 140 satisfies a predetermined range, a channel region 180 inverse to the well region 120 is formed in each well region island 121, and the channel region 180 is close to the isolation layer 130 and contacts the epitaxial layer 110, i.e., the N-type epitaxial layer 110 and the N-type channel region 180 jointly form a new PN junction with the P-type well region 120 again. At this time, the majority carrier concentrations in the N-type channel region 180, the P-type well region 120, and the N-type epitaxial layer 110 decrease in sequence, so the breakdown voltage of the PN junction between the first electrode 171 and the second electrode 172 is determined by the doping concentration of the P-type well region 120. In addition, the concentration of the N-type channel region 180 varies with the voltage of the third electrode 173, and further the doping concentration of the P-type well region 120 varies with the voltage of the third electrode 173, thereby achieving the purpose of voltage transformation.

With the semiconductor structure of this embodiment, a transformation device based on a PN junction, such as a transformer diode, a transformer triode, or the like, can be fabricated.

Fig. 3 to 11 show cross-sectional views of a method of manufacturing a semiconductor device at various stages according to an embodiment of the present invention. The method for manufacturing the semiconductor device of the present invention will be described in detail with reference to fig. 3 to 10.

The method of the embodiment of the present invention starts with a semiconductor substrate 101, and forms an epitaxial layer 110 on a first surface of the semiconductor substrate 101, as shown in fig. 3.

In this step, an N-type doped epitaxial layer 110 is formed on the first surface of the N-type doped semiconductor substrate 101, for example, using a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process. Wherein the doping concentration of the epitaxial layer 110 is less than the doping concentration of the semiconductor substrate 101. However, the embodiments of the present invention are not limited thereto, and since the doping concentration of the epitaxial layer 110 will determine the initial voltage of the semiconductor structure, those skilled in the art can set the doping concentration of the epitaxial layer 110 as needed.

Further, a photoresist mask is formed, for example, on the surface of the semiconductor structure, and then anisotropic etching is performed to pattern the epitaxial layer 110 to form isolation trenches 102 in the epitaxial layer 110, as shown in fig. 4.

In this step, the anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that a predetermined depth in the epitaxial layer 110 is etched. The photoresist mask is removed by dissolving or ashing in a solvent after etching. In this embodiment, at least one well region island is formed around the portion defined by the isolation trenches 102, and the isolation trenches 102 will be used to form isolation layers and doped regions for subsequent steps. For this reason, the depth of the isolation trench 102 is not less than 1000 angstroms.

Further, an isolation layer 130 is formed covering the surface of the epitaxial layer 110 and the inner surface of the isolation trench 102, as shown in fig. 5.

In this step, an isolation layer 130 is formed on the surface of the epitaxial layer 110 and the isolation trenches 102, for example, using a CVD or PVD process. In this embodiment, the thickness of the isolation layer 130 ranges from 20 to 1000 angstroms, and the material of the isolation layer 130 includes, but is not limited to, oxide.

Further, a polysilicon layer 103 is formed covering the isolation layer 130 and filling the isolation trench 102, as shown in fig. 6.

In this step, N-type doped polysilicon is deposited on the surface of the isolation layer 130, for example, by CVD or PVD process, wherein the polysilicon may be in-situ doped polysilicon and has a doping concentration greater than that of the epitaxial layer.

In some other embodiments, the polysilicon may also be ex-situ doped polysilicon, and after the deposition on the surface of the isolation layer 130, the polysilicon is doped by implantation, wherein the doping type of the polysilicon is N-type doping.

Further, a portion of the polysilicon layer 103 is removed so that the isolation layer 130 covering the surface of the epitaxial layer 110 is exposed, as shown in fig. 7.

In this step, the polysilicon layer 103 is etched, for example, using an etching process, stopping when the etch reaches the isolation layer 130 covering the surface of the epitaxial layer 110. At this time, only the polysilicon inside the isolation trench remains, thereby forming the doped region 140.

In some other embodiments, the polysilicon layer 103 is removed, for example, using a chemical mechanical polishing process, and the polishing is stopped when the isolation layer 130 covering the surface of the epitaxial layer 110 is reached. At this time, only the polysilicon inside the isolation trench remains, thereby forming the doped region 140.

Further, a well region 120 is formed in an upper portion of the epitaxial layer 110, as shown in fig. 8.

In this step, P-type dopant ions are implanted into the epitaxial layer 110 through the isolation layer 130 by, for example, an ion implantation process, so as to form the well region 120 and to retain a portion of the epitaxial layer 110 under the well region 120. Since the isolation trenches are formed in the preceding step, the boundary of the source region of the device has been defined by the well region islands surrounded by the isolation trenches, i.e. the trench isolation process. Thus, the formation of the P-well 120 may use a maskless global implantation process, which may save a reticle level.

In this embodiment, the doping concentration of the well 120 is greater than that of the epitaxial layer 110, so that the breakdown voltage of the PN junction is determined by the lower concentration of the N-type epitaxial layer 110. Meanwhile, when the applied control voltage received by the doped region 140 satisfies a predetermined range, the doping concentration of the P-type well region 120 should be less than the doping concentration of the N-type channel region formed next to the isolation layer 130, the channel region is connected to the epitaxial layer 110, so that the P-type well region 120 and the N-type channel region form a PN junction again, and the breakdown voltage of the PN junction formed again is determined by the well region 120 with a lower concentration.

The doping concentration of the well 120 can be adjusted as desired by those skilled in the art, but should be set to form an N-type channel region of an inversion P-type well to form a PN junction.

Further, an insulating layer 150 is formed such that the well region 120, the doped region 140 and the isolation layer 130 are located under the insulating layer 150, as shown in fig. 9.

In this step, an insulating dielectric is deposited on the surface of the semiconductor structure, for example by means of a CVD or PVD process, and an insulating layer 150 is formed in conjunction with a corresponding annealing, reflow or chemical-mechanical polishing process. The material of the insulating medium includes, but is not limited to, phosphosilicate glass, borophosphosilicate glass, undoped silicate glass, and fluorosilicate glass.

Further, contact holes 104 are formed through the insulating layer 150 and extending to the doped regions 140, through the insulating layer 150 and extending to the well region 120, respectively, as shown in fig. 10.

In this step, the contact hole 104 at the first surface of the semiconductor structure should extend to a predetermined depth inside the well region 120 or horizontally, and when the doped region 140 is applied with a voltage, a channel region is formed to be connected to the epitaxial layer 110.

Further, a first electrical connection structure 162 and a second electrical connection structure 163 are formed in the contact holes, respectively, as shown in fig. 11.

In this step, a conductive material, such as, but not limited to, metal tungsten, is deposited in the contact hole, for example, by a CVD or PVD process, and the contact hole is filled such that the conductive material is substantially in contact with the well region 120 and the doped region 140.

Further, a first electrode 171 is formed on the second surface of the semiconductor substrate 101, a second electrode 172 is formed on the insulating layer 150 and contacts the first electrical connection structure 162, and a third electrode 173 is formed on the insulating layer 150 and contacts the second electrical connection structure 163, wherein the second surface of the semiconductor substrate is opposite to the first surface, thereby forming the semiconductor structure of the embodiment of the present invention as shown in fig. 1a and 1 b.

Fig. 12 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

As shown in fig. 12, the semiconductor device according to the embodiment of the present invention includes a plurality of the above semiconductor structures, and the plurality of semiconductor structures are arranged in an array. Specifically, the first electrodes of the plurality of semiconductor structures are connected, and the second electrodes of the plurality of semiconductor structures are connected. The plurality of semiconductor structures share the same substrate and thus share the first electrode. The second electrodes 172 of the plurality of semiconductor structures are interconnected to form a first conductive region 191. In each semiconductor structure, the doped region 140 includes an extension portion 141, the third electrode 173 is located above the extension portion and electrically connected to the entire doped region 140 through the extension portion 141, and the plurality of well region islands 121 and the extension portion 141 are sequentially arranged in the X direction (the first direction). The plurality of semiconductor structures are arranged in a Y direction (second direction) perpendicular to the X direction, and the third electrodes 173 of the plurality of semiconductor structures are interconnected to form the second conductive regions 192.

A schematic diagram of a semiconductor device with 100 semiconductor structures connected in parallel is shown in fig. 12.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art can freely select the number of independent devices to match the current according to the current limit of the analog independent device.

According to the semiconductor structure, the manufacturing method thereof and the semiconductor device, the well region of the second doping type is formed on the epitaxial layer of the first doping type, so that the well region and the epitaxial layer form a PN junction, since the doping concentration of the well region is greater than that of the epitaxial layer, the breakdown voltage of the PN junction is determined by the doping concentration of the epitaxial layer, by forming doped regions extending from the well region into the epitaxial layer, at least one well region island is defined in the well region, and by forming an isolation layer between the well region and the doped region, applying a control voltage to the doped region, forming a channel region in each well region island that is inverted with respect to the well region when the control voltage satisfies a predetermined range, thereby changing the concentration of the epitaxial layer, which is a factor for determining the breakdown voltage of the PN junction, into the concentration of the well region, and further, the breakdown voltage of the PN junction is changed, and the purpose of changing the breakdown voltage of the PN junction is achieved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present invention, and these alternatives and modifications are intended to fall within the scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

the epitaxial layer is of a first doping type and is positioned on the first surface of the semiconductor substrate;

the well region is of a second doping type and is positioned on the epitaxial layer, the doping concentration of the well region is greater than that of the epitaxial layer, and the second doping type is opposite to the first doping type;

a doped region of a first doping type extending from the well region into the epitaxial layer to define at least one well region island in the well region; and

an isolation layer at least partially located between the well region and the doped region for separating the well region and the doped region,

and the doped region receives a control voltage, and when the control voltage meets a preset range, a channel region in an inversion shape with the well region is formed in each well region island, and the channel region is close to the isolation layer and is in contact with the epitaxial layer.

2. The semiconductor structure of claim 1, further comprising:

a first electrode electrically connected to the semiconductor substrate and/or the epitaxial layer;

a second electrode electrically connected to the well region; and

a third electrode electrically connected to the doped region to provide the control voltage.

3. The semiconductor structure of claim 2, wherein at least a portion of the isolation layer is located between the doped region and the epitaxial layer for electrically isolating the epitaxial layer from the doped region.

4. The semiconductor structure of claim 3, wherein the first electrode is located on a second surface of the semiconductor substrate, the second surface of the semiconductor substrate being opposite the first surface.

5. The semiconductor structure of claim 3, further comprising an insulating layer covering the well region, the doped region, and the isolation layer.

6. The semiconductor structure of claim 5, wherein the second and third electrodes are on the insulating layer, the semiconductor structure further comprising:

the first electric connection structure penetrates through the insulating layer and extends into the well region, and the first electric connection structure is electrically connected with the second electrode; and

and the second electric connection structure penetrates through the insulating layer and extends into the doped region, and the second electric connection structure is electrically connected with the third electrode.

7. The semiconductor structure of claim 2, wherein when the control voltage satisfies the predetermined range, a majority carrier concentration of the channel region varies with the control voltage and is higher than a majority carrier concentration of the well region.

8. The semiconductor structure of claim 2, wherein the doped region comprises polysilicon of the first doping type.

9. The semiconductor structure of claim 2, wherein a doping concentration of the doped region is greater than a doping concentration of the epitaxial layer.

10. The semiconductor structure of claim 2, wherein the substrate is of a first doping type and has a doping concentration greater than a doping concentration of the epitaxial layer.

11. The semiconductor structure of any of claims 2-10, wherein the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

12. A semiconductor device, comprising:

a plurality of semiconductor structures according to any of claims 2 to 11, wherein the plurality of semiconductor structures are arranged in an array.

13. The semiconductor device of claim 12, wherein the first electrodes of the plurality of semiconductor structures are connected and the second electrodes of the plurality of semiconductor structures are connected.

14. The semiconductor device of claim 13, wherein the plurality of semiconductor structures share the same substrate and thus share the first electrode.

15. The semiconductor device of claim 13, wherein the second electrodes of the plurality of semiconductor structures are interconnected to form a first conductive region.

16. The semiconductor device of claim 13, wherein, in each of the semiconductor structures,

the doped region comprises an extension portion, the third electrode is located above the extension portion and electrically connected with the whole doped region through the extension portion, and the well region islands and the extension portions are sequentially arranged in a first direction.

17. The semiconductor device according to claim 16, wherein the plurality of semiconductor structures are arranged in a second direction perpendicular to the first direction, and wherein the third electrode interconnections of the plurality of semiconductor structures form a second conductive region.