TWI867398B - Memory device - Google Patents

Abstract

Embodiments provide a memory device with high data reading performance. A memory device includes a first conductor, a first stacked body on the first conductor, a second conductor on the first stacked body, a second stacked body on the second conductor, and a third conductor on the second stacked body. The first stacked body includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in order from a side of the first conductor. The second and third ferromagnetic layers have magnetizations in opposite directions. The second stacked body includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in order from a side of the second conductor. The fifth and sixth ferromagnetic layers have magnetizations in opposite directions. The sixth ferromagnetic layer has a larger volume than the third ferromagnetic layer.

Description

Memory device

The embodiments described herein generally relate to a memory device. Cross-references to Related Applications

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-038263 (filed on March 11, 2022) and U.S. Patent Application No. 17/898913 (filed on August 30, 2022), the entire contents of which are incorporated herein by reference.

A memory device that uses a device having a variable resistance value to store data is known. The memory device must have a high storage capacity and a high data read performance.

The embodiment provides a memory device with high data reading performance.

Generally, according to one embodiment, the memory device includes a first conductor, a first stack on the first conductor, a second conductor on the first stack, a second stack on the second conductor, and a third conductor on the second stack.

The first stack includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in sequence from one side of the first conductor. The second ferromagnetic layer and the third ferromagnetic layer have magnetizations in opposite directions. The second stack includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in sequence from one side of the second conductor. The fifth ferromagnetic layer and the sixth ferromagnetic layer have magnetizations in opposite directions. The sixth ferromagnetic layer has a volume greater than that of the third ferromagnetic layer.

Multiple components having substantially the same function and configuration in one embodiment or different embodiments may have additional numerals or letters added to the end of the reference numeral to distinguish them from each other. In an embodiment following any described embodiment, the differences from the described embodiment are mainly described. All descriptions of one embodiment also apply to the description of another embodiment, unless explicitly excluded or its exclusion is obvious.

It is not necessary that each functional block is implemented as shown in the following example. For example, some functions may be performed by a functional block different from the example functional block. Furthermore, the example functional block may be subdivided into more detailed functional sub-blocks.

As used in this specification and the scope of the patent application, when a first element is "connected" to another second element, the first element can be directly connected to the second element, or via an element that becomes conductive either constantly or selectively. 1. First embodiment 1.1. Structure (configuration) 1.1.1. Overall configuration

FIG1 is a block diagram of a memory device of the first embodiment. The memory device 1 is a device for storing data. The memory device 1 uses a stack of magnetic materials exhibiting variable resistance to store data. The memory device 1 includes a core circuit 11, an input and output circuit 12, a control circuit 13, a decoding circuit 14, a page buffer 15, and a voltage generating circuit 16.

The core circuit 11 is a circuit that includes a memory cell MC (only one of which is depicted in FIG. 1 ), wiring for accessing the memory cell MC, and a peripheral circuit. The memory cell MC is an element that stores data in a non-volatile manner. The wiring includes a global word line GWL (not shown), a local word line LWL, a global bit line GBL (not shown), and a local bit line LBL. Each memory cell MC is connected to a local word line LWL and a local bit line LBL. The local word line LWL is assigned a column address. The local bit line LBL is assigned a row address.

The input and output circuit 12 is a circuit that inputs and outputs data and signals. The input and output circuit 12 receives a control signal CNT, a command CMD, an address signal ADD, and data DAT to be written into the memory cell MC from the outside of the memory cell 1 (eg, a memory controller).

The control circuit 13 is a circuit for controlling the operation of the memory device 1. The control circuit 13 receives the command CMD and the control signal CNT from the input and output circuit 12. The control circuit 13 controls the core circuit 11 based on the command CMD and the control signal CNT, and controls the reading of data from the memory cell MC and the writing of data to the memory cell MC. The control circuit 13 controls the voltage generating circuit 16 based on the command CMD and the control signal CNT.

The decoding circuit 14 is a circuit for decoding the address signal ADD. The decoding circuit 14 receives the address signal ADD from the input and output circuit 12. The decoding circuit 14 decodes the address signal ADD and generates a signal for selecting the memory unit MC from which data is read or written based on the result of the decoding. The generated signal is transmitted to the core circuit 11.

The page buffer 15 is a circuit that temporarily stores data of a certain size. The page buffer 15 receives data DAT written into the memory cell MC from the input and output circuit 12, temporarily stores the data, and transfers the data to the core circuit 11. The page buffer 15 also receives data read from the memory cell MC, temporarily stores the read data, and transfers the data DAT to the input and output circuit 12.

The voltage generating circuit 16 is a circuit that generates various voltages used in the memory device 1. The voltage generating circuit 16 generates voltages based on the control of the control circuit 13. The voltage generating circuit 16 supplies the voltage used for data writing to the core circuit 11 during the writing of data to the memory cell MC. The voltage generating circuit 16 supplies the voltage used for data reading to the core circuit 11 during the reading of data from the memory cell MC. 1.1.2.Core circuit configuration

FIG2 is a block diagram of the core circuit 11 of the first embodiment. As shown in FIG2, the core circuit 11 includes a plurality of groups, each including a memory cell array MA, a column selector RS, and a row selector CS. The core circuit 11 further includes a plurality of global word lines GWL, a plurality of local word lines LWL, a plurality of global bit lines GBL, a plurality of local bit lines LBL, a read circuit RC, and a write circuit WC. FIG2 depicts only one group, which includes the memory cell array MA, the column selector RS, and the row selector CS, together with one global word line GWL and one global bit line GBL.

The memory cell array MA is composed of a plurality of memory cells MC. A plurality of local word lines LWL and a plurality of local bit lines LBL are disposed in the memory cell array MA.

The column selector RS is provided for controlling a memory cell array MA. The column selector RS is a circuit for selecting a column of the corresponding memory cell array MA. The column selector RS receives a column address and connects one of the local word lines LWL of the corresponding memory cell array MA to a global word line GWL based on the received column address. The column selector RS includes a plurality of switches. Each switch is connected to a global word line GWL at one end and to a local word line LWL at the other end. The switch is, for example, a MOSFET (metal oxide semiconductor field effect transistor), for example, an n-type MOSFET.

A row selector CS is provided for controlling a memory cell array MA. The row selector CS is a circuit for selecting a row of the corresponding memory cell array MA. The row selector CS receives a row address and connects one of the local bit lines LBL of the corresponding memory cell array MA to a global bit line GBL based on the received row address. The row selector CS includes a plurality of switches. Each switch is connected to a global bit line GBL at one end and to a local bit line LBL at the other end. The switch is, for example, a MOSFET, for example, an n-type MOSFET.

The global word line GWL is connected to a plurality of row selectors RS. The global word line GWL is also connected to a read circuit RC and a write circuit WC.

The global bit line GBL is connected to a plurality of row selectors CS. The global bit line GBL is also connected to a read circuit RC and a write circuit WC.

The read circuit RC is a circuit that controls the reading of data from the memory cell MC. The read circuit RC determines the data stored in the data read target memory cell MC using a voltage based on the data stored in the data read target memory cell MC. The read circuit RC includes a plurality of sense amplifier circuits SAC. The sense amplifier circuit SAC is a circuit that outputs the data determined to be stored in the data read target memory cell MC by using a voltage based on the data stored in the data read target memory cell MC. The sense amplifier circuit SAC may output data based on a relationship between a voltage based on data stored in the data read target memory cell MC (e.g., a low holding voltage VhdL or a high holding voltage VhdH described below) and a reference voltage having a magnitude between the low holding voltage VhdL and the high holding voltage VhdH. The sense amplifier circuit SAC outputs data determined to be stored in the data read target memory cell MC based on the relationship between the two voltages.

The write circuit WC is a circuit that controls the writing of data into the memory cell MC. The write circuit WC receives data to be written. The write circuit WC writes data into the data write target memory cell MC by causing a current to flow through the data write target memory cell MC based on the data to be written. 1.1.3. Circuit configuration of memory cell array

FIG3 is a circuit diagram of the memory cell array MA of the first embodiment. As shown in FIG3, M+1 (M is a natural number) local word lines LWLA (LWLA <0>, LWLA <1>, ..., LWLA <M>) and M+1 local word lines LWLB (LWLB <0>, LWLB <1>, ..., LWLB <M>) are placed in the memory cell array MA. N+1 (N is a natural number) local bit lines LBL (LBL <0>, LBL <1>, ..., LBL <N>) are also placed in the memory cell array MA.

Each memory cell MC (MCA and MCB) is connected to a local word line LWL and a local bit line LBL. More specifically, the memory cell MCA includes memory cells MCA <α, β> for all combinations of all cases where α is an integer of 0 or greater and M or less and all cases where β is an integer of 0 or greater and N or less. The memory cell MCA <α, β> is connected between the local word line LWLA <α> and the local bit line LBL <β>. Similarly, the memory cell MCB includes memory cells MCB <α, β> for all combinations of all cases where α is an integer of 0 or greater and M or less and all cases where β is an integer of 0 or greater and N or less. The memory cell MCB ＜α, β＞ is connected between the local word line LWLB ＜α＞ and the local bit line LBL ＜β＞.

Each memory cell MC includes a magnetic tunneling junction (MTJ) element MTJ (MTJA or MTJB) and a switching element SE (SEA or SEB).

In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SEA of each memory cell MCA is connected to a local word line LWL. The MTJ element MTJA of each memory cell MCA is connected to a local bit line LBL. The switching element SEB of each memory cell MCB is connected to a local bit line LBL. The MTJ element MTJB of each memory cell MCB is connected to a local word line LWL.

MTJ element MTJ is an element that exhibits a tunneling magnetoresistance effect and includes, for example, a magnetic tunneling junction (MTJ). MTJ element MTJ can be switched between a low resistance state and a high resistance state. MTJ element MTJ can store 1 bit of data by utilizing the difference between the two resistance states. For example, MTJ element MTJ stores "0" data in a low resistance state and stores "1" data in a high resistance state.

The switching element SE is an element for selecting a memory cell MC in which the switching element SE is to be included. The switching element SE includes two terminals. When the voltage applied between the two terminals is less than a first critical voltage, the switching element SE is in a high resistance state, for example, a non-conductive state (OFF state). When the voltage applied between the two terminals increases and becomes equal to or higher than the first critical voltage, the switching element SE enters a low resistance state, for example, a conductive state (ON state). When the voltage applied between the two terminals of the switching element SE in the low resistance state decreases and becomes equal to or lower than a second critical voltage, the switching element SE enters a high resistance state. The switching element SE has the same function as a switching function between a high resistance state and a low resistance state based on the magnitude of a voltage applied in a first direction, in a second direction opposite to the first direction. That is, the switching element SE is a directional switching element. By turning the switching element SE on or off, it is possible to control whether current is supplied to the MTJ element MTJ connected to the switching element SE, that is, the selection or non-selection of the MTJ element MTJ. 1.1.4. Structure of memory cell array

FIG4 is a perspective view of a portion of the memory cell array MA of the first embodiment. The component shading shown in FIG4 is only added for the purpose of visual comparison of the figures. The material of the shaded component depends on the material indicated by the shaded pattern.

4, the memory cell array MA includes memory cells MCA and MCB. A plurality of conductors 21, a plurality of conductors 22, and a plurality of conductors 23 are disposed in the memory cell array MA.

The conductors 21 extend along the y-axis and are arranged along the x-axis. Each conductor 21 functions as a local word line LWLA.

The conductor 22 is placed on the conductor 21. The conductor 22 extends along the x-axis and is arranged along the y-axis. Each conductor 22 functions as a local bit line LBL.

The conductor 23 is disposed on the conductor 22. The conductor 23 extends along the y-axis and is arranged along the x-axis. Each conductor 23 functions as a local word line LWLB.

A memory cell MCA is provided at each intersection of the conductor 21 and the conductor 22. The memory cell MCA is arranged in a matrix configuration in the xy plane. Each memory cell MCA includes a structure that functions as a switching element SEA and a structure that functions as an MTJ element MTJA. The structure that functions as a switching element SEA and the structure that functions as an MTJ element MTJA each include one or a plurality of layers. The structure that functions as an MTJ element MTJA is placed on the upper surface of the structure that functions as a switching element SEA. The lower surface of the memory cell MCA is in contact with the upper surface of the conductor 21. The upper surface of the memory cell MCA is in contact with the lower surface of the conductor 22. The memory cell MCA may be referred to as a lower memory cell MCA.

A memory cell MCB is provided at each intersection of the conductor 22 and the conductor 23. The memory cell MCB is arranged in a matrix configuration in the xy plane. Each memory cell MCB includes a structure acting as a switching element SEB and a structure acting as an MTJ element MTJB. The structure acting as a switching element SEB and the structure acting as an MTJ element MTJB each include one or more layers. The structure acting as an MTJ element MTJB is arranged on the upper surface of the structure acting as a switching element SEB. The lower surface of the memory cell MCB is in contact with the upper surface of the conductor 22. The upper surface of the memory cell MC is in contact with the lower surface of the conductor 23. The memory cell MCB may be referred to as an upper memory cell MCB. 1.1.5. Memory cell structure

FIG. 5 shows a cross section of an example of the structure of the memory cell MC of the first embodiment. FIG. 5 shows a lower memory cell MCA and an upper memory cell MCB, and also shows conductors 21, 22, and 23 connected to the lower memory cell MCA and the upper memory cell MCB. The lower memory cell MCA and the upper memory cell MCB each include a number of substantially identical components. Among the components common to the lower memory cell MCA and the upper memory cell MCB, the components provided in the lower memory cell MCA may have "A" added to the end of the reference number and the components provided in the upper memory cell MCB may have "B" added to the end of the reference number.

5, the structure serving as the lower memory cell MCA includes a structure serving as a switching element SE, that is, a structure serving as a switching element SEA. The structure serving as the switching element SEA includes a variable resistance material 31, that is, a variable resistance material 31A.

The variable resistance material 31 is a material exhibiting a variable resistance. The variable resistance material 31 is a switching element between two terminals, a first terminal of the two terminals being one of the upper surface and the lower surface of the variable resistance material 31, and a second terminal of the two terminals being the other of the upper surface and the lower surface of the variable resistance material 31. When the voltage applied between the two terminals is less than a first critical voltage, the variable resistance material 31 is in a "high resistance" state, for example, a non-conductive state. When the voltage applied between the two terminals increases and becomes equal to or higher than the first critical voltage, the variable resistance material 31 is in a "low resistance" state, for example, a conductive state. When the voltage applied between the two terminals of the variable resistance material 31 in the low resistance state decreases and becomes equal to or lower than the second critical voltage, the variable resistance material 31 enters the high resistance state. The variable resistance material 31 includes an insulator and dopants introduced into the insulator by ion implantation. The insulator includes (for example) an oxide and a material containing _SiO2 or substantially composed of _SiO2 . The dopant includes (for example) arsenic (As) and germanium (Ge). As used in the specification and the scope of the patent application, the term "substantially" including the term "substantially formed (composed) of..." and similar terms means that the "substantially" formed element is allowed to contain undesirable impurities.

The structure serving as the switching element SE may further include a lower electrode and an upper electrode. In this case, the variable resistance material 31 is disposed on the upper surface of the lower electrode, and the upper electrode is disposed on the upper surface of the variable resistance material 31.

The structure serving as the lower memory cell MCA includes a ferromagnetic layer 32, an insulating layer 33, a ferromagnetic layer 34, and a metal layer 35, that is, a ferromagnetic layer 32A, an insulating layer 33A, a ferromagnetic layer 34A, and a metal layer 35A. The structure serving as the MTJ element MTJA further includes a ferromagnetic layer 41. The ferromagnetic layer 32, the insulating layer 33, the ferromagnetic layer 34, the metal layer 35, and the ferromagnetic layer 41 are stacked in this order on the upper surface of the variable resistance material 31A.

The ferromagnetic layer 32 is a layer of a material exhibiting ferromagnetism. The ferromagnetic layer 32 contains, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer 32 has an axis of simple magnetization along a direction penetrating the interface of the ferromagnetic layer 32, the insulating layer 33, and the ferromagnetic layer 34, for example, an axis of simple magnetization at an angle of 45° or more and 90° or less relative to the interface. For example, the ferromagnetic layer 32 has an axis of simple magnetization along a direction orthogonal to the interface. The magnetization direction of the ferromagnetic layer 32 is changeable by writing data into the memory cell MC, and the ferromagnetic layer 32 may function as a so-called storage layer (SL). Hereinafter, the ferromagnetic layer 32 may be referred to as the storage layer 32. The storage layer 32 may include a plurality of layers.

The insulating layer 33 is a layer of an insulator. The insulating layer 33 contains, for example, magnesium oxide (MgO) or consists essentially of MgO. The insulating layer 33 functions as a so-called tunneling barrier (TB).

The ferromagnetic layer 34 is a layer of a material exhibiting ferromagnetism. The ferromagnetic layer 34 has an axis of simple magnetization along a direction penetrating the ferromagnetic layer 32, the insulating layer 33, and the interface of the ferromagnetic layer 34, for example, an axis of simple magnetization at an angle greater than 45° and less than 90° relative to the interface. For example, the ferromagnetic layer 34 has an axis of simple magnetization along a direction orthogonal to the interface. It is desired that the magnetization direction of the ferromagnetic layer 34 remains unchanged during reading and writing data in the memory cell MC. The ferromagnetic layer 34 may act as a so-called reference layer (RL). Hereinafter, the ferromagnetic layer 34 may be referred to as the reference layer 34. The ferromagnetic layer 34 may include a plurality of layers.

When the magnetization direction of the storage layer 32 is parallel to the magnetization direction of the reference layer 34, the MTJ element MTJ has a certain low resistance value. When the magnetization direction of the storage layer 32 is antiparallel to the magnetization direction of the reference layer 34, the MTJ element MTJ has a resistance value higher than the resistance value when the magnetization direction of the storage layer 32 and the magnetization direction of the reference layer 34 are parallel. Hereinafter, the state in which the magnetization direction of the storage layer 32 is parallel to the magnetization direction of the reference layer 34 may be referred to as a "parallel state" or a "P state". The state in which the magnetization direction of the storage layer 32 is antiparallel to the magnetization direction of the reference layer 34 may be referred to as an "antiparallel state" or an "AP state".

When a switching current Icp having a certain magnitude flows from the storage layer 32 to the reference layer 34, the magnetization direction of the storage layer 32 becomes parallel to the magnetization direction of the reference layer 34. When another switching current Icap having a certain magnitude flows from the reference layer 34 to the storage layer 32, the magnetization direction of the storage layer 32 becomes antiparallel to the magnetization direction of the reference layer 34. The magnitude of the switching current Icap is different from the magnitude of the switching current Icp.

The metal layer 35 is a non-magnetic metal layer that antiferromagnetically couples two ferromagnetic materials sandwiching the metal layer 35. The metal layer 35 contains ruthenium (Ru) or iridium (Ir) or is substantially composed of Ru or Ir. Ru and Ir allow two ferromagnetic materials sandwiching the layers of Ru or Ir to be ferromagnetically or antiferromagnetically coupled based on the thickness of Ru or Ir. The metal layer 35 has a thickness that allows the ferromagnetic layer 32 and the ferromagnetic layer 41 to be antiferromagnetically coupled. Therefore, the ferromagnetic layer 32 and the ferromagnetic layer 41 are antiferromagnetically coupled.

The ferromagnetic layer 41 is a layer of a ferromagnetic material. The ferromagnetic layer 41 contains an element exhibiting ferromagnetism or is substantially composed of an element exhibiting ferromagnetism. The ferromagnetic layer 41 contains cobalt platinum (CoPt), cobalt nickel (CoNi), or cobalt palladium (CoPd) or is substantially composed of CoPt, CoNi, or CoPd. The ferromagnetic layer 41 includes, for example, a structure in which cobalt (Co) layers and platinum (Pt) layers are alternately repeated in one or more, a structure in which cobalt layers and nickel (Ni) layers are alternately repeated in one or more, or a structure in which cobalt layers and palladium (Pd) layers are alternately repeated in one or more.

The ferromagnetic layer 41 has magnetization in a direction opposite to the magnetization direction of the reference layer 34A. The ferromagnetic layer 41 reduces the magnetic field generated by the reference layer 34A and applied to the storage layer 32A, that is, the leakage magnetic field. The ferromagnetic layer 41 functions as a so-called shift cancellation layer (SCL). Hereinafter, the ferromagnetic layer 41 may be referred to as the shift cancellation layer 41.

The structure serving as the upper memory cell MCB includes a structure serving as a switching element SE, that is, a structure serving as a switching element SEB. The structure serving as a switching element SEB includes a variable resistance material 31, that is, a variable resistance material 31B.

The structure serving as the MTJ element MTJB includes a ferromagnetic layer 32, an insulating layer 33, a ferromagnetic layer 34, and a metal layer 35, that is, a ferromagnetic layer 32B, an insulating layer 33B, a ferromagnetic layer 34B, and a metal layer 35B. The structure serving as the MTJ element MTJB further includes a ferromagnetic layer 43. The ferromagnetic layer 32B, the insulating layer 33B, the ferromagnetic layer 34B, the metal layer 35B, and the ferromagnetic layer 43 are stacked in this order on the upper surface of the variable resistance material 31B.

The ferromagnetic layer 43 is a layer of a ferromagnetic material. The ferromagnetic layer 43 contains an element exhibiting ferromagnetism or is substantially composed of an element exhibiting ferromagnetism. The ferromagnetic layer 43 contains cobalt platinum (CoPt), cobalt nickel (CoNi), or cobalt palladium (CoPd), or is substantially composed of CoPt, CoNi, or CoPd. The ferromagnetic layer 43 includes, for example, a structure in which cobalt (Co) layers and platinum (Pt) layers are alternately repeated in one or more, a structure in which cobalt layers and nickel (Ni) layers are alternately repeated in one or more, or a structure in which cobalt layers and palladium (Pd) layers are alternately repeated in one or more.

The ferromagnetic layer 43 has magnetization in a direction opposite to the magnetization direction of the reference layer 34B. The ferromagnetic layer 43 reduces the magnetic field generated by the ferromagnetic layer 34B and applied to the ferromagnetic layer 32B, that is, the leakage magnetic field. The ferromagnetic layer 43 functions as a so-called shift cancellation layer. Hereinafter, the ferromagnetic layer 43 may be referred to as the shift cancellation layer 43.

The ferromagnetic layer 43 has the same coercive force per unit volume as the ferromagnetic layer 41. Therefore, the ferromagnetic layer 43 can be made of substantially the same material as the ferromagnetic layer 41. On the other hand, the ferromagnetic layer 43 has a volume greater than the volume of the ferromagnetic layer 41. That is, the ferromagnetic layer 41 has a volume VL1 and the ferromagnetic layer 43 has a volume VL2, and VL1 < VL2.

Because the ferromagnetic layer 43 has a volume greater than that of the ferromagnetic layer 41, the ferromagnetic layer 41 and the ferromagnetic layer 43 may have the dimensions described below. That is, the ferromagnetic layer 41 and the ferromagnetic layer 43 have the same shape along the xy plane and have different heights (dimensions along the z-axis). FIG. 5 shows such an example. As an example, the lower memory cell MCA and the upper memory cell MCB have substantially circular shapes along the xy plane, and the ferromagnetic layer 41 and the ferromagnetic layer 43 also have substantially circular shapes along the xy plane. The radius of the ferromagnetic layer 41 along the xy plane is substantially the same as the radius of the ferromagnetic layer 43 along the xy plane. On the other hand, the height of the ferromagnetic layer 43 is higher than the height of the ferromagnetic layer 41. A more specific example will be described with reference to FIG.

FIG6 shows the shapes of several memory cells of the memory device of the first embodiment, and shows the shapes of the lower memory cell MCA and the upper memory cell MCB. As shown in FIG6 , at least a portion of the lower memory cell MCA and at least a portion of the upper memory cell MCB are tilted on the side along the z-axis. For example, the lower memory cell MCA and the upper memory cell MCB have a substantially truncated cone shape, and the ferromagnetic layer 41 and the ferromagnetic layer 43 also have a substantially truncated cone shape. The ferromagnetic layer 43 is composed of a first portion 431 and a second portion 432. The first portion 431 is the lower portion of the ferromagnetic layer 43, and the second portion 432 is the upper portion of the ferromagnetic layer 43. The first portion 431 has substantially the same shape as the ferromagnetic layer 41. Therefore, the ferromagnetic layer 43 has a volume larger than that of the ferromagnetic layer 41 by the amount of the second portion 432.

Because the ferromagnetic layer 43 has a volume greater than that of the ferromagnetic layer 41, the ferromagnetic layer 43 has a higher refractive index than that of the ferromagnetic layer 41. Because the ferromagnetic layer 43 has a higher refractive index than that of the ferromagnetic layer 41, the magnitudes of the switching currents Icp and Icap of the lower memory cell MCA are different from the magnitudes of the switching currents Icp and Icap of the upper memory cell MCB.

7A and 7B show the distribution of the switching current of the first embodiment. More specifically, FIG. 7A and 7B show the relationship between the switching current and the number of memory cells MC.

7A and 7B show the upper memory cell MCB and the lower memory cell MCA, respectively. The horizontal axis in FIGS. 7A and 7B shows the magnitude of the current. A positive current is a current in the direction from the reference layer 34 to the storage layer 32. Hereinafter, the direction from the reference layer 34 to the storage layer 32 may be referred to as the AP direction. A negative current is a current in the direction from the storage layer 32 to the reference layer 34. Hereinafter, the direction from the storage layer 32 to the reference layer 34 may be referred to as the P direction.

The switching current Icap flows in the AP direction and may be referred to as the AP direction switching current Icap. The switching current Icp flows in the P direction and may be referred to as the P direction switching current Icp. The AP direction switching current Icap depends on the characteristics of the memory cell MC and therefore has different values for each memory cell MC. Similarly, the P direction switching current Icp depends on the characteristics of the memory cell MC and therefore has different values for each memory cell MC.

If the memory cell MC does not include the shift cancellation layer 41 and does not include the shift cancellation layer 43, the memory cell MC tends to be in the P state and is unlikely to be in the AP state. That is, the magnitude of the P direction switching current Icp is small and the magnitude of the AP direction switching current Icap is large. On the other hand, if the memory cell MC includes the shift cancellation layer 41 or 43, the AP direction switching current Icap is smaller than in the case where there is no shift cancellation layer 41 or 43. At the same time, if the memory cell MC includes the shift cancellation layer 41 or 43, the P direction switching current Icp is larger than in the case where there is no shift cancellation layer 41 or 43. That is, the shift cancellation layers 41 and 43 reduce the AP direction switching current Icap and increase the P direction switching current Icp. This function is higher as the magnetic correction force of the displacement cancellation layer 41 or 43 is higher.

As shown in FIG7B , the AP direction switching current Icap of the lower memory unit MCA is distributed to cover a range of certain values. Similarly, the P direction switching current Icp of the lower memory unit MCA is distributed to cover a range of certain values. Hereinafter, the P direction switching current Icp of the lower memory unit MCA may be referred to as the lower P direction switching current Icpd. The AP direction switching current Icap of the lower memory unit MCA may be referred to as the lower AP direction switching current Icapd.

As described with reference to FIG5, the shift canceling layer 43 of the upper memory cell MCB has a larger corrective magnetic force than the shift canceling layer 41 of the lower memory cell MCA. Therefore, as shown in FIG7A, the magnitude of the P direction switching current Icp of the upper memory cell MCB is greater than the magnitude of the P direction switching current Icp of the lower memory cell MCA. Furthermore, the magnitude of the AP direction switching current Icap of the upper memory cell MCB is less than the magnitude of the AP direction switching current Icap of the lower memory cell MCA.

Hereinafter, the P direction switching current Icp of the upper memory cell MCB may be referred to as the upper P direction switching current Icpu. The AP direction switching current Icap of the upper memory cell MCB may be referred to as the upper AP direction switching current Icapu.

FIG8 is a diagram showing an example of voltage and current characteristics of the memory cell MC of the first embodiment. The horizontal axis of the diagram shows the magnitude of the terminal voltage of the memory cell MC. The vertical axis of the diagram shows the magnitude of the current flowing through the memory cell MC on a logarithmic scale. In FIG8 , virtual characteristics that do not actually appear are shown by dotted lines. FIG8 shows a case where the memory cell MC is in a low resistance state and a case where the memory cell MC is in a high resistance state. The following description applies to both the low resistance state and the high resistance state of the memory cell MC.

When the voltage is increased from 0, the current continues to increase until the magnitude of the voltage reaches the threshold voltage Vth. Until the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is off, that is, non-conductive.

When the voltage is further increased and reaches the threshold voltage Vth, that is, when point A is reached, the relationship between the voltage and the current shows a discontinuous change and exhibits characteristics at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly greater than the magnitude of the current at point A. This sudden change in current is based on the fact that the switching element SE of the memory cell MC is turned on. The magnitude of the current at points B1 and B2 depends on the resistance value state of the MTJ element MTJ of the memory cell MC.

When the voltage is reduced from a state in which the switching element SE is on (eg, a state in which the voltage and the current show the relationship shown at point B1 or point B2), the current continues to decrease.

When the voltage is further reduced and reaches a certain value, the relationship between the voltage and the current shows a change of interruption. The voltage at which the relationship between the voltage and the current begins to show interruption depends on the terminal voltage of the MTJ element MTJ of the memory cell MC, that is, whether the MTJ element MTJ is in a high resistance state or a low resistance state. When the MTJ element MTJ is in a low resistance state, the relationship between the voltage and the current shows an interruption from point C1. When the MTJ element MTJ is in a high resistance state, the relationship between the voltage and the current shows an interruption from point C2. The relationship between voltage and current will show the characteristics shown at points D1 and D2, respectively, when points C1 and C2 are reached. The magnitudes of the currents at points D1 and D2 are significantly smaller than the magnitudes of the currents at points C1 and C2, respectively. The sudden change in current is based on the fact that the switching element SE of the memory cell MC is turned off.

The terminal voltage at point D1 of the memory cell MC including the MTJ element MTJ in the low resistance state may be referred to as a low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC including the MTJ element MTJ in the high resistance state may be referred to as a high holding voltage VhdH. 1.1.6. Reading out circuit configuration

FIG9 shows the components of the readout circuit of the first embodiment and the connections between the components. As shown in FIG9 , the readout circuit RC includes a read control circuit ROC, driver circuits RDH, RDUB, RDP, and RDUW, and a sense amplifier circuit SAC. FIG9 shows the components of only one global bit line GBL and one global word line GWL. The driver circuits RDH and RDUB are also provided to other global bit lines GBL. In addition, the driver circuits RDP and RDUW and the sense amplifier circuit SAC are also provided to other global word lines GWL.

The driver circuit RDH is configured so that a power supply voltage Vhh can be applied to the global bit line GBL. The power supply voltage Vhh is an internal power supply voltage of the memory device 1 and is higher than the ground voltage (or common voltage) Vss. The driver circuit RDH may have any configuration as long as the power supply voltage Vhh can be applied to the global bit line GBL. For example, the driver circuit RDH includes a switching circuit SW1. The switching circuit SW1 is connected to the global bit line GBL at one end and is connected to a node in the memory device 1 to which the power supply voltage Vhh is applied at the other end. The switch circuit SW1 is turned on or off based on the control signal S1, and transfers the power supply voltage Vhh to the global bit line GBL. The switch circuit SW1 receives the control signal S1 from, for example, the read control circuit ROC. The switch circuit SW1 is, for example, a MOSFET.

The driver circuit RDUB is configured so that a non-selection voltage Vusel can be applied to the global bit line GBL. The non-selection voltage Vusel is, for example, higher than the ground voltage Vss and lower than the power supply voltage Vhh. The ground voltage Vss is, for example, 0V. The driver circuit RDUB may have any configuration as long as the non-selection voltage Vusel can be applied to the global bit line GBL. For example, the driver circuit RDUB includes a switching circuit SW2. The switching circuit SW2 is connected to the global bit line GBL at one end and is connected to a node to which the non-selection voltage Vusel is applied in the memory device 1 at the other end. The switch circuit SW2 is turned on or off based on the control signal S2, and transfers the non-selection voltage Vusel to the global bit line GBL. The switch circuit SW2 receives the control signal S2 from, for example, the read control circuit ROC. The switch circuit SW2 is, for example, a MOSFET.

The driver circuit RDP is configured so that a precharge voltage Vprch can be applied to the global bit line GBL. The precharge voltage Vprch is higher than the ground voltage Vss and lower than the non-selection voltage Vusel. The driver circuit RDP may have any configuration as long as the precharge voltage Vprch can be applied to the global word line GWL. For example, the driver circuit RDP includes a switching circuit SW3. The switching circuit SW3 is connected to the global word line GWL at one end and to a node in the memory device 1 to which the precharge voltage Vprch is applied at the other end. The switching circuit SW3 is turned on or off based on the control signal S3 and transfers the precharge voltage Vprch to the global word line GWL. The switching circuit SW3 receives a control signal S3 from, for example, a read control circuit ROC. The switching circuit SW3 is, for example, a MOSFET.

The driver circuit RDUW is configured so that the non-selection voltage Vusel can be applied to the global word line GWL. The driver circuit RDUW can have any configuration as long as the non-selection voltage Vusel can be applied to the global word line GWL. For example, the driver circuit RDUW includes a switching circuit SW4. The switching circuit SW4 is connected to the global word line GWL at one end and is connected to a node in the memory device 1 to which the non-selection voltage Vusel is applied at the other end. The switching circuit SW4 is turned on or off based on the control signal S4 and transfers the non-selection voltage Vusel to the global word line GWL. The switching circuit SW4 receives the control signal S4 from, for example, the read control circuit ROC. The switching circuit SW4 is, for example, a MOSFET.

The sense amplifier circuit SAC includes an operational amplifier OP and a resistor R1. The operational amplifier OP is connected to the global word line GWL at a non-inverting input terminal. The inverting input terminal of the operational amplifier OP is grounded via the resistor R1, that is, connected to a node having a ground voltage Vss. The resistor R1 has a value so that a voltage having a value between a low holding voltage VhdL and a high holding voltage VhdH is applied to the inverting input terminal of the operational amplifier OP. The output OUT of the operational amplifier OP is 1-bit data, which is determined to be stored in a read target memory cell MC in the memory cell array MA to which the operational amplifier OP is connected.

The read control circuit ROC operates based on a control signal, which is generated by the control circuit 13 and the decoding circuit 14 based on the control signal CNT, the command CMD, and the address signal ADD. 1.1.7. Write circuit configuration

FIG10 shows the components of the write circuit of the first embodiment and the connections between the components. As shown in FIG10 , the write circuit WC includes a write control circuit WOC, driver circuits WDPU, WDAPD, WDPD, and WDAPU, and slot circuits WSB and WSW. FIG10 shows the components of only one global bit line GBL and one global word line GWL. The driver circuits WDPU and WDAPD, and the slot circuit WSB are also provided to other global bit lines GBL. In addition, the driver circuits WDPD and WDAPU, and the slot circuit WSW are also provided to other global word lines GWL.

The driver circuit WDPU is configured so that the upper P write voltage Vwpu can be applied to the global bit line GBL. The upper P write voltage Vwpu has a magnitude that allows the upper P write current Iwpu to flow through the write target upper memory cell MCB when it is applied to the write target upper memory cell MCB through wiring. The magnitude of the upper P write current Iwpu will be described later. The driver circuit WDPU may have any configuration as long as the upper P write voltage Vwpu can be applied to the global bit line GBL. For example, the driver circuit WDPU includes a switching circuit SW11. The switching circuit SW11 is connected to the global bit line GBL at one end and is connected to a node in the memory device 1 to which the upper P write voltage Vwpu is applied at the other end. The switch circuit SW11 is turned on or off based on the control signal S11, and transfers the upper P write voltage Vwpu to the global bit line GBL. The switch circuit SW11 receives the control signal S11 from, for example, the write control circuit WOC. The switch circuit SW11 is, for example, a MOSFET.

The driver circuit WDAPD is configured so that the lower AP write voltage Vwapd can be applied to the global bit line GBL. The lower AP write voltage Vwapd has a magnitude that allows the lower AP write current Iwapd to flow through the write target lower memory cell MCA when it is applied to the write target lower memory cell MCA via wiring. The magnitude of the lower AP write current Iwapd will be described later. The driver circuit WDAPD may have any configuration as long as the lower AP write voltage Vwapd can be applied to the global bit line GBL. For example, the driver circuit WDAPD includes a switch circuit SW12. The switch circuit SW12 is connected to the global bit line GBL at one end and to a node to which the lower AP write voltage Vwapd is applied in the memory device 1 at the other end. The switch circuit SW12 is turned on or off based on the control signal S12 and transfers the lower AP write voltage Vwapd to the global bit line GBL. The switch circuit SW12 receives the control signal S12 from, for example, the write control circuit WOC. The switch circuit SW12 is, for example, a MOSFET.

The slot circuit WSB is configured so that the ground voltage Vss can be applied to the global bit line GBL. The slot circuit WSB may have any configuration as long as the ground voltage Vss can be applied to the global bit line GBL. For example, the slot circuit WSB includes a switching circuit SW13. The switching circuit SW13 is connected to the global bit line GBL at one end and is connected to a node in the memory device 1 to which the ground voltage Vss is applied at the other end. The switching circuit SW13 is turned on or off based on the control signal S13 and transfers the ground voltage Vss to the global bit line GBL. The switching circuit SW13 receives the control signal S13 from, for example, the write control circuit WOC. The switching circuit SW13 is, for example, a MOSFET.

The driver circuit WDPD is configured so that the lower P write voltage Vwpd can be applied to the global word line GWL. The lower P write voltage Vwpd has a magnitude that allows the lower P write current Iwpd to flow through the write target lower memory cell MCA when it is applied to the write target lower memory cell MCA via wiring. The magnitude of the lower P write current Iwpd will be described later. The driver circuit WDPD may have any configuration as long as the lower P write voltage Vwpd can be applied to the global word line GWL. For example, the driver circuit WDPD includes a switch circuit SW14. The switch circuit SW14 is connected to the global word line GWL at one end and to a node to which the lower P write voltage Vwpd is applied in the memory device 1 at the other end. The switch circuit SW14 is turned on or off based on the control signal S14 and transfers the lower P write voltage Vwpd to the global word line GWL. The switch circuit SW14 receives the control signal S14 from, for example, the write control circuit WOC. The switch circuit SW14 is, for example, a MOSFET.

The driver circuit WDAPU is configured so that the upper AP write voltage Vwapu can be applied to the global word line GWL. The upper AP write voltage Vwapu has a value that allows the upper AP write current Iwapu to flow through the write target upper memory cell MCB when it is applied to the write target upper memory cell MCB through wiring. The value of the upper AP write current Iwapu will be described later. The driver circuit WDAPU may have any configuration as long as the upper AP write voltage Vwapu can be applied to the global word line GWL. For example, the driver circuit WDAPU includes a switching circuit SW15. The switching circuit SW15 is connected to the global word line GWL at one end and to a node to which the upper AP write voltage Vwapu is applied in the memory device 1 at the other end. The switching circuit SW15 is turned on or off based on the control signal S15 and transfers the upper AP write voltage Vwapu to the global word line GWL. The switching circuit SW15 receives the control signal S15 from, for example, the write control circuit WOC. The switching circuit SW15 is, for example, a MOSFET.

The slot circuit WSW is configured so that the ground voltage Vss can be applied to the global word line GWL. The slot circuit WSW can have any configuration as long as the ground voltage Vss can be applied to the global word line GWL. For example, the slot circuit WSW includes a switching circuit SW16. The switching circuit SW16 is connected to the global word line GWL at one end and is connected to a node in the memory device 1 to which the ground voltage Vss is applied at the other end. The switching circuit SW16 is turned on or off based on the control signal S16 and transfers the ground voltage Vss to the global word line GWL. The switching circuit SW16 receives the control signal S16 from, for example, the write control circuit WOC. The switching circuit SW16 is, for example, a MOSFET. 1.2. Operation 1.2.1. Data writing

11 to 14 show components related to data writing during data writing in the memory device 1 of the first embodiment and connections between the components. FIG. 11 shows the state when the MTJ element MTJA of the lower memory cell MCA is in the P state. FIG. 12 shows the state when the MTJ element MTJA of the lower memory cell MCA is in the AP state. FIG. 13 shows the state when the MTJ element MTJB of the upper memory cell MCB is in the P state. FIG. 14 shows the state when the MTJ element MTJB of the upper memory cell MCB is in the AP state. FIG. 11 to 14 show only the storage layer 32 and the reference layer 34 of the write target memory cell MC.

As shown in FIG. 11 , in order to put the MTJ element MTJA of a certain write target lower memory cell MCA into the P state, the write target lower memory cell MCA is connected to the global bit line GBL via the conductor 22 (local bit line LBL) and is connected to the global word line GWL via the conductor 21 (local word line LWLA). Furthermore, the lower P write voltage Vwpd is applied to the global word line GWL by the driver circuit WDPD, and the ground voltage Vss is applied to the global bit line GBL via the slot circuit WSB. As a result, the lower P write current Iwpd flows from the storage layer 32A to the reference layer 34A in the write target lower memory cell MCA. As a result, the MTJ element MTJA of the target memory cell MCA is in the P state.

As shown in FIG. 12 , in order to place the MTJ element MTJA of a certain write-target lower memory cell MCA into the AP state, the write-target lower memory cell MCA is connected to the global bit line GBL via the conductor 22 (local bit line LBL) and is connected to the global word line GWL via the conductor 21 (local word line LWLA). Furthermore, the lower AP write voltage Vwapd is applied to the global bit line GBL by the driver circuit WDAPD, and the ground voltage Vss is applied to the global word line GWL via the slot circuit WSW. As a result, the lower AP write current Iwapd flows from the reference layer 34A to the storage layer 32A in the write-target lower memory cell MCA. As a result, the MTJ element MTJA of the target memory cell MCA is in the AP state.

As shown in FIG. 13 , in order to put the MTJ element MTJB of a certain write-target memory cell MCB into the P state, the write-target memory cell MCB is connected to the global bit line GBL via the conductor 22 (local bit line LBL) and is connected to the global word line GWL via the conductor 23 (local word line LWLB). Furthermore, the upper P write voltage Vwpu is applied to the global bit line GBL by the driver circuit WDPU, and the ground voltage Vss is applied to the global word line GWL via the slot circuit WSW. As a result, the upper P write current Iwpu flows from the storage layer 32B to the reference layer 34B in the write-target memory cell MCB. As a result, the MTJ element MTJB of the memory cell MCB on the write target is in the P state.

As shown in FIG. 14 , in order to put the MTJ element MTJB of a write-target memory cell MCB into the AP state, the write-target memory cell MCB is connected to the global bit line GBL via the conductor 22 (local bit line LBL) and is connected to the global word line GWL via the conductor 23 (local word line LWLB). Furthermore, the upper AP write voltage Vwapu is applied to the global word line GWL by the driver circuit WDAPU, and the ground voltage Vss is applied to the global bit line GBL via the slot circuit WSB. As a result, the upper AP write current Iwapu flows from the reference layer 34B to the storage layer 32B in the write-target memory cell MCB. As a result, the MTJ element MTJB of the memory cell MCB on the target is in the AP state. 1.2.2. Data reading

15 and 16 show components related to data reading and connections between the components during data reading in the memory device 1 of the first embodiment. Fig. 15 shows the state during data reading from the lower memory unit MCA. Fig. 16 shows the state during data reading from the upper memory unit MCB.

At the same time, at the start of data reading, the global bit line GBL is applied with a non-selection voltage Vusel by a driver circuit RDUB (not shown), and the global word line GWL is applied with a non-selection voltage Vusel by a driver circuit RDUW (not shown). Therefore, there is no voltage difference between the global word line GWL and the global bit line GBL.

As shown in FIG. 15 , when data reading starts from the read target memory cell MCA, the read target memory cell MCA is connected to the global bit line GBL via the local bit line LBL (conductor 22) and is connected to the global word line GWL via the local word line LWLA (conductor 21).

Furthermore, the precharge voltage Vprch is applied to the global word line GWL through the driver circuit RDP. As a result, the global word line GWL is charged with the precharge voltage Vprch. Thereafter, the global word line GWL is disconnected from the driver circuit RDP, and the global word line GWL is placed in an electrically floating state. In this state, the power supply voltage Vhh is applied to the global bit line GBL through the driver circuit RDH. As a result, a voltage having a value of Vhh - Vprch is applied to both ends of the memory cell MCA under the read target. This voltage has a value that turns on the switching element SEA of the memory cell MCA under the read target. Therefore, the read current Irap flows from the reference layer 34A to the storage layer 32A, that is, in the AP direction. The read current Irap charges the global word line GWL and raises the voltage of the global word line GWL. As the voltage of the global word line GWL increases, the voltage difference between the two ends of the memory cell MCA under the read target decreases.

When the voltage difference between the two ends of the memory cell MCA under the read target drops to a certain value, the switching element SEA of the memory cell MCA under the read target is turned off. As a result, the voltage of the global word line GWL when the switching element SEA of the memory cell MCA under the read target is turned off is stored in the node of the non-inverting input terminal of the operational amplifier OP. The stored voltage is one of the low holding voltage VhdL and the high holding voltage VhdH based on the resistance value state of the memory cell MCA under the read target. The output OUT reflecting the data stored in the memory cell MCA under the read target is output based on the stored voltage and the voltage of the inverting input terminal of the operational amplifier OP.

As shown in FIG. 16 , when data reading starts from a memory cell MCB on a read target, the memory cell MCB on the read target is connected to the global bit line GBL via the local bit line LBL (conductor 22) and to the global word line GWL via the local word line LWLB (conductor 23).

Furthermore, the precharge voltage Vprch is applied to the global word line GWL through the driver circuit RDP. As a result, the global word line GWL is charged with the precharge voltage Vprch. Thereafter, the global word line GWL is disconnected from the driver circuit RDP, and the global word line GWL is placed in an electrically floating state. In this state, the power supply voltage Vhh is applied to the global bit line GBL through the driver circuit RDH. As a result, a voltage having a magnitude of Vhh - Vprch is applied to both ends of the memory cell MCB on the read target. Due to this voltage, the read current Irp flows from the storage layer 32B to the reference layer 34B, that is, in the P direction. The read current Irp charges the global word line GWL and increases the voltage of the global word line GWL. As the voltage of the global word line GWL increases, the voltage difference between both ends of the memory cell MCB on the read target decreases.

When the voltage difference between both ends of the memory cell MCB on the read target drops to a certain value, the switching element SEB of the memory cell MCB on the read target is turned off. As a result, one of the low holding voltage VhdL and the high holding voltage VhdH based on the resistance value state of the memory cell MCB on the read target is stored in the node of the non-inverting input terminal of the operational amplifier OP. The output OUT reflecting the data stored in the memory cell MCB on the read target is output based on the stored voltage and the voltage of the non-inverting input terminal of the operational amplifier OP.

1.2.3. Current value

17A and 17B show the magnitude of the current flowing during various operations in the memory device 1 of the first embodiment. Specifically, FIG. 17A and 17B show the write current and the read current for each of the upper memory cell MCB and the lower memory cell MCA. FIG. 17A shows the upper memory cell MCB and FIG. 17B shows the lower memory cell MCA. FIG. 17A and 17B also show the upper P direction switching current Icpu, the upper AP direction switching current Icapu, the lower P direction switching current Icpd, and the lower AP direction switching current Icapd shown in FIG. 7A and 7B.

In order to change the resistance value state of the memory cell MC, a write current having a magnitude greater than the magnitude of the switching current of the memory cell MC must flow through this memory cell MC. The write current actually flowing through the memory cell MC depends on the characteristics of the write circuit and/or the characteristics of the memory cell MC. Therefore, the write current actually flowing through the memory cell MC is different for each memory cell MC and is therefore distributed to cover a certain range. Similarly, the read current flowing through the memory cell MC depends on the characteristics of the read circuit and/or the characteristics of the memory cell MC. Therefore, the read current actually flowing through the memory cell MC is different for each memory cell MC and is therefore distributed to cover a certain range.

As shown in FIG. 17B , the magnitude of the lower AP write current Iwapd is greater than the magnitude of the lower AP direction switching current Icapd. That is, the minimum magnitude lower AP write current Iwapd is greater than the maximum magnitude lower AP direction switching current Icapd. The magnitude of the lower P write current Iwpd is greater than the magnitude of the lower P direction switching current Icpd. That is, the lower P write current Iwpd having the minimum magnitude is greater than the lower P direction switching current Icpd having the maximum magnitude.

As shown in FIG. 17A , the magnitude of the upper AP write current Iwapu is greater than the magnitude of the upper AP direction switching current Icapu. That is, the upper AP write current Iwapu having the minimum magnitude is greater than the upper AP direction switching current Icapu having the maximum magnitude. The magnitude of the upper P write current Iwpu is greater than the magnitude of the upper P direction switching current Icpu. That is, the upper P write current Iwpu having the minimum magnitude is greater than the upper P direction switching current Icpu having the maximum magnitude.

As shown in FIGS. 17A and 17B and described with reference to FIGS. 7A and 7B , the magnitude of the upper AP direction switching current Icapu is smaller than the magnitude of the lower AP direction switching current Icapd. Because the magnitude of the upper AP direction switching current Icapu is smaller than the magnitude of the lower AP direction switching current Icapd, the magnitude of the upper AP write current Iwapu may be smaller than the magnitude of the lower AP write current Iwapd. Therefore, the magnitude of the upper AP write current Iwapu is smaller than the magnitude of the lower AP write current Iwapd. That is, the distribution of the upper AP write current Iwapu is set closer to the origin on the horizontal axis than the distribution of the lower AP write current Iwapd. For example, the maximum value of the upper AP write current Iwapu is smaller than the maximum value of the lower AP write current Iwapd, and/or the minimum value of the upper AP write current Iwapu is smaller than the minimum value of the lower AP write current Iwapd.

As also shown in FIGS. 17A and 17B and described with reference to FIGS. 7A and 7B , the magnitude of the upper P direction switching current Icpu is greater than the magnitude of the lower P direction switching current Icpd. Because the magnitude of the upper P direction switching current Icpu is greater than the magnitude of the lower P direction switching current Icpd, the magnitude of the upper P write current Iwpu is greater than the magnitude of the lower P write current Iwpd. That is, the distribution of the upper P write current Iwpu is set farther from the origin on the horizontal axis than the distribution of the lower P write current Iwpd. For example, the maximum magnitude of the upper P write current Iwpu is greater than the maximum magnitude of the lower P write current Iwpd, and/or the minimum magnitude of the upper P write current Iwpu is greater than the minimum magnitude of the lower P write current Iwpd.

The current flowing through the memory cell MC may change the resistance value state of the memory cell MC, that is, it may cause a read disturbance in the memory cell MC. However, it is necessary that the read current does not change the resistance value state of the memory cell MC even if the read current flows through the memory cell MC. For this purpose, if a read current flows through a memory cell MC in a first direction (AP direction or P direction), the magnitude of this read current must be smaller than the switching current in the first direction of this memory cell MC. Based on this, the read current Irap is smaller than the lower AP direction switching current Icapd. That is, the distribution of the read current Irap is set closer to the origin on the horizontal axis than the distribution of the lower AP direction switching current Icapd. For example, the maximum value of the read current Irap is smaller than the minimum value of the lower AP direction switching current Icapd.

At the same time, the read current Irp is smaller than the upper P-direction switching current Icpu. That is, the distribution of the read current Irp is set closer to the origin on the horizontal axis than the distribution of the upper P-direction switching current Icpu. For example, the maximum value of the read current Irp is smaller than the minimum value of the upper P-direction switching current Icpu. 1.3. Advantages (Effects)

According to the first embodiment, as described below, a memory device is provided in which read disturbance is reduced and variation in data read margin for each memory cell MC is reduced.

The outline of the memory device 100 is described for comparison and reference. The memory device 100 includes a memory cell 101A and a memory cell 101B to replace the lower memory cell MCA and the upper memory cell MCB in the memory device 1 of the first embodiment, respectively. The memory cell 101A and the memory cell 101B have the same structure as the memory cell MCA.

Generally speaking, the switching current used to put the MTJ element in the AP state is larger than the switching current used to put the MTJ element in the P state. Therefore, in order to reduce the read disturbance, it is conceivable to pass the read current in the AP direction.

Applying a voltage to a wiring by a driver circuit can be performed by various methods. As a first method, the voltage to be applied by the driver circuit is generated as described in reference figures 9 and 10, and the generated voltage is transferred to the wiring via the switching circuit SW. As a second method, a reference voltage different from the voltage to be transferred (for example, an internal power supply or a ground voltage) is connected to the wiring via a MOSFET. Then, by adjusting the voltage of the gate of the MOSFET, a voltage having a value to be transferred (which is generated by raising or lowering the reference voltage) is applied to the wiring. When the second method is adopted in the memory device 100, the following phenomenon may occur.

18 and 19 are similar to FIGS. 15 and 16 and show components related to data reading and connections between the components during data reading in the memory device 100. FIG. 18 shows the state during data reading from the lower memory unit 101A. FIG. 19 shows the state during data reading from the upper memory unit 101B.

The case of reading data from the lower memory cell 101A is the same as that of the first embodiment (FIG. 15). That is, the global word line GWL is set to the precharge voltage Vprch, then placed in an electrically floating state, and then the power supply voltage Vhh is applied to the global bit line GBL. As a result, as shown in FIG. 18, the read current Ir flows from the reference layer 34 through the memory cell 101A toward the storage layer 32, that is, in the AP direction. The slot circuit 103 includes a p-type MOSFET 104 connected between the global word line GWL and a node having a ground voltage Vss.

At the same time, a read current in the AP direction can flow through the memory cell 101B by the following method. As shown in FIG. 19 , the sense amplifier circuit SAC is connected to the global word line GWL, as in the case of reading data from the lower memory cell 101A and the lower memory cell MCA in the first embodiment. The global word line GWL is charged with a pre-charge voltage Vprch2 by the driver circuit 111. The pre-charge voltage Vprch2 is higher than the non-selection voltage Vusel. After the charging is completed, the global word line GWL is disconnected from the driver circuit 111 and is placed in an electrically floating state. Next, the ground voltage Vss is applied to the global bit line GBL by the slot circuit 112. As a result, the read current Ir flows from the reference layer 34 through the upper memory cell MCB toward the storage layer 32, that is, in the AP direction.

The direction of the read current Ir when the global word line GWL is used as a reference is different in the case of reading data from the lower memory cell 101A and in the case of reading data from the upper memory cell 101B. Due to this phenomenon, the combination of wiring and transistors (including the path through which the read current Ir flows) is different in the cases of Figures 18 and 19. One of the differences is the type of transistor connected to the global word line GWL. That is, in the case of Figure 18, the p-type MOSFET 104 is connected to the global word line GWL; and in the case of Figure 19, the n-type MOSFET 115 is connected to the global word line GWL. For the operational amplifier OP connected to the global word line GWL, this effect is the difference in the characteristics of the components connected to the operational amplifier OP. The difference in the characteristics of the operational amplifier OP causes the operation of the operational amplifier OP in the cases of FIGS. 18 and 19 to be different, that is, depending on the location of the memory cell 101. This causes a change in the characteristics of the data read in the memory device 100.

As a countermeasure to this phenomenon, it is conceivable to allow the read current Ir to pass to the upper memory unit 101B in the P direction. In this case, the distribution of each current in the upper memory unit 101B is the same as the distribution of the lower memory unit MCA shown in Figures 17A and 17B. When the read current in the P direction flows to the upper memory unit 101B having such a distribution, the distribution of the P direction switching current Icpu of the upper memory unit 101B (the same as the distribution of the P direction switching current Icp of the lower memory unit 101A) and the P direction read current distribution (the same as the P direction read current Irp of the upper memory unit 101B) partially overlap. This can cause a read disturbance due to the read current Ir in the P direction.

Alternatively, the following measures may be considered to counteract the variation in the characteristics of data reading in the memory device 100. That is, the order of materials (layers) arranged from the conductor 22 (local bit line LBL) toward the conductor 21 (local word line LWLA) is the same as the order of materials (layers) arranged from the conductor 22 toward the conductor 23 (local word line LWLB). That is, the order in which the layers of the memory cell 101A are arranged and the order in which the layers of the memory cell 101B are arranged are line-symmetrical with respect to the conductor 22. In this way, the read current in the AP direction flows from the local bit line LBL to the local word line LWL in either of the memory cells 101A and 101B. However, changing the order in which the layers of memory cell 101 are arranged may change the characteristics of memory cells 101A and 101B. That is, memory cell 101 has a truncated cone shape (due to limitations of the manufacturing process, etc.), and the layers located above the truncated cone have a smaller volume than the layers located below the truncated cone, even with the same thickness. This causes the characteristics of the storage layer, reference layer, and/or switching element to be different in memory cells 101A and 101B. This significantly changes the characteristics of memory cell 101.

According to the first embodiment, the lower memory cell MCA and the upper memory cell MCB include substantially the same plurality of layers arranged in the same order along the z-axis. That is, in both the lower memory cell MCA and the upper memory cell MCB, the switching element SE, the storage layer 32, the reference layer 34, and the shift cancellation layer 41 or 43 are arranged in this order in the direction in which the z-axis coordinate increases (+z direction). In addition, the shift cancellation layer 43 of the upper memory cell MCB has a larger volume than the volume of the shift cancellation layer 41 of the lower memory cell MCA. Therefore, the magnitude of the upper P-direction switching current Icpu is greater than the magnitude of the upper P-direction switching current (that is, the magnitude of the lower P-direction switching current Icpd) when the shift cancel layer 43 has the same volume as the shift cancel layer 41. By utilizing this fact, it is possible to allow the read current to pass to the upper memory cell MCB in the P direction for reading data from the upper memory cell MCB. Because the magnitude of the upper P-direction switching current Icpu is greater than the magnitude of the upper P-direction switching current (when the shift cancel layer 43 has the same volume as the shift cancel layer 41), the MTJ element MTJB of the upper memory cell MCB is prevented from entering the P state even if the read current flows through the upper memory cell MCB in the P direction.

Because the read current Ir can flow through the upper memory cell MCB in the P direction (as clearly seen from FIGS. 15 and 16 ), the direction of the read current when the global word line GWL is used as a reference is the same in the case of reading data from the lower memory cell MCA and in the case of reading data from the upper memory cell MCB. That is, the read current flows toward the global word line GWL. This brings about the advantages described below.

20 and 21 show components related to data reading during data reading in the memory device 1 of the first embodiment and connections therebetween, and show examples of components and connections of FIGS. 15 and 16 , respectively. As shown in FIGS. 20 and 21 , the driver circuit RDP includes a p-type MOSFET TP1. The transistor TP1 is connected to the global word line GWL at one end and to a node having a ground voltage Vss at the other end. At the gate, the transistor TP1 receives a control signal from a portion of the driver circuit RDP other than the read circuit RC.

As can be seen from FIGS. 20 and 21 , the combination of wiring and transistors (including the path through which the read current Ir flows) is the same in the case of reading data from the lower memory cell MCA and in the case of reading data from the upper memory cell MCB. This means that for the operational amplifier OP connected to the global word line GWL, the difference in characteristics of the components connected to the operational amplifier OP is reduced. This reduction in difference leads to the fact that the change in operation due to the operational amplifier OP is reduced in the case of reading data from the lower memory cell MCA and in the case of reading data from the upper memory cell MCB. Therefore, it is possible to provide the memory device 1 in which variations in the characteristics of data reading based on the position of the memory cell MC are reduced.

Because the upper AP direction switching current Icapu is small (as described in reference to FIGS. 7A and 7B ), the distribution of the upper AP direction switching current Icapu has a very small interval or partially overlaps with the AP direction reading current Irap, as can be seen from FIGS. 17A and 17B . However, the AP direction reading current does not flow in the upper memory unit MCB. Therefore, the reading disturbance in the upper memory unit MCB does not occur. 1.4. Modification

The data determination by the sense amplifier circuit SAC is not limited to the form described above. For example, the global word line GWL is connected to the non-inverting input terminal of the operational amplifier via a first switch circuit. The global word line GWL is also connected to the input of the voltage adjustment circuit via a second switch circuit. The voltage adjustment circuit adjusts the input voltage and supplies the adjusted voltage to the inverting input terminal of the operational amplifier OP. The adjustment is performed so that the adjusted voltage has a value between, for example, a low holding voltage VhdL and a high holding voltage VhdH.

At the moment of data reading, the same data reading as described with reference to FIGS. 15 and 16 is performed, wherein the first switching circuit is turned on and the second switching circuit is turned off. As a result, one of a low holding voltage VhdL and a high holding voltage VhdH based on the resistance value state of the memory cell MCA under the read target appears on the global word line GWL. Then, when the first switching circuit is turned off, the voltage of the global word line GWL is held at the node of the non-inverting input terminal of the operational amplifier OP. The held voltage is referred to as a first sample voltage.

Next, predetermined reference data is written to the read target memory cell MC. The reference data may be "1" data or "0" data, for example, "0" data. After writing, the same data reading as described in reference figures 15 and 16 is performed, wherein the first switching circuit is closed and the second switching circuit is opened. As a result, a low holding voltage VhdL appears on the global word line GWL. Thereafter, when the second switching circuit is closed, the voltage adjusted for the voltage of the global word line GWL is held in the node of the inverting input terminal of the operational amplifier OP. The held voltage is referred to as the second sample voltage.

The operational amplifier OP outputs a value based on the magnitude of the first sample voltage and the second sample voltage. If the first sample voltage is less than the second sample voltage, the operational amplifier OP outputs an "L" level voltage. This is regarded as if the data read target memory cell MC holds the same "0" data as the reference data. Meanwhile, when the first sample voltage is greater than the second sample voltage, the operational amplifier OP outputs an "H" level voltage. This is regarded as if the data read target memory cell MC holds the "1" data as different from the reference data.

Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel embodiments described herein may be implemented in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.

1: memory device 11: core circuit 12: input and output circuit 13: control circuit 14: decoding circuit 15: page buffer 16: voltage generating circuit 21,22,23: conductor 31,31A,31B: variable resistance material 32,32A,32B: ferromagnetic layer 33,33A,33B: insulating layer 34,34A,34B: ferromagnetic layer 35,35A,35B: metal layer 41: ferromagnetic layer 43: ferromagnetic layer 100: memory device 101A: memory unit 101B: memory cell 111: driver circuit 112: tank circuit 115: n-type MOSFET 431: first part 432: second part GBL: global bit line GWL: global word line LBL: local bit line LWL: local word line MA: memory cell array MC: memory cell MTJ: MTJ element RC: read circuit SE: switch element WC: write circuit

[FIG. 1] is a block diagram of a memory device of the first embodiment;

[Figure 2] is a block diagram of the core circuit of the first embodiment.

[FIG. 3] is a circuit diagram of the memory cell array of the first embodiment.

[FIG. 4] is a perspective view of a portion of the memory cell array of the first embodiment.

[FIG. 5] is a cross-sectional view showing an example of the structure of the memory cell of the first embodiment.

[FIG. 6] is a diagram showing the shapes of some memory cells of the memory device of the first embodiment.

[Figures 7A and 7B] are diagrams showing the distribution of switching current in the memory device of the first embodiment.

[FIG. 8] is a diagram showing an example of voltage and current characteristics of a memory cell of the first embodiment.

[FIG. 9] is a diagram showing components of a readout circuit in a memory device of the first embodiment and connections between the components.

[FIG. 10] is a diagram showing components of a write circuit of the first embodiment and connections between the components.

[Figures 11-14] are diagrams showing components related to data writing and connections between the components during data writing in the memory device of the first embodiment.

[Figures 15-16] are diagrams showing components related to data reading and connections between the components during data reading in the memory device of the first embodiment.

[Figures 17A and 17B] are graphs showing the magnitude of current flowing during various operations in the memory device of the first embodiment.

[FIGS. 18-19] are diagrams showing components related to data reading and connections between the components during data reading in a memory device of a comparative example.

[Figures 20-21] are diagrams showing detailed examples of components related to data reading and connections between the components during data reading in the memory device of the first embodiment.

11: Core circuit

21,22,23: Conductor

31,31A: Variable resistance material

32,32A,32B: ferromagnetic layer

33A,33B: Insulation layer

34A,34B: ferromagnetic layer

35A,35B:Metal layer

41: Ferromagnetic layer

43: Ferromagnetic layer

LBL: Local Bit Line

LWLA, LWLB: local character line

MCA: Lower Memory Unit

MCB: Upper Memory Cell

MTJA,MTJB:MTJ components

RL: Reference layer

SCL: Shift cancel layer

SEA, SEB: switching element

SL: Storage layer

TB: Tunneling Barrier

Claims (20)

A memory device comprises: A first conductor; A first stack on the first conductor, comprising a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in sequence from one side of the first conductor, wherein the second ferromagnetic layer and the third ferromagnetic layer have magnetizations in opposite directions; A second conductor on the first stack; A second stack on the second conductor, comprising a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in sequence from one side of the second conductor, wherein the fifth ferromagnetic layer and the sixth ferromagnetic layer have magnetizations in opposite directions, and the sixth ferromagnetic layer has a volume greater than that of the third ferromagnetic layer; and A third conductor on the second stack. A memory device as claimed in claim 1, wherein the sixth ferromagnetic layer is longer than the third ferromagnetic layer along a direction from the first conductor to the third conductor. A memory device as claimed in claim 2, wherein the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled, and the fifth ferromagnetic layer and the sixth ferromagnetic layer are antiferromagnetically coupled. A memory device as claimed in claim 3, wherein the first metal layer has a thickness that allows the second ferromagnetic layer and the third ferromagnetic layer to be antiferromagnetically coupled, and the second metal layer has a thickness that allows the fifth ferromagnetic layer and the sixth ferromagnetic layer to be antiferromagnetically coupled. A memory device as claimed in claim 4, wherein the first stack further comprises a first variable resistance material between the first conductor and the first ferromagnetic layer, and the second stack further comprises a second variable resistance material between the second conductor and the fourth ferromagnetic layer. The memory device of claim 1 further comprises: A first circuit connected to the first conductor and the second conductor to allow a current to flow from the second ferromagnetic layer to the first ferromagnetic layer, and connected to the second conductor and the third conductor to allow a current to flow from the fourth ferromagnetic layer to the fifth ferromagnetic layer. The memory device of claim 6 further comprises: a first sense amplifier circuit connected to the first conductor; and a second sense amplifier circuit connected to the third conductor. A memory device as claimed in claim 7, wherein the first circuit includes a first driver circuit configured to apply a first voltage to the first conductor, a second driver circuit configured to apply a second voltage higher than the first voltage to the second conductor, and a third driver circuit configured to apply a third voltage lower than the second voltage to the third conductor. A memory device as claimed in claim 8, wherein the first driver circuit includes a p-type first MOSFET connected between the first conductor and a node having a fourth voltage lower than the first voltage, and the third driver circuit includes a p-type second MOSFET connected between the third conductor and a node having the fourth voltage. A memory device as claimed in claim 1, wherein the first stack and the second stack are each a magnetic tunneling junction element, and the first stack enters a low resistance state in response to a current having at least a first magnitude flowing through the first stack in a direction from the first conductor to the second conductor, and the second stack enters a low resistance state in response to a current having at least a second magnitude greater than the first magnitude flowing through the second stack in a direction from the second conductor to the third conductor. A memory device as claimed in claim 10, wherein the first stack enters a high resistance state in response to a current having at least a third magnitude flowing through the first stack in a direction from the second conductor to the first conductor, and the second stack enters a high resistance state in response to a current having at least a fourth magnitude less than the first magnitude flowing through the second stack in a direction from the third conductor to the second conductor. A memory device, comprising: a plurality of first word lines extending in a first direction; a plurality of bit lines extending in a second direction intersecting the first direction above the first word lines; a plurality of second word lines extending in the first direction above the bit lines; a plurality of lower memory cells, each of which is disposed between one of the first word lines and one of the bit lines; and a plurality of upper memory cells, each of which is disposed between one of the bit lines and one of the second word lines, Each of the lower memory cells includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in sequence in a third direction intersecting the first and second directions, wherein the second ferromagnetic layer and the third ferromagnetic layer have magnetizations in opposite directions, and Each of the upper memory cells includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in sequence in the third direction, wherein the fifth ferromagnetic layer and the sixth ferromagnetic layer have magnetizations in opposite directions, wherein each of the lower memory cells enters a low resistance state in response to a current having at least a first magnitude flowing through each of the lower memory cells in a direction from the first word lines to the bit lines, and each of the upper memory cells enters a low resistance state in response to a current having at least a second magnitude greater than the first magnitude flowing through each of the upper memory cells in a direction from the bit lines to the second word lines, and Each of the lower memory cells enters a high resistance state in response to a current having at least a third magnitude flowing through each of the lower memory cells in a direction from the bit lines to the first word lines, and each of the upper memory cells enters a high resistance state in response to a current having at least a fourth magnitude less than the first magnitude flowing through each of the upper memory cells in a direction from the second word lines to the bit lines. A memory device as claimed in claim 12, wherein the sixth ferromagnetic layer has a volume greater than the volume of the third ferromagnetic layer. A memory device as claimed in claim 13, wherein the sixth ferromagnetic layer is longer than the third ferromagnetic layer along the third direction. A memory device as claimed in claim 13, wherein the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled, and the fifth ferromagnetic layer and the sixth ferromagnetic layer are antiferromagnetically coupled. A memory device as claimed in claim 15, wherein the first metal layer has a thickness that allows the second ferromagnetic layer and the third ferromagnetic layer to be antiferromagnetically coupled, and the second metal layer has a thickness that allows the fifth ferromagnetic layer and the sixth ferromagnetic layer to be antiferromagnetically coupled. The memory device of claim 16 further comprises: a first variable resistance material between each of the first word lines and the lower memory cells, and a second variable resistance material between each of the bit lines and the upper memory cells. The memory device of claim 17 further comprises: a first sense amplifier circuit connected to each of the first word lines; and a second sense amplifier circuit connected to each of the second word lines. The memory device of claim 18 further comprises: a first driver circuit configured to apply a first voltage to the first word lines, a second driver circuit configured to apply a second voltage higher than the first voltage to the bit lines, and a third driver circuit configured to apply a third voltage lower than the second voltage to the second word lines. A memory device as claimed in claim 19, wherein the first driver circuit includes a p-type first MOSFET connected between the first word lines and a node having a fourth voltage lower than the first voltage, and the third driver circuit includes a p-type second MOSFET connected between the second word lines and a node having the fourth voltage.

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