TWI863479B - Package - Google Patents

Abstract

The present invention provides a package that ensures airtightness and prevents solder from flowing into a cavity. A frame portion 120 formed of ceramic has a first surface SF1 and a second surface SF2. The second surface SF2 has an inner edge surrounding a cavity CV and an outer edge EO surrounding the inner edge. A substrate portion 110 formed of ceramic has a third surface SF3, and the third surface SF3 has a portion of the second surface SF2 supporting the frame portion 120 and a portion facing the cavity CV. An electrode layer 200 is disposed on the third surface SF3 of the substrate portion 110. An interlayer electrode 510 has an end surface SFA having a diameter DA on the first surface SF1, and a bottom surface SFB having a diameter DB in contact with the electrode layer 200 on the second surface SF2. DA＜DB is satisfied. In a plan view, the bottom surface SFB of the interlayer electrode has a minimum dimension LI from the inner edge of the second surface SF2 of the frame portion 120 and a minimum dimension LO from the outer edge EO of the second surface SF2 of the frame portion 120, satisfying LO＞LI.

Description

Package

The present invention relates to a package, and more particularly to a package having a frame portion penetrated by an intermediate electrode.

As a ceramic component manufactured using a ceramic blank, a package for a crystal oscillator is known. A general crystal oscillator has a crystal blank, a package having a cavity for accommodating the crystal blank, and a cover for sealing the cavity. The package has a substrate portion that serves as the bottom surface of the cavity, a frame portion that surrounds the cavity, and a metallized layer provided on the frame portion. The cover is bonded to the metallized layer using solder. In this way, the airtightness of the cavity is ensured.

The metallization layer on the frame of the package is usually electrically short-circuited with the electrode pad for ground potential. This electrical path can generally be ensured by an interlayer electrode penetrating the frame. However, as the miniaturization of the package progresses, the material width of the frame (the dimension between the inner and outer edges of the frame) also becomes smaller, and the formation of the corresponding fine interlayer electrode becomes difficult. Specifically, it becomes difficult to form fine interlayer holes for fine interlayer electrodes in the green sheet that is formed into the frame by calcination. As a general method for forming a via hole, a mold having a pin shape is used. However, if the pin shape is miniaturized in order to miniaturize the via hole, the mechanical strength of the pin is likely to be insufficient. Therefore, according to the technology disclosed in Japanese Patent Application Laid-Open No. 2007-27592, a battlement-shaped electrode having a crescent shape is provided on the inner wall surface of the frame instead of the via electrode.

When the interlayer electrode is replaced with a crenellated electrode on the side wall of the cavity as in the technique of the above-mentioned publication, the electrode having high wettability to solder is longitudinally cut along the thickness direction of the inner wall of the cavity compared to the frame formed by ceramic. Therefore, in the joining step of the cover using solder, the solder easily flows into the cavity along the crenellated electrode. Once the flowing solder contacts the crystal blank, it may cause adverse effects on the mechanical properties of the crystal oscillator. Such adverse effects on mechanical properties are particularly concerned when the component mounted on the package body is a crystal blank, but they may also occur in the case of other piezoelectric components. Furthermore, as long as the components mounted in the package are electrical components, there is a concern about adverse effects on electrical characteristics such as unexpected short circuits. Therefore, it is important to avoid the inflow of solder, and from this point of view, interposer electrodes are more suitable than crenel-shaped electrodes. Since such a demand also exists for small packages, a technology is desired that can form fine interposer holes for interposer electrodes corresponding to the small material width of the frame.

Japanese Patent Publication No. 2009-234074 discloses a method of forming fine through holes, which serve as vias, in a ceramic green sheet by laser processing technology. Specifically, through holes with a diameter of 30μm to 50μm are formed in a ceramic green sheet with a thickness of less than 250μm using an ultraviolet laser. In the case of forming through holes with a smaller diameter relative to the thickness by laser processing in this way, it is pointed out that there is a tendency for "the through holes to have a pushed-out shape." In the above-mentioned publication, the pushed-out shape of the through holes is considered to be a problem in that it is difficult to fill the through holes with a conductive glue. Therefore, in the technology of the above-mentioned publication, the laser light irradiation conditions that can make the push-out rate above 60% are examined. Here, the push-out rate is defined by the ratio of the push-out diameter. A push-out rate of 100% means that the through hole has no push-out shape. In addition, a smaller push-out rate means a steeper push-out shape. [Known technical literature] [Patent literature]

Patent document 1: Japanese Patent Publication No. 2007-27592 Patent document 2: Japanese Patent Publication No. 2009-234074

[Problems to be solved by the present invention]

According to the review of the inventors of this case, if the above-mentioned laser processing technology is applied simply for the purpose of setting the interlayer electrode in the frame of the package, it is difficult to fully ensure the airtightness of the cavity. As the miniaturization of the package progresses, the material width of the frame becomes smaller, making this problem more serious. Therefore, from the perspective of ensuring airtightness, the above-mentioned battlement-shaped electrode is more suitable. On the other hand, as mentioned above, if a battlement-shaped electrode is provided, there is a situation where the inflow of solder into the cavity becomes a problem. From the above content, it can be seen that in the known technology, it is difficult to ensure sufficient airtightness of the cavity and prevent the inflow of solder into the cavity.

The present invention is proposed to solve the above-mentioned problem, and its purpose is to provide a package that can ensure sufficient airtightness of the cavity and prevent solder from flowing into the cavity. [Technical means for solving the problem]

Aspect 1 is a package having a cavity; comprising a frame portion formed of ceramic, the frame portion having a first surface and a second surface opposite to the first surface in the thickness direction; the second surface having an inner edge surrounding the cavity and an outer edge surrounding the inner edge; the package further comprising a substrate portion formed of ceramic; the substrate portion having a third surface, the third surface having a portion supporting the second surface of the frame portion and a portion facing the cavity; the package further comprising the substrate portion provided on the substrate portion The electrode layer on the third surface, and the intermediate electrode penetrating the frame between the first surface and the second surface; the intermediate electrode has an end surface with a diameter DA on the first surface, and a bottom surface with a diameter DB in contact with the electrode layer on the second surface, satisfying DA＜DB; when viewed from above, the bottom surface of the intermediate electrode has a minimum size LI from the inner edge of the second surface of the frame, and a minimum size LO from the outer edge of the second surface of the frame, satisfying LO＞LI

Aspect 2 is a package as in aspect 1, wherein the diameter DA is less than 50 μm.

Aspect 3 is a package body as in Aspect 1 or Aspect 2, wherein a minimum dimension between the inner edge and the outer edge of the second surface of the frame portion is less than 200 μm.

Aspect 4 is a package body as in any one of Aspects 1 to 3, wherein LO≧LI×1.5 is satisfied.

Aspect 5 is a package body as in any one of aspects 1 to 4, wherein the dielectric electrode has a diameter of less than (DA+DB)/2 at a middle position between the end surface and the bottom surface in the thickness direction.

Aspect 6 is a package body as in any one of aspects 1 to 5, wherein the dielectric electrode has a portion extending from the end surface in a reverse push-out shape in the thickness direction.

Aspect 7 is a package as in aspect 6, wherein the reverse push-pull shape has a push-pull angle of more than 5 degrees.

Aspect 8 is a package body as in any one of aspects 1 to 7, wherein the dielectric electrode has a portion extending from the end surface to the bottom surface in an inverted push-out shape and has a thickness greater than 1/2 of the thickness of the frame portion.

Aspect 9 is a package body as in any one of aspects 1 to 8, wherein the dielectric electrode has a side surface connecting the end surface and the bottom surface; and the side surface has at least one inflection point in a cross-sectional view parallel to the thickness direction.

Aspect 10 is a package body as described in aspect 9, wherein the at least one bending point includes two bending points that bend in opposite directions.

Aspect 11 is a package body as in any one of aspects 1 to 10, wherein the frame portion has an outer wall surface connecting the first surface and the outer edge of the second surface; the outer wall surface has a calcined surface (as-fired surface) connected to the first surface, and a fracture surface (fracture surface) connected to the second surface.

Aspect 12 is a package body as in any one of aspects 1 to 11, wherein LI>0 is satisfied.

Aspect 13 is a package body as in any one of aspects 1 to 11, wherein the interlayer electrode has an outer periphery on the second surface; the outer periphery is formed by an arc portion and a notch portion, the arc portion is along a circular shape of a diameter DB, and the notch portion is along a portion of the inner edge of the second surface of the frame portion.

Aspect 14 is a package body as in aspect 13, wherein the notch portion of the periphery of the interlayer electrode has a convex shape facing the inner side of the bottom surface of the interlayer electrode.

Aspect 15 is a package body as in any one of aspects 1 to 14, wherein the electrode layer is locally thickened at a portion contacting the bottom surface of the dielectric electrode.

Aspect 16 is a package body as in any aspect of aspects 1 to 15, wherein the second surface of the frame portion has a first region directly connected to the bottom surface of the interlayer electrode, and a second region connected to the bottom surface of the interlayer electrode via the first region; the second region is perpendicular to the thickness direction; the first region is inclined relative to the second region in such a manner that the closer to the bottom surface of the interlayer electrode, the smaller the thickness of the frame portion. [Effects of the Invention]

According to aspect 1, first, since the bottom surface of the dielectric electrode is arranged in a manner that satisfies LO>LI, the arrangement position of the stacking interface between ceramics can be ensured to a large extent between the outer edge of the bottom surface of the dielectric electrode and the outer edge of the second surface of the frame. Here, the stacking interface between ceramics has high airtightness compared to the stacking interface between metal and ceramic. Therefore, the reduction of the airtightness of the cavity caused by leakage along the stacking interface can be suppressed. Second, since the diameter DA of the end surface of the dielectric electrode is smaller than the diameter DB of the bottom surface of the dielectric electrode, even if the dielectric electrode is located near the cavity, as close as the bottom surface of the dielectric electrode reaches the cavity, the end surface of the dielectric electrode can still be located at a position separated from the cavity. In this way, the side surface of the dielectric electrode is prevented from being exposed to the cavity near the end surface of the dielectric electrode. Therefore, the inflow of solder into the cavity caused by the dielectric electrode can be prevented. From the above content, it is possible to ensure sufficient airtightness of the cavity and prevent the inflow of solder into the cavity.

According to aspect 2, the diameter DA of the interlayer electrode is a fine size of less than 50 μm. As a result, the width of the frame can also be miniaturized. As the miniaturization progresses, leakage along the laminate interface between the substrate and the frame becomes more likely to become a problem, but these problems can be effectively suppressed for the reasons mentioned above.

According to aspect 3, the minimum dimension between the inner edge and the outer edge of the second surface of the frame is 200 μm or less. As the miniaturization progresses, leakage along the lamination interface between the substrate and the frame becomes more likely to become a problem, but such problems are effectively suppressed for the reasons described above.

According to Aspect 4, LO≧LI×1.5 is satisfied. This can more effectively suppress the reduction in the airtightness of the cavity due to leakage along the lamination interface between the substrate portion and the frame portion.

According to aspect 5, the intermediate electrode has a diameter of (DA+DB)/2 or less in the middle position between the end surface and the bottom surface in the thickness direction. Thus, the distance between the intermediate position of the intermediate electrode and the outer wall surface of the frame can be sufficiently ensured. Therefore, the airtight reliability between the intermediate electrode and the frame can be improved.

According to aspect 6, the interlayer electrode has a portion extending from the end surface in a reverse push-out shape in the thickness direction. This makes it easy to ensure the distance between the end surface of the interlayer electrode and the cavity. Therefore, the inflow of solder into the cavity caused by the interlayer electrode can be more effectively prevented.

According to aspect 7, the reverse push-out shape of the interlayer electrode extending from the end surface has a push-out angle of more than 5 degrees. This makes it easy to ensure the distance between the end surface of the interlayer electrode and the cavity. Therefore, the inflow of solder into the cavity caused by the interlayer electrode can be more effectively prevented.

According to aspect 8, the reverse-pushed shape of the interlayer electrode extending from the end surface has a thickness of more than 1/2 of the thickness of the frame. This makes it easy to ensure the distance between the end surface of the interlayer electrode and the cavity. Therefore, the inflow of solder into the cavity caused by the interlayer electrode can be more effectively prevented.

According to aspect 9, the side surface of the interlayer electrode has at least one inflection point. This can prevent the side surface of the interlayer electrode from being separated from the frame due to sintering shrinkage during the manufacture of the package.

According to aspect 10, the side surface of the interlayer electrode has two bending points that bend in opposite directions. This can more effectively suppress the peeling between the side surface of the interlayer electrode and the frame portion caused by sintering shrinkage during the manufacture of the package.

According to the embodiment 11, the outer wall surface of the frame has a calcined surface connected to the first surface and a fracture surface connected to the second surface. The fracture surface is formed by the fracture step, but due to the influence of the difference in the step, the distance between the outer edge of the second surface of the frame and the bottom surface of the intermediate electrode becomes smaller. However, by satisfying LO>LI as described above, the distance is not easy to become too small. Therefore, the lack of airtightness caused by the distance being too small can be prevented.

According to aspect 12, LI>0 is satisfied. Thus, the side surface of the interlayer electrode is prevented from being exposed to the cavity near the bottom surface of the interlayer electrode. Therefore, the inflow of solder into the cavity can be more reliably prevented.

According to aspect 13, the outer periphery of the interlayer electrode has a notch portion along a portion of the inner edge of the second surface of the frame portion. This makes it easier to place the interlayer electrode close to the cavity. Therefore, the reduction in the airtightness of the cavity caused by leakage along the laminated interface between the substrate portion and the frame portion can be more effectively suppressed.

According to aspect 14, the notch portion of the outer periphery of the interlayer electrode has a convex shape facing the inner side of the bottom surface of the interlayer electrode. Thus, the interlayer electrode can be arranged at the corner of the cavity. Therefore, it is easy to ensure the minimum size LO to a large extent. Therefore, the reduction of the airtightness of the cavity caused by leakage along the stacking interface between the substrate part and the frame part can be more fully suppressed.

According to aspect 15, the electrode layer is locally thickened at the portion in contact with the bottom surface of the interlayer electrode. In this way, the blunt angle between the side surface of the interlayer electrode and the second surface of the frame can be further increased while roughly maintaining the structure of the interlayer electrode. Therefore, the thermal stress caused by the difference in thermal expansion between the interlayer electrode mainly formed of metal and the frame formed of ceramic can be alleviated. Therefore, cracks caused by thermal stress or separation between the interlayer electrode and the frame can be prevented.

According to aspect 16, the second surface of the frame has a first region directly connected to the bottom surface of the interlayer electrode, and a second region connected to the bottom surface of the interlayer electrode via the first region; the second region is perpendicular to the thickness direction; the first region is inclined relative to the second region in such a manner that the thickness of the frame becomes smaller as it approaches the bottom surface of the interlayer electrode. In this way, the blunt angle between the side surface of the interlayer electrode and the second surface of the frame can be further increased while roughly maintaining the structure of the interlayer electrode. Therefore, the thermal stress caused by the difference in thermal expansion between the interlayer electrode mainly formed of metal and the frame formed of ceramic can be alleviated. Therefore, cracks caused by thermal stress or separation between the dielectric electrode and the frame can be prevented.

Hereinafter, the implementation form of the present invention will be described with reference to the drawings. In addition, in some of the drawings, an xyz rectangular coordinate system is shown for easy understanding of the direction, and the z direction corresponds to the thickness direction. In addition, in this specification, "pushing-out shape" and "reverse pushing-out shape" have different meanings. In the case of defining a certain direction, the "pushing-out shape" extending along the direction is a shape that gradually narrows toward the direction, for example, a shape whose diameter gradually decreases toward the direction. On the other hand, the "reverse pushing-out shape" extending along the direction is a shape that gradually narrows toward the direction opposite to the direction, for example, a shape whose diameter gradually decreases toward the direction opposite to the direction. In other words, the "reverse push-pull shape" extending along the direction is a shape that gradually becomes wider toward the direction, for example, a shape whose diameter gradually increases toward the direction.

<Implementation Form 1> FIG. 1 is a top view schematically showing the structure of the crystal oscillator 900 (electrical component) of the present implementation form 1. FIG. 2 is a schematic cross-sectional view along the line II-II of FIG. 1. FIG. 3 is a top view schematically showing the structure after the crystal blank 890 (electrical component) is installed in the manufacturing method of the crystal oscillator 900 (FIG. 1). FIG. 4 is a schematic cross-sectional view along the line IV-IV of FIG. 3.

The crystal oscillator 900 includes a package 701, a crystal blank 890, a solder 960, and a cover 980. A cavity CV is provided in the package 701. The crystal blank 890 is accommodated in the cavity CV and mounted on the element electrode pad 211 and the element electrode pad 212 of the package 701. The cover 980 is bonded to the metallization layer 600 of the package 701 by the solder 960, thereby sealing the cavity CV. Generally speaking, the solder 960 is preferably formed of an alloy containing gold, for example, an alloy containing gold and tin, in other words, an Au-Sn alloy. The cover 980 is formed of a metal, for example, an alloy containing iron and nickel. In addition, in this specification, alloys are regarded as a type of metal.

The metallization layer 600 is formed of a metal containing at least one of molybdenum and tungsten, for example. A plating layer may be provided on the surface of the metallization layer 600 (the surface facing the solder 960), and generally, a gold plating layer is provided. In addition, a nickel plating layer may be provided as a base of the gold plating layer. In this embodiment, the metallization layer 600 directly provided on the frame top surface SF1 of the frame portion 120 of the package body 701 is bonded to the lid portion 980 only by the solder 960.

FIG5 is a top view schematically showing the structure of the package 701. FIG6 is a schematic cross-sectional view along the line VI-VI of FIG5. The package 701 has a ceramic part 100, a device electrode pad 211, a device electrode pad 212, and package body electrode pads 301 to 304. In addition, the package 701 has a structure for power supply wiring provided in the ceramic part 100, and the details will be described in detail later.

The ceramic part 100 is formed of ceramic, preferably having an oxide as a main component, more preferably having aluminum oxide as a main component, for example, substantially formed of aluminum oxide. The ceramic part 100 includes a substrate part 110 and a frame part 120. The material of the substrate part 110 may also be the same as the material of the frame part 120. The frame part 120 is stacked on the substrate part 110 in the thickness direction (z direction of FIG. 6). The frame part 120 has a frame top surface SF1 (first surface) and a frame bottom surface SF2 (a second surface opposite to the first surface in the thickness direction). In addition, the frame part 120 has an inner wall surface connecting the frame top surface SF1 and the frame bottom surface SF2 to each other, and the inner wall surface is a side wall of the cavity CV. The substrate part 110 has a substrate top surface SF3 (third surface). The substrate top surface SF3 includes a support surface portion SF3S that supports the frame bottom surface SF2 of the frame portion 120, and a cavity surface portion SF3C that faces the cavity CV. The cavity surface portion SF3C serves as the bottom surface of the cavity CV.

The element electrode pad 211 and the element electrode pad 212 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) facing the cavity CV. Specifically, the element electrode pad 211 and the element electrode pad 212 are arranged on the top surface (the surface facing the cavity CV) of the substrate part 110 (FIG. 6). The package body electrode pads 301-304 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) outside the cavity CV. Specifically, the package body electrode pads 301-304 are arranged on the bottom surface (the surface opposite to the surface facing the cavity CV) of the substrate part 110 (FIG. 6).

The relay electrode 220 (FIG. 5) is disposed on the substrate top surface SF3 of the substrate portion 110 (FIG. 6). The relay electrode 220 is at least partially disposed on the support surface portion SF3S (FIG. 6). Therefore, the relay electrode 220 (FIG. 5) is at least partially covered by the frame portion 120. The relay electrode 220 may further have a portion that is not covered by the frame portion 120 and is disposed on the bottom surface of the cavity CV. In other words, the relay electrode 220 may also be only partially covered by the frame portion 120.

Fig. 7 is a top view in which the metallization layer 600 (Fig. 5) and the frame portion 120 (Fig. 6) are omitted. Fig. 8 is a top view schematically showing the substrate portion 110 and the substrate interlayer electrodes 411-414 of Fig. 7, and showing the package body electrode pads 301-304 in dotted lines.

The wiring layers 401 to 403 are embedded in the substrate portion 110 of the ceramic portion 100 near the top surface thereof. The wiring layer 401 contacts the element electrode pad 211, the wiring layer 402 contacts the element electrode pad 212, and the wiring layer 403 contacts the relay electrode 220. The wiring layers 401 to 403 may be covered with an insulating film 110i (see FIG. 11 ) which is a part of the substrate portion 110 within a range that does not hinder the contact therebetween, and in particular, the element electrode pad 211 and the wiring layer 403 are insulated by the insulating film 110i. The wiring layer 403 and the relay electrode 220 constitute the electrode layer 200 .

The package 701 has substrate dielectric electrodes 411 to 414 embedded in the substrate portion 110 of the ceramic portion 100. The substrate dielectric electrode 411 connects the wiring layer 402 and the package electrode pad 301. The substrate dielectric electrode 412 connects the wiring layer 403 and the package electrode pad 302. The substrate dielectric electrode 413 connects the wiring layer 401 and the package electrode pad 303. The substrate dielectric electrode 414 connects the wiring layer 403 and the package electrode pad 304.

According to the above structure, the device electrode pad 211 is electrically connected to the package electrode pad 303 , the device electrode pad 212 is electrically connected to the package electrode pad 301 , and the relay electrode 220 is electrically connected to the package electrode pad 302 and the package electrode pad 304 .

Fig. 9 is a top view in which the metallization layer 600 of Fig. 5 is omitted. Fig. 10 is a partially enlarged view of Fig. 9. Fig. 11 is a schematic cross-sectional view along the line XI-XI of Fig. 5.

The frame bottom surface SF2 of the frame portion 120 has an inner edge EI surrounding the cavity CV and an outer edge EO surrounding the inner edge EI. The minimum dimension WD between the inner edge EI and the outer edge EO (FIG. 10) can be less than 200 μm, and is generally greater than 20 μm and less than 110 μm. The frame portion 120 has an outer wall surface SF4 connecting the frame top surface SF1 and the outer edge EO of the frame bottom surface SF2. In addition, the frame portion 120 has an inner wall surface (left side of FIG. 11) connecting the frame top surface SF1 and the inner edge EI of the frame bottom surface SF2, and the inner wall surface faces the cavity CV. In this embodiment, the outer wall surface SF4 has a calcined surface SF4A connected to the frame top surface SF1, and a fracture surface SF4B connected to the frame bottom surface SF2. The fracture surface SF4B may also be a surface substantially perpendicular to the frame top surface SF1 (a surface perpendicular to the z direction in FIG. 11 ). The calcined surface SF4A, as shown in FIG. 11 , may also be an angled surface that chamfers the frame top surface SF1 and the fracture surface SF4B. In other words, the normal direction of the calcined surface SF4A may also be different from the normal direction of the frame top surface SF1 and the fracture surface SF4B, and may also be located between them.

As described above, the electrode layer 200 is formed on the substrate top surface SF3 of the substrate portion 110 by the wiring layer 403 and the relay electrode 220. In addition, as described above, the substrate portion 110 has an insulating film 110i as a part thereof (FIG. 11). As a variation, the insulating film 110i may be omitted according to the design of the package. In addition, the electrode layer 200 may also be formed by only one of the wiring layer 403 and the relay electrode 220. For example, the electrode layer 200 may omit the relay electrode 220 but have the wiring layer 403. In this case, the boundary position between the wiring layer 403 and the insulating film 110i (the right end position of the wiring layer 403 in FIG. 11 ) may be shifted to the end position of the relay electrode 220 on the support surface portion SF3S (the right end position of the relay electrode 220 in FIG. 11 ), or the relay electrode 220 may be omitted. In addition, the end of the insulating film 110i facing the cavity CV may be deformed to reach the frame portion 120. In this case, the electrode layer 200 may be separated from the cavity CV by the insulating film 110i. In addition, the electrode layer 200 generally spans the support surface portion SF3S and the cavity surface portion SF3C as shown in FIG11 , but as a modification, it may be arranged only on the support surface portion SF3S. In addition, the electrode layer 200, as shown in FIG11 , preferably has an end (the right end in FIG11 ) separated from the outer edge EO of the frame bottom surface SF2 of the frame portion 120. In other words, the end preferably does not reach the outer edge EO. Thereby, the stacking interface of the metal and the ceramic that constitute the electrode layer 200 does not reach the outer edge EO. As a result, the interface between the metal and the ceramic, which has a lower airtightness than the interface between the ceramics, does not reach the outer edge EO. Therefore, the reduction in airtightness caused by the electrode layer 200 can be suppressed.

The package body 701 has an interlayer electrode 510. The interlayer electrode 510 penetrates the frame portion 120 between the frame top surface SF1 and the frame bottom surface SF2. The interlayer electrode 510 has an end surface SFA on the frame top surface SF1, and also has a bottom surface SFB on the frame bottom surface SF2. When viewed from above, the center position of the end surface SFA and the center position of the bottom surface SFB may be roughly the same. The bottom surface SFB contacts the electrode layer 200, and in this embodiment, contacts the relay electrode 220. As mentioned above, the relay electrode 220 contacts the wiring layer 403; in the wiring layer 403 (Figure 7), the substrate interlayer electrode 412 and the substrate interlayer electrode 414 are connected. Therefore, the substrate dielectric electrode 412 and the substrate dielectric electrode 414 are electrically connected to the dielectric electrode 510. Furthermore, the end surface SFA of the dielectric electrode 510 contacts the metallization layer 600 (FIG. 6). Therefore, the metallization layer 600 is electrically connected to the package body electrode pad 302 and the package body electrode pad 304 respectively through the substrate dielectric electrode 412 and the substrate dielectric electrode 414 (refer to FIG. 8).

The end surface SFA of the dielectric electrode 510 has a diameter DA (FIG. 10). The diameter DA is smaller than the minimum dimension WD and may be less than 50 μm. The bottom surface SFB of the dielectric electrode 510 has a diameter DB (FIG. 10) that is larger than the diameter DA. In other words, DA＜DB is satisfied. The ratio of the diameter DA to the diameter DB may be greater than 30% and less than 70%. The above ratio is particularly suitable when the thickness of the frame portion 120 is greater than 20 μm and less than 250 μm. The dielectric electrode 510 preferably has a diameter of less than (DA+DB)/2 in the middle position (the average position of the position of the end surface SFA and the position of the bottom surface SFB) between the end surface SFA and the bottom surface SFB in the thickness direction (z direction of FIG. 11). The pull-out ratio (the percentage of diameter DA to diameter DB) may also be less than 60%.

In a plan view ( FIG. 10 ), the bottom surface SFB has a minimum dimension LI from the inner edge EI of the frame bottom surface SF2 of the frame portion 120 and a minimum dimension LO from the outer edge EO of the frame bottom surface SF2 of the frame portion 120. LO>LI is satisfied, preferably LO≧LI×1.5 is satisfied. In addition, in this embodiment, LI>0.

In the planar layout shown in FIG10 , the shapes of the end surface SFA and the bottom surface SFB are generally circular, but these shapes may be slightly different from the strictly geometrically defined circle due to manufacturing errors. In this case, the diameter DA and the diameter DB can also be calculated by approximating the end surface SFA and the bottom surface SFB with a circular shape. In addition, in the case of providing a notch portion in the circular shape as in the modified example described later, the diameter can also be determined without considering the notch portion.

In addition, in the planar layout shown in FIG10, the inner edge EI of the frame bottom surface SF2 (see FIG11) has a first straight line portion (a straight line portion along the x direction in FIG10), a second straight line portion extending in a right angle direction relative to the first straight line portion (a straight line portion along the y direction in FIG10), and a corner portion connecting them. The minimum dimension LI may also be the dimension of the corner portion.

FIG. 12 to FIG. 22 are figures used to illustrate a manufacturing method for manufacturing a plurality of packages 701 at the same time. In addition, FIG. 12 to FIG. 21 show a state earlier than the calcination step that changes the state of FIG. 21 to the state of FIG. 22. Therefore, each structure in FIG. 12 to FIG. 21 is different from the structure in the completed package 701 and is formed by uncalcined materials. However, for the convenience of explanation, in FIG. 12 to FIG. 21 showing the steps earlier than the calcination step, the same symbols as the symbols representing the structure of the package 701 obtained through the calcination step are still given. In addition, for the sake of convenience, the above-mentioned names of the structures formed by the uncalcined materials may also use the names of the structures in the package body 701 obtained through the calcination step.

FIG. 12 is a partial top view schematically showing the structure of the substrate blank GS in the above-mentioned manufacturing method. FIG. 13 is a partial top view schematically showing the substrate portion 110 and substrate interlayer electrodes 411 to 414 of the substrate blank GS, and showing the package body electrode pads 301 to 304 in dotted lines. FIG. 14 is a schematic partial cross-sectional view along the line XIV-XIV of FIG. 12 and FIG. 13. The substrate blank GS includes a plurality of regions UN0 to UN4, each of which eventually becomes the substrate portion 110 and the structure near it of the package body 701 (FIG. 6). Regions UN1 to UN4 are all configured to be adjacent to region UN0. In addition, although only a specific structure of the area UN0 is shown in FIG. 12 and FIG. 13 , the areas UN1 to UN4 may also have the same structure.

In addition, in this specification, the term "green body" refers to the uncalcined structure that is calcined in a subsequent step. The green body is generally a powder molded body. In order to facilitate handling, the green body may also contain glass components and organic components as additives in addition to the main component. The organic component may also contain polyvinyl butyral or acrylic acid, for example. The green body is formed by any method, such as by a doctor blade method to form a green sheet that is at least a part of the green body. A green body may be further added to the green sheet, and this addition is generally performed by printing on the green sheet, or by stacking other green sheets. The printing is generally performed by screen printing. The main component of the green body that is formed into the ceramic part 100 (Figure 6) by calcination may be, for example, aluminum oxide powder. The main component of the green body that is formed into the wiring structure such as the dielectric electrode 510 and the electrode layer 200 (see FIG. 11 ) by calcination may be, for example, tungsten (W) powder, molybdenum (Mo) powder, a mixed powder of W powder and Mo powder, or W—Mo alloy powder.

In order to obtain the substrate blank GS, first, a blank that will become the substrate portion 110 is formed. For the blank, a via hole is formed by punching, and an electrode glue is printed into the via hole to form a blank that will become the substrate via electrode 411 to 414. In the electrode glue, at least one powder of tungsten and molybdenum is dispersed. Next, the electrode glue is printed on the blank to form a blank that will become the wiring layer 401 to 403. Next, the ceramic glue is printed on the blank to form a blank that will become the insulating film 110i. Next, the green sheet is printed with electrode glue to form a green body of the element electrode pads 211, 212 and the relay electrode 220. In addition, at any time after the green bodies of the substrate interlayer electrodes 411-414 are formed as described above, the green sheet is printed with electrode glue to form a green body of the package body electrode pads 301-304.

Figures 15 to 19 are partial cross-sectional views showing the steps of the frame blank GF used to form the frame 120 (Figure 11) and the structure near it. In the figure, the fracture surface BR is shown by a dot chain line, and the fracture step described later is performed along this line.

15, as the frame blank GF, first, a simple green sheet including a portion to be the frame 120 is formed. This formation can also be performed by, for example, a doctor blade method.

Referring to FIG. 16 , a via hole VH is formed in the frame portion 120 by laser processing. The laser light used for laser processing is irradiated in a manner of traveling from the frame bottom surface SF2 toward the frame top surface SF1. As a result, the via hole VH tends to have a push-pull shape in the direction from the frame bottom surface SF2 toward the frame top surface SF1. The aperture in the frame bottom surface SF2 is larger than the aperture in the frame top surface SF1.

Referring to FIG. 17 , a via hole VH ( FIG. 16 ) of the frame body GF is formed with an via electrode 510 ( FIG. 17 ). Specifically, the via hole VH is filled with electrode glue by screen printing. The filling is preferably performed from the frame bottom surface SF2 to the frame top surface SF1 .

Referring to FIG. 18 , a metallization layer 600 is formed. Specifically, electrode glue is applied. In FIG. 18 , electrode glue is applied to the entire frame top surface SF1, but the metallization layer 600 does not need to be applied to the area removed by the step of forming the cavity CV described later. Therefore, a screen printing method that does not apply the glue to at least a portion of the area can also be applied.

Referring to Fig. 19, the cavity CV is formed by stamping. Alternatively, the cavity CV may be formed in the frame blank GF at an earlier time. By the above method, the frame blank GF having a frame shape surrounding the cavity CV is completed.

Referring to Fig. 20, the frame blank GF (Fig. 19) is stacked on the substrate blank GS (Fig. 14) to form a blank 700G. The blank 700G includes a plurality of regions 701G, each of which eventually becomes a package 701 (refer to Fig. 11).

Referring to FIG. 21 , a groove TR1 ( FIG. 13 ) is formed on the frame top surface SF1 of the blank 700G. In addition, a groove TR2 is formed on the surface of the blank 700G opposite to the frame top surface SF1. The groove TR1 and the groove TR2 are arranged to face each other in the thickness direction. The groove TR1 and the groove TR2 are formed, for example, by pressing the tip of a knife against the blank 700G. Thereafter, a calcining step of calcining the blank 700G is performed. In addition, after the calcining step, a coating step may also be performed as necessary.

Referring to FIG. 22 , a calcined sheet 700F is formed by the above-mentioned calcining step. In the calcining step, the inner surface of the groove TR1 is exposed to the calcining ambient gas. Therefore, the inner surface of the groove TR1 of the calcined sheet 700F becomes a calcined surface. The calcined surface becomes the calcined surface SF4A of the package 701 ( FIG. 11 ). By applying stress to the calcined sheet 700F, a fracture step is performed to generate cracks from the groove TR1. A fracture surface is formed by breaking the frame portion 120 by the fracture step. The fracture surface becomes the fracture surface SF4B of the package 701 ( FIG. 11 ). The breaking step may be a step of generating a crack between the trench TR1 and the trench TR2. Through the breaking step, a plurality of packages 701 are cut out from the calcined sheet 700F. In the above manner, the package 701 is obtained ( FIG. 11 ).

In the above-mentioned breaking step, the crack from the trench TR1 ideally extends in the thickness direction as shown by the solid arrow in FIG. 22. However, in reality, as shown by the dotted arrow in FIG. 22, there is a case where the crack unexpectedly approaches the interlayer electrode 510. As a result, in the package 701 having the interlayer electrode 510 on one side, the minimum dimension LO (FIG. 10) of the frame bottom surface SF2 of the frame portion 120 becomes smaller. Since an excessively small minimum dimension LO is likely to cause leakage of the package 701, the minimum dimension LO should have a certain degree of margin. According to this embodiment, it is easy to ensure this margin.

FIG. 23 is a partial cross-sectional view schematically showing the structure of the package 791 of the first comparative example in the same view as FIG. 11. The shape of the interlayer electrode 510 of the package 791 of the first comparative example is a shape obtained by inverting the shape of the interlayer electrode 510 of the package 701 (FIG. 11) of the aforementioned embodiment 1 upside down. As a result, in the package 791, unlike the embodiment 1, the diameter of the end surface SFA is larger than the diameter of the bottom surface SFB. Therefore, in the step of manufacturing the package 791 (FIG. 23), there is an unignorable probability that the package 792 of the second comparative example shown in FIG. 24 will be manufactured due to the occurrence of manufacturing errors such as the cavity CV and the interlayer electrode 510 being close to each other.

In the package 792, the end surface SFA of the interlayer electrode 510 reaches the cavity CV. As a result, the side surface of the interlayer electrode 510 is exposed to the cavity CV near the end surface SFA of the interlayer electrode 510. In the step of joining the cover 980 (see FIG. 2) to the package 792, the solder 960 (see FIG. 2) easily flows into the cavity CV as shown by the arrow FL (FIG. 24). Since the inflowing solder contacts the crystal blank 890 (see FIG. 2), the performance of the crystal oscillator 900 (see FIG. 2) may be adversely affected. In addition, the adverse effect on mechanical properties caused by the inflow of solder 960 is particularly concerned when the component mounted on the package is a crystal blank 890, but it also occurs in the case of other piezoelectric components. Furthermore, as long as the component mounted on the package is an electrical component, adverse effects on electrical properties such as unexpected short circuits are concerned.

According to the package 701 (FIG. 10 and FIG. 11) of the present embodiment, first, since the bottom surface SFB of the interlayer electrode 510 is arranged in a manner satisfying LO>LI (refer to FIG. 10), the arrangement position of the stacking interface between ceramics can be ensured to a large extent between the bottom surface SFB of the interlayer electrode 510 and the outer edge EO of the frame bottom surface SF2 of the frame portion 120. Here, the stacking interface between ceramics has high airtightness compared to the stacking interface between metal and ceramic. Therefore, the reduction of the airtightness of the cavity CV caused by leakage along the stacking interface can be suppressed. Second, since the diameter DA of the end surface SFA of the dielectric electrode 510 is smaller than the diameter DB of the bottom surface SFB of the dielectric electrode 510, even if the dielectric electrode 510 is located near the cavity CV, to the extent that the bottom surface SFB of the dielectric electrode 510 reaches the cavity CV, the end surface SFA of the dielectric electrode 510 can still be located at a position separated from the cavity CV. In this way, the side surface of the dielectric electrode 510 is prevented from being exposed to the cavity CV near the end surface SFA of the dielectric electrode 510. Therefore, the inflow of the solder 960 into the cavity CV caused by the dielectric electrode 510 can be prevented. From the above, it is possible to ensure sufficient airtightness of the cavity CV and prevent the solder 960 from flowing into the cavity CV.

The diameter DA (FIG. 10) of the dielectric electrode 510 can also be made less than 50 μm. In this way, the minimum dimension WD (FIG. 10) of the frame portion 120 can also be miniaturized, for example, less than 200 μm. The more this miniaturization is advanced, the more likely leakage along the stacking interface between the substrate portion 110 and the frame portion 120 will become a problem, but such problems can be effectively suppressed for the reasons described above.

10 , when LO≧LI×1.5 is satisfied, the reduction in the airtightness of the cavity due to leakage along the stacking interface (see FIG. 11 ) between the substrate portion 110 and the frame portion 120 can be more effectively suppressed.

The dielectric electrode 510 may also have a diameter of less than (DA+DB)/2 in the middle position between the end surface SFA and the bottom surface SFB in the thickness direction (z direction of FIG. 11 ), referring to FIG. 10 . In this way, the distance between the middle position of the dielectric electrode 510 and the outer wall surface SF4 of the frame portion 120 can be fully ensured. In this way, the airtight reliability between the dielectric electrode 510 and the frame portion 120 can be improved. For example, even if a crack unexpectedly approaches the dielectric electrode 510 as shown by the dotted arrow in FIG. 22 , the crack can still be prevented from reaching the dielectric electrode 510.

The interlayer electrode 510 has a portion extending from the end surface SFA in a reverse push-pull shape in the thickness direction (z direction in FIG. 11 ). This makes it easy to ensure the distance between the end surface SFA of the interlayer electrode 510 and the cavity CV. Therefore, the inflow of the solder 960 into the cavity CV caused by the interlayer electrode 510 can be more effectively prevented. In particular, in the present embodiment, the interlayer electrode 510 is extended in a reverse push-pull shape as a whole, so that this effect can be more fully obtained.

The outer wall surface SF4 (FIG. 11) of the frame portion 120 has a calcined surface SF4A connected to the frame top surface SF1 and a fracture surface SF4B connected to the frame bottom surface SF2. The fracture surface SF4B is formed by a fracture step, but due to the influence of the difference in the step, the minimum dimension LO (FIG. 10) may become smaller. However, by satisfying LO>LI as described above, the minimum dimension LO is not easy to become too small. Therefore, the lack of airtightness caused by the minimum dimension LO being too small can be prevented.

When LI>0 is satisfied (FIG. 10), the side surface of the interlayer electrode 510 is prevented from being exposed to the cavity CV near the bottom surface SFB of the interlayer electrode 510. Therefore, the solder 960 can be more reliably prevented from flowing into the cavity CV. However, LI>0 does not necessarily have to be satisfied. The modification corresponding to LI=0 is described below.

FIG25 is a partial cross-sectional view schematically showing the structure of the package 710 of the modification of the present embodiment 1 in the same view as FIG11. FIG26 is a partial top view schematically showing the structure of the package 710 in the same view as FIG10. FIG27 is a top view illustrating the structure of the bottom surface SFB of the interlayer electrode 510 shown in FIG26. Referring to FIG11 (Implementation Form 1), in this modification, LI>0 is not satisfied.

The interlayer electrode 510 has an outer periphery PR (FIG. 27) on the frame bottom surface SF2 (FIG. 25). The outer periphery PR is formed by an arc portion PRa along a circle with a diameter DB and a notch portion PRb along a portion EIc of the inner edge EI of the frame bottom surface SF2. The notch portion PRb is located at a position where the above-mentioned circle is concave. In addition, in this variant, the inner edge EI of the frame portion 120 is regarded as including a portion EIc along the notch portion PRb. In this variant, since the bottom surface SFB of the interlayer electrode 510 is in contact with a portion EIc of the inner edge EI of the frame portion 120, the minimum dimension LI defined in FIG. 11 is zero.

According to this modification, the outer periphery PR of the interlayer electrode 510 has a notch portion EIc along a portion of the inner edge EI of the frame bottom surface SF2 of the frame portion 120. This makes it easier to arrange the interlayer electrode 510 close to the cavity CV. Therefore, the reduction in the airtightness of the cavity due to leakage along the stacking interface between the substrate portion 110 and the frame portion 120 can be more effectively suppressed.

The notch portion PRb (FIG. 27) of the outer periphery PR of the interlayer electrode 510 may also have a convex shape toward the inner side of the bottom surface SFB of the interlayer electrode 510. In this case, the interlayer electrode 510 can be arranged at the corner of the cavity CV. Thereby, it is easy to ensure the minimum size LO to a large extent (refer to FIG. 10). Thereby, the reduction of the airtightness of the cavity caused by leakage along the stacking interface between the substrate portion 110 and the frame portion 120 can be more fully suppressed. In addition, as a typical example of this case, the inner edge EI of the frame portion 120 is made to have a slightly rectangular shape, and a part EIc of the inner edge EI is extended along each corner of the rectangular shape. In the example shown in FIG. 10 , each corner is chamfered in an arc shape, and therefore a portion EIc of the inner edge EI also extends in an arc shape.

FIG. 28 is a diagram for explaining the details of the structure of the interlayer electrode 510 (FIG. 11). The interlayer electrode 510 has a reverse push-out shape from the end surface SFA to the bottom surface SFB in the entire thickness direction (z direction in FIG. 28). This reverse push-out preferably has a push-out angle TP of 5 degrees or more based on the thickness direction (z direction in the figure). Thereby, it is easy to ensure the distance between the end surface SFA of the interlayer electrode 510 and the cavity CV. Therefore, the inflow of the solder 960 into the cavity CV caused by the interlayer electrode 510 can be more effectively prevented. In addition, in this embodiment, the interlayer electrode 510 has a reverse push-out shape in the entire thickness direction as described above. Regarding the different forms therefrom, they are described in the following embodiments 2 and 3.

<Implementation Form 2> FIG. 29 is a diagram for explaining the details of the structure of the interlayer electrode 520 of the package body 702 of the present implementation form 2. In the cross-sectional view parallel to the thickness direction (FIG. 29), the interlayer electrode 520 has a side surface connecting the end surface SFA and the bottom surface SFB. Point KA and point KB respectively show the position of the side surface at the position of the end surface SFA and the bottom surface SFB in the thickness direction. Point KV shows the position of the side surface between point KA and point KB in the thickness direction. Point KW shows the position of the side surface between point KV and point KB in the thickness direction. The above-mentioned side surface may also have at least one bending point; in the present implementation form, there are point KV and point KW as two bending points that bend in opposite directions. The dielectric electrode 520 has: a portion 521 having a side from point KA to point KV; a portion 522 having a side from point KV to point KW; and a portion 523 having a side from point KW to point KB. The portion 521 extends from the end surface SFA in a reverse push-pull shape in the thickness direction, and the push-pull angle TP of this reverse push-pull shape is preferably greater than 5 degrees. The portion 522 has a reverse push-pull shape that is gentler than the portion 521, or a cylindrical shape. The portion 523 has a reverse push-pull shape that is steeper than the portion 522.

In addition, regarding the configuration other than the above, since it is almost the same as the configuration of the above-mentioned embodiment 1 or its modified example, the same symbols are given to the same or corresponding elements, and their descriptions are not repeated.

According to the second embodiment, the side surface of the interlayer electrode 520 has a bending point (specifically, point KV and point KW). This can suppress the peeling between the side surface of the interlayer electrode 520 and the frame 120 caused by sintering shrinkage during the manufacture of the package 702. By making the points KV and KW, which are the bending points, bend in opposite directions, the effect is more sufficient.

In addition, the portion of the interlayer electrode 520 extending from the end surface SFA to the bottom surface SFB in an inverted shape is preferably thicker than 1/2 of the thickness of the frame portion 120. This makes it easy to ensure the distance between the end surface SFA of the interlayer electrode 520 and the cavity CV (see FIG. 11). Therefore, the inflow of solder into the cavity CV caused by the interlayer electrode 520 can be more effectively prevented.

<Implementation Form 3> FIG. 30 is a diagram for explaining the details of the structure of the interlayer electrode 530 of the package body 703 of the present implementation form 3. The interlayer electrode 530 has: a portion 531 having a side from point KA to point KV; a portion 532 having a side from point KV to point KW; and a portion 533 having a side from point KW to point KB. The portion 531 extends from the end surface SFA in the thickness direction in a reverse push-out manner, and the push-out angle TP of this reverse push-out shape is preferably greater than 5 degrees. The portion 532 has a push-out shape rather than a reverse push-out shape in the direction from the end surface SFA to the bottom surface SFB. In other words, the portion 532 has a push-out shape in the direction from the end surface SFA to the bottom surface SFB. Part 533 has a reverse push-pull shape in the direction from the end surface SFA to the bottom surface SFB.

In addition, since the structures other than the above are almost the same as those of the above-mentioned embodiment 2, the same symbols are given to the same or corresponding elements, and their descriptions are not repeated. According to this embodiment, the effect of suppressing the peeling between the side surface of the interlayer electrode 520 and the frame portion 120 caused by sintering shrinkage is further improved than that of the embodiment 2.

In addition, the portion of the interlayer electrode 530 extending from the end surface SFA to the bottom surface SFB in an inverted shape, specifically, the portion 531 and the portion 533, preferably have a thickness greater than 1/2 of the thickness of the frame portion 120. This makes it easy to ensure the distance between the end surface SFA of the interlayer electrode 530 and the cavity CV (see FIG. 11). Therefore, the inflow of solder into the cavity CV caused by the interlayer electrode 530 can be more effectively prevented.

<Implementation Form 4> FIG. 31 is a partial top view schematically showing the structure of the package body 720 of the present implementation form 4 in the same view as FIG. 10 of the implementation form 1. FIG. 32 is a schematic partial cross-sectional view along the line XXXII-XXXII of FIG. 31. FIG. 33 is a partial top view schematically showing the structure of the package body 720 in the same view as FIG. 7 of the implementation form 1.

In the package 720, the electrode layer 200 is locally thickened at the portion in contact with the bottom surface SFB of the interlayer electrode 510. This is because the electrode layer 200 has a raised portion 222 in contact with the bottom surface SFB of the interlayer electrode 510 according to the reasons described later with reference to FIG. 34. In addition, due to this reason, the frame bottom surface SF2 of the frame portion 120 has an inclined region SF2d (first region) directly connected to the bottom surface SFB of the interlayer electrode 510, and a parallel region SF2f (second region) connected to the bottom surface SFB of the interlayer electrode 510 via the inclined region SF2d. The second region SF2f is perpendicular to the thickness direction. The inclined region SF2d is inclined relative to the parallel region SF2f in such a manner that the thickness of the frame portion 120 decreases as it approaches the bottom surface SFB of the intermediate electrode 510. The inclination angle is, for example, not less than 4° and not more than 20°.

When viewed from above (FIG. 31), the raised portion 222 is spaced from the outer edge EO of the frame bottom surface SF2 of the frame portion 120. In addition, when viewed from above, the minimum dimension (in other words, the minimum distance) of the raised portion 222 measured from the outer edge EO is preferably larger than the minimum dimension LI (FIG. 10), and more preferably LI×1.5 or more.

In the configurations illustrated in FIGS. 31 and 32 , when viewed from above, the inclined region SF2d completely surrounds the bottom surface SFB of the interlayer electrode 510, and the parallel region SF2f completely surrounds the inclined region SF2d. However, as a modification, the parallel region SF2f does not need to completely surround the inclined region SF2d. As another modification, the inclined region SF2d does not need to completely surround the bottom surface SFB of the interlayer electrode 510. These modifications, for example, are equivalent to applying the raised portion 222 to the configuration in which the interlayer electrode 510 is arranged next to the cavity CV as shown in FIGS. 25 and 26 (modification of embodiment 1).

In addition, in FIG32 , the raised portion 222 is completely separated from the substrate portion 110 (specifically, the insulating film 110i which is a part of the substrate portion 110) by the intermediate electrode 220. As a modification, the raised portion 222 may also be in contact with the substrate portion 110 (specifically, the insulating film 110i which is a part of the substrate portion 110).

By making the tilted region SF2d (FIG. 32) tilt as described above, the blunt angle SH (FIG. 32) between the side surface of the interlayer electrode 510 and the frame bottom surface SF2 can be further increased while roughly maintaining the structure of the interlayer electrode 510. Therefore, the thermal stress caused by the difference in thermal expansion between the interlayer electrode 510 mainly formed of metal and the frame portion 120 formed of ceramic can be alleviated. Therefore, cracks caused by thermal stress or separation between the interlayer electrode 510 and the frame portion 120 can be prevented.

FIG34 is a partial cross-sectional view schematically showing the steps corresponding to FIG17 of the embodiment 1 in the manufacturing method of the package body 720. In this step, the via hole VH (FIG. 16) of the frame body GF is formed with an via electrode 510 (FIG. 34). Specifically, the via hole VH is filled with electrode glue by screen printing and then dried. This filling is preferably performed by allowing the electrode glue to flow from the frame bottom surface SF2 to the frame top surface SF1. The electrode paste with a certain amount of margin is supplied to almost the entire via hole VH (FIG. 16) to form the via electrode 510 reliably, and then dried, and as shown in FIG34, a raised portion 222p of the electrode paste is formed on the frame bottom surface SF2 in a manner of rising from the via hole VH. This raised portion 222p is provided with a raised portion 222 (FIG. 32) on the package body 720 because the substrate blank GS is pressed against the via hole VH in the lamination step (refer to the steps of FIG19 and FIG20).

In addition, regarding the configuration other than the above, since it is almost the same as the configuration of any one of the above-mentioned embodiments 1 to 3 or its modified examples, the same symbols are given to the same or corresponding elements, and their description is not repeated.

100: Ceramic part 110: Substrate part 110i: Insulating film 120: Frame part 200: Electrode layer 211,212: Component electrode pad 220: Relay electrode 222: Raised part 222p: Raised part 301~304: Package electrode pad 401~403: Wiring layer 411~414: Substrate interlayer electrode 510,520,530: Interlayer electrode 521~523,531~533: Partial 600: Metallization layer 700F: Sintered sheet 700G: Green sheet 701,702,703,710,720: Package 701G: Area 791,792: Package 890: Crystal blank 900: Crystal oscillator (electrical parts) 960: Solder 980: Cover BR: Fracture surface CV: Cavity DA,DB: Diameter EI: Inner edge EIc: Part of the inner edge EO: Outer edge GF: Frame blank GS: Substrate blank KA,KB,KV,KW: Point LI: Minimum dimension from the inner edge LO: Minimum dimension from the outer edge PR: Periphery PRa: Arc part PRb: Notch part SF1: Frame top surface (first surface) SF2: frame bottom surface (second surface) SF2d: inclined area (first area) SF2f: parallel area (second area) SF3: substrate top surface (third surface) SF3C: cavity surface part SF3S: support surface part SF4: outer wall surface SF4A: calcined surface SF4B: fracture surface SFA: end surface SFB: bottom surface SH: blunt angle TP: push angle TR1,TR2: groove UN0~UN4: area VH: via WD: minimum size between inner edge and outer edge

FIG. 1 is a top view schematically showing the structure of the crystal oscillator of the embodiment 1. FIG. 2 is a schematic cross-sectional view along the line II-II of FIG. 1. FIG. 3 is a top view schematically showing a step of the manufacturing method of the crystal oscillator of FIG. 1. FIG. 4 is a schematic cross-sectional view along the line IV-IV of FIG. 3. FIG. 5 is a top view schematically showing the structure of the package of the embodiment 1. FIG. 6 is a schematic cross-sectional view along the line VI-VI of FIG. 5. FIG. 7 is a top view in which the metallization layer and the frame of FIG. 5 are omitted. FIG. 8 is a top view schematically showing the substrate and the interlayer electrode of FIG. 7, and showing the package electrode pad with a dotted line. FIG. 9 is a top view in which the metallization layer on the frame portion of FIG. 5 is omitted. FIG. 10 is a partially enlarged view of FIG. 9. FIG. 11 is a schematic partial cross-sectional view along line XI-XI of FIG. 5. FIG. 12 is a partial top view schematically showing the structure of the substrate blank in the method for manufacturing a package body of embodiment 1. FIG. 13 is a partial top view schematically showing the substrate portion and substrate interlayer electrode of the substrate blank shown in FIG. 12, and showing the package body electrode pad in dotted lines. FIG. 14 is a schematic partial cross-sectional view along line XIV-XIV of FIG. 12 and FIG. 13. FIG. 15 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 16 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 17 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 18 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 19 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 20 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 21 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 22 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 23 is a partial cross-sectional view schematically showing the structure of the package of the first comparative example in the same view as FIG. 11. FIG. 24 is a partial cross-sectional view schematically showing the structure of the package of the second comparative example in the same view as FIG. 11. FIG. 25 is a partial cross-sectional view schematically showing the structure of the package of the modified example of the implementation form 1 in the same view as FIG. 11. FIG. 26 is a partial top view schematically showing the structure of the package of the modified example of the implementation form 1 in the same view as FIG. 10. FIG. 27 is a top view illustrating the structure of the bottom surface of the interlayer electrode of the package of FIG. 26. FIG. 28 is a view for illustrating the details of the structure of the interlayer electrode shown in FIG. 11. FIG. 29 is a diagram for explaining the details of the structure of the interlayer electrode of the package body of the embodiment 2 of the present invention. FIG. 30 is a diagram for explaining the details of the structure of the interlayer electrode of the package body of the embodiment 3 of the present invention. FIG. 31 is a partial top view schematically showing the structure of the package body of the embodiment 4 in the same view as FIG. 10 of the embodiment 1. FIG. 32 is a schematic partial cross-sectional view along the line XXXII-XXXII of FIG. 31. FIG. 33 is a partial top view schematically showing the structure of the package body of the embodiment 4 in the same view as FIG. 7 of the embodiment 1. FIG. 34 is a partial cross-sectional view schematically showing a step corresponding to FIG. 17 of embodiment 1 in the method for manufacturing a package body of embodiment 4.

110: Baseboard

110i: Insulation film

120: Frame

200:Electrode layer

220: Relay electrode

302: Package electrode pad

403: Wiring layer

510: Dielectric electrode

600:Metallization layer

701:Package

CV: Cavity

EI: Internal edge

EO: Outer Edge

SF1: Frame top (1st side)

SF2: Frame bottom (2nd side)

SF3: Substrate top surface (3rd surface)

SF3C: Cavity surface part

SF3S: Support surface part

SF4: Outer wall

SF4A: calcined surface

SF4B: Broken surface

SFA: end face

SFB: Bottom surface

Claims (16)

A package body is provided with a cavity; It includes a frame portion formed of ceramic, the frame portion has a first surface, and a second surface opposite to the first surface in the thickness direction; the second surface has an inner edge surrounding the cavity, and an outer edge surrounding the inner edge; The package body further includes a substrate portion formed of ceramic; the substrate portion has a third surface, the third surface is provided with a portion supporting the second surface of the frame portion, and a portion facing the cavity; The package further includes an electrode layer disposed on the third surface of the substrate portion, and an interlayer electrode penetrating the frame portion between the first surface and the second surface; the interlayer electrode has an end surface with a diameter DA on the first surface, and a bottom surface with a diameter DB in contact with the electrode layer on the second surface, satisfying DA＜DB; When viewed from above, the bottom surface of the interlayer electrode has a minimum dimension LI from the inner edge of the second surface of the frame portion, and a minimum dimension LO from the outer edge of the second surface of the frame portion, satisfying LO＞LI. A package as claimed in claim 1, wherein the diameter DA is less than 50 μm. A package as claimed in claim 1 or 2, wherein the minimum dimension between the inner edge and the outer edge of the second surface of the frame is less than 200 μm. For the package of claim 1 or 2, LO≧LI×1.5 is satisfied. A package as claimed in claim 1 or 2, wherein the dielectric electrode has a diameter of less than (DA+DB)/2 at a position midway between the end surface and the bottom surface in the thickness direction. A package as claimed in claim 1 or 2, wherein the dielectric electrode has a portion extending from the end surface in a reverse push-out shape in the thickness direction. A package as claimed in claim 6, wherein the reverse push-pull shape has a push-pull angle of more than 5 degrees. A package as claimed in claim 1 or 2, wherein, the portion of the dielectric electrode extending from the end surface to the bottom surface in an inverted push-out shape has a thickness greater than 1/2 of the thickness of the frame portion. A package as claimed in claim 1 or 2, wherein: the interlayer electrode has a side surface connecting the end surface to the bottom surface; the side surface has at least one inflection point in a cross-sectional view parallel to the thickness direction. A package as claimed in claim 9, wherein the at least one bending point includes two bending points that bend in opposite directions. A package as claimed in claim 1 or 2, wherein: the frame portion has an outer wall surface connecting the first surface with the outer edge of the second surface; the outer wall surface has a calcined surface connected to the first surface and a broken surface connected to the second surface. A package as claimed in claim 1 or 2, wherein LI>0 is satisfied. A package as claimed in claim 1 or 2, wherein the interlayer electrode has an outer periphery on the second surface; the outer periphery is formed by an arc portion and a notch portion, the arc portion is along a circular shape of a diameter DB, and the notch portion is along a portion of the inner edge of the second surface of the frame portion. As in the package of claim 13, wherein, the notch portion of the outer periphery of the interlayer electrode has a convex shape facing the inner side of the bottom surface of the interlayer electrode. A package as claimed in claim 1 or 2, wherein the electrode layer is locally thickened at a portion in contact with the bottom surface of the dielectric electrode. A package as claimed in claim 1 or 2, wherein the second surface of the frame has a first region directly connected to the bottom surface of the interlayer electrode and a second region connected to the bottom surface of the interlayer electrode via the first region; the second region is perpendicular to the thickness direction; the first region is inclined relative to the second region in such a manner that the closer it is to the bottom surface of the interlayer electrode, the smaller the thickness of the frame becomes.

Images